KR20230059366A - Controller of memory system and operating method thereof - Google Patents

Abstract

A memory system includes: a memory which includes a request queue configured to enqueue therein operation requests provided from a host device; a temperature increment estimating unit which estimates temperature increments respectively corresponding to the operation requests; and a re-ordering unit which performs a re-ordering operation for re-arranging the operation requests enqueued in the request queue based on the temperature increments. Accordingly, the temperature increment of the memory system is delayed, and improved response performance is provided to the host device.

Description

Memory system controller and its operating method {CONTROLLER OF MEMORY SYSTEM AND OPERATING METHOD THEREOF}

The present invention relates to a memory system, and more particularly, to a memory system including a non-volatile memory device.

The memory system may be configured to store data provided from the host device in response to a write request of the host device. Also, the memory system may be configured to provide stored data to the host device in response to a read request from the host device. The host device is an electronic device capable of processing data and may include a computer, a digital camera, or a mobile phone. The memory system may operate by being embedded in the host device or manufactured in a detachable form and connected to the host device.

An electronic device includes many electronic components, and among them, a computer system may include many electronic components made of semiconductors. Among semiconductor devices constituting a computer system, a host such as a processor or a memory controller may perform data communication with the memory device. A memory device may include a plurality of memory cells, which may be specified as word lines and bit lines, to store data.

An embodiment of the present invention is to provide a memory system controller and an operating method thereof that provide improved response performance to a host device by delaying a temperature rise of the memory system.

A controller of a memory system according to an embodiment of the present invention includes a memory including a request queue in which operation requests transmitted from a host device are queued; a temperature increase amount prediction unit configured to predict temperature increase amounts respectively corresponding to the operation requests; and a reordering unit configured to perform a reordering operation for rearranging the operation requests in the request queue based on the temperature increments.

A method of operating a controller of a memory system according to an embodiment of the present disclosure includes estimating temperature increments respectively corresponding to operation requests transmitted from a host device; and performing a reordering operation for rearranging the operation requests in a request queue in which the operation requests are queued based on the temperature increase amounts.

A controller of a memory system according to an embodiment of the present invention includes a memory including a request queue in which operation requests transmitted from a host device are queued; a temperature increase amount prediction unit configured to predict temperature increase amounts respectively corresponding to the operation requests; a reordering unit configured to rearrange the operation requests in the request queue based on the temperature increase amounts to delay an increase in the temperature of the memory system when a temperature of the memory system exceeds a reordering trigger temperature; and a performance controller configured to change a performance mode of the memory system by comparing the temperature of the memory system with one or more performance control trigger temperatures.

A controller of a memory system and an operating method thereof according to an embodiment of the present disclosure may provide improved response performance to a host device by delaying an increase in temperature of the memory system.

1 is a block diagram illustrating a memory system according to an embodiment of the present invention;
Figure 2 is a diagram for explaining the operating method of the temperature increase predicting unit of Figure 1 according to an embodiment of the present invention;
3 is a diagram for explaining an operating method of the performance controller of FIG. 1 according to an embodiment of the present invention;
4 is a diagram for explaining an operating method of the reordering unit of FIG. 1 according to an embodiment of the present invention;
5 is a flowchart for explaining a method of operating a controller according to an embodiment of the present invention;
6 is a diagram exemplarily illustrating a data processing system including a solid state drive (SSD) according to an embodiment of the present invention;
7 is a diagram exemplarily illustrating a data processing system including a memory system according to an embodiment of the present invention;
8 is a diagram exemplarily illustrating a data processing system including a memory system according to an embodiment of the present invention;
9 is a diagram exemplarily illustrating a network system including a memory system according to an embodiment of the present invention;
10 is a block diagram exemplarily illustrating a nonvolatile memory device included in a memory system according to an embodiment of the present invention.

Advantages and features of the present invention, and methods for achieving them, will be explained in detail through the following embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. However, the present embodiments are provided to explain in detail enough to easily implement the technical idea of the present invention to those skilled in the art to which the present invention belongs.

In the drawings, embodiments of the present invention are not limited to the specific forms shown and are exaggerated for clarity. Although certain terms are used in this specification. This is used for the purpose of explaining the present invention, and is not used to limit the scope of the present invention described in the meaning or claims.

In this specification, the expression 'and/or' is used to mean including at least one of the elements listed before and after. In addition, the expression 'connected/coupled' is used as a meaning including being directly connected to another component or indirectly connected through another component. In this specification, the singular form also includes the plural form unless otherwise specified in the phrase. In addition, elements, steps, operations, and elements referred to as 'comprising' or 'including' used in the specification mean the presence or addition of one or more other elements, steps, operations, and elements.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 is a block diagram illustrating a memory system 100 according to an embodiment of the inventive concept.

The memory system 100 may be configured to store data provided from the host device in response to a write request from an external host device. Also, the memory system 100 may be configured to provide stored data to the host device in response to a read request from the host device.

The memory system 100 includes PCMCIA (Personal Computer Memory Card International Association) cards, CF (Compact Flash) cards, smart media cards, memory sticks, various multi-media cards (MMC, eMMC, RS-MMC, MMC-micro), SD (Secure Digital) card (SD, Mini-SD, Micro-SD), Universal Flash Storage (UFS) or Solid State Drive (SSD).

The memory system 100 may include a controller 110 and a nonvolatile memory device 120 .

The controller 110 may control overall operations of the memory system 100 . The controller 110 may control the non-volatile memory device 120 to perform a foreground operation according to instructions from the host device. The foreground operation may include an operation of writing data to the nonvolatile memory device 120 and reading data from the nonvolatile memory device 120 according to instructions from the host device, that is, a write request and a read request.

Also, the controller 110 may control the non-volatile memory device 120 to perform internally necessary background operations independently of the host device. The background operation may include at least one of a wear leveling operation, a garbage collection operation, an erase operation, a read reclaim operation, and a refresh operation for the nonvolatile memory device 120 . The background operation may include an operation of writing data to the nonvolatile memory device 120 and reading data from the nonvolatile memory device 120 like a foreground operation.

The controller 110 may include a memory 111 , a temperature increase estimation unit 112 , a performance control unit 113 , and a reordering unit 114 .

The memory 111 may perform functions such as an operating memory, a buffer memory, or a cache memory of the controller 110 . The memory 111 is an operating memory and may store a software program driven by the controller 110 and various program data. The memory 111 is a buffer memory and may buffer data transmitted between the host device and the nonvolatile memory device 120 . The memory 111 is a cache memory and may temporarily store cache data. The memory 111 may include a request queue (RQQ). The request queue (RQQ) may contain action requests sent from the host device. Operation requests may be queued in a request queue (RQQ) in the order they are transmitted from the host device. However, as will be described later, operation requests queued in the request queue RQQ may be rearranged by the reordering operation of the reordering unit 114 .

The temperature increase amount prediction unit 112 may predict temperature increase amounts respectively corresponding to operation requests queued in the request queue RQQ. The amount of temperature increase corresponding to the operation request may be the temperature of the memory system 100 that is expected to increase as the operation request is processed. Depending on the embodiment, the temperature increase estimation unit 112 may predict, ie, calculate the temperature increase corresponding to the operation request whenever an operation request is received from the host device. According to an embodiment, when the reordering unit 114 determines to perform a reordering operation, as will be described later, the temperature increase prediction unit 112 determines the temperature increase corresponding to each of the operation requests queued in the request queue RQQ. can be calculated.

The performance controller 113 may compare the temperature of the memory system 100 with one or more performance control trigger temperatures to perform a performance control operation for adjusting the performance of the memory system 100 . The performance adjusting unit 113 may perform a performance adjusting operation by selecting one of a plurality of performance modes and controlling the memory system 100 to operate in the selected performance mode. The temperature of the memory system 100 may be measured by a temperature sensor (not shown) located inside the memory system 100 .

The reordering unit 114 may perform a reordering operation for rearranging the operation requests queued in the request queue RQQ based on the temperature increments of the operation requests predicted by the temperature increase estimation unit 112. . The reordering unit 114 may perform a reordering operation by rearranging the operation request having the smallest temperature increase among the operation requests queued in the request queue RQQ in the earliest order. The reordering unit 114 may perform a reordering operation by rearranging operation requests queued in the request queue RQQ in an order of a small temperature increase. The reordering unit 114 converts a random request (ie, a random read request and/or a random write request), in which a user can more easily experience a response delay, than a sequential request (ie, a sequential read request and/or a sequential write request). A reordering operation can be performed by rearranging in the previous order. The reordering unit 114 may perform a reordering operation for random requests and sequential requests having the same temperature increase by rearranging the random requests in an order prior to the sequential requests. The reordering unit 114 may perform a reordering operation so that the temperature of the memory system 100 increases more slowly. The reordering unit 114 may perform a reordering operation so that more operation requests are processed until a performance adjustment operation for changing to a lower performance mode is performed.

Depending on the embodiment, the reordering unit 114 may perform a reordering operation when a preset reordering trigger condition is satisfied. The reordering trigger condition may include that the temperature of the memory system 100 exceeds the reordering trigger temperature. The reordering unit 114 may perform the reordering operation again whenever a new operation request is received from the host device while the reordering trigger condition is satisfied.

According to an embodiment, the reordering trigger temperature may be a first performance control trigger temperature that is the lowest among performance control trigger temperatures referenced in a performance control operation. According to embodiments, the reordering trigger temperature may be lower than the first performance control trigger temperature. According to embodiments, the reordering trigger temperature may be any one of performance control trigger temperatures referred to in a performance control operation.

The nonvolatile memory device 120 may store data transmitted from the controller 110 under the control of the controller 110 , read the stored data, and transmit the data to the controller 110 .

The non-volatile memory device 120 includes a flash memory device such as a NAND flash or a NOR flash, a ferroelectrics random access memory (FeRAM), a phase-change random access memory (PCRAM), or a magnetic random access memory (MRAM). Memory) or Resistive Random Access Memory (ReRAM).

The non-volatile memory device 120 may include one or more planes, one or more memory chips, one or more memory dies, or one or more memory packages.

FIG. 2 is a diagram for explaining an operating method of the temperature increase estimation unit 112 of FIG. 1 according to an embodiment of the present invention.

Referring to FIG. 2 , the temperature increase estimation unit 112 may calculate a temperature increase based on power consumption information and operation request information corresponding to the operation request transmitted from the host device.

The temperature increase estimation unit 112 may obtain power consumption information corresponding to an operation request by referring to a power consumption information table (PIT). The power consumption information table (PIT) may include power consumption corresponding to each operation type. For example, the type of operation may include a sequential read operation, a sequential write operation, a random read operation, and a random write operation. Power consumption corresponding to each operation type may include average power consumption and/or peak power consumption consumed in processing a processing unit (eg, a predetermined data size) of each operation. The power consumption information table (PIT) may be maintained in the memory 111 and/or the non-volatile memory device 120 . The power consumption information table (PIT) may be previously determined through a test.

Operation request information may include the size of data to be processed through a corresponding operation request.

For example, when the operation request is a sequential read request, the power consumption information corresponding to the operation request includes average power consumption of the sequential read operation, and the operation request information is data to be read from the nonvolatile memory device through the sequential read operation. size can be included.

The temperature increase estimation unit 112 may refer to a predetermined calculation equation (EQ) related to power consumption information and operation request information in order to calculate the temperature increase corresponding to the operation request. The calculation equation (EQ) may be determined in advance through a test.

3 is a diagram for explaining an operating method of the performance controller 113 of FIG. 1 according to an embodiment of the present invention.

Referring to FIG. 3 , the performance controller 113 may determine a performance mode of the memory system 100 according to the temperature of the memory system 100 . The performance controller 113 compares the temperature of the memory system 100 with the first to third performance control trigger temperatures TT1 to TT3 to determine the high performance mode (HP), medium performance mode (MP), and low performance One of the modes LP may be selected, and the memory system 100 may be controlled to operate in the selected performance mode. For example, the first to third performance control trigger temperatures TT1 to TT3 may be 85°C, 95°C, and 105°C, respectively. For example, the high performance mode (HP), medium performance mode (MP), and low performance mode (LP) may be modes in which the memory system 100 operates at 100%, 50%, and 5% performance, respectively. there is.

Specifically, the memory system 100 may operate in the high performance mode (HP) until the temperature of the memory system 100 increases to 95°C. When the temperature of the memory system 100 reaches 95° C., the performance mode of the memory system 100 may be changed from the high performance mode (HP) to the medium performance mode (MP). When the temperature of the memory system 100 is between 85°C and 105°C after the performance mode of the memory system 100 is changed to the medium performance mode (MP), the memory system 100 continues in the medium performance mode (MP). It can work. When the temperature of the memory system 100 decreases from 95°C to 85°C, the performance mode of the memory system 100 may be changed from the medium performance mode (MP) to the high performance mode (HP). When the temperature of the memory system 100 reaches 105° C. after the performance mode of the memory system 100 is changed to the medium performance mode (MP), the performance mode of the memory system 100 changes from the medium performance mode (MP) to the low performance mode. It can be changed to the mode LP. After the performance mode of the memory system 100 is changed to the low performance mode (LP), the memory system 100 may continue to operate in the low performance mode (LP) until the temperature of the memory system 100 decreases to 85°C. there is. When the temperature of the memory system 100 decreases to 85° C., the performance mode of the memory system 100 may be changed from the low performance mode (LP) to the high performance mode (HP).

The performance controller 113 may control an operating frequency and an allowable number of resources to adjust the performance of the memory system 100 . For example, the memory system 100 may operate with lower performance as the operating frequency and/or the allowed number of resources decrease.

Depending on the embodiment, the number of performance modes and performance control trigger temperatures may be variously set differently from those shown in FIG. 3 .

4 is a diagram for explaining an operating method of the reordering unit 114 of FIG. 1 according to an embodiment of the present invention. Case 41 represents a case in which the reordering unit 114 does not perform a reordering operation, and case 42 represents a case in which the reordering unit 114 performs a reordering operation.

Referring to case 41, the controller 110 sequentially sends a first sequential read request (SEQ_RD1), a second sequential read request (SEQ_RD2), a sequential write request (SEQ_WT), and a random read request (RAN_RD) from the host device. can receive The first sequential read request (SEQ_RD1), the second sequential read request (SEQ_RD2), the sequential write request (SEQ_WT), and the random read request (RAN_RD) may be queued in the request queue (RQQ) in transmission order. FIG. 4 exemplarily shows the time taken to process each operation request when the memory system 100 operates in the high performance mode (HP). Hereinafter, the high performance mode (HP) and the medium performance mode (MP) may be modes in which the memory system 100 operates at 100% performance and 50% performance, respectively, as shown in FIG. 3 .

The temperature increase prediction unit 112 may predict a temperature increase corresponding to each operation request. For example, the temperature increase predictor 112 may predict that the temperature of the memory system 100 will increase by 4°C due to processing of the first sequential read request SEQ_RD1. Also, the temperature increase estimation unit 112 may predict that the temperature of the memory system 100 will increase by 4°C due to the processing of the second sequential read request SEQ_RD2. Also, the temperature increase estimation unit 112 may predict that the temperature of the memory system 100 will increase by 2°C due to processing of the sequential write request SEQ_WT. Also, the temperature increase predictor 112 may predict that the temperature of the memory system 100 will increase by 1°C due to processing of the random read request RAN_RD.

If the reordering operation of the reordering unit 114 is not performed, the first sequential read request (SEQ_RD1), the second sequential read request (SEQ_RD2), and the sequential write request (SEQ_WT) may be processed in transmission order. . In the meantime, the temperature of the memory system 100 may not reach the second performance control trigger temperature TT2, that is, 95° C. Therefore, the first sequential read request SEQ_RD1 and the second sequential read request SEQ_RD2 ), and sequential write requests (SEQ_WT) can be processed in high performance mode (HP). After the sequential write request (SEQ_WT) is processed, when the temperature of the memory system 100 reaches 95° C., the performance mode of the memory system 100 is changed from the high performance mode (HP) to the medium performance mode (MP). It can be. Therefore, the random read request (RAN_RD) can be processed 100% in the medium performance mode (MP). As a result, if the random read request (RAN_RD) is 100% processed in the high performance mode (HP), the processing time may be 5 seconds, but since it is processed in the medium performance mode (MP) by the performance throttling operation, the random read request (RAN_RD) ) may be, for example, 10 seconds. That is, if the performance of the memory system 100 is reduced to 50%, the processing time of the random read request RAN_RD may be doubled.

Next, to easily explain the case 42, it can be assumed that the temperature of the memory system 100 increases in proportion to the processing rate of the operation request. For example, when 50% of the operation request is processed, the temperature of the memory system 100 may increase by 50% of the total temperature increase corresponding to the corresponding operation request.

Now, the operation of the reordering unit 114 will be described. The reordering unit 114 may perform a reordering operation when the temperature of the memory system 100 exceeds a reordering trigger temperature, and the reordering trigger temperature is, for example, a first performance control trigger temperature TT1, That is, it may be 85 °C. Accordingly, when the temperature of the memory system 100 rises from 85°C to 89°C as a result of processing the first sequential read request SEQ_RD1, the reordering unit 114 may perform a reordering operation. Specifically, the reordering unit 114 may perform a reordering operation by changing the order of the random read request (RAN_RD) and the second sequential read request (SEQ_RD2). That is, the reordering unit 114 generates a random read request (with the smallest temperature increase) among the second sequential read request (SEQ_RD2), the sequential write request (SEQ_WT), and the random read request (RAN_RD) queued in the request queue (RQQ). RAN_RD) may be processed in the earliest order. Meanwhile, the reordered order shown in case 42 includes the second sequential read request (SEQ_RD2), the sequential write request (SEQ_WT), and the random read request (RAN_RD) queued in the request queue (RQQ) in case 41. It may be the result of rearrangement in order of small temperature increase.

After the reordering operation is performed, the random read request (RAN_RD) and the sequential write request (SEQ_WT) may be sequentially processed. At this time, the temperature of the memory system 100 will rise to 92°C, but since the second performance regulating trigger temperature TT2, that is, 95°C has not yet been reached, the memory system 100 continues to operate in the high performance mode ( HP) can work. Also, when the second sequential read request SEQ_RD2 is processed up to 75%, the temperature of the memory system 100 may reach 95°C. Accordingly, the performance mode of the memory system 100 is changed from the high performance mode (HP) to the medium performance mode (MP), and the remaining 25% of the second sequential read request (SEQ_RD2) is processed in the medium performance mode (MP). can Therefore, if 100% of the second sequential read request (SEQ_RD2) is processed in the high performance mode (HP), the processing time may be 10 seconds, but 75% of the second sequential read request (SEQ_RD2) is processed in the high performance mode by the performance adjustment operation. Since it is processed in (HP) and 25% is processed in medium performance mode (MP), the processing time of the second sequential read request (SEQ_RD2) may be 12.5 seconds.

Comparing the cases 41 and 42 , an increase in temperature of the memory system may be delayed through the reordering operation. In other words, more operation requests can be processed through the reordering operation before changing to a lower performance mode. In addition, as a result of performing the reordering operation, the total execution time of operation requests queued in the request queue (RQQ) may be shortened and response performance to the host device may be improved.

5 is a flowchart illustrating an operating method of the controller 110 according to an embodiment of the present invention.

Referring to FIG. 5 , in step S110, the temperature increase amount predictor 112 may predict temperature increase amounts corresponding to operation requests transmitted from the host device. The amount of temperature increase corresponding to the operation request may be the temperature of the memory system 100 that is expected to increase as the operation request is processed.

In step S120, the reordering unit 114 may perform a reordering operation for rearranging operation requests in the request queue RQQ based on the temperature increase amounts predicted by the temperature increase amount prediction unit 112. there is. Depending on the embodiment, the reordering unit 114 may perform a reordering operation when a reordering trigger condition is satisfied.

6 is a diagram exemplarily illustrating a data processing system including a solid state drive (SSD) according to an embodiment of the present invention. Referring to FIG. 6 , the data processing system 1000 may include a host device 1100 and a solid state drive 1200 (hereinafter referred to as SSD).

The SSD 1200 may include a controller 1210, a buffer memory device 1220, non-volatile memory devices 1231 to 123n, a power supply 1240, a signal connector 1250, and a power connector 1260. .

The controller 1210 may control overall operations of the SSD 1200 . The controller 1210 may include a host interface unit 1211 , a control unit 1212 , a random access memory 1213 , an error correction code (ECC) unit 1214 , and a memory interface unit 1215 .

The host interface unit 1211 may exchange signals SGL with the host device 1100 through the signal connector 1250 . Here, the signal SGL may include a command, address, data, and the like. The host interface unit 1211 may interface the host device 1100 and the SSD 1200 according to the protocol of the host device 1100 . For example, the host interface unit 1211 includes secure digital, universal serial bus (USB), multi-media card (MMC), embedded MMC (eMMC), personal computer memory card international association (PCMCIA), Parallel advanced technology attachment (PATA), serial advanced technology attachment (SATA), small computer system interface (SCSI), serial attached SCSI (SAS), peripheral component interconnection (PCI), PCI Express (PCI-E), universal flash (UFS) storage) may communicate with the host device 1100 through any one of standard interface protocols.

The control unit 1212 may analyze and process the signal SGL input from the host device 1100 . The control unit 1212 may control operations of background functional blocks according to firmware or software for driving the SSD 1200 . The random access memory 1213 can be used as an operating memory for driving such firmware or software. The control unit 1212 may include the temperature increase estimation unit 112 , the performance control unit 113 , and the reordering unit 114 of FIG. 1 .

The error correction code (ECC) unit 1214 may generate parity data of data to be transmitted to the nonvolatile memory devices 1231 to 123n. The generated parity data may be stored in the non-volatile memory devices 1231 to 123n together with the data. The error correction code (ECC) unit 1214 may detect errors in data read from the nonvolatile memory devices 1231 to 123n based on the parity data. If the detected error is within the correction range, the error correction code (ECC) unit 1214 can correct the detected error.

The memory interface unit 1215 may provide control signals such as commands and addresses to the nonvolatile memory devices 1231 to 123n according to the control of the control unit 1212 . The memory interface unit 1215 may exchange data with the non-volatile memory devices 1231 to 123n according to the control of the control unit 1212 . For example, the memory interface unit 1215 provides data stored in the buffer memory device 1220 to the nonvolatile memory devices 1231 to 123n or buffers data read from the nonvolatile memory devices 1231 to 123n. It may be provided as the memory device 1220 .

The buffer memory device 1220 may temporarily store data to be stored in the nonvolatile memory devices 1231 to 123n. Also, the buffer memory device 1220 may temporarily store data read from the non-volatile memory devices 1231 to 123n. Data temporarily stored in the buffer memory device 1220 may be transmitted to the host device 1100 or the nonvolatile memory devices 1231 to 123n under the control of the controller 1210 .

The nonvolatile memory devices 1231 to 123n may be used as storage media of the SSD 1200 . Each of the nonvolatile memory devices 1231 to 123n may be connected to the controller 1210 through a plurality of channels CH1 to CHn. One or more nonvolatile memory devices may be connected to one channel. Nonvolatile memory devices connected to one channel may be connected to the same signal bus and data bus.

The power supply 1240 may provide power (PWR) input through the power connector 1260 to the background of the SSD 1200 . The power supply 1240 may include an auxiliary power supply 1241 . The auxiliary power supply 1241 may supply power so that the SSD 1200 is normally terminated when sudden power off occurs. The auxiliary power supply 1241 may include large-capacity capacitors.

The signal connector 1250 may be configured with various types of connectors according to an interface method between the host device 1100 and the SSD 1200 .

The power connector 1260 may be configured with various types of connectors according to a power supply method of the host device 1100 .

7 is a diagram exemplarily illustrating a data processing system including a memory system according to an embodiment of the present invention. Referring to FIG. 7 , a data processing system 2000 may include a host device 2100 and a memory system 2200 .

The host device 2100 may be configured in the form of a board such as a printed circuit board. Although not shown, the host device 2100 may include background functional blocks for performing functions of the host device.

The host device 2100 may include a connection terminal 2110 such as a socket, slot, or connector. The memory system 2200 may be mounted on the access terminal 2110 .

The memory system 2200 may be configured in the form of a substrate such as a printed circuit board. The memory system 2200 may be referred to as a memory module or a memory card. The memory system 2200 may include a controller 2210, a buffer memory device 2220, nonvolatile memory devices 2231 to 2232, a power management integrated circuit (PMIC) 2240, and a connection terminal 2250.

The controller 2210 may control overall operations of the memory system 2200 . The controller 2210 may have the same configuration as the controller 1210 shown in FIG. 6 .

The buffer memory device 2220 may temporarily store data to be stored in the nonvolatile memory devices 2231 to 2232 . Also, the buffer memory device 2220 may temporarily store data read from the nonvolatile memory devices 2231 to 2232 . Data temporarily stored in the buffer memory device 2220 may be transmitted to the host device 2100 or the nonvolatile memory devices 2231 to 2232 under the control of the controller 2210 .

The nonvolatile memory devices 2231 to 2232 may be used as storage media of the memory system 2200 .

The PMIC 2240 may provide power input through the access terminal 2250 to the background of the memory system 2200 . The PMIC 2240 may manage power of the memory system 2200 according to the control of the controller 2210 .

The access terminal 2250 may be connected to the access terminal 2110 of the host device. Signals such as commands, addresses, and data, and power may be transferred between the host device 2100 and the memory system 2200 through the connection terminal 2250 . The access terminal 2250 may be configured in various forms according to an interface method between the host device 2100 and the memory system 2200 . The connection terminal 2250 may be disposed on either side of the memory system 2200 .

8 is a diagram exemplarily illustrating a data processing system including a memory system according to an embodiment of the present invention. Referring to FIG. 8 , a data processing system 3000 may include a host device 3100 and a memory system 3200 .

The host device 3100 may be configured in the form of a board such as a printed circuit board. Although not shown, the host device 3100 may include background function blocks for performing functions of the host device.

The memory system 3200 may be configured in the form of a surface-mounted package. The memory system 3200 may be mounted on the host device 3100 through a solder ball 3250 . The memory system 3200 may include a controller 3210 , a buffer memory device 3220 and a nonvolatile memory device 3230 .

The controller 3210 may control overall operations of the memory system 3200 . The controller 3210 may have the same configuration as the controller 1210 shown in FIG. 6 .

The buffer memory device 3220 may temporarily store data to be stored in the nonvolatile memory device 3230 . Also, the buffer memory device 3220 may temporarily store data read from the nonvolatile memory devices 3230 . Data temporarily stored in the buffer memory device 3220 may be transmitted to the host device 3100 or the nonvolatile memory device 3230 under the control of the controller 3210 .

The nonvolatile memory device 3230 may be used as a storage medium of the memory system 3200 .

9 is a diagram exemplarily illustrating a network system including a memory system according to an embodiment of the present invention. Referring to FIG. 9 , a network system 4000 may include a server system 4300 and a plurality of client systems 4410 to 4430 connected through a network 4500 .

The server system 4300 may provide data service in response to requests from the plurality of client systems 4410 to 4430 . For example, the server system 4300 may store data provided from a plurality of client systems 4410 to 4430 . As another example, the server system 4300 may provide data to a plurality of client systems 4410 to 4430.

The server system 4300 may include a host device 4100 and a memory system 4200 . The memory system 4200 may include the memory system 100 of FIG. 1 , the SSD 1200 of FIG. 6 , the memory system 2200 of FIG. 7 , and the memory system 3200 of FIG. 8 .

10 is a block diagram exemplarily illustrating a nonvolatile memory device included in a memory system according to an embodiment of the present invention. Referring to FIG. 10 , the nonvolatile memory device 300 includes a memory cell array 310, a row decoder 320, a data read/write block 330, a column decoder 340, a voltage generator 350, and a control logic. (360).

The memory cell array 310 may include memory cells MC arranged in an area where word lines WL1 to WLm and bit lines BL1 to BLn cross each other.

The row decoder 320 may be connected to the memory cell array 310 through word lines WL1 to WLm. The row decoder 320 may operate under the control of the control logic 360 . The row decoder 320 may decode an address provided from an external device (not shown). The row decoder 320 may select and drive word lines WL1 to WLm based on a decoding result. For example, the row decoder 320 may provide the word line voltage provided from the voltage generator 350 to the word lines WL1 to WLm.

The data read/write block 330 may be connected to the memory cell array 310 through bit lines BL1 to BLn. The data read/write block 330 may include read/write circuits RW1 to RWn corresponding to each of the bit lines BL1 to BLn. The data read/write block 330 may operate under the control of the control logic 360 . The data read/write block 330 may operate as a write driver or a sense amplifier according to an operation mode. For example, the data read/write block 330 may operate as a write driver that stores data provided from an external device in the memory cell array 310 during a write operation. As another example, the data read/write block 330 may operate as a sense amplifier that reads data from the memory cell array 310 during a read operation.

The column decoder 340 may operate under the control of the control logic 360 . The column decoder 340 may decode an address provided from an external device. The column decoder 340 connects the read/write circuits RW1 to RWn of the data read/write block 330 corresponding to each of the bit lines BL1 to BLn and data input/output lines (or data input/output lines) based on the decoding result. buffer) can be connected.

The voltage generator 350 may generate a voltage used for a background operation of the nonvolatile memory device 300 . Voltages generated by the voltage generator 350 may be applied to memory cells of the memory cell array 310 . For example, a program voltage generated during a program operation may be applied to word lines of memory cells on which a program operation is to be performed. As another example, an erase voltage generated during an erase operation may be applied to a well-region of memory cells in which an erase operation is to be performed. As another example, a read voltage generated during a read operation may be applied to word lines of memory cells on which a read operation is to be performed.

The control logic 360 may control overall operations of the nonvolatile memory device 300 based on a control signal provided from an external device. For example, the control logic 360 may control read, write, and erase operations of the nonvolatile memory device 300 .

Since the person skilled in the art to which the present invention pertains may be embodied in other specific forms without changing the technical spirit or essential characteristics of the present invention, the embodiments described above are illustrative in all respects and not limiting. must be understood as The scope of the present invention is indicated by the claims to be described later rather than the detailed description above, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention. do.

100: memory system
110: controller
111: memory
112: temperature increase prediction unit
113: performance control unit
114: reordering unit
120: non-volatile memory device

Claims (19)

a memory including a request queue in which operation requests transmitted from the host device are queued;
a temperature increase amount prediction unit configured to predict temperature increase amounts respectively corresponding to the operation requests; and
and a reordering unit configured to perform a reordering operation for rearranging the operation requests in the request queue based on the temperature increase amounts. According to claim 1,
The temperature increase prediction unit calculates the temperature of the memory system, which is expected to increase as the operation request is processed, as a temperature increase corresponding to the operation request. According to claim 1,
The temperature increase prediction unit calculates a temperature increase corresponding to the operation request based on power consumption information and operation request information corresponding to the operation request,
The power consumption information includes at least one of average power consumption and peak power consumption corresponding to the operation request, and the operation request information includes a data size corresponding to the operation request. According to claim 1,
The reordering unit performs the reordering operation by rearranging an operation request having a smallest temperature increase among the operation requests in an earlier order. According to claim 1,
The controller of the memory system, wherein the reordering unit performs the reordering operation by rearranging the operation requests in an order of a small temperature increase. According to claim 1,
The reordering unit performs a reordering operation by rearranging the random requests in an order prior to the sequential requests for random requests and sequential requests having the same temperature increment. According to claim 1,
wherein the reordering unit performs the reordering operation when the temperature of the memory system exceeds a reordering trigger temperature. According to claim 7,
The controller of the memory system further comprising a performance control unit configured to compare the temperature of the memory system with one or more performance control trigger temperatures and perform a performance control operation for adjusting the performance of the memory system. According to claim 8,
The reordering trigger temperature is a first performance control trigger temperature that is the lowest among the one or more performance control trigger temperatures. estimating temperature increments respectively corresponding to the operation requests transmitted from the host device; and
and performing a reordering operation for rearranging the operation requests in a request queue in which the operation requests are queued based on the temperature increments. According to claim 10,
The estimating of the temperature increments may include calculating a temperature of the memory system, which is expected to increase as the operation request is processed, as a temperature increase corresponding to the operation request. According to claim 10,
The step of estimating the temperature increments includes calculating a temperature increase amount corresponding to the operation request based on power consumption information and operation request information corresponding to the operation request;
The power consumption information includes at least one of average power consumption and peak power consumption corresponding to the operation request, and the operation request information includes a data size corresponding to the operation request. According to claim 10,
The performing of the reordering operation may include rearranging an operation request having a smallest temperature increase among the operation requests in an earlier order. According to claim 10,
The performing of the reordering operation may include rearranging the operation requests in an order of a small temperature increase. According to claim 10,
The performing of the reordering operation may include rearranging the random requests in an order prior to the sequential requests with respect to random requests and sequential requests having the same temperature increase amount. According to claim 10,
The performing of the reordering operation may include performing the reordering operation when a temperature of the memory system exceeds a reordering trigger temperature. According to claim 16,
and comparing the temperature of the memory system with one or more performance control trigger temperatures to perform a performance control operation for adjusting performance of the memory system. According to claim 17,
The reordering trigger temperature is a first performance control trigger temperature that is the lowest among the one or more performance control trigger temperatures. a memory including a request queue in which operation requests transmitted from the host device are queued;
a temperature increase amount prediction unit configured to predict temperature increase amounts respectively corresponding to the operation requests;
a reordering unit configured to rearrange the operation requests in the request queue based on the temperature increase amounts to delay an increase in the temperature of the memory system when a temperature of the memory system exceeds a reordering trigger temperature; and
and a performance control unit configured to change a performance mode of the memory system by comparing the temperature of the memory system with one or more performance control trigger temperatures.

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