KR20230054136A - Neuromorphic Hardware - Google Patents

Abstract

The present invention relates to a neuromorphic hardware and specifically, relates to the neuromorphic hardware capable of probabilistic backpropagation learning. According to an embodiment of the present invention, an operation for probabilistic backpropagation learning can probabilistically be calculated through a probabilistic computing method of the neuromorphic hardware. The neuromorphic hardware comprises: a resistance memory array; and a probabilistic neuron array.

Description

Neuromorphic Hardware { Neuromorphic Hardware}

The present invention relates to neuromorphic hardware, and more specifically, to neuromorphic hardware capable of probabilistic backpropagation learning.

It can be used in various fields such as recognition, image recognition, voice recognition, and face recognition. An artificial neural network may be implemented in a Very Large Scale Integrated Circuit (VLSI). Similar to biological neural networks, artificial neural networks can include synapses and artificial neurons.

As technology develops, the complexity of artificial neural networks may gradually increase. Specifically, the number of synapses and artificial neurons of the artificial neural network may increase. As a result, there is a problem in that the area and power consumption of the artificial neural network implemented in hardware may increase.

The artificial neural network according to the prior art uses ex-situ training and transfer learning methods in which learning is performed in an external processor, and a weight map after learning is completed is extracted and applied to a resistance memory array. .

However, transfer learning according to the prior art has a problem in that accuracy of a circuit used for programming is increased because an error in a transition process directly affects a classification error.

1. Korean Patent Laid-open Publication No. 10-2020-0001377 "Neuromorphic Processor and Operation Method Thereof" (published on January 6, 2020)

The present invention provides neuromorphic hardware that generates both a sigmoid function and a sigmoid derivative function necessary for backpropagation learning and calculates a weight update amount using probabilistic computing.

The technical problem to be achieved by the present invention is not limited to the above-mentioned technical problem, and other technical problems not mentioned can be clearly understood by those skilled in the art from the description below. There will be.

According to one aspect of the present invention, neuromorphic hardware is provided.

Neuromorphic hardware according to an embodiment of the present invention includes a resistive memory array including a plurality of resistive memories; and a stochastic neuron array connected to the resistive memory array, wherein the stochastic neuron array includes a random number generator generating a random signal; and a plurality of probabilistic neuron circuits receiving the random signals and weights and performing comparison.

According to an embodiment of the present invention, an operation for stochastic backpropagation learning may be probabilistically calculated through a probabilistic computing method of neuromorphic hardware.

The effects of the present invention are not limited to the above effects, and should be understood to include all effects that can be inferred from the description of the present invention or the configuration of the invention described in the claims.

1 is a diagram illustrating an artificial neural network according to an embodiment of the present invention.
FIG. 2 is a block diagram showing an artificial neuron shown in FIG. 1 as an example.
3 is a diagram illustrating neuromorphic hardware according to an embodiment of the present invention.
4 is a diagram for explaining a stochastic neuron circuit according to an embodiment of the present invention.
5 and 6 are diagrams for explaining a sigmoid differential function circuit according to an embodiment of the present invention.
7 is a diagram for explaining a random number generator according to an embodiment of the present invention.
8 and 9 are diagrams for explaining a hybrid neuron circuit according to an embodiment of the present invention.

Hereinafter, the present invention will be described with reference to the accompanying drawings. However, the present invention may be embodied in many different forms and, therefore, is not limited to the embodiments described herein. And in order to clearly explain the present invention in the drawings, parts irrelevant to the description are omitted, and similar reference numerals are attached to similar parts throughout the specification.

Throughout the specification, when a part is said to be "connected (connected, contacted, combined)" with another part, this is not only "directly connected", but also "indirectly connected" with another member in between. "Including cases where In addition, when a part "includes" a certain component, it means that it may further include other components without excluding other components unless otherwise stated.

Terms used in this specification are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, terms such as "include" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, but one or more other features It should be understood that the presence or addition of numbers, steps, operations, components, parts, or combinations thereof is not precluded.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating an artificial neural network according to an embodiment of the present invention.

Artificial Neural Networks (ANNs) are statistical networks that process data in a manner similar to biological neural networks. Artificial neural networks can be used in various fields such as text recognition, image recognition, voice recognition, and face recognition. An artificial neural network may be implemented in a Very Large Scale Integrated Circuit (VLSI). Similar to biological neural networks, artificial neural networks can include synapses and artificial neurons.

Referring to FIG. 1, an Artificial Neural Network (ANN, 10) refers to an artificially constructed network similar to a biological neural network. Referring to FIG. 1 , an artificial neural network 10 may include an input layer 11, a hidden layer 12, and an output layer 13.

The input layer 11, the hidden layer 12, and the output layer 13 may be connected to each other through synapses. Biologically, a synapse is a junction between a neuron and another neuron. Similarly, artificial neurons and other artificial neurons in the artificial neural network 10 may be coupled to each other through synapses.

The artificial neural network 10 may include a plurality of artificial neurons 100 . The plurality of artificial neurons 100 include input neurons that receive input data (X1 　 to XI) from the outside, hidden neurons that receive data from the input neurons and process them, and receive data from the hidden neurons and output data (Yi 　 to YJ ) may include an output neuron that generates.

The input layer 11 may include a plurality of input neurons, the hidden layer 12 may include a plurality of hidden neurons, and the output layer 13 may include a plurality of output neurons. Here, the number of artificial neurons included in each of the input layer 11, the hidden layer 12, and the long output layer 13 is not limited to what is shown. The hidden layer 12 may include more layers than those shown in FIG. 1 , and the number of layers described above is related to the accuracy or learning speed of the artificial neural network 10 .

FIG. 2 is a block diagram showing an artificial neuron shown in FIG. 1 as an example.

Referring to FIG. 2 , the artificial neuron 100 may include a summation circuit 110 and an activation function circuit 120.

The summing circuit 110 may sum the input signals A1 ˜ AK using the weights W1 ˜ WK. Each of the input signals may represent an output signal generated from any artificial neuron. The synaptic strength of each of the weights (ie, the degree of coupling between artificial neurons and other artificial neurons) may be indicated. In detail, the summing circuit 110 may multiply the weights and the input signals, respectively, and then combine the multiplication results to generate the summation result B. Therefore, if the weight is low, the corresponding input signal has a low weight in the summation result (B), and if the weight is high, the weight of the corresponding input signal is high in the summation result (B). The summation result can be expressed by Equation 1.

[Equation 1]

The activation function circuit 120 may output an activation result (C) using the summation result (B) and an activation function (f).

The activation function converts the weighted sum of neuron inputs into a probability of a firing rate. As the activation function, various types based on stochastic computing can be used.

In the stochastic computing neuron circuit according to the present invention, circuit technologies such as step, identity, rectified-linear (ReLU), and sigmoid may be used for the activation function used for stochastic computing.

For example, the sigmoid function is a non-linear function and can output a value between 0 and 1 for all inputs. The activation result (C, i.e. the output of the sigmoid function) can be transmitted to another artificial neuron via synapse. That is, the activation result (C) can be an input to another artificial neuron.

The activation result (C) of the activation function (f) by the sigmoid function can be expressed by Equation 2.

[Equation 2]

As the activation function used in the present invention, a sigmoid differentiation function may be used. The sigmoid differentiation function will be described in detail with reference to FIG. 4 below.

3 is a diagram illustrating neuromorphic hardware according to an embodiment of the present invention.

Referring to FIG. 3 , the neuromorphic hardware may include a resistive memory (RERAM) array and a stochastic neuron array.

A resistive memory (RERAM) array can receive input data and pass it to a Stochastic Neuron Array. The resistive memory (RERAM) array may be configured by connecting a plurality of resistive memories (RERAM).

The stochastic neuron array may include an amplifier 200 , a stochastic neuron circuit 300 , and a random number generator 400 .

In the stochastic neuron circuit 300, the currents generated in the resistive memory RERAM are added by an integrator circuit composed of the amplifier 200 and the capacitor to form a voltage, and the stochastic neuron circuit 300 It is connected to the node of the neuron circuit 300. A node opposite the stochastic neuron circuit 300 is connected to the random number generator 400, and through several comparisons, an integrator voltage of voltage may be output as a probability value.

The random number generator 400 may generate and output a random signal.

4 is a diagram for explaining a stochastic neuron circuit according to an embodiment of the present invention.

Referring to Figure 4 (a), when the output (output) of the stochastic neuron (stochastic neuron) circuit is sigmoid, one comparator (comparator, 210) and a random number generator (RNG: random number generator, 400), inference according to a forward vector matrix multiplication (VMM) operation can be performed as shown in Equation 3 below.

[Equation 3]

In this case, Y may be an output value of the comparator, and f may be a sigmoid function.

Referring to FIG. 4(b), the stochastic neuron circuit of the present invention generates a signal signal through two comparators 320 and 330, a random number generator (RNG), and a first logic gate. You can implement the derivative function of the sigmoid.

Comparators are used to implement hard thresholds (steps) for activation functions in artificial neural networks. Each of the two comparators 320 and 330 may receive independent random signals Seed#1 and Seed#2 from the random number generator 400 and output result values.

The random number generator 400 may output two independent random signals (Seed#1, Seed#2) to implement a sigmoid derivative function.

The first logic gate may include an XOR gate that performs an exclusive OR operation on the output values Y1 and Y2 received from the two comparators 320 and 330, respectively, and a first AND gate that performs a AND operation between the output value of the XOR gate and an N-bit signal. can

Training according to the sigmoid differential function in a stochastic neuron circuit can be performed as shown in Equation 4 below.

[Equation 4]

Here, the output values Y1 and Y2 of each comparator may be independent values, and N is the number of conversions of the comparator.

5 and 6 are diagrams for explaining a sigmoid differential function circuit according to an embodiment of the present invention.

Referring to FIGS. 5 and 6, in back-propagation learning of stochastic computing, the sigmoid and sigmoid derivative functions required for learning are stochastic neurons ( stochastic neurons). Through this, the weight update amount can be calculated as shown in Equation 5 using stochastic computing.

[Equation 5]

, when j =hidden layer

, when j = hidden layer

, when j =output layer

, when j = output layer

W는 가중치 업데이트 양이고,

은 학습률(learning rate)을 나타낸다.here

W is the weight update amount,

represents the learning rate.

A stochastic neuron performs a complex back-propagation operation by passing a stochastic output generated at the same timing in each layer through a second logic gate. can be calculated probabilistically.

As shown in FIG. 6, the layers used for stochastic output include the first layer, the previous layer (Pre-layer, 610), the second layer, the current layer (620), and the second layer. It may include a third layer, the next layer (Post layer, 630).

In back-propagation learning of stochastic neurons, the sigmoid function is used as the activation function in the pre-layer, and the sigmoid differentiation function is used in the current layer as the activation function. is used, and a linear function may be used as an activation function in the next layer (Post layer).

) 일 수 있다. 현재 레이어 입력(Current layer Input)은 현재 레이어(620)에서 포워드 패스의 시그모이드 미분 함수(Fowerd, sigmoid-Derivative)에 따른 입력값

일 수 있다. 다음 레이어 입력(Post layer Input)은 다음 레이어(630)에서 백워드 패스의 선형함수(Backward, Linear)에 따른 입력값(

) 일 수 있다.At this time, the previous layer output (Pre-layer Output) is an output value according to the sigmoid function (Forward, sigmoid) of the forward pass in the previous layer 610 (

) can be The current layer input is an input value according to the sigmoid derivative function (Fowerd, sigmoid-Derivative) of the forward pass in the current layer 620

can be The next layer input (Post layer Input) is an input value according to the linear function (Backward, Linear) of the backward pass in the next layer 630 (

) can be

)과 현재 레이어 입력

이 입력되는 제2 AND 게이트(640), 제2 AND 게이트 출력 값, 다음 레이어 입력 (

) 내지 학습률(

)이 입력되는 제3 AND 게이트(650)를 포함하고, 제3 AND 게이트(650)는 가충치 업데이트양(

W)을 출력할 수 있다.According to an embodiment, the second logic gate outputs the previous layer (

) and the current layer input

The second AND gate 640 input, the second AND gate output value, and the next layer input (

) to learning rate (

) is input, and the third AND gate 650 includes a value update amount (

W) can be output.

7 is a diagram for explaining a random number generator according to an embodiment of the present invention.

Referring to FIG. 7(a), in order to implement a sigmoid derivative function in a stochastic neuron circuit, two independent random signals may be input. To this end, the random number generator (RNG) can generate two random number generator seeds (seed#1, seed#2) from one random number generator seed (RNG Seed) using a simple circuit.

The random number generator seed (RNG Seed, 700) can be divided into two groups of MSB and LSB by inputting two N bits to the XOR-based LFSR. Both groups can each generate a truncated LSB (LSB Truncated) through a full adder. Thereafter, a full adder of each generated truncated LSB (LSB Truncated) may be output as a final truncated LSB (LSB Truncated).

The final truncated LSB (LSB Truncated) is input to the MUX through Gaussian separation, and either one of the two LSBs may be input to the MUX through uniform separation. The MUX can control any type of bit stream applied to the DAC and output to the Resistive DAC (RDAC).

Referring to FIG. 7 (b), the random number generator 400 converts one of the two bits (D-Bit1 and D-Bit2) output from the LFSR logic into a first Uniform SNG and the other into a first Gaussian SNG. A first seed (Seed#1) may be generated.

In addition, the random number generator 400 inputs two bits (D-Bit1, D-Bit2) output from the LFSR logic to a circular shifter, and two bits (D-Bit1') output from the circular shifter , D-Bit2') may be used to generate a second seed (Seed#1) in which one is the second Uniform SNG and the other is the second Gaussian SNG.

8 and 9 are diagrams for explaining a hybrid neuron circuit according to an embodiment of the present invention.

As shown in FIG. 8, the hybrid neuron circuit operates not only as a stochastic neuron but also as a single slope ADC with high precision during transfer learning. It may be a circuit that

A hybrid neuron circuit may perform an inference & in-situ learning mode and a transfer learning mode.

Referring to FIG. 8(a), in the case of inference & in-situ learning mode, a hybrid neuron circuit 810 uses a random signal to generate stochastic neurons. neurons) can act.

According to an embodiment, the hybrid neuron circuit 810 may infer the sum of weights W received from the resistive memory array through an activation function and output a real-time learning result.

Referring to FIG. 8 (b), the hybrid neuron circuit 820 is a single slope analog-to-digital converter using a ramp signal in the transfer learning mode. It can work.

)를 아날로그-디지털[A/D] 변환부로 입력되어 현재 신호(

)를 출력할 수 있다. 이때, 현재 신호는 1-Wirte pulse 와 1-Read pulse를 포함할 수 있다. According to an embodiment, the hybrid neuron circuit 820 is a target signal received from the resistive memory array (

) is input to the analog-digital [A/D] conversion unit and the current signal (

) can be output. At this time, the current signal may include 1-Wirte pulse and 1-Read pulse.

)와 타겟 신호(

)과 동일한지 판단할 수 있다. 하이브리드(hybrid) 뉴런 회로(820)는 현재 신호(

)와 타겟 신호(

)과 동일한 경우, 현재 신호(

)를 다음 셀로 출력할 수 있다.Then, the hybrid neuron circuit 820 may calculate an output value according to the transfer learning mode. The hybrid neuron circuit 820 is a current signal (

) and the target signal (

) can be judged to be the same as The hybrid neuron circuit 820 is a current signal (

) and the target signal (

), the current signal (

) to the next cell.

)와 타겟 신호(

)과 동일하지 않은 경우, 현재 신호(

)를 아날로그-디지털[A/D] 변환부로 입력할 수 있다.On the other hand, the hybrid neuron circuit 820 is a current signal (

) and the target signal (

), the current signal (

) can be input to the analog-digital [A/D] conversion unit.

9 shows a random & ramp signal generator included in the hybrid neuron circuit.

Referring to FIG. 9, when the random and ramp signal generator operates as a stochastic neuron, a truncated LSB (LSB Truncated) is generated from two LFSRs through a full adder operation, and the MUX and DAC It can be generated as a random signal through

When the random and ramp signal generator operates as a single slope analog-to-digital converter, a signal received from one counter can be generated as a ramp signal through a MUX and a DAC.

The above-described probabilistic backpropagation learning method may be implemented as computer readable code on a computer readable medium. The computer-readable recording medium may be, for example, a removable recording medium (CD, DVD, Blu-ray disc, USB storage device, removable hard disk) or a fixed recording medium (ROM, RAM, computer-equipped hard disk). can The computer program recorded on the computer-readable recording medium may be transmitted to another computing device through a network such as the Internet, installed in the other computing device, and thus used in the other computing device.

In the above, even though all the components constituting the embodiment of the present invention have been described as being combined or operated as one, the present invention is not necessarily limited to these embodiments. That is, within the scope of the object of the present invention, all of the components may be selectively combined with one or more to operate.

Although actions are shown in a particular order in the drawings, it should not be understood that the actions must be performed in the specific order shown or in a sequential order, or that all shown actions must be performed to obtain a desired result. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of the various components in the embodiments described above should not be understood as requiring such separation, and the described program components and systems may generally be integrated together into a single software product or packaged into multiple software products. It should be understood that there is

So far, the present invention has been looked at mainly by its embodiments. Those skilled in the art to which the present invention pertains will be able to understand that the present invention can be implemented in a modified form without departing from the essential characteristics of the present invention. Therefore, the disclosed embodiments should be considered from a descriptive point of view rather than a limiting point of view. The scope of the present invention is shown in the claims rather than the foregoing description, and all differences within the equivalent scope will be construed as being included in the present invention.

10: artificial neural networks
100: artificial neuron
110: summing circuit
120 active function circuit
200: amplifier
300: stochastic neuron circuit
400: random number generator

Claims (8)

a resistive memory array comprising a plurality of resistive memories; and
a stochastic neuron array coupled to the resistive memory array;
The stochastic neuron array
a random number generator for generating a random signal; and
Including a plurality of stochastic neuron circuits for performing comparison by receiving the random signal and weights
Neuromorphic hardware.
According to claim 1,
The stochastic neuron circuit is
two comparators each receiving independent random signals from the random number generator;
an XOR gate for performing an exclusive OR operation on the output values received from the two comparators; and
A first AND gate for performing an AND operation of the output value of the XOR gate and an N-bit signal
Neuromorphic hardware.
According to claim 2,
The stochastic neuron circuit is
generating a sigmoid derivative function as an activation function.
Neuromorphic hardware.
According to claim 3,
The stochastic neuron array
Calculating the weight update amount using stochastic computing according to the sigmoid differentiation function
Neuromorphic hardware.
According to claim 4,
The stochastic neuron array
previous layer using the sigmoid function as the activation function;
a current layer using the sigmoid differentiation function as an activation function;
The next layer uses a linear function as an activation function; and
Including a logic gate that stochastically calculates the stochastic output generated in each layer by backpropagation operation
Neuromorphic hardware.
According to claim 5,
The logic gate is
a second AND gate receiving an output of the previous layer and an input of the current layer; and
A third AND gate receiving an output of the second AND gate, an input of the next layer, or a learning rate;
The third AND gate outputs the weight update amount
Neuromorphic hardware.
According to claim 1,
Further comprising a single slope analog-to-digital converter that receives the ramp signal and performs comparison
Neuromorphic hardware.
According to claim 1,
The single slope analog-to-digital converter
Calculate the output value according to the transfer learning mode
Neuromorphic hardware.

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