KR20230047534A - Fast Successive Approximation ADC With series Time-Interleaved Architecture - Google Patents

Abstract

An analog-to-digital converter based on a serial time interleave structure comprises: a first comparison unit that sequentially receives sample data from which an input signal is sampled in response to a clock signal in the order of the most significant bit and compares it with a first reference voltage; a first group unit delay unit for delaying an output signal of the first comparison unit by a unit in response to the clock signal to output it; and a 1-bit digital-to-analog converter that processes the output signal of the first group unit delay unit to output a second reference voltage.

Description

High-performance analog-to-digital converter based on serial time-interleaved architecture {Fast Successive Approximation ADC With series Time-Interleaved Architecture}

The present invention relates to an analog-to-digital converter, and more particularly, to an analog-to-digital converter based on a serial time interleave structure.

An analog-to-digital converter is a mixed-signal integrated circuit that converts an analog signal into a digital signal.

Analog-to-digital converters are critical for data acquisition, communications, radar and instrumentation systems. The overall speed and resolution of these systems depends on the performance of the analog-to-digital converter.

Different analog-to-digital converter architectures have been developed and used in different applications based on specific functional requirements such as power consumption, sampling rate, resolution, chip area and latency.

In data acquisition systems where medium-high speed and higher resolution are required, the Successive Approximation Register (SAR) analog-to-digital converter architecture (Prior Document 1) is used.

1 is a block diagram of a 6-bit Successive Approximation Register (SAR) analog-to-digital converter architecture.

The input signal sampled from the analog-to-digital converter is fed into a digital-to-analog converter (DAC) and compared to several digital codes, which is done by initially setting bits to zero. Then, starting with the most significant bit (MSB), each bit is set to 1 in order, and the output of the digital-to-analog converter is compared with the input sample.

The bit is set to 0 if samples are less than the digital-to-analog converter output, otherwise it is held at 1. Finally, when the least significant bit (LSB) is resolved, the bit is stored in the latch, then the cycle begins again by setting the bit to 0 and taking a new sample from the input analog signal. Therefore, the Nbit resolution conversion time is N+1 clock cycles. Given a clock frequency fCK, the maximum possible sampling frequency fs = fCK /(N+1).

Several architectures are currently being studied to overcome the speed limitations of conventional successive approximation register analog-to-digital converters (SAR ADCs).

(Prior Document 1) Yuan Zhou, Benwei Xu, and Yun Chiu. A 12-b 1-gs/s 31.5-mw time-interleaved sar adc with analog hpf-assisted skew calibration and randomly sampling reference adc. IEEE Journal of Solid-State Circuits, 54(8):2207.2218, 2019

The present invention has been proposed to solve the above technical problems, and provides a new high-speed successive approximation analog-to-digital converter using a serial time interleave architecture that can solve the speed limit problem of the existing successive approximation register analog-to-digital converter (SAR ADC). do.

According to an embodiment of the present invention for solving the above problem, a first comparator for receiving sample data obtained by sampling an input signal in response to a clock signal in order of highest bit and comparing the sample data with a first reference voltage; A 1-bit digital-to-analog converter processing the output signal of the first group unit delay unit and outputting a second reference voltage; There is provided an analog-to-digital converter based on a serial time interleave structure including a.

In addition, the analog-to-digital converter based on the serial time interleave structure of the present invention includes a first sampling unit delay unit that sequentially unit-delays and outputs the sample data in order of most significant bit in response to a clock signal; A second comparison unit that compares the output signal of the first sampling unit delay unit with the output signal of the 1-bit digital-to-analog converter, and unit delays the output signals of the first and second comparison units in response to the clock signal and outputs the output signal. and a 2-bit digital-to-analog converter processing an output signal of the second group-based delay unit and outputting a third reference voltage.

In addition, the analog-to-digital converter based on the serial time interleave structure of the present invention includes a second sampling unit delay unit that unit-delays and outputs an output signal of the first sampling unit delay unit in response to the clock signal, and a second sampling unit delay unit that responds to the clock signal. a third comparator for comparing the output signal of the second sampling unit delay unit with the output signal of the 2-bit digital-to-analog converter, and unit delaying the output signals of the first to third comparators in response to the clock signal, respectively. It is characterized in that it further comprises a third group unit delay unit for outputting.

Further, the analog-to-digital converter based on the serial time interleaving structure of the present invention may further include an output signal latch unit for latching an output signal of the third group unit delay unit in response to the clock signal.

The analog-to-digital converter of the present invention uses a serial time-interleave architecture to solve the speed limit problem of conventional successive approximation register analog-to-digital converters (SAR ADCs).

1 is a block diagram of a 6-bit Successive Approximation Register (SAR) analog-to-digital converter architecture;
2 is a block diagram of a fast successive approximation analog-to-digital converter 1 according to an embodiment of the present invention.
3 is a diagram showing a MATLAB Simulink simulation
4 to 7 are diagrams showing output signals of the anode, cathode and output terminals of the first, second, third and twelfth comparators.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings in order to describe in detail enough for those skilled in the art to easily implement the technical idea of the present invention.

In the present invention, a new fast successive approximation analog-to-digital converter architecture is proposed.

Fast successive approximation analog-to-digital converters do not use registers of successive approximation registers, and incorporate the concept of time-interleaved sampling in a serial fashion, so that multiple samples (data) of different samples (data) per clock cycle are obtained. Bit resolution improves conversion speed by a factor of N+1 compared to a conventional N-bit Successive Approximation Register analog-to-digital converter architecture with the same clock frequency.

In the embodiment of the present invention, the 12-bit unipolar fast successive approximation analog-to-digital converter was simulated in MATLAB SIMULINK to verify the architecture design. For the same clock frequency of the 12-bit successive approximation register analog-to-digital converter, the proposed fast successive approximation analog-to-digital converter is confirmed to be 13 times better in terms of conversion speed.

2 is a block diagram of a fast successive approximation analog-to-digital converter 1 according to an embodiment of the present invention.

The proposed fast successive approximation analog-to-digital converter (FAST SA ADC) has a maximum sampling frequency fs = fCK given the clock frequency fCK.

This speed was achieved by introducing two major modifications to the existing SAR ADC architecture.

First, the closed loop system was opened and the use of the SAR register was eliminated.

Next, multiple samples (data) are fed into an analog-to-digital converter (ADC) in a serial time-interleaved fashion before all N bits of a single sample (data) are resolved.

The conversion method of the proposed fast successive approximation analog-to-digital converter is as follows.

Initially, the sampler 10 of the Fast SA ADC samples the input signal VIN in the sampler 10 and outputs sample data, and the first comparator 21 converts it to a first clock signal. It is compared with half of the reference voltage (Vr) in the signal cycle.

First, the comparator (first comparator 21) checks the most significant bit (MSB) of the sample data and outputs the reference voltage (Vr) if the sampled value is greater than the reference voltage (0.5Vr), otherwise 0 create v. The output of the first comparator (first comparator 21) is supplied to a 1-bit digital-to-analog converter (DAC) 51 through a unit delay 41.

Next, the 1-bit digital-to-analog converter (DAC, 51) outputs 0.75Vr or 0.25Vr based on the first comparator 21 output.

That is, the first comparator 21 sequentially receives sample data obtained by sampling the input signal VIN in response to the clock signal in order of the most significant bit and compares the sample data with the first reference voltage 0.5Vr.

The first group unit delay unit 41 unitly delays the output signal of the first comparator 21 in response to the clock signal and outputs the unit delay.

The 1-bit digital-to-analog converter 51 processes the output signal of the first group unit delay unit 41 and outputs a second reference voltage (0.75Vr or 0.25Vr).

The first sampling unit delay unit 31 sequentially unit delays sample data in order of most significant bit in response to a clock signal and outputs the sample data.

The second comparator 22 compares the output signal of the first sampling unit delay unit 31 and the output signal of the 1-bit digital-to-analog converter 51 in response to the clock signal.

The second group unit delay unit 42 unitly delays the output signals of the first and second comparators 21 and 22 in response to the clock signal and outputs the unit delay.

The 2-bit digital-to-analog converter 52 processes the output signal of the second group unit delay unit 42 and outputs a third reference voltage.

The second sampling unit delay unit 32 unitly delays the output signal of the first sampling unit delay unit 31 in response to the clock signal and outputs the unit delay.

The third comparator 23 compares the output signal of the second sampling unit delay unit 32 and the output signal of the 2-bit digital-to-analog converter 52 in response to the clock signal.

The third group unit delay unit respectively delays the output signals of the first to third comparators 21, 22 and 23 in response to the clock signal and outputs the unit delay.

Finally, the output signal latch unit 60 latches and outputs the output signal of the third group unit delay unit in response to the clock signal.

The structure of the above-described high-speed successive approximation analog-to-digital converter (Fast SA ADC, 1) is briefly described as an example when the input signal (VIN) is 3 bits,

Actually, as in the configuration of FIG. 2, after N clock cycles, the Nth comparator compares the first sample data with the (N-1) bit DAC output of N-1 bits of the first sample data to determine the least significant bit (LSB). do.

Finally, after N+1 cycles, all N bits of the first sample data can be used in the output signal latch unit 60.

In the proposed fast successive approximation analog-to-digital converter (Fast SA ADC, 1), unlike the existing SAR ADC architecture, all N bits of the second sample data can be used in (N+2) clock cycles.

Therefore, a fast successive approximation analog-to-digital converter (Fast SA ADC, 1) with N-bit resolution conversion time has N+1 clock cycles and the maximum possible sampling frequency fs = fCK, which is an N+1 improvement over conventional SAR ADCs.

3 is a diagram showing a MATLAB Simulink simulation.

That is, a 12-bit high-speed successive approximation analog-to-digital converter (Fast SA ADC) was simulated in SIMULINK.

The input signal is a sinusoidal signal with a frequency of 1MHz and the sampling frequency is 16MHz, and the anode, cathode and output terminals of each comparator are connected to a 3-input scope.

4 to 7 are diagrams showing output signals of the anode, cathode, and output terminals of the first, second, third, and twelfth comparators. It can be seen from the figure that the ith comparator takes i+1 clock cycles to resolve the ith bit of the sample data and pass it to the next comparator.

To facilitate cross-architecture comparisons, we consider the power dissipated in the comparators and digital-to-analog converters (DACs) and the maximum fs for fCK of the overall architecture system.

It is assumed that power consumed by a 1-bit digital-to-analog converter (DAC) is Pb, and an increase in power consumption according to the number of bits of the digital-to-analog converter (DAC) is assumed to be linear. Assume also that Pc is the power consumed by a single comparator.

<Table 1>

The fast successive approximation analog-to-digital converter (FAST SA ADC) architecture is compared with the 12-bit conventional SAR, 12-bit, 12 time-interleaved channels, conventional ADC architecture (REF2, REF3) in Table 1.

As can be seen from the table, the 12 time-interleaved channels of the 12-bit SAR ADC architecture is the second best in terms of maximum fs, but consumes 12x the power of the conventional SAR ADC architecture. Fast SA ADC with ADC has 1.3x increase in Pb and 1.5x in Pc compared to Ref[3] ADC, but Fast SA ADC is 2.5x better in terms of maximum fs.

These results show that the proposed Fast SA ADC architecture has the most efficient architecture and solves the speed limitation of the existing SAR ADC architecture.

As such, those skilled in the art to which the present invention pertains will be able to understand that the present invention may be embodied in other specific forms without changing its technical spirit or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting. The scope of the present invention is indicated by the following claims rather than the detailed description above, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention. do.

Claims (4)

a first comparator configured to sequentially receive sample data of which an input signal is sampled in order of a most significant bit in response to a clock signal and compare the sample data with a first reference voltage;
a first group unit delay unit unit delaying an output signal of the first comparison unit in response to the clock signal; and
a 1-bit digital-to-analog converter processing the output signal of the first group unit delay unit and outputting a second reference voltage;
An analog-to-digital converter based on a serial time interleave structure comprising a.
According to claim 1,
a first sampling unit delay unit configured to sequentially perform unit delay of the sample data in order of most significant bits in response to the clock signal and output the sample data;
a second comparison unit comparing an output signal of the first sampling unit delay unit and an output signal of the 1-bit digital-to-analog converter in response to the clock signal;
a second group unit delay unit configured to delay and output signals output from the first and second comparators in response to the clock signal; and
A 2-bit digital-to-analog converter for processing the output signal of the second group unit delay unit and outputting a third reference voltage.
According to claim 2,
a second sampling unit delay unit unit delaying an output signal of the first sampling unit delay unit in response to the clock signal;
a third comparison unit comparing an output signal of the second sampling unit delay unit and an output signal of the 2-bit digital-to-analog converter in response to the clock signal; and
A serial time interleave structure-based analog-to-digital converter further comprising a third group unit delay unit configured to delay output signals of the first to third comparators by unit in response to the clock signal and output the unit delay.
According to claim 3,
An analog-to-digital converter based on a serial time interleave structure further comprising: an output signal latch unit latching an output signal of the third group unit delay unit in response to the clock signal.

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