KR20230044908A - Gate driving circuir and display panel including the same - Google Patents

Abstract

Disclosed are a gate driving circuit capable of reducing stress applied to a pull-down transistor, and a display panel including the same. The gate driving circuit according to an embodiment of the present disclosure includes: a control unit which charges and discharges a first control node pulling up an output voltage and a second control node pulling down the output voltage; an output unit including a pull-up transistor which applies a gate-high voltage to an output node in response to a charging voltage of the first control node, and a pull-down transistor which applies a gate-low voltage to the output node in response to a charging voltage of the second control node; a sensing unit which senses a threshold voltage of the pull-down transistor; and a compensation unit which changes the charging voltage of the second control node in response to an output of the sensing unit.

Description

Gate driving circuit and display panel including the same {GATE DRIVING CIRCUIR AND DISPLAY PANEL INCLUDING THE SAME}

The present invention relates to a gate driving circuit and a display panel including the same.

Display devices include a liquid crystal display (LCD), an electroluminescence display (ELD), a field emission display (FED), a plasma display panel (PDP), and the like.

The electroluminescent display device is divided into an inorganic light emitting display device and an organic light emitting display device according to the material of the light emitting layer. An active matrix type organic light emitting display reproduces an input image by using a self-emitting device that emits light itself, for example, an organic light emitting diode (OLED). The organic light emitting display device has a fast response speed, a high light emitting efficiency, luminance, and a large viewing angle.

Some of the display devices, for example, a liquid crystal display or an organic light emitting display, include a display panel including a plurality of pixels, a driving unit outputting a driving signal for driving the display panel, and a power supply unit generating power to be supplied to the display panel or the driving unit. included The driving unit includes a gate driving unit supplying gate signals such as a scan signal and an emission control signal to the display panel, and a data driving unit supplying data signals to the display panel.

In such a display device, when a driving signal, for example, a gate signal and a data signal, is supplied to a plurality of sub-pixels formed on a display panel, the selected sub-pixel transmits light or emits light directly, thereby displaying an image. .

At this time, the gate driver outputs a signal once during one frame and maintains a low voltage most of the remaining time through the turn-on of the pull-down transistor. In this way, the pull-down transistor is driven for a long period of time and is vulnerable to reliability due to stress. Therefore, there is a need for a method to improve circuit life by reducing the stress applied to the pull-down transistor.

The present invention aims to address the aforementioned needs and/or problems.

The present invention provides a gate driving circuit capable of reducing stress applied to a pull-down transistor and a display panel including the gate driving circuit.

The objects of the present invention are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the following description.

A gate driving circuit of the present invention includes a control unit that charges and discharges a first control node that pulls up an output voltage and a second control node that pulls down the output voltage; A pull-up transistor for applying a gate high voltage to an output node in response to the charging voltage of the first control node, and a pull-down transistor for applying a gate low voltage to the output node in response to the charging voltage of the second control node. output unit; a sensing unit sensing a threshold voltage of the pull-down transistor; and a compensation unit that changes the charging voltage of the second control node in response to an output of the sensing unit.

The present invention senses the threshold voltage of the pull-down transistor in the output of the gate driving circuit and varies the voltage applied to the Qb node or the gate node of the pull-down transistor according to the sensed threshold voltage, thereby reducing the stress of the pull-down transistor, This can improve circuit life.

In the present invention, since the initial voltage applied to the Qb node is low and the gate-source voltage of the pull-down transistor is low, an increase in the threshold voltage of the pull-down transistor may be delayed.

The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

1 is a diagram showing a gate driving circuit according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating the configuration of a sensing unit shown in FIG. 1 .
FIG. 3 is a waveform diagram showing input/output signals of the sensing unit shown in FIG. 2 and voltages of nodes.
4 is a view showing another configuration of the sensing unit shown in FIG. 1;
FIG. 5 is a waveform diagram showing input/output signals of the sensing unit shown in FIG. 4 and voltages of nodes.
FIG. 6 is a view showing another configuration of the sensing unit shown in FIG. 1;
FIG. 7 is a waveform diagram showing input/output signals of the sensing unit shown in FIG. 6 and voltages of nodes.
8A and 8B are diagrams for explaining changes in the threshold voltage of the pull-down transistor shown in FIG. 1 .
FIG. 9 is a diagram showing the configuration of the compensation unit shown in FIG. 1;
10 is a diagram showing a gate driving circuit according to a second embodiment of the present invention.
11 is a waveform diagram showing input/output signals of a gate driving circuit and voltages of nodes.
12 is a diagram showing a gate driving circuit according to a third embodiment of the present invention.
13 is a waveform diagram showing input/output signals of a gate driving circuit and voltages of nodes.
14 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.
FIG. 15 is a view showing a cross-sectional structure of the display panel shown in FIG. 14 .
16A and 16B are diagrams for explaining the position of a gate driver according to an embodiment.
17 is a diagram showing an actually implemented circuit of a gate driver according to an embodiment.
18A to 18B are waveform diagrams showing input/output signals of the gate driver shown in FIG. 17 and voltages of nodes.
19 is a diagram showing a result of sensing a threshold voltage of a pull-down transistor.

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various forms different from each other, only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention pertains. It is provided to completely inform the person who has the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative, so the present invention is not limited to the details shown. Like reference numbers designate like elements throughout the specification. In addition, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted.

When 'includes', 'has', 'consists of', etc. mentioned in this specification is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, when the positional relationship of two parts is described as 'on ~', 'upon ~', '~ below', 'next to', etc., 'right' Or, unless 'directly' is used, one or more other parts may be located between the two parts.

In the description of the embodiment, first, second, etc. are used to describe various constituent elements, but these constituent elements are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may also be the second component within the technical spirit of the present invention.

Like reference numbers designate like elements throughout the specification.

Features of various embodiments can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment can be implemented independently of each other or together in an association relationship.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram showing a gate driving circuit according to a first embodiment of the present invention.

Referring to FIG. 1 , the gate driving circuit according to the first embodiment of the present invention includes a first control node (hereinafter referred to as a "Q node") pulling up an output voltage and a second control node (hereinafter referred to as a "Q node") pulling down an output voltage. , referred to as a "Qb node"), a control unit 120-1, an output unit 120-2, a sensing unit 120-3, and a compensation unit 120-4.

The control unit 120-1 may serve to charge and discharge the first control node and the second control node.

The output unit 120-2 may output a gate signal in response to the charging voltages of the first control node and the second control node. The output unit 120-2 may include a pull-up transistor and a pull-down transistor. The pull-up transistor may output a gate high voltage to an output node in response to the charging voltage of the first control node, and the pull-down transistor may output a gate low voltage to the output node in response to the charging voltage of the second control node.

The sensing unit 120-3 may sense the threshold voltage of the pull-down transistor.

The compensator 120-4 may change the charging voltage of the second control node in response to the output of the sensing unit. At this time, in the embodiment, the high potential voltage line for applying the high potential voltage to the first control node and the second control node is separated, and the first high potential voltage is connected to the first control node through the first high potential voltage line (GVDD_1). and apply the second high potential voltage to the second control node through the second high potential voltage line GVDD_2. Accordingly, the compensator 120 - 4 may change the charging voltage of the second control node by changing the magnitude of the second high potential voltage applied through the second high potential voltage line GVDD_2 in response to the output of the sensing unit. .

FIG. 2 is a diagram showing the configuration of the sensing unit shown in FIG. 1 , and FIG. 3 is a waveform diagram showing input/output signals of the sensing unit shown in FIG. 2 and voltages of nodes.

Referring to FIGS. 2 and 3 , the sensing unit 120-3 according to the embodiment includes a first sensing unit 120-3a including a first switch element M01 and a second switch element M02. 2 sensing units 120-3b may be included.

The first switch element M01 may be turned on when the gate signal is higher than the gate-on voltage and apply the high-potential voltage to the second control node. The first switch element M01 includes a gate to which a gate signal is applied, a first node connected to a high potential voltage line to which a high potential voltage is applied, and a second electrode connected to a second control node.

The second switch element M02 may be turned on when the gate signal is higher than the gate-on voltage, sense the threshold voltage of the pull-down transistor, and transfer the sensed voltage to the sensing line. The second switch element M02 includes a gate to which a gate signal is applied, a first electrode connected to a sensing line, and a second electrode connected to an output node.

As shown in FIG. 3 , while the high voltage of the first gate signal is maintained, the first switch element M01 and the second switch element M02 are turned on to sense the threshold voltage of the pull-down transistor.

FIG. 4 is a diagram showing another configuration of the sensing unit shown in FIG. 1 , and FIG. 5 is a waveform diagram showing input/output signals of the sensing unit shown in FIG. 4 and voltages of nodes.

4 to 5, the sensing unit 120-3 according to the embodiment includes a first sensing unit 120-3a including a first switch element M01, a capacitor C, and a second switch element ( M02) may include a second sensing unit 120-3b.

The first switch element M01 may be turned on when the gate signal is higher than the gate-on voltage and apply the high-potential voltage to the second control node. The first switch element M01 includes a gate to which a gate signal is applied, a first node connected to a high potential voltage line, and a second electrode connected to a second control node.

The second switch element M02 may be turned on when the gate signal is higher than the gate-on voltage, sense the threshold voltage of the pull-down transistor, and transfer the sensed voltage to the sensing line. The second switch element M02 includes a gate to which a gate signal is applied, a first electrode connected to a sensing line, and a second electrode connected to an output node.

The capacitor C is connected between the gate electrode and the source node of the first switch element M01. Capacitor C may serve to form a bootstrapping voltage at the gate node.

As shown in FIG. 5 , while the high voltage of the first gate signal is maintained, the first switch element M01 and the second switch element M02 are turned on to sense the threshold voltage of the pull-down transistor. At this time, the transfer capability may be improved by bootstrapping through the coupling of the capacitor C.

FIG. 6 is a diagram showing another configuration of the sensing unit shown in FIG. 1 , and FIG. 7 is a waveform diagram showing input/output signals of the sensing unit shown in FIG. 6 and voltages of nodes.

6 and 7, the sensing unit 120-3 according to the embodiment includes a first sensing unit 120-3 including a first switch element M01, a second switch element M02, and a capacitor C. 3a), and a second sensing unit 120-3b made of a third switch element M03.

The first switch element M01 may be turned on when the first gate signal is a high voltage equal to or higher than the gate-on voltage, and may apply a high potential voltage to the first node. The first switch element M01 includes a gate to which a first gate signal is applied, a first electrode connected to a high potential voltage line to which a high potential voltage is applied, and a second electrode connected to the first node.

The second switch element M02 is turned on when the voltage of the first node is higher than the gate-on voltage to apply the high potential voltage to the second control node. The second switch element M02 includes a gate connected to a first node, a first node connected to a high potential voltage line to which a high potential voltage is applied, and a second electrode connected to a second control node.

The third switch element M03 may be turned on when the second gate signal is a high voltage equal to or greater than the gate-on voltage, sense the threshold voltage of the pull-down transistor, and transfer the sensed threshold voltage to the sensing line. The third switch element M03 includes a gate to which the second gate signal is applied, a first electrode connected to the sensing line, and a second electrode connected to the output node.

The capacitor C is connected between the signal line to which the second control signal is applied and the first node. Capacitor C may serve to form a bootstrapping voltage at the first node.

As shown in FIG. 7 , the threshold voltage sensing period may include a first period in which the high voltage of the first gate signal is maintained and a second period in which the high voltage of the second gate signal is maintained. In the first period, the first switch M01 and the second switch M02 may be turned on, and in the second period, the second switch M02 and the third switch M03 may be turned on. In this case, sensing capability, that is, transmission capability may be improved by bootstrapping through coupling of the capacitor C.

8A and 8B are diagrams for explaining changes in the threshold voltage of the pull-down transistor shown in FIG. 1 .

Referring to FIG. 8A , in the comparative example, when the high potential voltage applied to the second control node is fixed, the initial high potential voltage is applied low and the initial gate-to-source voltage Vgs of the pull-down transistor is formed high to form a threshold voltage. An increase in (Vth) may occur.

At this time, the gate-to-source voltage (Vgs) may be defined as the following [Equation 1].

[Equation 1]

Vgs = Vg - Vs - Vth = GVDD - GVSS - Vth

Here, Vg is the voltage of the gate node, Vs is the voltage of the source node, Vth is the threshold voltage, GVDD is the high potential voltage, and GVSS is the low potential voltage.

The amount of change (ΔVth) of the threshold voltage can be expressed as in [Equation 2] below.

[Equation 2]

Here, t is time, τ is a time constant, β is a constant expressing dispersion, E _A is activation energy, v is frequency, k is Boltzmann constant, and T is temperature.

Referring to FIG. 8B , in the embodiment, when the high potential voltage applied to the second control node is varied, the initial high potential voltage is applied low and increased through sensing of the threshold voltage. An initial gate-to-source voltage (Vgs) of the pull-down transistor is formed low because an initial high potential voltage is applied low, and thus an increase in the threshold voltage (Vth) may be delayed.

Since the high potential voltage gradually rises through the sensing of the threshold voltage, the rise of the threshold voltage is delayed accordingly, and thus the lifetime of the transistor may also increase.

FIG. 9 is a diagram showing the configuration of the compensation unit shown in FIG. 1;

Referring to FIG. 9 , the compensation unit according to the embodiment may include an analog-to-digital converter (ADC) 120-4a and a compensation voltage generating circuit 120-4b.

The analog-to-digital converter 120-4a may convert the voltage sensed through the sensing line, that is, the threshold voltage of the pull-down transistor into digital data.

The compensation voltage generating circuit 120-4b may change the level of the high potential voltage based on the converted digital data and the look-up table (LUT) 120-4c and apply it to the Qb node. At this time, the compensation voltage generating circuit 120-4b may change the high potential voltage in proportion to the sensed threshold voltage.

For example, the compensating voltage generating circuit 120-4b determines the size of the high potential voltage based on the converted digital data and the lookup table, and sends an instruction signal for instructing to change to the high potential voltage of the determined size using PMIC (Power Management). Integrated Circuit) to change the size of the high potential voltage to be applied to the Qb node through the PMIC.

10 is a diagram showing a gate driving circuit according to a second embodiment of the present invention, and FIG. 11 is a waveform diagram showing input/output signals and voltages of nodes of the gate driving circuit.

10 and 11, the gate driving circuit according to the second embodiment includes a control unit 120-1, an output unit 120-2, a first sensing unit 120a and a second sensing unit 120b. It may include a sensing unit 120-3 and a compensating unit 120-4.

The control unit 120-1 may serve to charge and discharge the first control node and the second control node. The controller 120-1 includes a first transistor T1, a third transistor T3, a 3N transistor T3N, a fourth transistor T4, a 4N transistor T4N, a fifth transistor T5, a th A 5B transistor (T5Q) may be included.

The first transistor T1 may supply the gate-on voltage VGH to the Q node in response to the start pulse VST received through the VST terminal. The first transistor T1 includes a gate electrode connected to the VST terminal, a first electrode connected to a high potential voltage line to which a high potential voltage is applied, and a second electrode connected to the Q node.

The third transistor T3 is turned on in response to the carry signal VNEXT of the next signal transfer unit received through the VNEXT terminal to discharge the Q node. The third transistor T3 includes a gate electrode connected to the VNEXT terminal, a first electrode connected to the Q node, and a second electrode connected to a low potential voltage line to which a low potential voltage is applied.

The 3N transistor T3N may discharge the Q node in response to the voltage of the QB node. The 3N transistor T3N includes a gate electrode connected to the QB node, a first electrode connected to the Q node, and a second electrode connected to a low potential voltage line to which a low potential voltage is applied.

The fourth transistor T4 may be turned on by the high potential voltage and transfer the high potential voltage applied to the high potential voltage line to the QB node. The fourth transistor T4 includes a gate electrode and a first electrode commonly connected to the high potential voltage line, and a second electrode connected to the QB node.

The 4N transistor T4N is turned on in response to the carry signal VNEXT of the next signal transfer unit received through the VNEXT terminal, and supplies a high potential voltage to the QB node to charge the QB node to the gate-on voltage VGH or higher. let it The 4N transistor T4N includes a gate electrode connected to the VNEXT terminal, a first electrode connected to the high potential voltage line, and a second electrode connected to the QB node.

The fifth transistor T5 discharges the QB node to a low potential voltage by connecting the QB node to the low potential voltage line in response to the start pulse VST received through the VST terminal. The fifth transistor T5 includes a gate electrode connected to the VST terminal, a first electrode connected to the QB node, and a second electrode connected to the low potential voltage line.

The fifth Q transistor T5Q is turned on when the voltage of the Q node Q is higher than the gate-on voltage VGH, and connects the QB node to the low potential voltage line to discharge the QB node to the low potential voltage. The fifth Q transistor T5Q includes a gate electrode connected to the Q node Q, a first electrode connected to the QB node, and a second electrode connected to the low potential voltage line.

The output unit 120-2 may output a gate signal in response to the charging voltages of the first control node and the second control node. The output unit 120 - 2 may include buffer transistors T6 and T7 outputting gate signals. The buffer transistors T6 and T7 are divided into a pull-up transistor T6 that turns on based on the potential of the Q node Q and a pull-down transistor T7 that turns on based on the potential of the QB node QB. It can be. The pull-up transistor T6 includes a gate electrode connected to the Q node Q, a first electrode connected to the clock signal line CLK to which a clock signal is applied, and a second electrode connected to the output terminal GOUT(n). do. The pull-down transistor T7 includes a gate electrode connected to the QB node QB, a first electrode connected to the output terminal GOUT(n), and a second electrode connected to the low potential voltage line GVSS0.

The sensing unit 120-3 may sense the threshold voltage of the pull-down transistor. The sensing unit 120-3 includes a first sensing unit 121-3a including a first switch element M01, a second switch element M02, and a capacitor C, and a third switch element M03. 2 sensing units 121-3b may be included.

The first switch element M01 may be turned on when the first gate signal is a high voltage equal to or higher than the gate-on voltage, and may apply a high potential voltage to the first node. The first switch element M01 includes a gate to which a first gate signal is applied, a first electrode connected to a high potential voltage line to which a high potential voltage is applied, and a second electrode connected to the first node.

The second switch element M02 is turned on when the voltage of the first node is higher than the gate-on voltage to apply the high potential voltage to the second control node. The second switch element M02 includes a gate connected to a first node, a first node connected to a high potential voltage line to which a high potential voltage is applied, and a second electrode connected to a second control node.

The third switch element M03 may be turned on when the second control signal is a high voltage equal to or higher than the gate-on voltage, sense the threshold voltage of the pull-down transistor, and transfer the sensed threshold voltage to the sensing line. The third switch element M03 includes a gate to which the second control signal is applied, a first electrode connected to the sensing line, and a second electrode connected to the output node.

The capacitor C is connected between the signal line to which the second control signal is applied and the first node. Capacitor C may serve to form a bootstrapping voltage at the first node.

The compensator 120-4 may change the charging voltage of the second control node in response to the output of the sensing unit. The compensator 120 - 4 may change the second high potential voltage applied to the second high potential voltage line GVDD_2 connected to the second control node in response to the output of the sensing unit.

The compensator 120 - 4 may change the second high potential voltage applied to the second high potential voltage line GVDD_2 in proportion to the threshold voltage of the pull-down transistor T7 sensed by the sensing unit.

12 is a diagram showing a gate driving circuit according to a third embodiment of the present invention, and FIG. 13 is a waveform diagram showing input/output signals of the gate driving circuit and voltages of nodes.

12 to 1, the gate driving circuit according to the third embodiment includes a controller 120-1, an output unit 120-2, a first sensing unit 120a, and a second sensing unit 120b. It may include a sensing unit 120-3 and a compensating unit 120-4.

The control unit 120-1 may serve to charge and discharge the first control node. The controller 120-1 may include a first transistor T1, a third transistor T3, a fourth transistor T4, and a fifth transistor T5.

The first transistor T1 may supply the gate-on voltage VGH to the Q node in response to the start pulse VST(N−2) received through the VST terminal. The first transistor T1 includes a gate electrode and a first electrode commonly connected to the VST terminal, and a second electrode connected to the Q node. Vout(N-2) shown in FIG. 13 corresponds to the start pulse VST(N-2).

The third transistor T3 may be turned on in response to the carry signal VNEXT(N+2) of the next signal transfer unit received through the VNEXT terminal to discharge the Q node. The third transistor T3 may discharge the VNEXT terminal. and a gate electrode connected to a Q node, a first electrode connected to a Q node, and a second electrode connected to a low potential voltage line to which a low potential voltage is applied Vout(N+2) shown in FIG. 13 is a start pulse ( VNEXT(N+2)).

The fourth transistor T4 may discharge the Q node in response to the reset signal Vreset received through the VRESET terminal. The fourth transistor T4 includes a gate electrode connected to the VRESET terminal, a first electrode connected to the Q node, and a second electrode connected to the low potential voltage line.

The fifth transistor T5 is turned on in response to the clock signal CLK(N−1) of the previous signal transfer unit and connects the Q node to the output terminal GOUT(n−1) of the previous signal transfer unit. The fifth transistor T5 includes a gate electrode to which the clock signal of the previous signal transfer unit is applied, a first electrode connected to the Q node, and a second electrode connected to the output terminal of the previous signal transfer unit.

The output unit 120 - 2 may output a gate signal to the output terminal GOUT(n) in response to the charging voltages of the first control node and the second control node. The output unit 120 - 2 may include buffer transistors T6 and T7 outputting gate signals. Buffer transistors T6 and T7 are a pull-up transistor T6 that turns on based on the potential of the Q node Q and a clock signal (CLK(N+2) that turns on based on the potential of the previous cycle). It may be divided into a pull-down transistor T7.The pull-up transistor T6 includes a gate electrode connected to the Q node Q, a first electrode connected to the clock signal line CLK to which a clock signal is applied, and an output terminal GOUT( The pull-down transistor T7 includes a gate electrode to which the clock signal CLK(N+2) of the previous period is applied and a first electrode connected to the output terminal GOUT(n). , and a second electrode connected to the low potential voltage line GVSS0.

The sensing unit 120-3 may sense the threshold voltage of the pull-down transistor. The sensing unit 120-3 includes a first sensing unit 121-3a including a first switch element M01, a second switch element M02, and a capacitor C, and a third switch element M03. 2 sensing units 121-3b may be included.

The first switch element M01 may be turned on when the first gate signal is a high voltage equal to or higher than the gate-on voltage, and may apply a high potential voltage to the first node. The first switch element M01 includes a gate to which a first gate signal is applied, a first electrode connected to a high potential voltage line to which a high potential voltage is applied, and a second electrode connected to the first node.

The second switch element M02 may be turned on when the voltage of the first node is higher than the gate-on voltage to apply the high-potential voltage to the gate node of the pull-down transistor. The second switch element M02 includes a gate connected to the first node, a first node connected to a high potential voltage line to which a high potential voltage is applied, and a second electrode connected to the gate node of the pull-down transistor.

The third switch element M03 may be turned on when the second gate signal is a high voltage equal to or greater than the gate-on voltage, sense the threshold voltage of the pull-down transistor, and transfer the sensed threshold voltage to the sensing line. The third switch element M03 includes a gate to which the second gate signal is applied, a first electrode connected to the sensing line, and a second electrode connected to the output node.

The capacitor C is connected between the signal line to which the second control signal is applied and the first node. Capacitor C may serve to form a bootstrapping voltage at the first node.

The compensator 120-4 may change the voltage of the gate node of the pull-down transistor in response to the output of the sensing unit. The compensator 120-4 may change the voltage of the second clock signal applied to the second clock signal line connected to the gate node in response to the output of the sensing unit.

The compensator 120-4 may change the voltage of the second clock signal applied to the second clock signal line in proportion to the threshold voltage of the pull-down transistor T7 sensed by the sensing unit.

14 is a block diagram showing a display device according to an exemplary embodiment, and FIG. 15 is a view showing a cross-sectional structure of the display panel shown in FIG. 14 .

Referring to FIG. 11 , a display device according to an exemplary embodiment of the present invention includes a display panel 100, a display panel driving circuit for writing pixel data to pixels of the display panel 100, and pixels and a display. It includes a power supply unit 140 that generates power necessary for driving the panel driving circuit.

The display panel 100 includes a pixel array AA displaying an input image. The pixel array AA includes a plurality of data lines 102, a plurality of gate lines 103 crossing the data lines 102, and pixels arranged in a matrix form.

The pixel array AA includes a plurality of pixel lines L1 to Ln. Each of the pixel lines L1 to Ln includes one line of pixels disposed along the line direction X in the pixel array AA of the display panel 100 . Pixels arranged on one pixel line share gate lines 103 . Sub-pixels arranged in the column direction (Y) along the data line direction share the same data line 102 . One horizontal period (1H) is a time obtained by dividing one frame period by the total number of pixel lines (L1 to Ln).

Touch sensors may be disposed on the display panel 100 . A touch input may be sensed using separate touch sensors or sensed through pixels. The touch sensors are on-cell type or add-on type, and are arranged on the screen of the display panel or in-cell type touch sensors embedded in the pixel array (AA). can be implemented as

The display panel 100 may be implemented as a flexible display panel. The flexible display panel may be made of a plastic OLED panel. An organic thin film may be disposed on a back plate of the plastic OLED panel, and a pixel array AA may be formed on the organic thin film.

The back plate of the plastic OLED may be a polyethylene terephthalate (PET) substrate. An organic thin film is formed on the back plate. A pixel array AA and a touch sensor array may be formed on the organic thin film. The back plate blocks moisture permeation so that the pixel array AA is not exposed to humidity. The organic thin film may be a thin polyimide (PI) film substrate. A multi-layered buffer film may be formed on the organic thin film with an insulating material (not shown). Wires for supplying power or signals applied to the pixel array AA and the touch sensor array may be formed on the organic thin film.

Each of the pixels is composed of a red sub-pixel (hereinafter referred to as "R sub-pixel"), a green sub-pixel (hereinafter referred to as "G sub-pixel"), and a blue sub-pixel (hereinafter referred to as "B sub-pixel") for color implementation. can be divided Each of the pixels may further include a white sub-pixel. Each of the subpixels 101 includes a pixel circuit. The pixel circuit is connected to the data line 102 and the gate line 103.

Hereinafter, a pixel may be interpreted as having the same meaning as a sub-pixel.

Viewed from a cross-sectional view, the display panel 100 includes a circuit layer 12, a light emitting element layer 14, and an encapsulation layer 16 stacked on a substrate 10 as shown in FIG. can include

The circuit layer 12 includes pixel circuits connected to wirings such as data lines, gate lines, and power lines, a gate driver (GIP) connected to gate lines, a demultiplexer array 112, and a circuit for auto probe inspection omitted from the drawings. etc. may be included. The wiring and circuit elements of the circuit layer 12 may include a plurality of insulating layers, two or more metal layers separated with an insulating layer interposed therebetween, and an active layer including a semiconductor material. All transistors formed on the circuit layer 12 may be implemented as oxide TFTs including n-channel oxide semiconductors.

The light emitting element layer 14 may include a light emitting element EL driven by a pixel circuit. The light emitting element EL may include a red (R) light emitting element, a green (G) light emitting element, and a blue (B) light emitting element. The light emitting element layer 14 may include a white light emitting element and a color filter. The light emitting elements EL of the light emitting element layer 14 may be covered by a protective layer including an organic layer and a protective layer.

An encapsulation layer 16 covers the light emitting element layer 14 so as to seal the circuit layer 12 and the light emitting element layer 14 . The encapsulation layer 16 may have a multi-insulation layer structure in which organic layers and inorganic layers are alternately stacked. The inorganic film blocks the penetration of moisture or oxygen. The organic layer flattens the surface of the inorganic layer. When the organic layer and the inorganic layer are stacked in multiple layers, the movement path of moisture or oxygen is longer than that of a single layer, so that penetration of moisture and oxygen affecting the light emitting element layer 14 can be effectively blocked.

A touch sensor layer formed on the encapsulation layer 16 may be disposed. The touch sensor layer may include capacitive touch sensors that sense a touch input based on a change in capacitance before and after the touch input. The touch sensor layer may include metal wiring patterns and insulating layers forming capacitance of the touch sensors. Capacitance of the touch sensor may be formed between the metal wiring patterns. A polarizer may be disposed on the touch sensor layer. The polarizer may improve visibility and contrast ratio by converting polarization of external light reflected by the touch sensor layer and the metal of the circuit layer 12 . The polarizing plate may be implemented as a polarizing plate in which a linear polarizing plate and a phase retardation film are bonded together or a circular polarizing plate. A cover glass may be adhered on the polarizing plate.

The display panel 100 may further include a touch sensor layer and a color filter layer stacked on the encapsulation layer 16 . The color filter layer may include red, green, and blue color filters and a black matrix pattern. The color filter layer may absorb some wavelengths of light reflected from the circuit layer and the touch sensor layer to serve as a polarizer and increase color purity. In this embodiment, the light transmittance of the display panel PNL can be improved and the thickness and flexibility of the display panel PNL can be improved by applying the color filter layer 20 having higher light transmittance than that of the polarizer to the display panel. A cover glass may be adhered on the color filter layer.

The power supply unit 140 uses a DC-DC converter to generate DC power necessary for driving the pixel array AA of the display panel 100 and the display panel driving circuit. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, and the like. The power supply unit 140 adjusts a DC input voltage from a host system (not shown) to generate a gamma reference voltage (VGMA) and gate-on voltages (VGH, VEH). DC voltages such as gate-off voltages (VGL and VEL), pixel driving voltages (EVDD), and pixel low potential power supply voltages (EVSS) may be generated. The gamma reference voltage VGMA is supplied to the data driver 110 . Gate-on voltages VGH and VEH and gate-off voltages VGL and VEL are supplied to the gate driver 120 . The pixel driving voltage EVDD and the pixel low potential power supply voltage EVSS are commonly supplied to the pixels.

The display panel driving circuit writes pixel data (digital data) of an input image into pixels of the display panel 100 under the control of a timing controller (TCON) 130 .

The display panel driving circuit includes a data driver 110 and a gate driver 120 .

A demultiplexer (DEMUX) 112 may be disposed between the data driver 110 and the data lines 102 . The demultiplexer 112 sequentially connects one channel of the data driver 110 to a plurality of data lines 102 to time-division distribute the data voltage output from one channel of the data driver 110 to the data lines 102. By doing so, the number of channels of the data driver 110 can be reduced. The demultiplexer array 112 may be omitted. In this case, the output buffers AMP of the data driver 110 are directly connected to the data lines 102 .

The display panel driving circuit may further include a touch sensor driver for driving the touch sensors. The touch sensor driver is omitted in FIG. 1 . In a mobile device, the timing controller 130, the power supply unit 140, the data driver 110, and the like may be integrated into one drive IC (Integrated Circuit).

The data driver 110 converts pixel data of an input image received from the timing controller 130 in each frame period into a gamma compensation voltage using a digital to analog converter (DAC) to generate a data voltage Vdata. The gamma reference voltage VGMA is divided for each gray level through a voltage divider circuit. The gamma compensation voltage divided from the gamma reference voltage VGMA is provided to the DAC of the data driver 110 . The data voltage Vdata is output from each of the channels of the data driver 110 through the output buffer AMP.

The output buffer AMP included in one channel of the data driver 110 may be connected to neighboring data lines 102 through the demultiplexer array 112 . The demultiplexer array 112 may be directly formed on the substrate of the display panel 100 or integrated into one drive IC together with the data driver 110 .

The gate driver 120 may be implemented as a gate in panel (GIP) circuit formed directly on the bezel area (Bezel, BZ) of the display panel 100 together with the TFT array of the pixel array AA. The gate driver 120 sequentially outputs gate signals to the gate lines 103 under the control of the timing controller 130 . The gate driver 120 may sequentially supply the gate signals to the gate lines 103 by shifting the gate signals using a shift register.

The gate signal may include a scan signal for selecting pixels of a line on which data is to be written in synchronization with the data voltage, and an EM signal for defining emission times of pixels charged with the data voltage.

The gate driver 120 may include a scan driver 121 , an EM driver 122 , and an initialization driver 123 .

The scan driver 121 outputs a scan signal SCAN in response to a start pulse from the timing controller 130 and a shift clock, and shifts the scan signal SCAN according to the shift clock timing. do. The EM driver 122 outputs an EM signal EM in response to a start pulse and a shift clock from the timing controller 130 and sequentially shifts the EM signal EM according to the shift clock. The initialization driver 123 outputs an initialization signal INIT in response to a start pulse from the timing controller 130 and a shift clock, and shifts the initialization signal INIT according to the shift clock timing. do. Accordingly, the scan signal SCAN, the EM signal EM, and the initialization signal INIT are sequentially supplied to the gate lines 103 of the pixel lines L1 to Ln. In the case of a model without a bezel, at least some of the transistors constituting the gate driver 120 and clock wires may be distributed in the pixel array AA.

The timing controller 130 receives digital video data (DATA) of an input image and a timing signal synchronized therewith from a host system (not shown). The timing signal includes a vertical sync signal (Vsync), a horizontal sync signal (Hsync), a main clock (CLK), and a data enable signal (Data Enable, DE). Since the vertical period and the horizontal period can be known by counting the data enable signal DE, the vertical sync signal Vsync and the horizontal sync signal Hsync can be omitted. The data enable signal DE has a period of one horizontal period (1H).

The host system may be any one of a TV (Television) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a vehicle system, and a mobile device system.

The timing controller 130 multiplies the input frame frequency by i to control the operation timing of the display panel driving circuit with the frame frequency of the input frame frequency Хi (i is a positive integer greater than 0) Hz. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) method and 50 Hz in the Phase-Alternating Line (PAL) method.

The timing controller 130 controls the data timing control signal for controlling the operation timing of the data driver 110 and the operation timing of the demultiplexer array 112 based on the timing signals Vsync, Hsync, and DE received from the host system. MUX signals MUX1 and MUX2 for processing and gate timing control signals for controlling the operation timing of the gate driver 120 are generated.

The voltage level of the gate timing control signal output from the timing controller 130 is converted into gate-on voltages (VGH, VEH) and gate-off voltages (VGL, VEL) through a level shifter (not shown) to form a gate driver ( 120) can be supplied. That is, the level shifter converts the low level voltage of the gate timing control signal into the gate low voltage (VGL, VEL) and converts the high level voltage of the gate timing control signal into the gate high voltage (VGH). , VEH). The gate timing control signal includes a start pulse and a shift clock.

16A to 16B are diagrams for explaining the location of a gate driver according to an embodiment, FIG. 17 is a diagram showing an actually implemented circuit of a gate driver according to an embodiment, and FIGS. 18A to 18B are shown in FIG. 17 19 is a waveform diagram showing input/output signals of a gate driver and voltages of nodes, and FIG. 19 is a diagram showing a result of sensing a threshold voltage of a pull-down transistor. Here, a case in which the gate driver is implemented as a scan driver will be described as an example.

Referring to FIGS. 16A and 16B , the scan driver according to the exemplary embodiment may be implemented in a structure in which shift registers are disposed in left and right non-display areas of a display panel. The shift register may include a plurality of signal transfer units ST and a plurality of dummy signal transfer units D_ST, respectively.

At this time, each of the plurality of signal transmission parts ST is connected to the gate lines. Each of the plurality of dummy signal transfer units D_ST may be disposed at uppermost portions A and B and lowermost portions C and D of both sides of the display panel PNL. Here, a case in which four dummy signal transfer units D_ST are formed is shown.

The plurality of dummy signal transfer units disposed at the top and bottom of the display panel may be implemented to include the sensing unit and the compensating unit shown in FIG. 1 . The reason why only the dummy signal transfer unit includes the sensing unit and the compensating unit is to minimize an increase in the bezel of the display panel.

17 and 18a to 18b, the dummy SCAN GIP according to the embodiment of the present invention includes a controller 121-1, an output unit 121-2, a first sensing unit 120a, and a second sensing unit. It may be implemented to include a sensing unit 121-3 and a compensating unit 121-4 composed of (120b).

The control unit 121-1 may serve to charge and discharge the first control node and the second control node. The controller 121-1 includes a first transistor T1, a 1A transistor, a third transistor T3, a 3A transistor T3A, a 3q transistor T3q, a 3n transistor T3n, a 3nA transistor ( T3nA), 3nB transistor T3nB, 3nC transistor T3nC, 4th transistor T4, 41st transistor T41, 4qth transistor T4q, 5th transistor T5, 5qth transistor T5q can include

The first transistor T1 is turned on by the N-2th carry signal applied through the N-2th carry signal line C(n-2), and based on the N-2th carry signal, the Q node ( Q) is charged. The first transistor T1 includes a gate electrode and a first electrode commonly connected to the N−2 th carry signal line C(n−2), and a second electrode connected to the Q node Q.

The 1A-th transistor is turned on by the N-2 th carry signal applied through the N-2 th carry signal line (C(n-2)) and connects the Q node Q based on the N-2 th carry signal. charge The 1A transistor T1A has a gate electrode connected to the N-2th carry signal line C(n-2), a first electrode connected to the second electrode of the first transistor T1, and a Q node ( A second electrode is connected to Q).

The third transistor T3 is turned on by the QB node QB and discharges the Q node Q with the third low potential voltage of the third low potential voltage line GVSS2 together with the 3A transistor T3A. . The third transistor T3 has a gate electrode connected to the QB node QB, a first electrode connected to the Q node Q, and a second electrode connected to the first electrode of the 3A transistor T3A.

The 3A transistor T3A is turned on by the QB node QB and discharges the Q node Q with the third low potential voltage of the third low potential voltage line GVSS2 together with the third transistor T3. . The gate electrode of the 3A transistor T3A is connected to the QB node QB, the first electrode is connected to the second electrode of the 3A transistor T3A, and the second electrode is connected to the third low potential voltage line GVSS2. do.

The 3n-th transistor T3n is turned on by the N+2-th carry signal applied through the N+2-th carry signal line C(n+2), and is turned on at the third low potential together with the 3nA transistor T3nA. The Q node Q is discharged with the third low potential voltage of the voltage line GVSS2. The 3nth transistor T3n has a gate electrode connected to the N+2th carry signal line C(n+2), a first electrode connected to the Q node Q, and a first electrode of the 3nA transistor T3nA. The second electrode is connected to

The 3nA transistor T3nA is turned on by the N+2 th carry signal applied through the N+2 th carry signal line C(n+2) and has a third low potential together with the 3n transistor T3n. The Q node Q is discharged with the third low potential voltage of the voltage line GVSS2. The 3nA transistor T3nA has a gate electrode connected to the N+2th carry signal line C(n+2), a first electrode connected to the second electrode of the 3nth transistor T3n, and a third low potential voltage. A second electrode is connected to the line GVSS2.

The 3qth transistor T3q is turned on by the Q node Q and transfers the high potential voltage of the first high potential voltage line GVDD_1 to the Qh node Qh. The 3q transistor T3q has a gate electrode connected to the Q node Q, a first electrode connected to the first high potential voltage line GVDD_1, and a second electrode connected to the Qh node Qh.

The 3 nB transistor T3 nB is turned on by the start pulse received through the VST terminal, and is connected to the third low potential voltage of the third low potential voltage line GVSS2 together with the 3 nC transistor T3 nC to the Q node (Q ) and discharging the Qh node (Qh). The gate electrode of the 3nB transistor T3nB is connected to the VST terminal, the first electrode is connected to the Q node Q, and the second electrode is connected to the first electrode of the 3nC transistor T3nC.

The 3 nC transistor T3 nC is turned on by the start pulse received through the VST terminal, and together with the 3 nB transistor T3 nB is applied to the third low potential voltage of the third low potential voltage line GVSS2 at the Q node (Q ) and discharging the Qh node (Qh). The gate electrode of the 3nC transistor T3nC is connected to the VST terminal, the first electrode is connected to the second electrode of the 3nB transistor T3nB, and the second electrode is connected to the third low potential voltage line GVSS2. .

The fourth transistor T4 is turned on by the second high potential voltage transmitted through the 41st transistor T41 and is applied to the second high potential voltage line GVDD_2 to the QB node (QB ) is charged. The first capacitor Ca serves to form a bootstrapping voltage at the gate node of the fourth transistor T4. In the fourth transistor T4, a gate electrode is connected to one end of the first capacitor Ca and the second electrode of the forty-first transistor T41, and a first electrode is connected to the second high potential voltage line GVDD_2. A second electrode is connected to the other end of the capacitor Ca and the QB node QB.

The forty-first transistor T41 is turned on by the second high potential voltage and transfers the second high potential voltage applied to the second high potential voltage line GVDD_2 to the gate node of the fourth transistor T4. The forty-first transistor T41 has a gate and a first electrode connected to the high potential voltage line GVDD, and a second electrode connected to the gate electrode of the fourth transistor T4 and the first electrode of the 4q transistor T4q. .

The 4q transistor T4q is turned on when the voltage of the QB node is higher than the gate-on voltage VGH, and connects the gate node of the 4th transistor T4 to the low-potential voltage line GVSS1, thereby connecting the 4th transistor T4 to the low potential voltage line GVSS1. The gate node of (T4) is discharged to a low potential voltage. The gate electrode of the 4qth transistor T4q is connected to the QB node, the first electrode is connected to the gate electrode of the fourth transistor T4 and the second electrode of the forty-first transistor T41, and the low potential voltage line GVSS1 ) to which the second electrode is connected.

The fifth transistor T5 is turned on by the N−2 th carry signal applied through the N−2 th carry signal line C(n−2) and connects the QB node to the low potential voltage line GVSS2. to discharge the QB node to a low potential voltage. The fifth transistor T5 includes a gate electrode connected to the N−2 th carry signal line C(n−2), a first electrode connected to the QB node, and a second electrode connected to the low potential voltage line. .

The 5qth transistor T5q is turned on when the voltage of the Q node Q is higher than the gate-on voltage VGH, and connects the QB node to the low potential voltage line to discharge the QB node to the low potential voltage. The 5qth transistor T5q includes a gate electrode connected to the Q node Q, a first electrode connected to the QB node, and a second electrode connected to the low potential voltage line GVSS2.

The output unit 121-2 may output a gate signal in response to the charging voltages of the first control node and the second control node. The output unit 121-2 includes first buffer transistors T6cr and T7cr for outputting a carry signal, second buffer transistors T6sc and T7sc for outputting a scan signal, and third buffer transistors T6se and T7se for outputting a scan signal. can include

The first buffer transistors T6cr and T7cr include a first pull-up transistor T6cr that is turned on based on the potential of the Q node Q and a first pull-down transistor that is turned on based on the potential of the QB node QB. It can be divided into a transistor T7cr. The first pull-up transistor T6cr has a gate electrode connected to the Q node Q, a first electrode connected to the clock signal line SC_CRCLK, and a second electrode connected to the output terminal Carry(n). The gate electrode of the first pull-down transistor T7cr is connected to the QB node QB, the first electrode is connected to the output terminal Carry(n), and the second electrode is connected to the low potential voltage line GVSS2.

The second buffer transistors T6sc and T7sc include a second pull-up transistor T6sc that is turned on based on the potential of the Q node Q and a second pull-down transistor that is turned on based on the potential of the QB node QB. It can be classified as a transistor T7sc. The second pull-up transistor T6sc has a gate connected to the Q node Q and one end of the second capacitor Cb, a first electrode connected to the clock signal line SCCLK to which a clock signal is applied, and a second capacitor Cb. The second electrode is connected to the other side of (Cb) and the output terminal (SCOUT(n)). The second pull-down transistor T7sc has a gate electrode connected to the QB node QB, a first electrode connected to the output terminal SCOUT(n) and the other terminal of the second capacitor Cb, and a low potential voltage line GVSS0. ) to which the second electrode is connected.

The third buffer transistors T6se and T7se include a third pull-up transistor T6se that is turned on based on the potential of the Q node Q and a third pull-down transistor that is turned on based on the potential of the QB node QB. It can be classified as a transistor T7se. The third pull-up transistor T6se has a gate electrode connected to the Q node Q, a first electrode connected to the clock signal line SECLK, and a second electrode connected to the output terminal SEOUT(n). The third pull-down transistor T7se has a gate electrode connected to the QB node QB, a first electrode connected to the output terminal SEOUT(n), and a second electrode connected to the low potential voltage line GVSS0.

The sensing unit 121-3 may sense the threshold voltage of the pull-down transistor. The sensing unit 120-3 includes a first sensing unit 121-3a including a first switch element M01, a second switch element M02, and a capacitor C, and a third switch element M03. 2 sensing units 121-3b may be included.

The first switch element M01 may be turned on when the first gate signal is a high voltage equal to or higher than the gate-on voltage, and may apply a high potential voltage to the first node. The first switch element M01 includes a gate electrode to which a first gate signal is applied, a first electrode connected to a high potential voltage line to which a high potential voltage is applied, and a second electrode connected to a first node.

The second switch element M02 is turned on when the voltage of the first node is higher than the gate-on voltage to apply the high potential voltage to the second control node. The second switch element M02 includes a gate connected to a first node, a first node connected to a high potential voltage line to which a high potential voltage is applied, and a second electrode connected to a second control node.

The third switch element M03 may be turned on when the second gate signal is a high voltage equal to or greater than the gate-on voltage, sense the threshold voltage of the pull-down transistor, and transfer the sensed threshold voltage to the sensing line. The third switch element M03 includes a gate to which the second gate signal is applied, a first electrode connected to the sensing line, and a second electrode connected to the output node.

The capacitor C is connected between the signal line to which the second control signal is applied and the first node. Capacitor C may serve to form a bootstrapping voltage at the first node.

The compensator 120-4 may change the charging voltage of the second control node in response to the output of the sensing unit. The compensator 120 - 4 may change the second high potential voltage applied to the second high potential voltage line GVDD_2 connected to the second control node in response to the output of the sensing unit.

The compensator 120 - 4 may change the second high potential voltage applied to the second high potential voltage line GVDD_2 in proportion to the threshold voltage of the pull-down transistor T7 sensed by the sensing unit.

Referring to FIG. 19 , it can be seen that the threshold voltage of the pull-down transistor is normally sensed by the sensing unit during the sensing period in the dummy signal transfer unit according to the embodiment. It can be seen that even if the threshold voltage of the pull-down transistor is changed, it is normally sensed.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and may be variously modified and implemented without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed according to the claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: display panel
110: data driving unit
120: gate driver
130: timing controller
140: power supply

Claims (24)

a controller that charges and discharges a first control node that pulls up an output voltage and a second control node that pulls down the output voltage;
A pull-up transistor for applying a gate high voltage to an output node in response to the charging voltage of the first control node, and a pull-down transistor for applying a gate low voltage to the output node in response to the charging voltage of the second control node. output unit;
a sensing unit sensing a threshold voltage of the pull-down transistor; and
and a compensation unit configured to change a charging voltage of the second control node in response to an output of the sensing unit. According to claim 1,
The sensing unit,
a first sensing unit applying an initialization voltage to the second control node; and
And a second sensing unit for sensing a threshold voltage of the pull-down transistor. According to claim 2,
The first sensing unit,
A gate driving circuit including a first switch element having a gate electrode to which a first gate signal is applied, a first electrode connected to a high potential voltage line to which a high potential voltage is applied, and a second electrode connected to a second control node. . According to claim 2,
The first sensing unit,
a first switch element having a gate electrode to which a first gate signal is applied, a first electrode connected to a high potential voltage line to which a high potential voltage is applied, and a second electrode connected to a second control node; and
A gate driving circuit comprising a capacitor connected between a gate electrode and a second electrode of the first switch element. According to claim 3 or 4,
The second sensing unit,
A gate driving circuit including a second switch element having a gate electrode to which the first gate signal is applied, a first electrode connected between sensing nodes, and a second electrode connected to the output node. According to claim 2,
The first sensing unit,
a first switch element having a gate electrode to which a first gate signal is applied, a first electrode connected to a high potential voltage line to which the gate high voltage is applied, and a second electrode connected to a first node;
a second switch element having a gate electrode connected to the first node, a first electrode connected to the high potential voltage line, and a second electrode connected to a second control node; and
and a capacitor connected between the first node and a signal line to which the first gate signal is applied. According to claim 6,
The second sensing unit,
A gate driving circuit including a third switch element having a gate electrode to which a second gate signal is applied, a first electrode connected between sensing nodes, and a second electrode connected to the output node. According to claim 7,
The period for sensing the threshold voltage includes a first period in which the high voltage of the first gate signal is maintained and a second period in which the high voltage of the second gate signal is maintained;
In the first period, the first switch and the second switch are turned on,
In the second period, the second switch and the third switch are turned on, the gate driving circuit. According to claim 1,
a first high potential voltage line for applying a first high potential voltage to the first control node; and
And a second high potential voltage line for applying a second high potential voltage to the second control node. According to claim 9,
The compensation part,
A gate driving circuit that changes the second high potential voltage according to the threshold voltage sensed by the sensing unit. According to claim 10,
The compensation part,
A gate driving circuit that changes the second high potential voltage in proportion to the sensed threshold voltage. According to claim 1,
The second control node is a gate node of the pull-down transistor;
a first clock signal line for applying a first clock signal to the first control node; and
and a second clock signal line for applying a second clock signal to the second control node. According to claim 12,
The compensation part,
A gate driving circuit that changes the magnitude of the second clock signal according to the threshold voltage sensed by the sensing unit. According to claim 12,
The compensation part,
A gate driving circuit that changes a magnitude of the second clock signal in proportion to the sensed threshold voltage. a data driver outputting a data voltage;
a gate driver outputting a gate signal according to voltages of a first control node that pulls up an output voltage and a second control node that pulls down the output voltage; and
A plurality of pixel circuits receiving the data voltage and the gate signal and reproducing an input image;
The gate driver,
a controller for charging and discharging the first control node and the second control node;
a pull-up transistor for applying a gate signal of a gate high voltage to an output node in response to the charging voltage of the first control node; and applying a gate signal of a gate low voltage to the output node in response to the charging voltage of the second control node. an output unit including a pull-down transistor that
a sensing unit sensing a threshold voltage of the pull-down transistor; and
and a compensation unit configured to change a charging voltage of the second control node in response to an output of the sensing unit. According to claim 15,
The sensing unit,
a first sensing unit applying an initialization voltage to the second control node; and
and a second sensing unit configured to sense a threshold voltage of the pull-down transistor. According to claim 16,
The first sensing unit,
A display panel comprising: a first switch element having a gate electrode to which a gate signal is applied, a first electrode connected to a high potential voltage line to which a high potential voltage is applied, and a second electrode connected to a second control node. According to claim 16,
The first sensing unit,
a first switch element having a gate electrode to which a gate signal is applied, a first electrode connected to a high potential voltage line to which a high potential voltage is applied, and a second electrode connected to a second control node; and
and a capacitor connected between a gate electrode and a second electrode of the first switch element. The method of claim 17 or 18,
The second sensing unit,
and a second switch element having a gate electrode to which the first gate signal is applied, a first electrode connected between sensing nodes, and a second electrode connected to the output node. According to claim 16,
The first sensing unit,
a first switch element having a gate to which a first control signal is applied, a first electrode connected to a high potential voltage line to which a high potential voltage is applied, and a second electrode connected to the first node;
a second switch element having a gate connected to the first node, a first electrode connected to the high potential voltage line, and a second electrode connected to a second control node; and
and a capacitor connected between the first node and a signal line to which the first control signal is applied. According to claim 20,
The second sensing unit,
A display panel comprising: a third switch element having a gate to which a second control signal is applied, a first electrode connected between sensing nodes, and a second electrode connected to the output node. According to claim 15,
a first high potential voltage line for applying a first high potential voltage to the first control node; and
and a second high potential voltage line for applying a second high potential voltage to the second control node. According to claim 15,
The second control node is a gate node of the pull-down transistor;
a first clock signal line for applying a first clock signal to the first control node; and
and a second clock signal line for applying a second clock signal to the second control node. According to claim 15,
All transistors in the panel including the data driver, the gate driver, and the pixel circuit are implemented as oxide TFTs including an n-channel type oxide semiconductor.

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