KR20230041553A - Skew calibration circuit based on simple filiflop structure and time interleaved analog-digital converter - Google Patents

Abstract

A skew correction circuit based on a simple flip-flop structure and a time interleaved analog-to-digital converter using the same are disclosed. The skew correction circuit includes a reference clock unit receiving a reference clock as a clock and a channel clock unit receiving a clock of a channel as a clock. Here, when a polarity of timing skew is detected, one of the reference clock unit and the channel clock unit is reset by an output of another clock unit and the polarity of the timing skew is detected through outputs of the reference clock unit and the channel clock unit.

Description

SKEW CALIBRATION CIRCUIT BASED ON SIMPLE FILIFLOP STRUCTURE AND TIME INTERLEAVED ANALOG-DIGITAL CONVERTER}

The present invention relates to a skew correction circuit based on a simple flip-flop structure and a time interleaved analog-to-digital converter using the same.

In the case of a time-interleaved analog-to-digital converter that uses multiple ADC channels in turn, it operates at a high speed, but timing skew errors inevitably occur. This occurs because the time difference between the clocks applied to each channel is not constant, and if this is not corrected, the performance of the analog-to-digital converter deteriorates.

KR 10-2166908 B

The present invention provides a skew correction circuit based on a simple flip-flop structure and a time interleaved analog-to-digital converter using the same.

In order to achieve the above object, a skew correction circuit according to an embodiment of the present invention includes a reference clock unit receiving a reference clock as a clock; and a channel clock unit receiving a clock of a channel as a clock. Here, when the polarity of the timing skew is detected, one of the reference clock unit and the channel clock unit is reset by an output of the other clock unit, and the polarity of the timing skew is detected through the outputs of the reference clock unit and the channel clock unit.

A skew correction circuit according to another embodiment of the present invention includes a reference clock unit receiving a reference clock as a clock; and a channel clock unit receiving a clock of a channel as a clock. Here, the clock units are interlocked, the polarity of the timing skew is detected through the output of the reference clock unit and the outputs of the channel clock unit, and after the polarity of the timing skew is detected, before the polarity of the next timing skew is detected, the reference clock unit and Outputs of the channel clock unit are initialized.

In the time interleaved analog-to-digital converter using a plurality of channels according to an embodiment of the present invention, each of the plurality of channels includes a skew correction circuit, and the same reference clock is input to the skew correction circuit. . Each skew correction circuit includes a reference clock unit receiving the reference clock as a clock; and a channel clock unit receiving a clock of a corresponding channel as a clock. Here, when the polarity of the timing skew is detected, one of the reference clock unit and the channel clock unit is reset by an output of the other clock unit, and the polarity of the timing skew is detected through the outputs of the reference clock unit and the channel clock unit.

Since the skew correction circuit according to the present invention detects the polarity of the timing skew for skew correction using only two D flip-flops, the structure of the skew correction circuit can be simple.

The skew correction circuit minimizes a timing skew between a clock applied to each channel and a reference clock, thereby correcting a timing skew between channels.

1 is a diagram illustrating a skew correction circuit according to an embodiment of the present invention.
FIG. 2 is a diagram showing a timing skew comparison result between a reference clock and an input clock in the circuit of FIG. 1 .
3 is a diagram illustrating a skew correction circuit according to another embodiment of the present invention.
4 and 5 are diagrams showing simulation results of the skew correction circuit of FIG. 3 .
6 is a diagram illustrating timing skew correction simulation results.

Singular expressions used herein include plural expressions unless the context clearly dictates otherwise. In this specification, terms such as "consisting of" or "comprising" should not be construed as necessarily including all of the various components or steps described in the specification, and some of the components or some of the steps It should be construed that it may not be included, or may further include additional components or steps. In addition, terms such as "...unit" and "module" described in the specification mean a unit that processes at least one function or operation, which may be implemented as hardware or software or a combination of hardware and software. .

The present invention relates to a skew correction circuit, and can be particularly used for a time interleaved analog-to-digital converter that uses several analog-to-digital converter (ADC) channels in turn.

According to an embodiment, the skew correction circuit may detect a polarity of a timing skew between a clock applied to the channel and a reference clock to correct the timing skew of the channel. For example, the skew correction circuit may correct timing skew between channels by minimizing timing skew between a clock applied to each channel and a reference clock.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a diagram showing a skew correction circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing a timing skew comparison result between a reference clock and an input clock in the circuit of FIG. 1 . 3 is a diagram showing a skew correction circuit according to another embodiment of the present invention, FIGS. 4 and 5 are diagrams showing simulation results of the skew correction circuit of FIG. 3, and FIG. 6 shows timing skew correction simulation results. It is an illustrated drawing.

Referring to FIG. 1 , the skew correction circuit of this embodiment is a circuit implemented in one channel and may include a reference clock unit 100 and a channel clock unit 102 .

The reference clock unit 100 is a circuit to which the reference clock φ _R is input as a clock, and an output may be provided to a reset terminal of the channel clock unit 102 .

According to one embodiment, the reference clock unit 100 is implemented as a D flip-flop, a power supply voltage (V _DD ) is input to an input terminal, a reference clock (φ _R ) is input to a clock terminal, and a channel clock unit 102 ) can be input to the reset terminal.

The channel clock unit 102 is a circuit to which a channel clock is input as a clock, and an output may be input to a reset terminal of the reference clock unit 100 . Hereinafter, for convenience of explanation, it will be assumed that the clock of the channel is the clock (φ ₂ ) of the second channel.

According to one embodiment, the channel clock unit 102 is implemented as a D flip-flop, a power supply voltage (V _DD ) is input to an input terminal, a channel clock (φ ₂ ) is input to a clock terminal, and a reference clock unit ( 100) may be input to the reset terminal.

That is, the reference clock unit 100 and the channel clock unit 102 interlock with each other and may form a latch structure.

Looking at the operation of this skew correction circuit in detail, when the output of the clock unit that is triggered first among the reference clock unit 100 and the channel clock unit 102 has a high logic level, the other clock unit is reset before outputting a high logic level. As a result, the output of the other clock unit is fixed to low logic, and therefore may not respond even if a clock is input thereafter.

For example, if the rising edge of the reference clock (φ _R ) precedes the rising edge of the channel clock (φ ₂ ), the output (a2) of the reference clock unit 100 first has a high logic, and as a result, the channel The clock unit 102 is reset so that the output b2 of the channel clock unit 102 is fixed to low logic. A simulation result of this operation is shown on the left side of FIG. 2 .

As another example, if the rising edge of the channel clock (φ ₂ ) precedes the rising edge of the reference clock (φ _R ), the output (b2) of the channel clock unit 102 first has a high logic, and as a result, the reference clock The unit 100 is reset and the output a2 of the reference clock unit 100 is fixed to low logic. Simulation results of this operation are shown on the right side of FIG. 2 .

According to an embodiment, the polarity of the timing skew of a corresponding channel can be detected by using the output of the reference clock unit 100 and the output of the channel clock unit 102 .

The skew correction circuit may apply an output value corresponding to the polarity of the detected timing skew to an up/down counter, and up/down bits of a delay line as much as an output of the up/down counter to adjust a clock delay of a channel. there is. As a result, the clocks of the channels may be aligned based on the reference clock φ _R .

Meanwhile, such a skew correction circuit may exist for each channel, so that the same reference clock φ _R may be provided to all channels. That is, there is a skew correction circuit for each channel, and each skew correction circuit includes a reference clock unit 100 using the reference clock (φ _R ) as a clock, a channel clock unit 102, an up/down counter, and a delay line. can do. As a result, the clocks of each channel may be aligned based on the reference clock φ _R .

Meanwhile, as shown in FIG. 2, the outputs of the clock units 100 and 102 continue to maintain their states. In this case, when the delay is changed during the operation of the skew compensating circuit, the polarity of the new timing skew may not be detected.

Therefore, after detecting the polarity of the timing skew through the outputs of the clock units 100 and 102, it is necessary to initialize the latch composed of the clock units 100 and 102 in order to detect a new timing skew.

According to one embodiment, for this initialization, switches switched by the clock (φ ₁ ) of the previous channel may be connected to reset terminals of each clock unit 100 and 102 .

)에 의해 스위칭될 수 있다. Specifically, a first switch is formed between the reset terminal of the reference clock unit 100 and the output of the channel clock unit 102, and a second switch is formed between the reset terminal and the power supply voltage (V _DD ), and the channel A third switch may be formed between the reset terminal of the clock unit 102 and the output of the reference clock unit 100, and a fourth switch may be formed between the reset terminal and the power supply voltage V _DD . At this time, the first switch and the third switch are switched by a clock of another channel, for example, a clock (φ ₁ ) of the previous channel, and the second switch and the fourth switch are inverted clocks of the previous channel (

) can be switched.

In this circuit structure, if the clock φ ₁ of the previous channel has a high logic, the polarity of the timing skew is detected through the outputs of the clock units 100 and 102, and if the clock φ ₁ of the previous channel has a low logic Reset terminals of the clock units 100 and 102 may be connected to the power supply voltage V _DD to initialize the clock units 100 and 102 . Accordingly, the clock units 100 and 102 can detect the polarity of the next pulse of the clock φ ₂ of the channel.

According to one embodiment, the clock units 100 and 102 may be reset after operating an up/down counter that corrects timing skew.

Looking at the simulation results, the process of resetting the clock units 100 and 102 using the clock (φ ₁ ) of the previous channel before detecting the polarity of the timing skew is confirmed by FIG. 4 .

Referring to FIG. 5 , it can be confirmed that timing skew correction is properly performed. In FIG. 5, the green waveform at the upper end of the graph above represents the reference clock (φ _R ), the red waveform represents the channel clock (φ ₂ ), and the green at the lower end indicates that the reference clock unit 100 outputs (a2), Ocher color represents the output (b2) of the channel clock unit 102.

Looking at the first part of the red dotted line, the pulse of the channel's clock (φ ₂ ) precedes the pulse of the reference clock (φ _R ). As a result, a2=Low and b2=High are generated, and these results are reflected in the delay line, so that the next pulse of the clock (φ ₂ ) of the channel follows the pulse of the reference clock (φ _R ).

It is also confirmed that the outputs of the clock units 100 and 102 are reset by the clock φ ₁ of the previous channel immediately before the next measurement. In the second measurement, the pulses of the channel's clock (φ ₂ ) come after the pulses of the reference clock (φ _R ), resulting in a2=High and b2=Low. For reference, after the timing skew is successfully corrected, as shown in FIG. 5, the timing of the pulse repeats the state of going back and forth between two slightly different states.

6 is a result of simulating the skew correction operation, the upper stage shows a timing skew of about 14 ps as a waveform around 2.5 ns, and the lower stage shows the result observed at 26 ns, and the timing skew is corrected to about hundreds of fs. You can see that it has almost disappeared. That is, it can be confirmed that the skew correction has been properly performed.

In summary, the skew correction circuit of this embodiment can detect the polarity of the timing skew with a simple circuit having two D flip-flops, and therefore, compared to timing skew correction technology that does not require separate calculations and performs statistical signal processing, digital Signal processing can be simple.

On the other hand, the components of the above-described embodiment can be easily grasped from a process point of view. That is, each component can be identified as each process. In addition, the processes of the above-described embodiments can be easily grasped from the viewpoint of components of the device.

The embodiments of the present invention described above have been disclosed for illustrative purposes, and those skilled in the art having ordinary knowledge of the present invention will be able to make various modifications, changes, and additions within the spirit and scope of the present invention, and such modifications, changes, and additions will be considered to fall within the scope of the following claims.

100: reference clock unit 102: channel clock unit

Claims (12)

a reference clock unit that receives a reference clock as a clock; and
Including a channel clock unit that receives the clock of the channel as a clock,
When the polarity of the timing skew is detected, one of the reference clock unit and the channel clock unit is reset by an output of the other clock unit, and the polarity of the timing skew is detected through outputs of the reference clock unit and the channel clock unit. skew correction circuitry. The skew correction circuit of claim 1 , wherein when an output of one of the reference clock unit and the channel clock unit first has a high logic level, the other clock unit is reset to have a low level logic output. The method of claim 1, wherein the reference clock unit has a first D flip-flop, and the channel clock unit includes a second D flip-flop,
A power supply voltage is input to an input terminal of the first D flip-flop, the reference clock is input as a clock, and an output of the second D flip-flop is provided to a reset terminal;
The skew correction circuit of claim 1 , wherein a power supply voltage is input to an input terminal of the second D flip-flop, a clock of the channel is input as a clock, and an output of the first D flip-flop is provided to a reset terminal. 4. The method of claim 3, wherein a first switch is formed between the reset terminal of the first D flip-flop and an output of the second D flip-flop, and a second switch is formed between the reset terminal of the first D flip-flop and the power supply voltage. Is formed, the first switch or the second switch is controlled by a clock of another channel, the first switch and the second switch operate complementaryly,
A third switch is formed between the reset terminal of the second D flip-flop and the output of the first D flip-flop, and a fourth switch is formed between the reset terminal of the second D flip-flop and the power supply voltage. The third switch or the fourth switch is controlled by the clock of the other channel, and the third switch and the fourth switch operate complementaryly. The skew of claim 3 , wherein after the polarity of the timing skew is detected through the outputs of the D flip-flops, the outputs of the D flip-flops are initialized by a clock of a previous channel before the polarity of the next timing skew is detected. correction circuit. According to claim 1,
an up/down counter counting a value of the detected timing skew; and
and a delay line correcting the timing skew by delaying the output by the output of the up/down counter. a reference clock unit that receives a reference clock as a clock; and
Including a channel clock unit that receives the clock of the channel as a clock,
The clock units are interlocked, and the polarity of the timing skew is detected through outputs of the reference clock unit and outputs of the channel clock unit, and after the polarity of the timing skew is detected, the reference clock unit and the channel before the polarity of the next timing skew is detected. A skew correction circuit, characterized in that the outputs of the clock unit are initialized. The method of claim 7, wherein the reference clock unit and the channel clock unit each include a D flip-flop,
The skew correction circuit of claim 1 , wherein when an output of one of the reference clock unit and the channel clock unit has a high logic first, the other clock unit is reset and has a low logic output. The skew correction circuit of claim 7 , wherein the reference clock unit and the channel clock unit are initialized by a clock of a previous channel after the polarity of the timing skew is detected and before the polarity of the next timing skew is detected. In a time interleaved analog-to-digital converter using a plurality of channels,
A plurality of channels among the channels each include a skew correction circuit, and the same reference clock is input to the skew correction circuit,
Each skew correction circuit,
a reference clock unit receiving the reference clock as a clock; and
Including a channel clock unit that receives the clock of the corresponding channel as a clock,
When the polarity of the timing skew is detected, one of the reference clock unit and the channel clock unit is reset by an output of the other clock unit, and the polarity of the timing skew is detected through outputs of the reference clock unit and the channel clock unit. A time-interleaved analog-to-digital converter. 11. The time interleaved analog-digital of claim 10 , wherein the reference clock unit and the channel clock unit are initialized by a clock of a previous channel after the polarity of the timing skew is detected and before the polarity of the next timing skew is detected. converter. 11. The method of claim 10, wherein the reference clock unit has a first D flip-flop, and the channel clock unit includes a second D flip-flop,
A power supply voltage is input to an input terminal of the first D flip-flop, the reference clock is input as a clock, and an output of the second D flip-flop is provided to a reset terminal;
A time interleaved analog-to-digital converter characterized in that a power supply voltage is input to an input terminal of the second D flip-flop, a clock of the channel is input as a clock, and an output of the first D flip-flop is provided to a reset terminal. .

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