KR20230035719A - Calculation method of binary neural network and binary neural network using the same - Google Patents

Abstract

The embodiment of the present invention relates to a method for calculating a binary neural network. The method includes the steps of: converting provided input values into a linear transformation function; calculating a weighted sum of the converted input values; and calculating an output value by comparing a threshold value converted by the linear conversion function with the weighted sum. Therefore, the present invention has high energy efficiency and computing characteristics.

Description

Binary neural network calculation method and binary neural network calculation device using the same

The present technology relates to a binary neural network calculation method and a binary neural network calculation device using the same.

In order to overcome the structural limitations of chips based on the existing von Neumann structure, neural network hardware or neural network hardware based on a neural network consisting of neurons, which are the basic units of the human brain, and synapses connecting these neurons, Lomorphic hardware is being developed. Neural networks exceed the limits of existing machine learning algorithms and show image, video, and pattern learning and recognition capabilities close to those of humans, and are already being used in numerous fields. Numerous companies and researchers have been developing dedicated ASIC chips to perform these neural network computations quickly and with less power.

Like the human brain, a neural network connects neurons to form a network and performs learning and reasoning. A neural network includes neurons and synapses to which neurons are connected, and the degree of connection between neurons may be strong or weak, and the degree of connection between neurons is called a weight.

Learning a neural network is a process of forming a network, inputting data to be trained, and controlling weight values until a desired result is output.

A process of training a neural network can be described as a process of expressing weight values between n neurons and m neurons as an n*m weight matrix and changing element values of the matrix. In addition, it is common to describe a process of performing inference using a neural network as a process of performing a multiplication operation between a vector provided by a neuron and a weight matrix.

A binary neural network (BNN) is a type of neural network, and means a network composed of any two values for which weights and/or inputs are determined. In general, the weights and/or input activation values of a conventional binary neural network are composed of signed values of +1 and -1, through which weight values and operation results are stored. It is advantageous in that it can efficiently utilize and replace the multiplication operation in the MAC operation with a simple exclusive NOR (XNOR) operation.

Conventional binary neural network algorithms that represent weights and/or input values with two signed values of +1 and -1 have superior recognition rates and higher learning rates than algorithms using other values. However, hardware that computes existing binary neural network algorithms does not have high energy efficiency and computational characteristics.

One of the problems to be solved by the present technology is to develop a neural network calculation method and hardware having higher energy efficiency and calculation characteristics than hardware that calculates the conventional binary neural network algorithm while maintaining the recognition rate and learning rate of the conventional binary neural network algorithm. is to provide

The operation method of the binary neural network according to the present embodiment includes: converting provided input values into a linear transformation function, and calculating a weighted sum of the transformed input values and calculating an output value by comparing a weighted sum with a threshold value converted by the step and linear conversion function.

The binary neural network calculation device according to the present embodiment includes: at least one processor; and a memory for storing one or more programs executed by the processor, and when the programs are executed by the one or more processors, a binary neural network calculation method is performed in the one or more processors, and the calculation method includes: a binary neural network ( binary neural network), the method comprising: transforming provided input values into a linear transformation function, calculating a weighted sum of the transformed input values, and transforming into a linear transformation function and calculating an output value by comparing a weighted sum with a threshold value.

In the binary neural network calculation method according to the present embodiment, the calculation method includes: precharging a bit line and an inverted bit line, providing a voltage corresponding to the converted input component to a word line, and being included in a unit cell to be included in the bit line Controlling the first pass switch connected to and the second pass switch connected to the inverted bit line, detecting the voltage change of the bit line and the voltage change of the inverted bit line, and the conversion weighted sum from the detected voltage changes It involves calculating the value.

According to the present embodiments, while maintaining the high recognition rate and learning rate of the existing binary neural network algorithm, it is possible to perform binary neural network calculation using hardware with improved calculation speed and energy efficiency.

1 is a flowchart illustrating an outline of a method for calculating a binary neural network according to an embodiment of the present invention.
2 is a block diagram showing the outline of a binary neural network calculator according to an embodiment.
3(a) is a diagram illustrating a process of calculating a weighted sum according to the prior art, and FIG. 3(b) is a diagram illustrating a process of calculating a weighted sum according to the present embodiment.
4 is a diagram illustrating a process of calculating a binary output Zb from the weighted sum calculated in FIG. 3(b) according to the present embodiment.
5 is a flowchart illustrating an outline of a binary neural network calculation method according to another embodiment.
6 is a diagram showing an outline of a binary neural network calculation device.
7 is a diagram showing the outline of a unit cell according to this embodiment.
8 and 9 are diagrams for explaining the calculation process of the binary neural network according to the present embodiment.

Hereinafter, this embodiment will be described with reference to the accompanying drawings. 1 is a flowchart illustrating an outline of a method for calculating a binary neural network according to an embodiment of the present invention. Referring to FIG. 1, the binary neural network calculation method according to the present embodiment includes a step of converting provided input values into a linear transformation function (S100), and a weighted sum of the transformed input values. Computing (S200) and calculating an output value by comparing a weighted sum with a threshold value converted by a linear conversion function (S300).

2 is a binary neural network calculator according to an embodiment

It is a block diagram showing the outline of. As illustrated in FIG. 2 , the binary neural network calculator 1 is not limited to the type of calculation and can be implemented using an unrestricted microprocessor capable of performing calculations. According to another embodiment to be described later, the binary neural network calculator may be implemented as a dedicated calculator.

2 is a block diagram showing the outline of the binary neural network calculator 1 according to the present embodiment. Referring to FIG. 2 , the binary neural network calculator 1 according to the present embodiment includes an input unit 21, an output unit 22, a processor 25, a memory 24, and a database 23. The binary neural network calculator 1 of FIG. 2 is according to an embodiment. All blocks shown in FIG. 2 are not essential components, and some blocks included in the binary neural network calculator 1 may be added, changed, or deleted in other embodiments. Meanwhile, the binary neural network calculator 1 may be implemented as a computing device that performs binary neural network calculations, and each component included in the binary neural network calculator 1 may be implemented as a separate software device or , can be implemented as a separate hardware device in which software is combined.

The binary neural network calculator 1 converts the provided input values using a linear transformation function (S100, see FIG. 1), and calculates a weighted sum of the converted input values (S200, FIG. 1) and calculating the output value by comparing the weighted sum with the threshold value converted by the linear conversion function (S300, see FIG. 1).

The input unit 21 means means for receiving input values. The input unit 21 may receive an input value from an external device, a user, or another layer of a binary neural network. In addition, the input unit 21 may input various types of signals or data in conjunction with the processor 25, or directly acquire data in association with an external device and transmit it to the processor 25. The input unit 21 may be a device or server for inputting or receiving log information (log), various condition information or control signals, etc., but is not necessarily limited thereto.

The output unit 22 may display binary neural network operation results, success or failure log information, etc. in conjunction with the processor 25 . In order to output predetermined information, the output unit 22 preferably displays various information through a display (not shown) provided in the binary neural network calculator 1, but is not necessarily limited thereto.

Processor 25 executes at least one instruction or program included in memory 24 . The processor 25 according to the present embodiment calculates data for performing each step based on data obtained from the input unit 21 or the database 23 . For example, the processor 25 converts the provided input values into a linear transformation function (S100, see FIG. 1), and calculates a weighted sum of the converted input values (S200, 1) and calculating an output value by comparing a weighted sum with a threshold value converted by a linear conversion function (S300, see FIG. 1).

The processor 25 may calculate a sum of weights or a threshold value by performing a learning process of a binary neural network. In addition, the processor 25 may perform an inference process by performing a multiply and accumulate (MAC) operation between an input and a weight using a binary neural network for which learning has been completed.

Memory 24 stores at least one instruction or program executable by processor 25 . Memory 24 may store instructions or programs for performing processing. The memory 24 may store associated values such as results, intermediate values, etc. performed at each step. For example, the memory 24 may store results performed in each step, such as transformed input values, a transformed weighted sum calculated with the transformed input values, and a transformed threshold value. In addition, the memory 24 may further store a weight, a sum of the weights, and a threshold value generated when learning of the binary neural network is completed.

The database 23 refers to a general data structure implemented in the storage space (hard disk or memory) of a computer system using a database management program (DBMS), and searches (extracts), deletes, edits, adds, etc. of data. It is a form of data storage that can be used freely. An example of the database 23 is a relational database management system (RDBMS) such as Oracle, Informix, Sybase, DB2, Gemston, Orion, O2, etc. There may be the same object-oriented database management system (OODBMS) and Excelon, Tamino, Sekaiju, etc., which use XML Native Database It can be implemented according to the purpose and has appropriate fields or elements to achieve its function.

The database 23 according to this embodiment may store results performed in each step, such as log information, converted input values, a weighted sum of converted input values, and a converted threshold value. In addition, the database 23 may store weights, a sum of weights, a threshold value, and the like generated when learning of the binary neural network is completed, and provide the stored data. Meanwhile, although the database 24 is described as being implemented in the binary neural network calculator 1, it is not necessarily limited thereto and may be implemented as a separate data storage device.

Referring to FIGS. 1 and 2 , provided input values are converted into a linear transformation function (S100). In one embodiment, the input values may include signed values such as -1 and +1, and the linear conversion function converts signed input values to unsigned values such as 0 and 1. (unsigned) value.

Although -1 and +1 are illustrated as signed values, this is only an example, and in other embodiments, signed values of -2 and +4 may be used as input values. Furthermore, although 0 and 1 are illustrated as unsigned values, this is only an example and unsigned values such as 2 and 4 may be used. However, in the following description, -1 and +1 are exemplified as signed values, and 0 and 1 are exemplified and described as unsigned values. This is for convenience and concise explanation and is not intended to limit the scope of the present invention.

[Equation 1]

(f: linear transformation function, x: input components, x ^t : transformed input components, p, q: constants that are real numbers)

Equation 1 is an equation illustrating a linear conversion function. The linear transformation function can be expressed as a first order polynomial, as exemplified by equation 1 in Equation 1. In addition, since the linear transformation function maps 1:1 between the domain and the range, the values transformed by the linear transformation function can be inversely transformed into untransformed values.

For example, when the input components are signed values of -1 and +1, using a linear conversion function of p = q = 0.5 as shown in ② of Equation 1 has a sign of -1 and +1 ( You can convert signed input components to unsigned 0, 1 values.

[Equation 2]

As an embodiment, in the case of obtaining a linear conversion function for converting signed values -A and +B to two unsigned values of M and N, p and q in Equation 2 above Solve to obtain the desired linear transformation function.

The above embodiments describe an example of converting a signed value to an unsigned value using a linear conversion function, but an unsigned value using a linear conversion function. It is of course also possible to convert to a signed value.

A weighted sum of the transformed input components (x ^t ) and the weight (w) is calculated (S200). 3(a) is a diagram illustrating a process of calculating a weighted sum according to the prior art, and FIG. 3(b) is a diagram illustrating a process of calculating a weighted sum according to the present embodiment. Referring to FIG. 3(a), in the input map (X) including the input component (x), the first row and the first column component of the calculation area shown as a thick broken line is -1 and the first row of the weight matrix (W). Multiply with +1, the first column component of row 1, to get -1. +1 is obtained by multiplying +1, which is a component of the first row and second column of the calculation area, and +1, which is a component of the first row and second column of the weight matrix (W).

In this way, the result of performing the operation up to the third row and third column components of the input map (X) and the third row and third column components of the weight matrix (W) is -1, +1, -1, -1, -1, -1, +1, +1, -1, and by accumulating them, -3, which is a component of the first row and first column of the output matrix Y, can be obtained. The result of performing the above-described multiply and accumulate (MAC) operation while striding the operation area shown by the thick dashed line is a weighted sum matrix (Y) illustrated in FIG. 3 (a) Same as

Referring to FIG. 3(b) illustrating a process of calculating a transform weighted sum according to the present embodiment. In this embodiment illustrated in FIG. 3(b), the signed value -1 is converted to the unsigned value 0 by the linear conversion function, and the signed value +1 is It is converted to 1, which is an unsigned value. An input map (X ^t ) including the converted input component (x ^t ) in this way is the same as illustrated in FIG. 3(b).

The result of multiplying the operation domain of the transformed input map (X ^t ) illustrated by the thick dashed line and the first row and column components of the weight matrix (W) by the third row and third column components is 0, +1, - 1, -1, 0, 0, 1, 0, -1, and when these are accumulated, -1, which is the transform weighted sum component (y ^t ) exemplified by the first row and first column of the transform weight sum matrix (Y ^t ), is obtained. can When a transform weighting sum matrix (Y ^t ) is formed by performing a MAC operation while striding the operation area, it is the same as illustrated in FIG. 3(b).

An output value is calculated by comparing the threshold value converted by the linear conversion function with the converted weighted sum component (S300). The transformation weighted sum component (y ^t ) included in the transformation weighted sum matrix (Y ^t ) is the MAC operation result of the input component (x ^t ) and the weight (w) transformed by the linear transformation function, so it is expressed as in Equation 3 below It can be.

[Equation 3]

(y ^t : transform weighted sum, y: weighted sum, w: weight, x ^t : transformed input, x: input)

As shown in Equation 3, the transform weighted sum component (y ^t ) is the weighted sum (y), which is the result of the MAC operation of the untransformed input component (x) and the weight (w), and p, which is the coefficient of x in the transform function It can be expressed as the sum of the product of the product (see equation ① in Equation 2) and the multiplication result of the sum of the weights (Σw) and the constant q in the conversion function (see equation ① in Equation 2). For example, if the linear conversion function is equal to the expression ② in Equation 2, both p and q may be 0.5.

In the case of transforming an input using a linear transformation function, the sum of the weights is already calculated and stored in the memory 24 and/or database 23 or stored in the computing device 1 when the learning process is completed. In addition, since the MAC operation process between the untransformed input (x) and the weight (w) is performed even in a conventional method that does not transform the input, even if the input transformation is further performed, more computing resources are consumed or , it can be seen that the computation time is not additionally consumed.

An output is formed by comparing the calculated weighted sum (y ^t ) with the transformed threshold value (th ^t ). 4 is a diagram illustrating a process of calculating a binary output Zb from the weighted sum calculated in FIG. 3(b) according to the present embodiment. In this embodiment, the transform weighted sum component (y ^t ) is compared with the transformed threshold value (th ^t ) to form an output value. The transformed weighted sum component (y ^t ) calculated with the transformed input has a relationship with the weighted sum component (y) calculated with the untransformed input as shown in Equation 3 above. According to Equation 3, a process of calculating an output value by comparing a transform weighted sum component (y ^t ) and a transformed threshold value (th ^t ) may be expressed as Equation 4 below.

[Equation 4]

(Z _b : binary output, y ^t : transformation weighted sum component, th: threshold value, w: weight, p: coefficient of linear transformation function, q: constant of linear transformation function, y: weighted sum component, th ^t : transformation threshold)

Equation 4 above is for an embodiment in which p is a positive number. In other embodiments where p is negative, the direction of the inequality sign is reversed.

3 and 4, when the learning of the binary neural network is completed, the sum of the weights (W) and the threshold value (th) can be obtained. At this time, the obtained threshold value (th) is -1.4 and the weight ( It is assumed that the sum of w) is 1 as illustrated in FIG. 3(b).

The transformed threshold value (th ^t ) is calculated as the sum of the product of the threshold value (th) and p, which is the coefficient of x of the linear transformation function, and the product of the sum of the weights and the constant term q of the linear transformation function, as shown in Equation 4 above. do. Assuming that the binary output outputs -1 and +1, which are signed values, in the linear conversion function, p, the coefficient of X, is 0.5, and q, the constant term, is 0.5, as shown in Equation 1 (2) .

The threshold value (th ^t ) converted therefrom is calculated as 0.5×(-1.4) + 0.5×(+1) = -0.2. Therefore, a binary output (Zb) is calculated by comparing the transformed weighted sum (Y ^t ) and the transformed threshold value (th ^t ). That is, the transformation weighted sum (y ^t ) is compared with the transformed threshold value (th ^t ), and if the transformation weighted sum (y ^t ) is greater than or equal to the transformed threshold value (th ^t ), a signed value of +1 is output. If the transformation weighted sum (Y ^t ) is less than the transformed threshold value (th ^t ), a value with a sign of -1 is output.

Example 2

Hereinafter, a method for calculating a binary neural network according to another embodiment will be described with reference to the accompanying drawings. FIG. 5 is a flowchart illustrating an outline of a binary neural network calculation method according to another embodiment, and FIG. 6 is a diagram showing an outline of a binary neural network calculation device 2. Referring to FIGS. 5 and 6 , the binary neural network calculation method includes programming the unit cell 100 and the threshold value memory cell 110 (S1000), and corresponds to the bit line BL and the converted input component. providing a voltage to the word line WL to control the first pass switch included in the unit cell 100 and connected to the bit line BL and the second pass switch connected to the inverted bit line BLB (S2000) and detecting the voltage change of the bit line BL and the voltage change of the inverted bit line BLB (S3000) and calculating a binary output from the detected voltage changes (S4000).

However, in the illustrated embodiment, the first and second inverters I1 and I2 pull down the bit line BL or the inverted bit line BLB so that the voltage is applied to the bit line BL or the inverted bit line BLB. The effect of pulling up is dominant compared to the effect of pulling up. Hereinafter, the effect of pull-down will be described based on this point for easy understanding.

In the embodiment illustrated in FIG. 6 , column 2 of the binary neural network includes unit cells 100 connected to the bit line BL and the inverted bit line BLB, and a threshold value for storing a threshold value. The memory cells 110 and the sense amplifier 200 compare the voltage of the bit line with the voltage formed on the inverted bit line and output the result.

In the illustrated embodiment, each of the plurality of unit cells 100 may be connected to word lines WL, and each of the plurality of unit cells 100 may be connected to the same bit line BL and inverted bit line BLB. can In addition, each of the plurality of threshold value memory cells 110 may receive a threshold value control signal through a word line, and may be connected to the same bit line BL and inverted bit line BLB as the unit cells 100 .

In the illustrated embodiment, bit line BL and inverting bit line BLB are connected to an inverting input and a non-inverting input of sense amplifier 200, respectively. However, this is just an example, and the bit line BL, the inverted bit line BLB and the input of the sense amplifier 200 may be connected differently. However, for concise and clear description and easy understanding, an embodiment in which the bit line BL and the inverted bit line BLB are respectively connected to an inverting input and a non-inverting input of the sense amplifier 200 will be described.

The sense amplifier 200 outputs a logic low signal when the voltage formed on the bit line BL is greater than the voltage formed on the inverted bit line BLB, and the voltage formed on the inverted bit line BLB is applied to the bit line BL. If it is greater than the formed voltage, a logic high signal is output. An output signal of the sense amplifier 200 may be an output signal of a binary neural network as will be described later.

FIG. 7 is a diagram showing an outline of any one unit cell 100 among the unit cells 100 shown in FIG. 6 . Referring to FIG. 7 , the unit cell 100a includes two inverters I1 and I2 cross-coupled to each other and a first pass switch P1 connecting the two inverters to the bit line BL. and a second pass switch P2 connected to the inverted bit line BLB.

The output of one of the two inverters I1 and I2 is provided to the input of the other. Accordingly, the two inverters I1 and I2 store data in a complementary form. Data stored by the two inverters I1 and I2 may be a weight component w of a binary neural network.

A signal corresponding to the converted input component (x ^t ) is provided to the word line (WL). For example, if the converted input component is unsigned (unsigned) 1, a logic high state voltage is provided through the word line (WL), and if the converted input component is unsigned (unsigned) 0, the word line ( A logic low state voltage is provided through WL).

The unit cell 100 may be a static random access memory (SRAM) as in the illustrated embodiment, and may store a weight value of a binary neural network as described above. The unit cell 100 may include a total of 6 transistors. From this, an advantage is provided that it can be formed in a smaller area than a conventional neural network calculation cell that requires 14 or more transistors, and can be easily formed through a conventional memory process.

The configuration of the threshold value memory cell 110 is the same as that of the unit cell 100 . Therefore, the threshold value memory cell 110 is cross-coupled with two inverters I1 and I2 connected to each other and a first pass switch P1 connecting the two inverters to the bit line BL and inverted. A second pass switch P2 connected to the bit line BLB is included.

Hereinafter, a binary neural network calculation method according to the present embodiment will be described with reference to FIGS. 5 to 7 . A step (S1000) of programming the unit cells 100 and the threshold value memory cells 110 is performed. The unit cell 100 is programmed to store weight values. The step of programming the unit cell 100 is performed so that the first and second inverters I1 and I2 constituting the unit cell 100 store weight values in a form complementary to each other.

The step of programming the threshold value memory cells 110 is performed so that the threshold value memory cells 110 pull down the bit line BL or the inverted bit line BLB to correspond to the integerized threshold value th ^t _i . .

The converted threshold value (th ^t ) may be a real number including an integer and a decimal number. Since the converted weighted sum component (y ^t ) is an integer value such as -1 or +1, consistency with the result of the operation with the converted weighted sum component (y ^t ) (for example, equation (2) in Equation 4) The converted threshold value (th ^t ) can be converted into an integer (inteter) while maintaining . For example, the process of integerizing the converted threshold value (th ^t ) may be performed by performing a ceil operation or a floor operation.

In one embodiment, when the converted weighted sum component (y ^t ) is greater than or equal to the converted threshold value (th ^t ) as shown in ② of Equation 4, the binary neural network outputs +1, and in other cases - If 1 is output, the converted threshold value is rounded up to the nearest integer. Even if the converted threshold value is integerized in this way, it is the same as the operation result without integerization.

In an embodiment not illustrated, the binary neural network outputs +1 when the transformed weighted sum component (y ^t ) is greater than the transformed threshold value (th ^t ), and outputs -1 in other cases. The converted threshold value is converted into an integer by performing a floor operation on the converted threshold value to a nearest integer. Even if the converted threshold value is integerized in this way, it is the same as the operation result without integerization.

In the embodiment illustrated by ② of Equation 4, if the threshold value is -(m + α) (m: a positive integer, α: a real number with 0≤ α < 1), the integer converted threshold value (th ^t _i ) is -m. In the process of programming the threshold value memory cell 110, the controller programs the threshold value memory cell 110 so that m threshold value memory cells 110 pull down the bit line BL.

α< 1인 실수)이면, 정수화된 변환된 문턱값(th^t _i)은 n+1 이다. 위에서 설명된 문턱값 메모리 셀(110)을 프로그램하는 과정에서 n+1 개의 문턱값 메모리 셀(110)이 반전 비트 라인(BLB)를 풀 다운 하도록 문턱값 메모리 셀(110)을 프로그램한다. In addition, if the threshold value is n + α (n: positive integer, α: 0

If α<1 real number), the integer transformed threshold value (th ^t _i ) is n+1. In the process of programming the threshold value memory cell 110 described above, the threshold value memory cell 110 is programmed so that n+1 threshold value memory cells 110 pull down the inverted bit line BLB.

In one embodiment, when the integer converted threshold value is m, k of the plurality of threshold value memory cells may be programmed as +1, and j of the threshold value memory cells may be programmed as -1. When the threshold value memory cells 110 programmed as described above are activated, they may be programmed so that k - j = m.

As another embodiment, when the integer converted threshold value is m, m of the plurality of threshold value memory cells may be programmed to +1, and when the integer converted threshold value is -m , can be performed by programming m of the plurality of threshold value memory cells as -1.

As will be described later, when the weight value stored in any one unit cell 100 is +1 and the first and second pass transistors are turned on, the bit line BL is pulled down, but the value stored in the threshold value memory cell 100 When the converted threshold value th ^t is +1 and the first and second pass transistors are conductive, the inverting bit line BLB is pulled down.

When the weight value stored in any one unit cell 100 is -1 and the first and second pass transistors are turned on, the inverted bit line BLB is pulled down, but the converted threshold stored in the threshold value memory cell 100 If the value th ^t is -1, the bit line BL is pulled down when the first and second pass transistors are conductive.

That is, when the weight value stored in the unit cell 100 for storing the weight value and the converted threshold value (th ^t ) stored in the threshold value memory cell 100 for storing the converted threshold value are the same, each bit A different line (BL) and an inverted bit line (BLB) are pulled down.

When a voltage corresponding to the converted input component xt is supplied through the word line WL, the gate electrode of the first pass switch P1 and the gate electrode of the second pass switch P2 pass through the word line WL. A voltage corresponding to the converted input component (x ^t ) is provided (S2000). The first pass switch P1 and the second pass switch P2 are either blocked or conducted according to the voltage applied to the gate electrode.

In the unit cell 100, the first pass switch P1 is conducted to connect the output of the first inverter I1 and the input of the second inverter I2 to the bit line BL, and the second pass switch P2 ) is conducted to connect the input of the first inverter I1 and the output of the second inverter I2 to the inverting bit line BLB. In the illustrated embodiment, both the first pass switch P1 and the second pass switch P2 are illustrated as NMOS transistors, but this is only an example and may be formed as a PMOS transistor of opposite conductivity type. However, in this case, it will be obvious to those skilled in the art that a changed signal method should be used.

In the illustrated embodiment, if the converted input component (x ^t ) is 1, a logic high state signal is provided to the word line WL to allow the first pass switch P1 and the second pass switch P2 to conduct. do. For example, the signal in the logic high state may be a voltage greater than or equal to a threshold voltage at which the first pass switch P1 and the second pass switch P2 are turned on. In addition, when the converted input component (x ^t ) is 0, a signal in a logic low state in which the first pass switch P1 and the second pass switch P2 are blocked is provided to the word line WL.

A signal corresponding to the input component converted through the word line WL is provided to the unit cells 100 and a threshold value control signal is provided to the threshold value memory cells 110, so that a logic operation is performed, and a bit The voltage of the line BL and the inverted bit line BLB is affected (S3000). Table 1 below shows results schematically illustrating operations performed by the unit cell 100 .

(0: logic low, 1: logic high, PU: pull up, PD: pull down)

When the signal provided through the word line WL is in a logic low state, both the first pass switch P1 and the second pass switch P2 are cut off. Accordingly, the voltages of the bit line BL and the inverted bit line BLB do not change regardless of the weight value w stored by the two inverters I1 and I2.

When a signal provided through the word line WL is a signal in a logic high state, both the first pass switch P1 and the second pass switch P2 are conducted. When the value of the weight w stored in the unit cell 100 is -1, the output Q of the first inverter I1 is logic high and the output Qb of the second inverter I2 is logic low. Accordingly, the first inverter I1 pulls up the bit line BL and the second inverter I2 pulls down the inverted bit line BLB.

Similarly, when the signal provided through the word line WL is a signal in a logic high state, both the first pass switch P1 and the second pass switch P2 are conducted. When the value of the weight w stored in the unit cell 100a is +1, the output Qb of the second inverter I2 is logic high and the output Q of the first inverter I1 is logic low. Accordingly, the first inverter I1 pulls down the bit line BL and the second inverter I2 pulls up the inverted bit line BLB.

Table 2 below is a table schematically illustrating an operation performed by the threshold value memory cell 110 . In one embodiment,

Input Threshold Output BL BLB 0 One - - 0 -One - - One One PU PD One -One PD PU

(0: logic low, 1: logic high, PU: pull up, PD: pull down)

When the converted threshold value th ^t stored in the threshold value memory cell 110 is 1 and the first and second pass transistors are conducted, the inverted bit line BLB is pulled down. When the converted threshold value th ^t stored in the threshold value memory cell 110 is -1, when the first and second pass transistors are turned on, the bit line BL is pulled down. This is due to the fact that the converted weighted sum component (y ^t ) and the converted threshold value (th ^t ) in equation (2) of Equation 4 have different signs when transposed in the same direction.

In addition, if the integer converted threshold value (th ^t _i ) is -m, it is the same as that m threshold value memory cells 100 are conducted and the bit line BL is pulled down, and the integer converted threshold value (th ^t _i ) is n, it is the same as that n threshold value memory cells 100 are conducted and the inverted bit line BL is pulled down. From this, it can be seen that the effect of the converted weighted sum component (y ^t ) and the converted threshold value (th ^t ) is added to the bit line BL/inverted bit line BLB.

A component of a binary neural network (BNN) output value is obtained by comparing the voltage formed on the bit line BL with the voltage formed on the inverted bit line BLB (S4000). In one embodiment, the sense amplifier 200 compares the voltage formed on the bit line BL with the voltage formed on the inverted bit line BLB and outputs a corresponding result. As described above, the voltage formed on the bit line BL and the inverted bit line BLB causes the unit cells 100 and the threshold value memory cells 110 to pull up the bit line BL or the inverted bit line BLB. / This is the result formed by pulling down. Therefore, by comparing them, the output value of the binary neural network can be obtained.

Hereinafter, a calculation process will be described with reference to the embodiment illustrated in FIGS. 8 and 9 . In the embodiment illustrated in FIG. 8 , the converted threshold value (th ^t ) is -0.2, and the converted weighted sum component (y ^t ) is greater than the converted threshold value (th ^t ) as in equation ② in Equation 4, or Assume an embodiment in which the output of the binary neural network is +1 when they are equal and the output of the binary neural network is -1 when the transformed weighted sum component (y ^t ) is smaller than the transformed threshold value (th ^t ).

The sum of the multiplication result of the converted input components (xt) and the weight component is calculated as 2×(+1) + 3×(−1) as shown in FIG. 8 . This can be represented by three unit cells 100 pulling down the inverted bit line BLB and two unit cells 100 pulling down the bit line BLB.

Subsequently, the transformed threshold value (th ^t ) is -0.2, and the output of the binary neural network is +1 when the transformed weighted sum component (y ^t ) is greater than or equal to the transformed threshold value (th ^t ), so the integerized The transformed threshold value (th ^t _i ) is 0 rounded up to -0.2. Therefore, the threshold value memory cell 110 does not pull down both the bit line BL and the inverted bit line BLB.

Therefore, the sense amplifier 200 compares the voltage of the bit line BL connected to the inverting input with the voltage of the inverting bit line BLB connected to the non-inverting input. In the above example, since the voltage of the inverted bit line BLB is greater than the voltage of the inverted bit line BL, a signal in a logic low state as a result of the comparison is output.

In the embodiment illustrated in FIG. 9 , when the converted threshold value (tht) is -3.2 and the converted weighted sum component (yt) is greater than or equal to the converted threshold value (tht) as shown in Equation 2 in Equation 4 + Assume an embodiment that outputs 1.

The sum of the multiplication results of the converted input components (xt) and the weight components is calculated as 2×(+1) + 4×(−1) as shown in FIG. 9 . This can be represented as four unit cells 100 pulling down the inverted bit line BLB and two unit cells 100 pulling down the bit line BL.

The transformed threshold value (th ^t ) is -3.2, and when the transformed weighted sum component (y ^t ) is greater than or equal to the transformed threshold value (th ^t ), the output of the binary neural network is +1. The integer transformed threshold value (th ^t _i ) is obtained, and the integer transformed transformed threshold value (th ^t _i ) is -3.

In order to implement the converted threshold value (th ^t ) that has been rounded up, the control unit provides a threshold value control signal corresponding to the threshold value memory cell 110 . That is, since the three threshold value memory cells 100 conduct and pull down the bit line BL, they contribute to the voltage formed on the bit line BLB by the integer converted threshold value th ^t _i .

As a result, two unit cells 100 and three threshold value memory cells 110 are conducted to pull down the bit line BL, and four unit cells 100 are conducted to pull down the inverted bit line BLB. down

The sense amplifier 200 compares the voltage of the bit line (BLB) connected to the inverting input and the voltage of the inverting bit line (BLB) connected to the non-inverting input, and in the illustrated example, the voltage of the inverted bit line (BLB) is Since it is greater than the voltage of the bit line BL, a signal in a logic high state as a result of the comparison is output.

Conventionally, a large amount of data movement was required according to a large number of MAC operations, but there was a problem that a bottleneck phenomenon occurred due to a bandwidth limitation during data movement and power consumption was high. However, since the MAC operation is possible in the memory, the present embodiment can reduce the amount of data movement to solve the data bottleneck of the prior art and reduce power consumption for data transmission.

Furthermore, in the prior art, in order to calculate a binary neural network, the area of the device has increased by implementing elements capable of performing an XNOR operation in a circuit. However, the present embodiment also provides an advantage of being economical in terms of die size because a binary neural network can be calculated without performing an XNOR operation.

It has been described with reference to the embodiments shown in the drawings to aid understanding of the present invention, but this is an embodiment for implementation and is merely illustrative, and various modifications and equivalents may be made by those skilled in the art. It will be appreciated that other embodiments are possible. Therefore, the true technical scope of protection of the present invention will be defined by the appended claims.

1: binary neural network arithmetic unit 21: input unit
22: output unit 23: database
24: memory 24: processor
2: binary neural network computing unit 100: unit cell
110: threshold value memory cell

Claims (24)

An operation method of a binary neural network, the method comprising:
converting the provided input values into a linear transformation function;
calculating a weighted sum of the converted input values; and
and calculating an output value by comparing a threshold value converted by the linear conversion function with the weighted sum. According to claim 1,
The binary neural network includes a plurality of layers,
The calculation method of the binary neural network,
A method of calculating a binary neural network performed in at least one or more layers among the plurality of layers. According to claim 1,
Calculating the weighted sum of the converted input values,
A method of calculating a binary neural network, comprising calculating a weighted sum of untransformed input values. According to claim 1,
The linear transformation function is
math formula

The calculation method of the binary neural network represented by . (f(x): linear transformation function, X: input values, p, q: constants that are real numbers) According to claim 4,
In the step of calculating the weighted sum,
A multiplication result of the p and the weighted sum of the unconverted input values;
A method of calculating a binary neural network performed by calculating a sum of a multiplication result of the q and the calculated weight sum. According to claim 1,
The threshold value converted by the linear conversion function is
The multiplication result of the p and the untransformed threshold value;
A method of calculating a binary neural network, which is the sum of the multiplication result of the q and the calculated weight sum. According to claim 1,
Calculating the output value,
When the weighted sum is greater than or equal to the converted threshold value, +1 is set as an output value,
A method of calculating a binary neural network that is performed with -1 as an output value when the weighted sum is smaller than the converted threshold value. According to claim 1,
the provided input value includes a signed value;
The converted input values include unsigned values,
The output value is a method of calculating a binary neural network including a signed value. A computation unit of a binary neural network, the computation unit comprising:
at least one processor; and
and a memory storing one or more programs executed by the processor, wherein the programs, when executed by the one or more processors, are stored in the one or more processors.
A calculation method of a binary neural network is performed, wherein the calculation method:
An operation method of a binary neural network, the method comprising:
converting the provided input values into a linear transformation function;
calculating a weighted sum of the converted input values; and
and calculating an output value by comparing a threshold value converted by the linear conversion function with the weighted sum. According to claim 9,
The binary neural network includes a plurality of layers,
The calculation method of the binary neural network,
An apparatus for calculating a binary neural network performed in at least one layer among the plurality of layers. According to claim 9,
Calculating the weighted sum of the converted input values,
An apparatus for calculating a binary neural network, comprising calculating a weighted sum of untransformed input values. According to claim 9,
The linear transformation function is
math formula

The computing unit of the binary neural network represented by . (f(X): linear transformation function, X: input value, p, q: constant real number) According to claim 12,
In the step of calculating the weighted sum,
A multiplication result of the p and the weighted sum of the unconverted input values;
A binary neural network calculator performed by calculating the sum of the multiplication result of the q and the calculated weight sum. According to claim 9,
The threshold value converted by the linear conversion function is
The multiplication result of the p and the untransformed threshold value;
A binary neural network calculator that is the sum of the multiplication result of the q and the calculated weight sum. According to claim 9,
Calculating the output value,
When the weighted sum is greater than or equal to the converted threshold value, +1 is set as an output value,
A binary neural network calculation device that performs -1 as an output value when the weighted sum is smaller than the converted threshold value. According to claim 9,
the provided input value includes a signed value;
The converted input values include unsigned values,
The output value is a binary neural network calculation device including a signed value. A calculation method for a binary neural network, the calculation method comprising:
Storing and programming weight values in a plurality of unit cells;
providing a voltage corresponding to an input component converted to a word line connected to each unit cell and performing an operation with the weight value;
detecting voltages of a bit line corresponding to the converted weighted sum component and voltages of an inverted bit line; and
A method of calculating a binary neural network comprising calculating a binary neural network output from the detected voltages. According to claim 17,
The programming step is
A method of calculating a binary neural network, further performing the step of storing the converted threshold value converted into an integer in a plurality of threshold value memory cells. According to claim 17+1,
The integer converted threshold value is,
The neural network calculation method, which is an integer value by performing a ceil operation and a floor operation on the converted threshold value. According to claim 18,
The voltage of the bit line and the voltage of the inverted bit line are
The method of calculating a binary neural network comprising a voltage component formed on the bit line and a voltage component formed on the inverted bit line by the plurality of threshold value memory cells corresponding to the integer converted threshold value. According to claim 18,
When the weight value stored in the unit cell and the threshold value stored in the threshold value memory cell are the same value,
When the unit cell pulls down any one of the bit line and the inverted bit line,
The threshold value memory cell pulls down the other one of the bit line and the inverted bit line. According to claim 18,
The unit cell and the threshold value memory cell are each composed of 6 transistors. According to claim 17,
The calculation method of the binary neural network,
Neural network calculation method that does not perform XNOR operation. According to claim 17,
The binary neural network calculation method is a binary neural network calculation method performed in a memory.

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