KR20230035193A - Digital Circuits Comprising Quantum Wire Resonant Tunneling Transistors - Google Patents

Abstract

A digital circuit includes: an emitter terminal; a base terminal; a collector terminal; an emitter region connected to the emitter terminal; a base region connected to the base terminal; a collector region connected to the collector terminal; an emitter barrier region between the emitter region and the base region; and a collector barrier region between the collector region and the base region. At least one of the emitter region, the base region, and the collector region includes a plurality of metal quantum wires.

Description

Digital circuits comprising quantum wire resonant tunneling transistors {Digital Circuits Comprising Quantum Wire Resonant Tunneling Transistors}

This application relates generally to digital circuitry, and more specifically to digital circuitry including quantum wire resonant tunneling transistors. This application is based on commonly assigned US Patent Application Serial No. 16/852,493, entitled "Quantum Wire Resonant Tunneling Transistor" filed on April 19, 2020 by the same inventor and is a continuation-in-part patent application17 in the United States. /467,188, the contents of which are incorporated herein by reference.

The MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is a fundamental building block of semiconductor technology. Much of its success is due to the fact that it can be continuously scaled down to smaller sizes while increasing circuit performance and lowering manufacturing costs. After more than 50 years of miniaturization, the benefits of device scaling have gradually diminished. However, according to the 2015 International Technology Roadmap for Semiconductors (ITRS), scaling of MOS devices may stop in the near future (R. Courtland, "Transistors Could Stop Shrinking in 2021," IEEE Spectrum, vol. 53, no. 9, pp. 9-11, Sep. 2016, doi: 10.1109/MSPEC.2016.7551335, and International Technology Roadmap for Semiconductors, 2015 Edition. http://www.itrs2.net/.

Therefore, there is an urgent need for low-cost/high-efficiency transistors beyond CMOS to meet the growing demand for computing power. Such new transistors can have very different operating mechanisms and behaviors than MOSFETs, bringing new challenges to circuit design.

In one general aspect of the present invention, the present invention relates to a digital circuit comprising one or more Quantum Wire Resonant Tunneling Transistors (QWRTTs), at least one of which is an emitter terminal ( emitter terminal), base terminal, collector terminal, emitter region connected to the emitter terminal, base region connected to the base terminal, collector area connected to the collector terminal region), an emitter barrier region between the emitter region and the base region, and a collector barrier region between the collector region and the base region, and among the emitter region, the base region, and the collector region At least one includes a plurality of metal quantum wires.

Implementations of the system may include one or more of the following. The digital circuit includes an input node, an output node, a pull-down network including one or more QWRTTs, and a pull-up network including one or more QWRTTs. network), and in this case, the pull-down network and the pull-up network form a dual network, and the pull-down network A parallel connection of one or more QWRTTs in a network corresponds to a series connection of one or more QWRTTs in the pull-up network, or a series connection of one or more QWRTTs in the pull-down network corresponds to a series connection of one or more QWRTTs in the pull-down network. Corresponds to the parallel connection of one or more QWRTTs in the up network. An input node of the complementary logic gate is connected to the base terminal of the one or more QWRTTs in the pull-down network, in which case the input node of the complementary logic gate is connected to the base terminal of the one or more QWRTTs in the pull-up network. It is connected to the base terminal. The pull-down network of the complementary logic gates includes one or more enhancement mode QWRTTs having a positive on voltage V _ON , and the pull-up network of the complementary logic gates comprises: Includes one or more enhancement mode QWRTTs with negative V _ON . The pull-down network of the complementary logic gates includes one or more normally on QWRTTs, and the pull-up network of the complementary logic gates includes one or more normally on QWRTTs. The pull-down network of the complementary logic gates includes one or more n-type QWRTTs, and the pull-up network of the complementary logic gates includes one or more n-type QWRTTs. The complementary logic gate includes an AND gate, an OR gate, a NOT gate, a buffer, a NAND gate, a NOR gate, or a combination thereof. The pass transistor logic gate further includes: one or more enhancement mode QWRTT with positive V _ON , one or more enhancement mode QWRTT with negative V _ON , or a combination thereof. A memory element comprising a bistable circuit for storing bits of data, further comprising the bistable circuit comprising one or more QWRTTs. The bistable circuit includes two inverters or a buffer. The storage element includes two cross-coupled inverters formed by four enhancement mode QWRTTs; two access transistors formed by two enhancement mode QWRTTs; word line WL ; and a 6-transistor (6T) SRAM cell including two bit lines BL , in which case the word line and the two bit lines address the SRAM cell and read and It is configured to access stored data in a write operation. The storage element may include a buffer formed by two normally-on transistors; an access transistor formed by one enhancement mode transistor; word line; and a bit line; wherein the word line and the bit line are configured to address the SRAM cell and access stored data in read and write operations. . The one or more QWRTTs include n-type and p-type devices, wherein the n-type and p-type devices are normally on transistors with V _ON = 0 V, enhancement mode transistors with positive V _ON , or It consists of an enhancement mode transistor with negative V _ON . The enhancement mode QWRTT has multiple V _ON values, and the enhancement mode QWRTT is configured to operate with multiple power supply voltages. The plurality of metal quantum wires are formed by implanting metal ions into an open channel of a crystalline semiconductor, and a mask layer used for ion implantation is formed on a wafer surface with a lattice arranged in a lattice structure.

The details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features, objects and advantages of the present invention will become apparent from the detailed description, drawings and claims.

,

,

)를 갖는 3개의 n-형QWRTT의 전송 I-V 곡선을 도시한다.
도 11은 QWRTT의 회로 심볼을 도시한다.
도 12a는 n-형 및 p-형 노멀리 온 QWRTT을 모두 사용하여 구성된 2-입력 AND 게이트의 회로도를 도시한다.
도 12b는 n-형 및 p-형 노멀리 온 QWRTT을 모두 사용하여 구성된 2-입력 OR 게이트의 회로도를 도시한다.
도 13a는 n-형 노멀리 온 QWRTT만 사용하여 구성된 2-입력 AND 게이트의 회로도를 도시한다.
도 13b는 n-형 노멀리 온 QWRTT만 사용하여 구성된 2-입력 OR 게이트의 회로도를 도시한다.
도 14a는 n-형 및 p-형 인핸스먼트 모드 QWRTT를 모두 사용하여 구성된 인버터의 회로도를 도시한다.
도 14b는 n-형 인핸스먼트 모드 QWRTT만 사용하여 구성된 인버터의 회로도를 도시한다.
도 15a는 n-형 및 p-형 노멀리 온 QWRTT 모두 사용하여 구성된 버퍼의 회로도를 도시한다.
도 15b는 n-형 노멀리 온 QWRTT만 사용하여 구성한 버퍼의 회로도를 도시한다.
도 16a는 n-형 및 p-형 인핸스먼트 모드 QWRTT를 모두 사용하여 구성한 2-입력 NAND 게이트의 회로도를 도시한다.
도 16b는 n-형 및 p-형 인핸스먼트 모드 QWRTT를 모두 사용하여 구성된 2-입력 NOR 게이트의 회로도를 도시한다.
도 17a는 n-형 인핸스먼트 모드 QWRTT만 사용하여 구성한 2-입력 NAND 게이트의 회로도를 도시한다.
도 17b는 n-형 인핸스먼트 모드 QWRTT만 사용하여 구성한 2-입력 NOR 게이트의 회로도를 도시한다.
도 18a는 양의 V _ON 을 갖는 n-형 인핸스먼트 모드 QWRTT를 사용하는 패스 트랜지스터 로직에서 구현된 XOR 게이트의 회로도를 도시한다.
도 18b는 음의 V _ON 을 갖는 n-형 인핸스먼트 모드 QWRTT를 사용하여 패스 트랜지스터 로직에서 구현된 XNOR 게이트의 회로도를 도시한다.
도 19a는 n-형 및 p-형 인핸스먼트 모드 QWRTT를 모두 사용하여 구성된 전송 게이트의 회로도를 도시한다.
도 19b는 n-형 인핸스먼트 모드 QWRTT만 사용하여 구성된 전송 게이트의 회로도를 도시한다.
도 20a는 두 개의 교차-결합된 인버터로 구성된 쌍안정 회로의 회로 개략도를 도시한다.
도 20b는 n-형 및 p-형 QWRTT를 모두 사용하여 구성된 도 20a에 도시된 바와 같은 쌍안정 회로의 회로도를 도시한다.
도 20c는 n-형 QWRTT만 사용하여 구성된 도 20a에 도시된 바와 같은 쌍안정 회로의 회로도를 도시한다.
도 21a는 버퍼로 구성된 쌍안정 회로의 회로 개략도를 도시한다.
도 21b는 n-형 및 p-형 QWRTT를 모두 사용하여 구성된 도 21a에 도시된 바와 같은 쌍안정 회로의 회로도를 도시한다.
도 21c는 n-형 QWRTT만 사용하여 구성된 도 21a에 도시된 바와 같은 쌍안정 회로의 회로도를 도시한다.
도 22a는 2개의 인버터와 2개의 전송 게이트로 구성된 래치의 회로 개략도를 도시한다.
도 22b는 n-형 및 p-형 QWRTT를 모두 사용하여 구성된 도 22a에 도시된 래치의 회로도를 도시한다.
도 22c는 n-형 QWRTT만 사용하여 구성된 도 22a에 도시된 래치의 회로도를 도시한다.
도 23a는 버퍼와 두개의 전송 게이트로 구성된 래치의 회로 개략도이다.
도 23b는 n-형 및 p-형 QWRTT를 사용하여 구성된 도 23a에 도시된 래치의 회로도를 도시한다.
도 23c는 n-형 QWRTT만 사용하여 구성된 도 23a에 도시된 래치의 회로도를 도시한다.
도 24a는 2 개의 교차 결합된 인버터와 2 개의 액세스 트랜지스터로 구성된 6T SRAM을 도시한다.
도 24b는 n-형 및 p-형 QWRTT를 모두 사용하여 구성된 도 24a에 도시된 6T SRAM 셀의 회로도를 도시한다.
도 24c는 n-형 QWRTT만 사용하여 구성된 도 24a에 도시된 6T SRAM 셀의 회로도를 도시한다.
도 25a는 버퍼와 엑세스 트랜지스터를 사용하여 구성된 싱글-앤드 3T SRAM 셀을 도시한다.
도 25b는 n-형 및 p-형 QWRTT를 사용하여 구성된 도 25a에 도시된 3T SRAM 셀의 회로도를 도시한다.
도 25c는 n-형 QWRTT만 사용하여 도 25a에 도시된 3T SRAM 셀의 회로도를 도시한다.The accompanying drawings, which are incorporated in and constitute a part of this specification, together with the description illustrate embodiments of the present invention and serve to explain the principles of the present invention.
1 shows a schematic diagram of a quantum wire resonant tunneling transistor (QWRTT).
2A shows a band diagram of an n-type QWRTT.
2b shows a band diagram of a p-type QWRTT.
Figure 3a shows a silicon lattice structure viewed from the <110> direction.
Figure 3b shows the same silicon lattice structure after ion implantation.
4A shows the layer structure in the ion implantation step.
Figure 4b shows the layer structure after the metal layer has been deposited and patterned.
5 shows the ground state energy ( E ₁ ) versus the number of quantum wires ( N ) of a superlattice structure.
6 plots electron transmission coefficients and 1-D DOS ( σ _1-D ) versus energy of an n-type QWRTT.
7A shows the transmission IV curve of an n-type QWRTT.
7B plots the device drive current versus V _B of an n-type QWRTT.
7C shows output characteristics of an n-type QWRTT.
8A shows the transmission IV curve of p-type QWRTT.
8B plots device drive current versus V _B of a p-type QWRTT.
8C shows the output characteristics of a p-type QWRTT.
9 shows transmission IV curves of three n-type QWRTTs with different ( NE , N _B , N _C ) _.
10 shows a different (

,

,

) shows the transmission IV curves of three n-type QWRTTs with
11 shows circuit symbols of QWRTT.
12A shows a circuit diagram of a two-input AND gate constructed using both n-type and p-type normally on QWRTTs.
12B shows a circuit diagram of a two-input OR gate constructed using both n-type and p-type normally on QWRTTs.
13A shows a circuit diagram of a two-input AND gate constructed using only n-type normally-on QWRTTs.
13B shows a circuit diagram of a two-input OR gate constructed using only n-type normally-on QWRTTs.
14A shows a circuit diagram of an inverter constructed using both n-type and p-type enhancement mode QWRTT.
14B shows a circuit diagram of an inverter constructed using only the n-type enhancement mode QWRTT.
15A shows a circuit diagram of a buffer constructed using both n-type and p-type normally on QWRTTs.
15B shows a circuit diagram of a buffer constructed using only n-type normally-on QWRTTs.
Figure 16a shows a circuit diagram of a two-input NAND gate constructed using both n-type and p-type enhancement mode QWRTT.
16B shows a circuit diagram of a two-input NOR gate constructed using both n-type and p-type enhancement mode QWRTT.
Figure 17a shows a circuit diagram of a two-input NAND gate constructed using only the n-type enhancement mode QWRTT.
Figure 17b shows a circuit diagram of a two-input NOR gate constructed using only n-type enhancement mode QWRTT.
18A shows a circuit diagram of an XOR gate implemented in pass transistor logic using n-type enhancement mode QWRTT with positive V _ON .
18B shows a circuit diagram of an XNOR gate implemented in pass transistor logic using n-type enhancement mode QWRTT with negative V _ON .
19A shows a circuit diagram of a transfer gate constructed using both n-type and p-type enhancement mode QWRTT.
19B shows a circuit diagram of a transfer gate constructed using only n-type enhancement mode QWRTT.
20A shows a circuit schematic of a bistable circuit composed of two cross-coupled inverters.
FIG. 20B shows a circuit diagram of a bistable circuit as shown in FIG. 20A constructed using both n-type and p-type QWRTTs.
Fig. 20c shows a circuit diagram of a bistable circuit as shown in Fig. 20a constructed using only n-type QWRTTs.
Fig. 21A shows a circuit schematic of a bistable circuit composed of a buffer.
FIG. 21B shows a circuit diagram of a bistable circuit as shown in FIG. 21A constructed using both n-type and p-type QWRTTs.
Fig. 21c shows a circuit diagram of a bistable circuit as shown in Fig. 21a constructed using only n-type QWRTTs.
22A shows a circuit schematic of a latch composed of two inverters and two transfer gates.
FIG. 22B shows a circuit diagram of the latch shown in FIG. 22A constructed using both n-type and p-type QWRTTs.
Fig. 22c shows a circuit diagram of the latch shown in Fig. 22a constructed using only n-type QWRTTs.
23A is a circuit schematic diagram of a latch composed of a buffer and two transfer gates.
FIG. 23B shows a circuit diagram of the latch shown in FIG. 23A constructed using n-type and p-type QWRTTs.
Fig. 23c shows a circuit diagram of the latch shown in Fig. 23a constructed using only n-type QWRTTs.
24a shows a 6T SRAM composed of two cross-coupled inverters and two access transistors.
FIG. 24B shows a circuit diagram of the 6T SRAM cell shown in FIG. 24A constructed using both n-type and p-type QWRTTs.
Fig. 24c shows a circuit diagram of the 6T SRAM cell shown in Fig. 24a constructed using only n-type QWRTTs.
25A shows a single-ended 3T SRAM cell constructed using a buffer and an access transistor.
FIG. 25B shows a circuit diagram of the 3T SRAM cell shown in FIG. 25A constructed using n-type and p-type QWRTTs.
Fig. 25c shows a circuit diagram of the 3T SRAM cell shown in Fig. 25a using only n-type QWRTTs.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Reference will now be made in detail to preferred embodiments of the present invention, which are exemplified together with the drawings. Although the invention will be described in connection with preferred embodiments, it will be understood that it is not intended to limit the invention to these embodiments. Rather, the invention is intended to cover alternatives, modifications and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims. In addition, in the detailed description of the invention that follows, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, components and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.

A Quantum Wire Resonant Tunneling Transistor (QWRTT) is a three-terminal device. 1 shows a schematic drawing of a QWRTT (101). The three terminals include an emitter terminal 121, a base terminal 122 and a collector terminal 123. The device structure of the QWRTT 101 includes an emitter region 111, a base region 112, a collector region 113, and an emitter barrier region. region 114, and a collector barrier region 115. Each of the emitter region 111, the base region 112, and the collector region 113 includes a semiconductor embedded with two or more metal quantum wires. The semiconductor of the emitter region 111, base region 112 and collector region 113 may be, for example, silicon, germanium or a silicon germanium alloy. Emitter barrier region 114 and collector barrier region 115 are made of one or more semiconductor materials such as silicon, germanium, or a silicon germanium alloy. Semiconductors can be undoped or lightly doped.

는 정공에 대한 쇼트키 배리어 높이

보다 작다. 따라서 주요 캐리어는 전자이다. 반면, p-형 QWRTT(202)에 대하여, E _F 는 E _C 보다 E _V 에 더 가깝고,

는

보다 작다. 따라서, 주요 캐리어는 정공이다.QWRTT has two complementary device types, n-type and p-type. The major carriers are electrons in n-type QWRTTs and holes in p-type QWRTTs. 2A shows a band diagram of an n-type QWRTT (201), and FIG. 2B shows a band diagram of a p-type QWRTT (202). The n-type QWRTT 201 and the p-type QWRTT 202 include an emitter region 211, a base region 212, a collector region 213, an emitter barrier region 214, and a collector barrier region 215, respectively. includes E _C is the conduction band edge of the semiconductor, and E _V is the valence band edge. E _F is the Fermi level of the metal forming the quantum wire. For the n-type QWRTT (201), E _F is closer to E _C than E _V , and the Schottky barrier height for electrons

is the Schottky barrier height for holes

smaller than Therefore, the major carriers are electrons. On the other hand, for the p-type QWRTT (202), E _F is closer to E _V than E _C ,

Is

smaller than Therefore, the major carriers are holes.

Silicon has a diamond cubic lattice structure, which is a very open structure with an atomic packing factor of 0.34. Figure 3a shows a silicon lattice structure viewed from the <110> direction. A honeycomb structure formed by silicon atoms 301 can be seen. The honeycomb structure has an array of hexagonal hollow cells 302 . Each cell has a large opening in the center. The aperture forms an open channel 303 in an ion implantation process. In the silicon example, the open channels are oriented along the <110> direction and are substantially parallel to each other. If ions of a light element are implanted along the open channel direction, the ions will be directed along those open channels without encountering any target nuclei. The implant range can be much longer than in other directions. This effect is called ion channeling. This is an undesirable effect for most semiconductor processes. However, this undesirable ion channeling effect can be used to create atomic-sized quantum wires. Figure 3b shows the silicon lattice structure viewed from the <110> direction after ion implantation. Metal atoms 304 are embedded in the open channel 303 as shown in FIG. 3B. Quantum wires are formed when metal atoms 304 in open channels 303 are continuously distributed and electrically connected.

의 두께를 갖는 상부 실리콘 층(top silicon layer)(402), 중간 산화물층(mid oxide layer)(403) 및 하부 실리콘 기판(silicon substrate)(404)을 포함한다. 상부 실리콘 층(402)은 도 3a에 도시된 바와 같이 개방 채널들(303)을 포함하는 결정 격자를 갖는다. 상부 실리콘 층(402)의 두께는 일반적으로 500

미만이다. 이산화 규소(silicon dioxide SiO₂)의 층(405)이 증착되고(deposit) 패턴화된다. SiO₂ 층(405)은 이온 주입 단계를 위한 마스크 층(mask layer)으로 사용된다. 이산화 규소 외에도, 질화 규소(silicon nitride Si₃N₄), 폴리실리콘 (polysilicon), 금속 및 포토레지스트와(photoresist) 같이 완전히 다양한 물질들은 이온 주입을 위한 마스킹 물질들로서 사용될 수 있다. 적합한 일함수들을 갖는 금속들의 이온들은 <110> 방향으로 실리콘 웨이퍼에 수직으로 주입된다. 주입된 이온들은 개방 채널들(303)을 따라 이동한다. 이산화 규소가 비정질이기(amorphous) 때문에 채널들은 실리콘-산화물 계면에서 끝난다. 주입 후, 개방 채널들(303)은 금속 원자들로 채워지고, 양자 와이어들(406)이 형성된다. 표면상의 실리콘 격자에 대한 주입 손상은(implantation damage) 화학적 에칭에(chemical etch) 의해 제거된다. 상호 연결을(interconnection) 위해 금속 층(407)이 증착되고 패턴화된다.An exemplary fabrication process for building QWRTT is described below. Fig. 4a shows the layer structure in the ion implantation step, and Fig. 4b shows the layer structure after the metal layer is patterned. The starting material is a silicon-on-insulator (SOI) 110 wafer 401 . Wafer is about 100

It includes a top silicon layer 402, a mid oxide layer 403 and a lower silicon substrate 404 having a thickness of . Upper silicon layer 402 has a crystal lattice that includes open channels 303 as shown in FIG. 3A. The thickness of the upper silicon layer 402 is typically 500

is less than A layer 405 of silicon dioxide SiO ₂ is deposited and patterned. The SiO ₂ layer 405 is used as a mask layer for the ion implantation step. Besides silicon dioxide, a whole variety of materials can be used as masking materials for ion implantation, such as silicon nitride Si ₃ N ₄ , polysilicon, metals and photoresists. Ions of metals with suitable work functions are implanted vertically into the silicon wafer in the <110> direction. The implanted ions move along the open channels 303 . Since silicon dioxide is amorphous, the channels terminate at the silicon-oxide interface. After implantation, open channels 303 are filled with metal atoms, and quantum wires 406 are formed. Implantation damage to the silicon grid on the surface is removed by chemical etch. A metal layer 407 is deposited and patterned for interconnection.

As shown in FIG. 4B , the emitter region 411 , the base region 412 and the collector region 413 have a metal quantum wire 406 buried in a semiconductor 402 . Emitter region 411 and base region 412 are separated by emitter barrier region 414 . The collector region 413 and the base region 412 are separated by a collector barrier region 415 . W _E is the width of the emitter region 411, W _B is the width of the base region 412, W _C is the width of the collector region 413, W _EB is the width of the emitter barrier region 414, , W _CB is the width of the collector barrier region 415 .

보다 짧다. 이미터 영역(411), 베이스 영역(412) 및 컬렉터 영역(413)은 이미터-베이스-컬렉터(E-B-C) 방향을 따라 동일하거나 상이한 개수의 금속 양자 와이어(406)를 가질 수 있다. 더욱이, 이미터 영역(411), 베이스 영역(412) 및 컬렉터 영역(413)에 있는 금속 양자 와이어(406)는 동일하거나 상이한 물질들로 형성될 수 있다.In some embodiments, metal quantum wire 406 may be approximately perpendicular to silicon layer 402 . The length of the metal quantum wire 406 is typically 500

shorter than The emitter region 411 , the base region 412 , and the collector region 413 may have the same or different numbers of metal quantum wires 406 along the emitter-base-collector (EBC) direction. Moreover, the metal quantum wires 406 in the emitter region 411 , base region 412 and collector region 413 may be formed of the same or different materials.

및 W _E = W _B = W _C = 10

의 치수를 갖는다. 극자외선(EUV) 리소그래피 (lithography)의 출현으로, 해상도 요구사항은 다중 패터닝(multiple patterning)과 측벽 스페이서(sidewall spacers)와 같은 다른 기술들과 EUV 리소그래피를 결합함으로써 달성될 수 있다. 일반적으로 정밀도는 마스크 위의 패턴들이 얼마나 정확하게 웨이퍼 위에 이전에 정의된 패턴들에 정렬될 수 있는지 측정하는 것이다. 예시적인 QWRTT 제조 과정에서, 오픈 채널(303)이 이온 주입 단계에서 완전히 개방되거나 차폐되도록 정밀하게 제어될 수 있게 주입 마스크 층(405) 이 실리콘 격자 구조로 정렬될 필요가 있다. 마스크 위의 패턴들이 웨이퍼 표면에서 격자 구조로 정렬되는 것이 리소그래피의 새로운 요구 사항이다. 원자 규모의 해상도로 웨이퍼 표면을 이미지화 할 수 있는 주사 터널링 현미경(scanning tunneling microscope: STM)와 같은 현미경들이 있다. 이미지 정보는 마스크 정렬을 위해 리소그래피 장비로 제공되고 마스크 층은 웨이퍼 표면 격자 구조로 정렬될 수 있다.In the QWRTT manufacturing process, photolithography must meet stringent requirements for resolution and registration. As a quantum device, the QWRTT has a very small size. A typical device in the simulation is W _EB = W _CB = 26

and W _E = W _B = W _C = 10

has the dimensions of With the advent of extreme ultraviolet (EUV) lithography, resolution requirements can be achieved by combining EUV lithography with other techniques such as multiple patterning and sidewall spacers. In general, precision is a measure of how accurately the patterns on the mask can be aligned to previously defined patterns on the wafer. In the exemplary QWRTT fabrication process, the implant mask layer 405 needs to be aligned with the silicon lattice structure so that the open channels 303 can be precisely controlled to be fully open or shielded during the ion implantation step. Aligning the patterns on the mask into a grid structure on the wafer surface is a new requirement in lithography. There are microscopes such as scanning tunneling microscopes (STMs) that can image wafer surfaces with atomic-scale resolution. Image information is provided to the lithography tool for mask alignment and the mask layer may be aligned in a wafer surface grid structure.

)와 같은 포텐셜 배리어 높이의(potential barrier height) 함수인 것으로 밝혀졌다. 도 5는 E-B-C 방향인 전류 흐름 방향을 따라 초격자 내에서 양자 와이어의 개수(N)에 대한 함수로서 전자에 대한 기저 상태 에너지(E ₁ )를 도시한다. 포텐셜 배리어 높이(

)는 0.42eV인 것으로 간주된다. 초격자 크기는 양자 와이어의 개수(N)에 비례하므로, 더 많은 양자 와이어를 갖는 더 큰 초격자일수록 E ₁ 이 더 작다는 것을 발견했다.As shown in FIG. 4B, the emitter/base/collector (E/B/C) regions 411 to 413 are periodic structures of metal and semiconductor that can be regarded as a superlattice structure. Electrons in metal quantum wires are confined to a second-order (2-D) potential well. The ground state energy ( E ₁ ) shown in FIG. 2a is superlattice size such as W _E , W _B , and W _C , and (

) was found to be a function of the potential barrier height equal to 5 shows the ground state energy E ₁ for an electron as a function of the number N of quantum wires in the superlattice along the direction of current flow, which is the EBC direction. Potential barrier height (

) is considered to be 0.42 eV. Since the superlattice size is proportional to the number of quantum wires ( N ), we found that the larger the superlattice with more quantum wires, the smaller E ₁ .

Device characteristics of QWRTT can be obtained by solving the one-dimensional (1-D) time-independent Schrödinger equation.

(1)

(One)

는 파동 함수(wave function)이고, U(x)는 포텐셜 에너지(potential energy)이고, E는 총 에너지이고, m은 캐리어 유효 질량(carrier effective mass)이며,

는 감소된 플랑크 상수(reduced Planck constant)이다. 일반적인 해는 다음의 형태를 갖는다.here

is the wave function, U(x) is the potential energy, E is the total energy, m is the carrier effective mass,

is the reduced Planck constant. A general solution has the form

(2)

(2)

는 파동 수(wave number)이고, 다음과 같이 주어진다.here,

is the wave number and is given by

(3)

(3)

The tunneling probability or transmission coefficient T is given by

(4)

(4)

where A _C and A _E are the coefficients ( A) of the collector and emitter, respectively. According to Fermi's golden rule, the tunneling current from the emitter to the collector is proportional to the transmission coefficient multiplied by the occupied states at the emitter and the unoccupied states at the collector. . The tunneling current from collector to emitter can be obtained correspondingly. Since the Fermi golden ratio refers to a proportional relationship, the tunneling current shown in the present invention uses an arbitrary unit (au) as a scale. The tunneling current is given by

(5)

(5)

(6)

(6)

와

는 각각 이미터와 컬렉터의 상태 밀도(density of states: DOS)이다. QWRTT는 E/B/C 영역에서 1차원 (1-D) 금속 양자 와이어들을 갖으므로, 캐리어들은 아래 주어진 1차원 상태 밀도(DOS)

를 갖는다. F _E and F _C are the Fermi-Dirac distribution functions of the emitter and collector, respectively.

and

is the density of states (DOS) of the emitter and collector, respectively. Since QWRTT has one-dimensional (1-D) metal quantum wires in the E/B/C domain, the carriers have a one-dimensional density of states (DOS) given below.

cast have

(7)

(7)

where E is greater than E ₁ . The net tunneling current I is expressed as

(8)

(8)

When carriers with lower energy in the barrier height travel through the potential barrier, they contribute to the tunneling current. When carriers with higher energy than the barrier height travel through the potential barrier, they contribute to the thermionic emission current. Eq. The integral of 8 occurs at E ₁ to infinity (or energy much higher than the barrier height). Eq. The current obtained from Fig. 8 includes both tunneling current and thermionic emission current. Since the device bias is very small, few carriers can gain energy above the barrier height. The thermionic emission current is negligible. The quantum tunneling effect is the most important feature of the carrier transport process. Eq. The current obtained from 8 is mainly due to the tunneling current.

)는 E/B/C 영역에서 각각

,

, 및

로 표시된다. 정공에 대한 쇼트키 배리어 높이(

)는 E/B/C 영역에서 각각

,

, 및

로 표시된다.When the E/B/C regions have the same superlattice structure (ie, the number of quantum wires ( N ) and the Fermi level ( E _F ) are the same in the E/B/C region), their E ₁ values are the same. . E ₁ can be said to be "in alignment" in the E/B/C area. The number of quantum wires ( N ) is indicated as N _E , N _B , and N _C respectively along the emitter-base-collector (EBC) direction in the E/B/C region. The ground state energies ( E ₁ ) are represented by E _1E , E _1B , and E _1C in the E/B/C domains, respectively. Schottky barrier height for electrons (

) are respectively in the E/B/C area

,

, and

is indicated by Schottky barrier height for holes (

) are respectively in the E/B/C area

,

, and

is indicated by

대(versus) N _E = N _B = N _C = 3이고

=

=

= 0.42eV, W _EB = W _CB = 26

및 V _E = V _B = V _C = 0V인 n-형 QWRTT의 에너지를 도시한다. T ₁ 은 베이스와 컬렉터 사이(또는 베이스와 이미터 사이)의 싱글-배리어 구조(single-barrier structure)에 대한 투과 계수이다. T ₂ 는 이미터와 컬렉터 사이의 더블-배리어 구조(double-barrier structure)에 대한 투과 계수이다. T ₂ 는 공진 터널링 효과를 나타낸다(resonant tunneling effect). 주입된 전자가 E ₁ 의 에너지를 가질 때, T ₂ 는 100%의 최대치에 도달한다. 디바이스는 "공진 상태에"(in resonance) 있다고 말할 수 있고, 이미터와 컬렉터 사이에 전압 차가 존재하면 더블-배리어 구조를 통해 최대량의 전류가 흐를 수 있다. T ₂ 는 E ₁ 에서 벗어날 수록 급격하게 감소한다.In some embodiments, emitter region 111 , base region 112 and collector region 113 (shown in FIG. 1 ) each include three metal quantum wires buried in a semiconductor along the EBC direction. 6 is electron transmission coefficient and 1-D DOS

versus N _E = N _B = N _C = 3 and

=

=

= 0.42 eV, W _EB = W _CB = 26

and the energy of an n-type QWRTT where V _E = V _B = V _C = 0V. T ₁ is the transmission coefficient for a single-barrier structure between base and collector (or between base and emitter). T ₂ is the transmission coefficient for a double-barrier structure between the emitter and the collector. T ₂ represents a resonant tunneling effect (resonant tunneling effect). When the injected electron has an energy of E ₁ , T ₂ reaches a maximum value of 100%. The device can be said to be "in resonance", and the maximum amount of current can flow through the double-barrier structure if there is a voltage difference between the emitter and collector. T ₂ rapidly decreases as it moves away from E ₁ .

The barrier width of the single-barrier structure is narrower than the combined barrier width of the double-barrier structure. As shown in FIG. 6 , T ₂ is smaller than T ₁ at most energy values. T ₂ becomes much greater than T ₁ only when the energy is near E ₁ and the device is in resonance. According to Fermi's Golden Rule, the tunneling current is proportional to the transmission coefficient. The base leakage current flowing in the single-barrier structure between the base and the collector (or between the base and the emitter) is proportional to T ₁ , and the device driving current flowing in the double-barrier structure between the emitter and the collector ( device driving current) is proportional to T ₂ . The one-dimensional (1-D) density of states, σ _1-D , is maximum at E ₁ and drops off rapidly beyond E ₁ . Both T ₂ and σ _1-D are maximal when the energy is around E1. QWRTT can have a large drive current and a small base leakage current because (a) the current conduction mechanism is a resonant tunneling effect and (b) the emitter and collector have a one-dimensional quantum wire structure with a one-dimensional density of states.

=

=

= 0.42eV, W _EB = W _CB = 26

, V _E = 0 V 및 V _C = 1mV인 n-형 QWRTT의 전송 I-V곡선을(transfer I-V curve) 도시한다. 디바이스 구동 전류(I _CE )는 컬렉터 단자(123) 및 이미터 단자(121) 사이의 전류이다(도 1에 도시됨). I _CE 는 전자 전류(electron current I _CEe ) 및 정공 전류(hole current I _CEh )가 결합된 전류, 즉, I _CE = I _CEe + I _CEh 이다. 전자와 정공 전류는 V _B 의 변화에 대해 다르게 행동하기 때문에, n-형 디바이스는 전자들이 다수의 캐리어이고 정공 전류가 동작 범위에서 항상 전자 전류 보다 작도록 설계된다. 본 발명에 표시된 모든 시뮬레이션 결과는 300°K의 온도에서 수행된다. 대부분의 재료 특성은 양자학적 터널링 효과가 온도에 무관해도 온도에 따라 좌우된다.7a shows that N _E = N _B = N _C = 3,

=

=

= 0.42 eV, W _EB = W _CB = 26

, the transfer IV curve of the n-type QWRTT with V _E = 0 V and V _C = 1 mV. The device drive current ( I _CE ) is the current between the collector terminal 123 and the emitter terminal 121 (shown in FIG. 1). I _CE is a combined current of electron current I _CEe and hole current I _CEh , that is, I _CE = I _CEe + I _CEh . Since electron and hole currents behave differently to changes in V _B , n-type devices are designed so that electrons are the majority carriers and the hole current is always less than the electron current over the operating range. All simulation results presented herein are performed at a temperature of 300°K. Most material properties are temperature dependent, even though the quantum tunneling effect is temperature independent.

The electron current ( I _CEe ) reaches a peak when V _B is approximately 0V. When V _B is in the range of [0,50] mV, I _CEe decreases as V _B increases. I _CEe exhibits a negative differential resistance (NDR) phenomenon due to the resonant tunneling effect. The peak-to-valley current ratio is about three orders of magnitude to introduce an on/off current ratio. The hole current ( I _CEh ) also exhibits the NDR phenomenon when V _B is in the [-50,0] mV range due to the resonant tunneling effect.

Swing S is defined as the change in the control voltage (the gate voltage ( V _G ) of a MOSFET or the base voltage ( V _B ) of a QWRTT) required to change the device current by one decade. do. A small swing means that the transmission IV curve has a steep slope. As shown in FIG. 7A, the swing has a very small value when V _B is around 0 V. For example, when V _B is in the positive range of [0, 5] mV, S = 3 mV/dec, and when V _B is in the negative range of [-5, 0] mV, S = 7.4 mV/dec. am. The swing is required to be small so that the transistor can switch between on and off with small changes in the control voltage. Accordingly, power supply voltage and power consumption can be reduced. Theoretically, the swing below the minimum threshold of a conventional MOSFET at room temperature is 60mV/dec. The swing of the QWRTT is due to two main factors that are much smaller than that of the MOSFET: (a) resonant tunneling and (b) one-dimensional density of states.

7B plots V _B versus device drive current ( I _CE ) on a linear scale for the same device with V _C = V _CC and V _E = 0V. The supply voltage ( V _CC ) is assumed to be 50mV. The device drive current is maximum when V _B is approximately 0V. The current drops rapidly when V _B moves away from 0V. The IV curve looks like a nearly symmetrical impulse for V _B = 0V. QWRTT is the only known device with an impulse-like IV characteristic curve. The device turns on when V _B = 0 V and turns off when V _B equals +V _CC or -V _CC . When E ₁ is aligned in the E/B/C region (ie, E _1E = E _1B = E _1C ), QWRTT is a normally on transistor.

The on voltage V _ON is defined as the base-emitter voltage ( V _BE ) when the QWRTT is on, or the base voltage ( V _B ) when VE = _0V . A normally-on transistor with V _ON = 0V is on when V _B = VE = _0V . However, this does not mean that the device current is maximum when V _B = 0V. The device current of a normally-on device in the simulation is maximum when V _B is around 0 V, but may not be exactly 0 V. For example, as shown in FIG. 7A , I _CEe is maximum when V _B = -1 mV, and as shown in FIG. 7B , I _CE is maximum when V _B = -2 mV. Since the value of this V _B is close to 0V, V _ON is regarded as 0V in the digital circuit invention. V _ON is primarily used to distinguish between normally-on transistors and enhancement-mode transistors. For example, a device with V _ON = 0V is a normally on transistor. A device with positive V _ON is an enhancement-mode transistor that turns on when V _BE is positive (ie, V _CC ). A device with negative V _ON is an enhancement-mode transistor that turns on when V _BE is negative (ie - V _CC ).

Figure 7c shows the output characteristics of the same device with V _E = V _B = 0V. DC current gain ( h _FE ) is the amplification factor of the transistor. It is the ratio of the device drive current and input current. The input current is the base current ₍ I B ) composed of the base-collector current ( I _BC ) and the base-emitter current ( I _BE ). Since V _BE = 0V, I _BE = 0 and I _B = I _BC . The DC current gain ( h _FE = I _CE / I _B ) is in the operating range of 7 to 28. The device driving current ( I _CE ) flowing through the double-barrier structure is greater than the base current ( I _B ) flowing through the single-barrier structure, which is due to the resonant tunneling effect and the one-dimensional density of states of the quantum wires in the emitter and collector regions. .

=

=

= 0.24eV, W _EB = W _CB = 26

, V _E = 0V, 및 V _C = -1mV인 p-형 QWRTT의 전송 I-V 곡선을 도시한다. 디바이스 구동 전류(I _EC )는 이미터 단자(121) 및 컬렉터 단자(123) 사이의 전류이다(도 1에 도시됨). I _EC 는 정공 전류(I _ECh ) 및 전자 전류(I _ECe )를 합한 전류, 즉, I _EC = I _ECh + I _ECe 이다. p-형 QWRTT에서, 금속 페르미 준위(E _F )는 전도대 가장자리보다 가전자대 가장자리에 더 가깝기 때문에, 1차 캐리어들은 정공들이다. 전자 전류는 항상 작동 범위에서 정공 전류보다 작다. 정공 전류(I _ECh )는 최대이고, 디바이스는 V _B 가 0 V일 때 공진 상태에 있다. 정공 전류(I _ECh )는 V _B 가 [-50, 0]mV의 범위에 있을 때 NDR 현상을 나타낸다. 피크 대 밸리 전류 비는 약 두 자릿수이다. 전자 전류(I _CEe )는 V _B 가 [0, 50]mV의 범위에 있을 때 NDR 현상을 나타낸다. 정공 전류(I _CEh )는 V _B 가 0 V에 가까울 때 작은 스윙을 갖는다. V _B 가 [-5, 0]mV의 음의 범위에 있을 때 S = 3.3mV/dec이고, V _B 가 [0, 5]mV의 양의 범위에 있을 때 S = 8.1mV/dec이다.8a shows that N _E = N _B = N _C = 3,

=

=

= 0.24 eV, W _EB = W _CB = 26

, V _E = 0 V, and V _C = -1 mV, showing the transmission IV curve of the p-type QWRTT. The device drive current ( I _EC ) is the current between the emitter terminal 121 and the collector terminal 123 (shown in FIG. 1). I _EC is the sum of the hole current ( I _ECh ) and the electron current ( I _ECe ), that is, I _EC = I _ECh + I _ECe . In p-type QWRTT, the primary carriers are holes because the metallic Fermi level ( E _F ) is closer to the valence band edge than the conduction band edge. The electron current is always less than the hole current in the operating range. The hole current ( I _ECh ) is at its maximum and the device is in resonance when V _B is 0 V. The hole current ( I _ECh ) exhibits NDR when V _B is in the range of [-50, 0] mV. The peak-to-valley current ratio is in the order of two orders of magnitude. The electron current ( I _CEe ) exhibits the NDR phenomenon when V _B is in the range of [0, 50] mV. The hole current ( I _CEh ) has a small swing when V _B is close to 0 V. When V _B is in the negative range of [-5, 0] mV, S = 3.3 mV/dec, and when V _B is in the positive range of [0, 5] mV, S = 8.1 mV/dec.

Figure 8b shows the device drive current ( I _EC ) on a linear scale versus V _B for the same device with V _C = -V _CC = -50mV and V _E = 0V. Driving The driving current is maximum when V _B is approximately 0 V. The current rapidly decreases when V _B moves away from 0V. The impulse-like IV curve looks like an almost symmetrical impulse for V _B = 0V. When V _B = V _ON = 0V, the device is on, and when V _B is +V _CC or -V _CC , the device is off. A p-type QWRTT is a normally on transistor with V _ON = 0 V when E ₁ is aligned in the E/B/C region (ie, E _1E = E _1B = E _1C ).

Figure 8c shows the output characteristics of the same device where V _E = V _B = 0V. Since the base-collector current ( I _BC ) is zero due to V _BE = 0V, the base current ( I _B ) is equal to the base-collector current ( I _BC ). The DC current gain ( h _FE = I _EC / I _B ) ranges from 1.5 to 12 within the operating range, which is smaller than that of n-type devices because the hole effective mass is larger than the electron effective mass of silicon. Since both devices in FIGS. 7c and 8c have the same dimensions, the effective mass is the main difference between the n-type and p-type devices in the simulation.

7c and 8c show output characteristics of n- and p-type normally-on QWRTTs. The base current ( I _B ) is | While increasing continuously as V _C | increases, the device drive current | It saturates when V _C | is greater than about 30 mV. In the saturation region, the device drive current | It remains approximately constant with respect to changes in V _C | Therefore, scaling down of the supply voltage ( V _CC ) can reduce both dynamic and static power consumption without significant performance degradation because the device drive current of the normally-on transistor in the saturation region is almost independent of V _CC . .

=

=

= 0.42eV 및 W _EB = W _CB = 26

의 동일한 디바이스 파라미터들을 갖는다. 그러나, 그들은 다른 N _E 및 N _C 값, 예를 들어, Q1, Q2 및 Q3에 대해 (N _E , N _B , N _C ) = (2, 3, 2), (3, 3, 3) 및 (5, 3, 5)를 각각 가진다. 도 9는 V _E = 0V 및 V _C = 1mV 인 3개의 QWRTT들의 전송 I-V 곡선(즉, I _CEe 대 V _B )을 도시한다. (N _E , N _B , N _C ) = (3, 3, 3)인 Q2의 경우, E ₁ 은 정렬 상태이고, Q2는 노멀리 온 트랜지스터이다. (N _E , N _B , N _C ) = (5, 3, 5)인 Q3의 경우, E ₁ 은 정렬되지 않는다. V _B 가 약 50mV일 때, I _CEe 는 최대이다. 전원 전압V _CC 가 50 mV라고 가정한다. V _B = V _ON = V _CC = 50mV 일 때 Q3는 켜져있고, V _B = 0V 일 때 Q3는 꺼져있다. 따라서, Q3는 양의 V _ON 에서 인핸스먼트 모드 트랜지스터이다. (N _E , N _B , N _C ) = (2, 3, 2)인 Q1의 경우, E ₁ 은 정렬되지 않는다. V _B 가 약 -50mV일 때, I _CEe 는 최대이다. V _B = V _ON = -V _CC = -50mV일 때 Q1은 켜져있고, V _B = 0V일 때 Q1은 꺼져있다. 따라서, Q1은 음의 V_ON에서 인핸스먼트 모드 트랜지스터이다. 도 9는 E/B/C영역에 있는 양자 와이어들(N _E , N _B , N _C )의 수를 변경함으로써, QWRTT가 V _ON = 0V인(Q2와 같은) 노멀리 온 트랜지스터, 양의 V _ON 인(Q3와 같은) 인핸스먼트 모드 트랜지스터, 또는 음의 V _ON 인(Q1과 같은) 인핸스먼트 모드 트랜지스터로 구성될 수 있음을 보여준다. E/B/C 영역에서 양자 와이어들(N _E , N _B , N _C )의 개수는 도 4a의 SiO₂ 층(405)과 같은 주입 마스크층에 의해 제어된다. (N _E , N _B , N _C )의 값들은 어떠한 추가 프로세스 단계가 요구되지 않는 레이아웃 설계로(layout design) 제어될 수 있다.In some embodiments, QWRTT can be configured as an enhancement mode transistor by having E ₁ out of alignment in the E/B/C region. Since E ₁ depends on the superlattice size and potential barrier height, E ₁ can be modified by changing the number of quantum wires or the Schottky barrier height in the E/B/C region. Let's look at an example of three n-type QWRTTs (Q1, Q2 and Q3). They N _B = 3,

=

=

= 0.42 eV and W _EB = W _CB = 26

has the same device parameters of However, they have ( NE , N B _, N C _{) =} (2, 3, 2), (3 _, 3, 3) and ₍ 5, 3, 5) respectively. 9 shows the transmission IV curves (ie, I _CEe versus V _B ) of three QWRTTs with V _E = 0V and V _C = 1 mV. For Q2 where ( N _E , N _B , N _C ) = (3, 3, 3), E ₁ is in alignment and Q2 is a normally-on transistor. For Q3 where ( N _E , N _B , N _C ) = (5, 3, 5), E ₁ is not sorted. When V _B is about 50mV, I _CEe is at its maximum. Assume that the supply voltage V _CC is 50 mV. When V _B = V _ON = V _CC = 50mV, Q3 is on, and when V _B = 0V, Q3 is off. Thus, Q3 is an enhancement mode transistor at positive V _ON . For Q1 where ( N _E , N _B , N _C ) = (2, 3, 2), E ₁ is not sorted. When V _B is around -50mV, I _CEe is at its maximum. Q1 is on when V _B = V _ON = -V _CC = -50mV, and Q1 is off when V _B = 0V. Thus, Q1 is an enhancement mode transistor at negative V _ON . 9 shows that by changing the number of quantum wires ( NE , N _B , N _C ) in the E/B/C region, QWRTT is a normally-on transistor with V _{ON =} 0V (like Q2), positive V It can be configured with an enhancement mode transistor that is _ON (such as Q3), or an enhancement mode transistor that is negative V _ON (such as Q1). The number of quantum wires NE _, N _B , and N _C in the E/B/C region is controlled by an implantation mask layer such as the SiO ₂ layer 405 in FIG. 4A. The values of ( N _E , N _B , N _C ) can be controlled with a layout design that requires no additional process step.

=

= 0.42eV 및 W _EB = W _CB = 26

의 동일한 디바이스 파라미터를 갖는다. 그러나, 그들은 다른

값, 예를 들어, Q4, Q5 및 Q6 각각에 대해 (

,

,

) = (0.42, 0.26, 0.42) eV, (0.42, 0.42, 0.42) eV 및 (0.42, 0.6, 0.42)를 각각 가진다. 도 10은 V _E = 0 V 및 V _C = 1 mV인 3개의 QWRTT들에 대한 전송 I-V 곡선(즉, I _CEe 대 V _B )을 도시한다. (

,

,

) = (0.42, 0.42, 0.42)eV인 Q5의 경우, E ₁ 은 정렬 상태이고, Q5는 노멀리 온 트랜지스터이다. (

,

,

) = (0.42, 0.6, 0.42)eV인 Q6의 경우, E ₁ 은 정렬되지 않는다. I _CEe 는 V _B 가 약 50mV일 때 최대이다. Q6는 V _B = V _ON = V _CC = 50mV일 때 켜져있고, Q6는 V _B = 0V일 때 꺼져있다. 따라서, Q6는 양의 V_ON인 인핸스먼트 모드 트랜지스터이다. (

,

,

) = (0.42, 0.26, 0.42)eV인 Q4의 경우, E ₁ 은 정렬되지 않는다. I _CEe 는V _B 가 약 -50mV일 때 최대이다. Q4는 V _B = V _ON = -V _CC = -50mV일 때 켜져있고, Q4는 V _B = 0V일 때 꺼져있다. 따라서, Q4는 음의 V _ON 인 인핸스먼트 모드 트랜지스터이다. 도 10은 E/B/C 영역에서 쇼트키 배리어 높이(즉,

,

,

)를 변경함으로써, QWRTT가 (Q5와 같은) 노멀리 온 트랜지스터, 양의 V _ON 인(Q6와 같은) 인핸스먼트 모드 트랜지스터, 또는 음의 V _ON 인(Q4와 같은) 인핸스먼트 모드 트랜지스터로 구성될 수 있음을 보여준다. 그러나, (

,

,

)에 대한 변화를 제공하기 위해 추가 프로세스 단계가 제공된다.Let's look at another example of three n-type QWRTTs (Q4, Q5 and Q6). they are N _E = N _B = N _C = 3,

=

= 0.42 eV and W _EB = W _CB = 26

has the same device parameters of However, they are different

For each of the values, e.g., Q4, Q5, and Q6 (

,

,

) = (0.42, 0.26, 0.42) eV, (0.42, 0.42, 0.42) eV and (0.42, 0.6, 0.42) respectively. 10 shows transmission IV curves (ie, I _CEe versus V _B ) for three QWRTTs with V _E = 0 V and V _C = 1 mV. (

,

,

) = (0.42, 0.42, 0.42) eV, E ₁ is in alignment and Q5 is a normally-on transistor. (

,

,

) = (0.42, 0.6, 0.42) eV, E ₁ is not aligned. I _CEe is maximum when V _B is about 50mV. Q6 is on when V _B = V _ON = V _CC = 50mV, and Q6 is off when V _B = 0V. Thus, Q6 is an enhancement mode transistor with positive V _ON . (

,

,

) = (0.42, 0.26, 0.42) eV, E ₁ is not aligned. I _CEe is maximum when V _B is around -50mV. Q4 is on when V _B = V _ON = -V _CC = -50mV, and Q4 is off when V _B = 0V. Thus, Q4 is an enhancement mode transistor with negative V _ON . 10 shows the height of the Schottky barrier in the E / B / C region (ie,

,

,

), QWRTT can be configured with a normally on transistor (such as Q5), an enhancement mode transistor with positive V _ON (such as Q6), or an enhancement mode transistor with negative V _ON (such as Q4). show that you can however, (

,

,

), an additional process step is provided to provide a change to

Similarly, a p-type QWRTT can also be configured as an enhancement mode transistor if E1 is not aligned in the E/B/C region. 11 shows the circuit symbol of QWRTT. QWRTT has two device types, n-type and p-type. The n-type and p-type QWRTTs can be configured with a normally on transistor with V _ON = 0V, an enhancement mode transistor with positive V _ON or an enhancement mode transistor with negative V _ON . Thus, a QWRTT includes two transistor families (normally on transistors and enhancement mode transistors).

In total, QWRTT has six different device variants. The letter "N" or "P" in a circuit symbol indicates its device type, i.e., n-type or p-type. A plus or minus sign in a circuit symbol indicates the sign of its V _ON value. If the circuit symbol does not have a plus or minus sign, the device is a normally on transistor. For example, “P” means the device is p-type normally on QWRTT, and “N+” means it is n-type enhancement mode QWRTT with positive V _ON .

=

, 그리고, W _EB = W _CB ), 이미터 단자(121)와 컬렉터 단자(123)는 상호 교환 가능하다. 캐리어는 디바이스가 온 될 때 이미터 영역(111)에서 컬렉터 영역(113)으로 이동하기 때문에, 이미터 단자(121) 및 컬렉터 단자(123)는 캐리어 흐름 방향에 의해 결정된다. 일반적으로 컬렉터 단자(123)는 n-형 QWRTT의 경우 이미터 단자(121)보다 높은 전위를 갖고, p-형 QWRTT의 경우 낮은 전위를 갖는다. 단자들은 쉽게 식별할 수 있다, 그래서 그것들의 라벨(label)은 단순화를 위해 본 발명의 회로도에서 생략된다.Referring back to FIG. 1 , the QWRTT consists of three terminals labeled “E” for emitter terminal 121, “B” for base terminal 122 and “C” for collector terminal 123. have terminals When the device structure is symmetric (i.e. N _E = N _C ,

=

, and W _EB = W _CB ), the emitter terminal 121 and the collector terminal 123 are interchangeable. Since carriers move from the emitter region 111 to the collector region 113 when the device is turned on, the emitter terminal 121 and the collector terminal 123 are determined by the carrier flow direction. In general, the collector terminal 123 has a higher potential than the emitter terminal 121 in the case of n-type QWRTT, and has a lower potential in the case of p-type QWRTT. The terminals are easily identifiable, so their labels are omitted from the circuit diagrams of the present invention for simplicity.

The QWRTT has six different device variants shown in Figure 11 while the MOSFETs used in digital circuits have only two device variants (n- and p-channel devices), both of which are in enhancement mode. Therefore, QWRTT circuit designs can be more versatile and efficient than CMOS circuit designs. It is possible to construct an entire logic circuit using only one type of device. As described above, both n-type and p-type QWRTTs consist of normally-on transistors with V _ON = 0 V, enhancement-mode transistors with positive V _ON , or enhancement-mode transistors with negative V _ON . It can be. The p-type enhancement mode QWRTT can be replaced by an n-type enhancement mode QWRTT with the same V _ON because two devices with the same V _ON perform the same logic function. Moreover, both n-type and p-type normally-on QWRTTs turn on when V _B = 0 V and turn off when V _B is +V _CC or -V _CC . Both devices have impulse-like transfer IV curves, which are approximately symmetric about V _B = 0 V. The p-type normally-on QWRTT can be replaced by the n-type normally-on QWRTT since both devices perform the same logic function. Therefore, a QWRTT digital circuit can be constructed using only one type of device, and an n-type device is clearly the choice.

Constructing a digital circuit using only one type of device has the following key advantages over a combination of both n-type and p-type devices: (1) Better circuit performance—in silicon and most other semiconductors, electrons have a lower effective mass and higher mobility than holes. The n-type QWRTT has a larger drive current, a higher on/off current ratio, and a larger DC current gain than a p-type QWRTT with the same device dimensions. Thus, circuits constructed using n-type devices outperform circuits constructed using a combination of both n-type and p-type devices. (2) Better current matching—p-type devices are generally weaker than n-type devices because the hole mobility is smaller than the electron mobility. A p-type device needs to be larger to deliver the same drive current as an n-type device. If only one type of device is being used, there is no current balance problem between n-type and p-type devices. (3) Lower manufacturing cost - When only one type of device is required for circuit design, manufacturing process steps are reduced, cycle time is shortened, and fabrication required to implement both n-type and p-type devices. Compared to the process, the manufacturing cost can be lowered.

The speed and power consumption of digital circuits are closely related to the supply voltage. In general, both speed and power consumption increase when the supply voltage increases, and vice versa. The chip's digital circuitry can be divided into several areas with different priorities for speed and power consumption. The supply voltage may be different in different areas. For example, since speed is emphasized in critical path circuits, the supply voltage in the critical-path region can be higher to achieve higher circuit speeds. In non-critical paths, the supply voltage can be lowered to reduce power consumption. As a result, the signal level may be different in different areas. Level shifting circuits can be used to equalize signal levels when passing signals between different areas. Variations in the supply voltage generally do not affect the normally-on QWRTT's logic function. On the other hand, variations in the supply voltage may affect the logic function of the enhancement mode QWRTT. The value of V _ON for enhancement mode QWRTT is typically V _CC or -V _CC . Since the supply voltage can have different values in different regions, the enhancement mode QWRTTs have different V _ON to operate at different supply voltages. It can be configured to have a value.

Digital circuits can generally be divided into combinational logic circuits and sequential logic circuits. Combinational logic has the property that the output is only a function of the current input. This contrasts with sequential logic, where the output is a function of both the current and previous inputs. In other words, sequential logic has memory, but combinatorial logic does not. Any combinational logic function can be implemented as a network of logic gates. {AND, NOT}, {OR, NOT}, {NAND}, and {NOR} are functionally complete sets of logical operators. The above logic gates (including AND, OR, NOT, NAND and NOR) and the three memory elements including latches, registers and SRAM cells are digital using QWRTT. It is used in the following example to illustrate that the circuit can be implemented efficiently. It should be noted that QWRTT is not limited to the example described below. Instead, QWRTT is suitable for constructing many different logic circuits.

Non-inverting logic gates such as AND and OR gates can be efficiently implemented using QWRTT. On the other hand, CMOS logic needs to combine two inverting logic gates to form one inverting logic gate. For example, an AND gate is obtained by combining a NAND gate and a NOT gate. 12A shows a circuit diagram of a 2-input AND gate 1201, and FIG. 12B shows a circuit diagram of a 2-input OR gate 1202. Both gates are configured using n-type and p-type normally-on QWRTTs. Assume that a high voltage, such as the supply voltage ( V _CC ), represents a logic one, and a low voltage, such as the ground voltage ( GND ), represents a logic zero. Similar to the complementary static CMOS logic gates, each gate is a pull-down network (pull-down network 1211 of AND gates 1201 and OR gates 1202). such as the pull-down network 1212 of ) and the pull-up network (pull-up network 1213 of the AND gate 1201 and pull-up network 1214 of the OR gate 1202). such as). The function of the pull-down network is to connect the output to GND when the output is a logic 0, and the function of the pull-up network is to provide a connection between the output and V _CC when the output is a logic 1. Pull-down networks 1211-1212 are configured using n-type normally on QWRTT 1221, and pull-up networks 1213-1214 are configured using p-type normally on QWRTT 1222. do. The n-type QWRTTs 1221 are connected in parallel in the pull-down network 1211 of AND gates 1201 and in series in the pull-down network 1212 of OR gates 1202. The p-type QWRTT 1222 is connected in series in the pull-up network 1213 of the AND gate 1201 and in parallel in the pull-up network 1214 of the OR gate 1202. On the other hand, n-channel MOSFETs connected in series correspond to an AND function, and those connected in parallel represent an OR function. P-channel MOSFETs connected in series correspond to the NOR function, and those connected in parallel represent the NAND function. The circuit configuration of the AND gate shown in FIG. 12A is similar to a CMOS NOR gate, and the OR gate shown in FIG. 12B is similar to a CMOS NAND gate.

As mentioned earlier, both the n-type and p-type normally-on QWRTTs are on when V _B = 0 V, and off when V _B is +V _CC or -V _CC . Since both devices perform the same logic function, the p-type normally-on QWRTT can be replaced with an n-type normally-on QWRTT. The AND gate 1201 and the OR gate 1202 replace the p-type normally-on QWRTT 1222 of the pull-up networks 1213-1214 with n-type normally-on QWRTT using only the n-type QWRTT. can be implemented 13A shows a circuit diagram of a 2-input AND gate 1301, and FIG. 13B shows a circuit diagram of a 2-input OR gate 1302. The two circuits are similar to the pull-down network (such as pull-down network 1311 of AND gate 1301 and pull-down network 1312 of OR gate 1302) and the pull-up network (AND gate 1301 is implemented using only the n-type normally on QWRTT 1321 in the pull-up network 1313 of ) and the pull-up network 1314 of the OR gate 1302.

A NOT gate (i.e., an inverter) can be implemented using QWRTT. 14A shows n-type enhancement mode QWRTT 1421 with positive V _ON in pull-down network 1411 and p-type enhancement mode QWRTT 1422 with negative V _ON in pull-up network 1412. It shows a circuit diagram of the inverter 1401 including.

The inverter 1401 shown in FIG. 14A can be implemented using only n-type QWRTT by replacing the p-type enhancement mode QWRTT 1422 with an n-type enhancement mode QWRTT with the same V _ON . 14B shows n-type enhancement mode QWRTT 1421 with positive V _ON in pull-down network 1413 and n-type enhancement mode QWRTT 1423 with negative V _ON in pull-up network 1414. It shows a circuit diagram of the inverter 1402 including.

A digital buffer is a logic gate with one input and one output. Its output is always equal to its input. The main purpose of a buffer is to drive a large capacitive load or increase the propagation delay of a signal. The buffer can be implemented efficiently with only two QWRTTs, but four transistors are required to implement two cascaded inverters in CMOS. 15A shows a circuit diagram of a buffer 1501 comprising an n-type normally on QWRTT 1521 in a pull-down network 1511 and a p-type normally on QWRTT 1522 in a pull-up network 1512. show

The buffer 1501 shown in FIG. 15A can be implemented using only an n-type QWRTT by replacing the p-type normally-on QWRTT 1522 with an n-type normally-on QWRTT. 15B shows a circuit diagram of a buffer 1502 comprising a pull-down network 1513 and a pull-up network 1514. Each network includes an n-type normally on QWRTT 1521.

General-purpose logic gates such as NAND and NOR gates commonly used in CMOS digital circuits can be implemented using QWRTT. 16A shows a circuit diagram of a 2-input NAND gate 1601, and FIG. 16B shows a circuit diagram of a 2-input NOR gate 1602. Both gates are configured using n-type and p-type enhancement mode QWRTT. Similar to complementary static CMOS gates, each gate has a pull-down network (such as pull-down network 1611 of NAND gates 1601 and pull-down network 1612 of NOR gates 1602) and a pull-down network of up networks (such as the pull-up network 1613 of NAND gates 1601 and the pull-up network 1614 of NOR gates 1602). Pull-down networks 1611-1612 are configured using n-type enhancement mode QWRTT 1621 with positive V _ON , and pull-up networks 1613-1614 are configured using p-type enhancement mode with negative V _ON . ment mode is configured using QWRTT 1622.

NAND gate 1601 and NOR gate 1602 can be implemented using only n-type QWRTT by replacing the p-type enhancement mode QWRTT 1622 with an n-type enhancement mode QWRTT with the same V _ON . 17A shows a circuit diagram of a 2-input NAND gate 1701, and FIG. 17B shows a circuit diagram of a 2-input NOR gate 1702. The pull-down network 1711 of NAND gates 1701 and the pull-down network 1712 of NOR gates 1702 are configured using n-type enhancement mode QWRTT 1721 with positive V _ON . The pull-up network 1713 of the NAND gate 1701 and the pull-up network 1714 of the NOR gate 1702 are configured using n-type enhancement mode QWRTT 1722 with negative V _ON .

All of the QWRTT logic gates described above are called complementary QWRTT logic gates, combining dual pull-down and pull-up networks. For dual networks, a parallel connection of transistors in a pull-down network corresponds to a series connection of corresponding devices in a pull-up network, and vice versa. A pull-down network can create a "strong zero" by pulling the output down to GND , and a pull-up network can create a "strong one" by charging the output to the supply voltage ( V _CC ). can create When the pull-down network is configured using normally-on QWRTT, the pull-up network is also configured using normally-on QWRTT. Normally-on QWRTTs used in pull-down and pull-up networks can be n-type, p-type, or a combination of both types. When the pull-down network is configured using enhancement mode QWRTT with positive V _ON , the pull-up network is configured using enhancement mode QWRTT with negative V _ON . The enhancement mode QWRTT used in pull-down and pull-up networks can be n-type, p-type or a combination of both types. The pull-down and pull-up networks are mutually exclusive since one or one of the networks is conducting in the steady state. Since there is no static current between the power supply and GND, the static power loss is zero. A path always exists between the output node and the power supply when the output is "1", and between the output node and GND when the output is "0". The output node is always a steady-state, low-impedance node. This circuit has good noise immunity because the output node exhibits full rail-to-rail swing.

Pass transistor logic is a popular and widely used alternative to complementary logic in CMOS digital circuit design. Pass transistor logic attempts to reduce transistor count by having the main input drive the gate terminal as well as the source/drain terminals. This is in contrast to interactive logic, which allows the primary input to drive only the gate terminal. Some specific circuits, such as multiplexers and adders, can be implemented efficiently using pass transistor logic with fewer transistors.

The pass transistor logic can be efficiently implemented using QWRTT as shown in the following examples of XOR and XNOR gates. 18A shows a circuit diagram of a two-input XOR gate 1801 constructed using an n-type enhancement mode QWRTT 1811 with positive V _ON . 18B shows a circuit diagram of a two-input XNOR gate 1802 configured using an n-type enhancement mode QWRTT 1812 with negative V _ON . It can be seen that the pass transistor logic uses fewer transistors than the complementary logic which requires a pull-down and pull-up network. A pass transistor logic circuit can be implemented using an enhancement mode QWRTT with a combination of positive V _ON and negative V _ON .

The main drawback of pass transistor logic is the voltage drop across the pass transistor. The most popular solution is to use a transmission gate. The transfer gate of CMOS includes an n-channel device connected in parallel with a p-channel device. The transmission gate enables rail-to-rail swing with n-channel devices pulled down and p-channel devices pulled up.

)에 의해 제어되는 양방향 스위치(bilateral switch) 역할을 한다. 제어 신호(C)가 높으면 두 디바이스(1911-1912)는 모두 켜져, 입력 신호가 게이트를 통과할 수 있다. 제어 신호(C)가 낮으면 두 디바이스(1911-1912)가 모두 꺼져, 노드 A와 B 사이에 개방 회로(open circuit)가 생성된다.Transmission gates can be implemented using QWRTT. 19A shows a circuit diagram of a transfer gate 1901 constructed using n-type enhancement mode QWRTT 1911 with positive V _ON and p-type enhancement mode QWRTT 1912 with negative V _ON . The transmission gate is a control signal ( C ) and its complement (

) to act as a bilateral switch controlled by When control signal C is high, both devices 1911-1912 are on, allowing the input signal to pass through the gate. When control signal C is low, both devices 1911-1912 are turned off, creating an open circuit between nodes A and B.

The transfer gate 1901 shown in FIG. 19A can be implemented using only n-type QWRTT by replacing the p-type enhancement mode QWRTT 1912 with an n-type enhancement mode QWRTT with the same V _ON . 19B shows a circuit diagram of a transmission gate ₁₉₀₂ constructed using n -type enhancement mode QWRTT 1911 with positive V _ON and n-type enhancement mode QWRTT 1913 with negative V ON.

Memories are generally built using the positive feedback of bistable circuits. 20A shows a circuit schematic of a bistable circuit 2001 comprising two cross-coupled inverters 2011-2012. The output of the second inverter 2012 is connected to the input of the first inverter 2011. A pair of cross-coupled inverters creates a bistable circuit with two stable states representing 0 and 1. In the absence of a trigger, the circuit maintains a single state and thus remembers a value. To change the state of the circuit, a trigger pulse is applied to input D that overwhelms the feedback loop.

The bistable circuit 2001 shown in FIG. 20A can be implemented using QWRTT as shown in FIGS. 20B and 20C for two different approaches. FIG. 20B is a circuit diagram of a bistable circuit 2002 in which inverters 2021-2022 have the same design as QWRTT inverter 1401 as shown in FIG. 14A. 20C is a circuit diagram of a bistable circuit 2003 in which inverters 2031-2032 have the same design as the QWRTT inverter 1402 as shown in FIG. 14B. 14 b. The bistable circuit 2002 shown in FIG. 20B is constructed using both n-type and p-type QWRTTs, whereas the bistable circuit 2003 shown in FIG. 20C is constructed using only n-type QWRTTs.

A buffer and two cascaded inverters have the same logic function. Thus, the buffer can be used to replace two cascaded inverters. 21A shows a circuit diagram of a bistable circuit 2101 including a buffer 2111. The output of the buffer 2111 is connected to the input of the same buffer 2111 to generate positive feedback and save the state. The bistable circuit 2101 can be implemented using QWRTT as shown in FIGS. 21B and 21C for two different approaches. FIG. 21B shows a circuit diagram of a bistable circuit 2102 in which the buffer 2121 has the same design as the QWRTT buffer 1501 shown in FIG. 15A. 21C shows a circuit diagram of a bistable circuit 2103 in which the buffer 2131 has the same design as the QWRTT buffer 1502 shown in FIG. 15B. The bistable circuit 2102 shown in FIG. 21B is constructed using both n-type and p-type QWRTTs, whereas FIG. 21C is constructed using only n-type QWRTTs.

Three storage elements (including latches, registers and SRAM cells) that use bistable circuits to store data are described below to illustrate that memory circuits can be efficiently implemented using QWRTT. A bistable circuit usually includes two cross-coupled inverters. The logic function of two inverters connected in cascade is the same as that of the buffer. The buffer can replace two cascaded inverters, resulting in significant reductions in transistor count (ie, from four to two), area, propagation delay, and power consumption. The above advantage is not available in CMOS because the buffer is actually implemented as two inverters connected in cascade. These single-bit storage elements are the basic building blocks of larger memory circuits such as latch arrays, shift registers and SRAMs. Memory circuitry occupies a large portion of the chip area in today's microprocessors, and the trend continues to increase. Therefore, implementing a memory circuit using QWRTT has significant advantages over using a CMOS device.

A latch is a level-sensitive storage element. When the clock signal is high, the latch passes the input to the output, and the latch is in transparent mode. When the clock is low, the input data sampled on the falling edge of the clock is held stable at the output, and the latch is in hold mode. A latch that operates under the above conditions is a positive latch. Similarly, a negative latch passes the input to the output when the clock is low. There are many different approaches to constructing a latch. 22A shows a circuit diagram of a latch 2201 comprising two inverters 2211-2212 and two transfer gates 2213-2214. When clock CLK is high, transfer gate 2213 is on. Input D is passed through two cascaded inverters 2211-2212 to output Q , the latch is in transmissive mode. At this stage, transmission gate 2214 is off and the feedback loop is open. The input signal does not need to overcome the feedback loop to write the memory, so transistor sizing is not critical to achieve correct functionality. When clock CLK is low, transfer gate 2213 is off and transfer gate 2214 is on. The feedback loop is active, and the latch is in hold mode.

The latch 2201 shown in FIG. 22A can be implemented using QWRTT as shown in FIGS. 22B and 22C for two different approaches. 22B shows a circuit diagram of a latch 2202 comprising two inverters 2221-2222 and two transfer gates 2223-2224. The two inverters 2221-2222 have the same design as the QWRTT inverter 1401 as shown in FIG. 14A. The two transfer gates 2223-2224 have the same design as the QWRTT transfer gate 1901 as shown in FIG. 19A. 22C shows a circuit diagram of a latch 2203 comprising two inverters 2231-2232 and two transfer gates 2233-2234. The two inverters 2231-2232 have the same design as the QWRTT inverter 1402 as shown in FIG. 14B. The two transfer gates 2233-2234 have the same design as the QWRTT transfer gate 1902 as shown in FIG. 19B. The latch 2202 shown in FIG. 22B is constructed using both n-type and p-type QWRTTs, whereas the latch 2203 shown in FIG. 22C is constructed using only n-type QWRTTs.

As previously discussed, the two cascaded inverters can be replaced with buffers. 23A shows a circuit diagram of a latch 2301 comprising a buffer 2311 and two transfer gates 2312-2313. The latch 2301 shown in FIG. 23A can be implemented using QWRTT as shown in FIGS. 23B and 23C for two different approaches. 23B shows a circuit diagram of a latch 2302 comprising a buffer 2321 and two transfer gates 2322-2323. The buffer 2321 has the same design as the QWRTT buffer 1501 as shown in FIG. 15A. The two transfer gates 2322-2323 have the same design as the QWRTT transfer gate 1901 as shown in FIG. 19A. 23C shows a circuit diagram of a latch 2303 comprising a buffer 2331 and two transfer gates 2332-2333. Buffer 2331 has the same design as QWRTT buffer 1502, as shown in FIG. 15B. The two transfer gates 2332-2333 have the same design as the QWRTT transfer gate 1902 as shown in FIG. 19B. The latch 2302 shown in FIG. 23B is constructed using both n-type and p-type QWRTTs, whereas the latch 2303 shown in FIG. 23B is constructed using only n-type QWRTTs.

Registers (sometimes called flip-flops) have a rising trigger edge and negative edge-triggered registers on clock transitions, for example in the case of positive edge-triggered registers. In the case of , it is an edge-triggered memory element that samples only the input at the falling trigger edge. The output then remains stable until the next clock transition. The most common approach to configuring registers is to use a master-slave configuration. Positive edge triggered registers include a positive latch (slave stage) and a cascaded negative latch (master stage). A negative edge triggered register can be constructed using the same principle by simply switching the order of the positive and negative latches. Since latches can be implemented using QWRTT, so can registers.

)과 셀 사이의 전류의 양방향 흐름을 허용한다. 액세스 트랜지스터(2413-2414)는 읽기 및 쓰기 동작(read and write operations) 동안 비트 셀의 접근을 제어하기 위해 워드 라인(word line)(WL)을 사용하여 활성화/비활성화된다.The fundamental building block within an SRAM (Static Random-Access Memory) array is an SRAM cell that stores a single bit of data. The most commonly used SRAM bit cell architecture is a 6- Transistor 6T SRAM Cell Figure 24A shows a 6T SRAM cell 2401 comprising two cross-coupled inverters 2411-2412 and two access transistors 2413-2414. Since SRAM cells contain bistable circuitry, they do not require periodic refresh like DRAM (Dynamic Random-Access Memory) to retain stored information, as long as power is supplied. The two access transistors 2413-2414 are connected to the bit lines ( BL and

) and allows bi-directional flow of current between the cells. Access transistors 2413-2414 are enabled/disabled using word lines ( WL ) to control access to bit cells during read and write operations.

SRAM has three modes of operation: retain, read and write. In hold mode, the word line is not asserted and the access transistor disconnects the cell from the bit line. In a read operation, both bit lines are pre-charged to a high voltage. The word line is then driven high to activate the access transistor. One of the bit lines is also pulled down by the cell, and a small voltage difference is created between the two bit lines. A sense amplifier is activated and captures the value of the bit line. In a write operation, the surrounding column driver circuit (column driver circuit) drives the bit line differently. The word line is then driven high to activate the access transistor. The bit line overwrites the logic state of the cell. To ensure proper operation, all transistors in an SRAM cell must be carefully sized so that the stored value is not destroyed in a read operation and the bit-line voltage can override the previous state of the bit cell in a write operation.

The SRAM cell 2401 shown in FIG. 24A can be implemented using QWRTT as shown in FIGS. 24B and 24C for two different approaches. 24B shows a circuit diagram of a 6T SRAM cell 2402 that includes two cross-coupled inverters 2421-2422 and two access transistors 2423-2424. The two inverters 2421-2422 have the same design as the QWRTT inverter 1401 as shown in FIG. 14A. 24C shows a circuit diagram of a 6T SRAM cell 2403 that includes two cross-coupled inverters 2431-2432 and two access transistors 2433-2434. The two inverters 2431-2432 have the same design as the QWRTT inverter 1402 as shown in FIG. 14B. The SRAM cell 2402 shown in FIG. 24B is constructed using both n-type and p-type QWRTTs, and the SRAM cell 2403 shown in FIG. 24C is constructed using only n-type QWRTTs.

As previously discussed, the two cascaded inverters can be replaced with buffers. 25A shows a single-ended three-transistor (3T) SRAM cell 2501 that includes a buffer 2511 and an access transistor 2512. The output of the buffer 2511 is connected to the input of the same buffer 2511 to generate positive feedback and store data. The 3T SRAM cell 2501 of FIG. 25A occupies a smaller area and requires fewer transistors than the 6T SRAM cell 2401 of FIG. 24A. Memory bit lines usually have heavy capacitive loading. Switching heavy bit lines consumes significant power in read and write operations. The single-ended design minimizes the number of bit lines. Since the 3T SRAM cell 2501 uses fewer transistors and bit lines than the conventional 6T SRAM cell, power consumption can be reduced.

The SRAM cell 2501 shown in FIG. 25A can be implemented using QWRTT as shown in FIGS. 25B and 25C for two different approaches. 25B shows a circuit diagram of a 3T SRAM cell 2502 including a buffer 2521 and an access transistor 2522. The buffer 2521 has the same design as the QWRTT buffer 1501 shown in FIG. 15A. 25C shows a circuit diagram of a 3T SRAM cell 2503 including a buffer 2531 and an access transistor 2532. Buffer 2531 has the same design as QWRTT buffer 1502 shown in FIG. 15B. The SRAM cell 2502 shown in FIG. 25B is constructed using both n-type and p-type QWRTTs, whereas the SRAM cell 2503 shown in FIG. 25C is constructed using only n-type QWRTTs.

The access transistor shown in Figs. 24A and 25A is an n-type enhancement mode QWRTT with positive V _ON . As previously discussed in the Pass Transistor Logic section, enhancement mode QWRTTs with negative V _ON can also be used as access transistors. When the access transistor has negative V _ON , the WL voltage is high to disable the access transistor in hold mode and enable the access transistor in read and write operations.

Claims (15)

One or more quantum wire resonant tunneling transistors (QWRTTs), wherein at least one of the QWRTTs:
emitter terminal;
base terminal;
collector terminal;
an emitter region connected to the emitter terminal;
a base area connected to the base terminal;
In the collector region connected to the collector terminal, at least one of the emitter region, the base region, and the collector region includes a plurality of metal quantum wires;
an emitter barrier region between the emitter region and the base region; and
A collector barrier region between the collector region and the base region;
digital circuit. According to claim 1,
input node;
output node;
a pull-down network comprising one or more QWRTTs; and
A pull-up network comprising one or more QWRTTs;
The pull-down network and the pull-up network form a dual network, and parallel connection of one or more QWRTTs in the pull-down network corresponds to serial connection of one or more QWRTTs in the pull-up network, or The serial connection of one or more QWRTTs in the pull-down network corresponds to the parallel connection of one or more QWRTTs in the pull-up network.
digital circuit. According to claim 2,
an input node of the complementary logic gate is connected to a base terminal of one or more QWRTTs in the pull-down network;
An input node of the complementary logic gate is connected to a base terminal of one or more QWRTTs in the pull-up network.
digital circuit. According to claim 2,
the pull-down network of the complementary logic gates includes one or more enhancement mode QWRTTs having a positive on-voltage V _ON ;
wherein the pull-up network of the complementary logic gates comprises one or more enhancement mode QWRTTs with negative V _ON .
digital circuit. According to claim 2,
the pull-down network of the complementary logic gates includes one or more normally on QWRTTs;
wherein the pull-up network of the complementary logic gates comprises one or more normally on QWRTTs.
digital circuit. According to claim 2,
the pull-down network of the complementary logic gates includes one or more n-type QWRTTs;
the pull-up network of the complementary logic gates comprises one or more n-type QWRTTs;
digital circuit. According to claim 2,
wherein the complementary logic gate comprises an AND gate, an OR gate, a NOT gate, a buffer, a NAND gate, a NOR gate, or a combination of at least two of the AND gate, OR gate, NOT gate, buffer, NAND gate, and NOR gate;
digital circuit. According to claim 1,
further comprising a pass transistor logic gate comprising one or more enhancement mode QWRTTs with positive V _ON or one or more enhancement mode QWRTTs with negative V _ON ;
digital circuit. According to claim 1,
A storage element comprising a bistable circuit for storing bits of data, said bistable circuit further comprising said storage element comprising one or more QWRTTs.
digital circuit. According to claim 9,
The bistable circuit comprises two inverters or one buffer,
digital circuit. According to claim 9,
The memory element,
two cross-coupled inverters formed by four enhancement mode QWRTTs;
two access transistors formed by two enhancement mode QWRTTs;
word line; and
It is characterized in that it comprises a 6-transistor (6T) SRAM cell including; two bit lines,
wherein the word line and the two bit lines are configured to address the SRAM cell and access stored data in read and write operations.
digital circuit. According to claim 9,
The storage element is:
a buffer formed by two normally-on transistors;
an access transistor formed by one enhancement mode transistor;
word line; and
It is characterized in that it comprises a 3-transistor (3T) SRAM cell including a; bit line,
wherein the word line and the bit line are configured to address the SRAM cell and access stored data in read and write operations.
digital circuit. According to claim 1,
the one or more QWRTTs include n-type and p-type devices;
Wherein the n-type and the p-type devices are configured as normally on transistors with V _ON = 0 V, enhancement mode transistors with positive V _ON , or enhancement mode transistors with negative V _ON ,
digital circuit. According to claim 13,
wherein the enhancement mode QWRTT has multiple V _ON values, and the enhancement mode QWRTT is configured to operate with multiple supply voltages.
digital circuit. According to claim 1,
The plurality of metal quantum wires are formed by implanting metal ions into open channels of a crystalline semiconductor, and a mask layer used for ion implantation is aligned in a lattice structure on a wafer surface.
digital circuit.

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