KR20230034832A - Display panel and electronic device including same - Google Patents

Abstract

Disclosed are a display panel and an electronic device including the same. A circuit layer of the display panel at least includes a first transistor and a second transistor. The first transistor includes: a first oxide semiconductor pattern; a gate electrode overlapped with the first oxide semiconductor on the first oxide semiconductor pattern; a first electrode coming in contact with one side of the first oxide semiconductor pattern on the first oxide semiconductor pattern; a second electrode coming in contact with the other side of the first oxide semiconductor pattern on the first oxide semiconductor pattern; and a first-1 light shield pattern disposed on the substrate to be overlapped with the first oxide semiconductor pattern. The second transistor includes: a second oxide semiconductor pattern; a gate electrode overlapped with the second oxide semiconductor on the second oxide semiconductor pattern; a first electrode coming in contact with one side of the second oxide semiconductor pattern on the second oxide semiconductor pattern; a second electrode coming in contact with the other side of the second oxide semiconductor pattern on the second oxide semiconductor pattern; a first-2 light shield pattern disposed on the substrate to be overlapped with the second oxide semiconductor pattern; and a second light shield pattern disposed between the second oxide semiconductor pattern and the first-2 light shield pattern. Therefore, the present invention is capable of improving image quality by improving low-gradation stains.

Description

Display panel and electronic device including the same {DISPLAY PANEL AND ELECTRONIC DEVICE INCLUDING SAME}

The present invention relates to a display panel and an electronic device including the display panel.

Electroluminescence displays can be divided into inorganic light emitting displays and organic light emitting displays according to the material of the light emitting layer. An active matrix type organic light emitting display includes an organic light emitting diode (OLED) that emits light by itself, and has a fast response speed, high luminous efficiency, luminance, and viewing angle. There are advantages. Organic Light Emitting Diode (OLED) is formed in each pixel of the organic light emitting display device. The organic light emitting display device has a fast response speed, excellent luminous efficiency, luminance, viewing angle, etc., as well as black gradation. Since it can be expressed in complete black, the contrast ratio and color gamut are excellent.

The organic light emitting display reproduces video content or visually displays information in various electronic devices such as TV (Television) systems, tablet computers, notebook computers, navigation systems, vehicle systems, as well as small/portable terminals such as wearable devices and smart phones. It is used as a display device.

A display panel of an organic light emitting display device includes a pixel circuit and many transistors constituting a driving circuit for driving the pixel circuit. In order to reduce the number of manufacturing processes of the display panel, transistors formed in the display panel are generally manufactured with the same structure. As a result, transistors formed on the display panel may cause unnecessary power consumption and may unnecessarily increase in size.

The present invention aims to address the aforementioned needs and/or problems. The present invention provides a display panel capable of improving power consumption by optimizing the S-factor (subthreshold slope factor) of transistors according to the purpose, reducing a bezel area of the display panel, and improving image quality, and An electronic device including the same is provided.

The objects of the present invention are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the following description.

A display panel according to an exemplary embodiment of the present invention includes a circuit layer including a plurality of transistors and disposed on a substrate; a light emitting element layer including a plurality of light emitting elements disposed on the circuit layer; and an encapsulation layer covering the light emitting element layer.

All transistors of the circuit layer are n-channel oxide transistors.

The circuit layer includes at least a first transistor and a second transistor.

The first transistor includes a first oxide semiconductor pattern, a gate electrode overlapping the first oxide semiconductor on the first oxide semiconductor pattern, and a first electrode contacting one side of the first oxide semiconductor pattern on the first oxide semiconductor pattern. , a second electrode contacting the other side of the first oxide semiconductor pattern on the first oxide semiconductor pattern, and a 1-1 light shield pattern disposed on the substrate and overlapping the first oxide semiconductor pattern.

The second transistor includes a second oxide semiconductor pattern, a gate electrode overlapping the second oxide semiconductor on the second oxide semiconductor pattern, and a first electrode contacting one side of the second oxide semiconductor pattern on the second oxide semiconductor pattern. , a second electrode contacting the other side of the second oxide semiconductor pattern on the second oxide semiconductor pattern, a 1-2 light shield pattern disposed on the substrate and overlapping the second oxide semiconductor pattern, and the second and a second light shield pattern disposed between the oxide semiconductor pattern and the first-second light shield patterns.

In the display panel according to an exemplary embodiment, the first transistor may include a first oxide semiconductor pattern, a gate electrode overlapping the first oxide semiconductor pattern on the first oxide semiconductor pattern, and the first oxide semiconductor pattern on the first oxide semiconductor pattern. It includes a first electrode contacting one side of the 1 oxide semiconductor pattern, and a second electrode contacting the other side of the first oxide semiconductor pattern on the first oxide semiconductor pattern.

The second transistor includes a second oxide semiconductor pattern, a gate electrode overlapping the second oxide semiconductor on the second oxide semiconductor pattern, and a first electrode contacting one side of the second oxide semiconductor pattern on the second oxide semiconductor pattern. , a second electrode contacting the other side of the second oxide semiconductor pattern on the second oxide semiconductor pattern, a first light shield pattern disposed on the substrate and overlapping the second oxide semiconductor pattern, and the second oxide semiconductor and a second light shield pattern disposed between the pattern and the first light shield pattern.

An electronic device according to an embodiment of the present invention includes the display panel.

In the display panel of the present invention, all transistors are implemented as n-channel oxide TFTs (Thin Film Transistors). The n-channel oxide TFTs have S-factor (subthreshold slope factor) characteristics optimized for the use of transistors by using two metal layers and an insulating layer disposed thereunder. As a result, the present invention can reduce power consumption of the display panel, reduce the bezel area of the display panel, and improve image quality by improving low grayscale stains.

The present invention can further reduce the bezel area of the display panel by removing the VSS lines to which the pixel reference voltage (EVSS) is applied from the display panel from the bezel area where the gate driver is disposed and placing them in the pixel array. Also, by reducing the resistance of the VSS lines, the present invention can prevent a luminance change of pixels due to a rising pixel reference voltage applied to the VSS lines.

The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

1 is a block diagram showing a display device according to an exemplary embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a cross-sectional structure of the display panel shown in FIG. 1 .
3 is a plan view illustrating an example in which a plurality of drive ICs are attached to a display panel.
4 is a diagram schematically showing an example of ESD wiring and ESD elements.
5 is a circuit diagram showing a pixel circuit applicable to the display panel of the present invention.
6A and 6B are cross-sectional views illustrating a cross-sectional structure of a display panel according to an exemplary embodiment of the present invention.
FIG. 7A is an enlarged cross-sectional view of the lower structure of the first TFT, omitting the first and second electrodes in FIG. 6A.
FIG. 7B is an enlarged cross-sectional view of the lower structure of the first TFT, omitting the first and second electrodes in FIG. 6B.
8 is an enlarged cross-sectional view of the lower structure of the second TFT, omitting the first and second electrodes in FIGS. 6A and 6B.

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, only the embodiments will make the disclosure of the present invention complete, and those of ordinary skill in the art to which the present invention belongs It is provided to fully inform the scope of the invention, the invention is defined only by the scope of the claims.

Since the shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, the present invention is not limited to those shown in the drawings. Like reference numbers designate substantially like elements throughout the specification. In addition, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted.

When “has”, “includes”, “has”, “is made of”, etc. mentioned in this specification is used, other parts may be added unless 'only' is used. When a component is expressed in the singular, it may be interpreted in the plural unless specifically stated otherwise.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, when a positional relationship between two components is described as 'on ~', 'on top of ~', 'on the bottom of ~', 'next to', etc., ' One or more other components may be interposed between those components where 'immediately' or 'directly' is not used.

Although first, second, etc. may be used to distinguish the components, the function or structure of these components is not limited to the ordinal number or component name attached to the front of the component.

The following embodiments may be partially or wholly combined or combined with each other, and technically various interlocking and driving operations are possible. Each of the embodiments may be implemented independently of each other or together in an association relationship.

Each of the pixels is divided into a plurality of sub-pixels having different colors for color implementation, and each of the sub-pixels includes a transistor used as a switch element or a driving element. Such a transistor may be implemented as a TFT (Thin Film Transistor).

A driving circuit of the display device writes pixel data of an input image into pixels. A driving circuit of a flat panel display device includes a data driver for supplying data signals to data lines and a gate driver for supplying gate signals to gate lines.

The display panel of the present invention may include a plurality of transistors. A transistor is basically a three-terminal device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. The transistor of the present invention may be implemented as a 4-terminal device to which a back gate bias is applied to shift the threshold voltage to a desired voltage. Within a transistor, carriers start flowing from the source. The drain is an electrode through which carriers exit the transistor. The flow of carriers in a transistor flows from the source to the drain. In the case of an n-channel transistor, since carriers are electrons, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. The direction of current in an n-channel transistor is from drain to source. In the case of a p-channel transistor, since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain may change depending on the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as first and second electrodes.

The gate signal can swing between a Gate On Voltage and a Gate Off Voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor. The gate-off voltage is set to a voltage lower than the threshold voltage of the transistor.

A transistor is turned on in response to a gate-on voltage, while it is turned off in response to a gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate high voltage (VGH), and the gate-off voltage may be a gate low voltage (VGL).

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following embodiments, the display device will be described mainly with an organic light emitting display device, but the present invention is not limited thereto.

An electronic device of the present invention includes a display device including a display panel on which an input image is reproduced, and a host system that transmits pixel data of an input image to the display device.

Referring to FIGS. 1 and 2 , a display device according to an exemplary embodiment of the present invention includes a display panel 100, a display panel driver for writing pixel data to pixels of the display panel 100, and pixels and a power supply unit 140 generating power necessary for driving the display panel driving unit.

The display panel 100 may have a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. The display panel 100 includes a pixel array AA that displays an input image on a screen. The pixel array AA includes a plurality of data lines 102, a plurality of gate lines 103 crossing the data lines 102, and pixels arranged in a matrix form. The display panel 100 may further include power lines commonly connected to pixels. The power supply lines supply the pixels 101 with a constant voltage necessary for driving the pixels 101 . For example, the display panel 100 may include a VDD line to which the pixel driving voltage EVDD is applied and a VSS line to which the pixel reference voltage EVSS is applied. In addition, the power lines may further include a REF line to which the reference voltage Vref is applied and an INIT line to which the initialization voltage Vinit is applied.

As shown in FIG. 2 , the cross-sectional structure of the display panel 100 may include a circuit layer 12, a light emitting element layer 14, and an encapsulation layer 16 stacked on a substrate 10. can

The circuit layer 12 may include a TFT array including pixel circuits connected to wires such as data lines, gate lines, and power lines, a demultiplexer array 112 , a gate driver 120 , and the like. The wiring and circuit elements of the circuit layer 12 may include a plurality of insulating layers, two or more metal layers separated with an insulating layer interposed therebetween, and an active layer including a semiconductor material. All transistors formed on the circuit layer 12 may be implemented as n-channel oxide TFTs of a coplanar structure.

The light emitting element layer 14 may include a light emitting element EL driven by a pixel circuit. The light emitting element EL may include a red (R) light emitting element, a green (G) light emitting element, and a blue (B) light emitting element. In another embodiment, the light emitting device layer 14 may include a white light emitting device and a color filter. The light emitting elements EL of the light emitting element layer 14 may be covered by a protective layer including an organic layer and a protective layer.

The encapsulation layer 16 covers the light emitting element layer 14 so as to seal the circuit layer 12 and the light emitting element layer 14 . The encapsulation layer 16 may have a multi-insulation layer structure in which organic layers and inorganic layers are alternately stacked. The inorganic film blocks the penetration of moisture or oxygen. The organic layer flattens the surface of the inorganic layer. When the organic layer and the inorganic layer are stacked in multiple layers, the movement path of moisture or oxygen is longer than that of a single layer, so that penetration of moisture and oxygen affecting the light emitting element layer 14 can be effectively blocked.

A touch sensor layer, which is omitted in the drawings, is formed on the encapsulation layer 16, and a polarizing plate or color filter layer may be disposed thereon. The touch sensor layer may include capacitive touch sensors that sense a touch input based on a change in capacitance before and after the touch input. The touch sensor layer may include metal wiring patterns and insulating layers forming capacitance of the touch sensors. The insulating layers may insulate portions where the metal wiring patterns intersect and planarize a surface of the touch sensor layer. The polarizer may improve visibility and contrast ratio by converting polarization of external light reflected by metal of the touch sensor layer and the circuit layer. The polarizing plate may be implemented as a polarizing plate in which a linear polarizing plate and a phase retardation film are bonded together or a circular polarizing plate. A cover glass may be adhered on the polarizing plate. The color filter layer may include red, green, and blue color filters. The color filter layer may further include a black matrix pattern. The color filter layer may absorb some wavelengths of light reflected from the circuit layer and the touch sensor layer to replace the role of a polarizer and increase color purity of an image reproduced in the pixel array AA.

The pixel array AA includes a plurality of pixel lines L1 to Ln. Each of the pixel lines L1 to Ln includes one line of pixels disposed along a line direction (X-axis direction) in the pixel array AA of the display panel 100 . Pixels arranged on one pixel line share gate lines 103 . Sub-pixels arranged in the column direction (Y) along the data line direction share the same data line 102 . One horizontal period is a time obtained by dividing one frame period by the total number of pixel lines L1 to Ln.

The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device in which an image is displayed on a screen and a real object in the background is visible. The display panel 100 may be made of a flexible display panel.

Each of the pixels 101 may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color implementation. Each of the pixels may further include a white sub-pixel. Each of the sub-pixels includes a pixel circuit. Hereinafter, a pixel may be interpreted as having the same meaning as a sub-pixel. Each pixel circuit is connected to data lines, gate lines, and power lines. Pixel circuits may be implemented as circuits of FIG. 5 , but are not limited thereto.

Pixels can be arranged as real color pixels and pentile pixels. A pentile pixel can implement a higher resolution than a real color pixel by driving two sub-pixels of different colors as one pixel 101 using a preset pixel rendering algorithm. The pixel rendering algorithm may compensate for insufficient color expression in each pixel with the color of light emitted from an adjacent pixel.

The power supply unit 140 uses a DC-DC converter to generate DC voltage (or constant voltage) required to drive the pixel array AA of the display panel 100 and the display panel driver. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, and the like. The power supply unit 140 adjusts the level of a DC input voltage applied from a host system (not shown) to generate a gamma reference voltage (VGMA) and a gate-on voltage (VGH). DC voltages (or constant voltages) such as a gate-off voltage (VGL), a pixel driving voltage (EVDD), a pixel reference voltage (EVSS), an initialization voltage (Vinit), and a reference voltage (Vref) may be generated. The gamma reference voltage VGMA is supplied to the data driver 110 . A gate-on voltage (VGH) and a gate-off voltage (VGL) are supplied to the gate driver 120 . Constant voltages such as the pixel driving voltage EVDD, the pixel reference voltage EVSS, the initialization voltage Vinit, and the reference voltage Vref are supplied to the pixels 101 through power lines commonly connected to the pixels 101. . The constant voltages applied to the pixel circuit may have different voltage levels.

The display panel driver writes pixel data of an input image into pixels of the display panel 100 under the control of a timing controller 130 .

The display panel driver includes a data driver 110 and a gate driver 120 . The display panel driver may further include a demultiplexer array 112 disposed between the data driver 110 and the data lines 102 .

The demultiplexer array 112 sequentially supplies data voltages output from channels of the data driver 110 to the data lines 102 using a plurality of demultiplexers (DEMUX). The demultiplexer may include a plurality of switch elements disposed on the display panel 100 . When the demultiplexer is disposed between the output terminals of the data driver 110 and the data lines 102, the number of channels of the data driver 110 may be reduced. The demultiplexer array 112 may be omitted.

The display panel driver may further include a touch sensor driver for driving touch sensors. The touch sensor driver is omitted in FIG. 1 . The data driver 110 or the data driver 110 and the touch sensor driver may be integrated into one drive IC (Integrated Circuit, DIC) shown in FIG. 3 . In a mobile device or a wearable device, the timing controller 130, the power supply unit 140, the data driver 110, and the like may be integrated into one drive IC.

The display panel driver may operate in a low speed driving mode under the control of the timing controller 130 . The low-speed driving mode may be set to reduce power consumption of the display device when the input image does not change by a preset number of frames by analyzing the input image. The low-speed driving mode can reduce power consumption of the display panel driver and the display panel 100 by lowering the refresh rate of pixels when a still image is input for a predetermined period of time or longer. The low-speed drive mode is not limited when a still image is input. For example, when the display device operates in a standby mode or when a user command or an input image is not input to the display panel driving circuit for a predetermined period of time or more, the display panel driving circuit may operate in a low speed driving mode.

The data driver 110 receives pixel data of an input image received as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 generates a data voltage Vdata by converting pixel data of an input image into a gamma compensation voltage for each frame period using a digital to analog converter (DAC). The gamma reference voltage VGMA is divided into gamma compensation voltages for each gray level through a voltage divider circuit. The gamma compensation voltage for each gray level is provided to the DAC of the data driver 110 . The data voltage Vdata is output from each of the channels of the data driver 110 through an output buffer.

The gate driver 120 may be implemented as a gate in panel (GIP) circuit formed on the circuit layer 12 on the display panel 100 together with the TFT array and wires of the pixel array AA. The gate driver 120 may be disposed on the bezel area (BZ), which is a non-display area of the display panel 100, or may be distributedly disposed within the pixel array AA where an input image is reproduced. The gate driver 120 sequentially outputs gate signals to the gate lines 103 under the control of the timing controller 130 . The gate driver 120 may sequentially supply the gate signals to the gate lines 103 by shifting the gate signals using a shift register. The gate signal may include various gate pulses such as a scan pulse, an emission control pulse (hereinafter referred to as “pulse”), an initialization pulse, and a sensing pulse.

The gate driver 120 may be disposed in the bezel area BZ on one side of the display panel 100 to supply gate pulses to the gate lines 103 in a single feeding method. In addition, the gate driver 120 is disposed in the bezel area BZ on both sides of the display panel 100 with the pixel array AA interposed therebetween to apply gate pulses to the gate lines 103 in a double feeding method. can supply

The timing controller 130 receives digital video data (DATA) of an input image and a timing signal synchronized therewith from the host system. The timing signal may include a vertical sync signal (Vsync), a horizontal sync signal (Hsync), a clock (CLK), and a data enable signal (DE). Since the vertical period and the horizontal period can be known by counting the data enable signal DE, the vertical sync signal Vsync and the horizontal sync signal Hsync can be omitted. The data enable signal DE has a period of one horizontal period (1H).

The host system may be any one of a television (TV) system, a tablet computer, a notebook computer, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, and a vehicle system. The host system may scale an image signal from a video source according to the resolution of the display panel 100 and transmit the timing signal to the timing controller 130 together with the timing signal.

In the normal driving mode, the timing controller 130 multiplies the input frame frequency by i to control the operation timing of the display panel driver at a frame frequency of input frame frequency × i (i is a natural number) Hz. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) method and 50 Hz in the Phase-Alternating Line (PAL) method.

The timing controller 130 lowers the frequency of the frame rate at which pixel data is written into pixels in the low-speed driving mode compared to the normal driving mode. For example, in the normal driving mode, the data refresh frame frequency in which pixel data is written to the pixels may occur at a frequency of 60 Hz or higher, for example, at a refresh rate of any one of 60 Hz, 120 Hz, and 144 Hz, and the data refresh in the low speed driving mode The frame DRF may be generated at a refresh rate of a lower frequency than that of the low-speed driving mode.

The timing controller 130 controls the data timing control signal for controlling the operation timing of the data driver 110 and the operation timing of the demultiplexer array 112 based on the timing signals Vsync, Hsync, and DE received from the host system. A gate timing control signal for controlling the operation timing of the gate driving unit 120 is generated. The timing controller 130 controls the operation timing of the display panel driver to synchronize the data driver 110 , the demultiplexer array 112 , the touch sensor driver, and the gate driver 120 .

The gate timing control signal generated from the timing controller 130 may be input to the shift register of the gate driver 120 through a level shifter (not shown). The level shifter may receive a gate timing control signal, generate a start pulse and a shift clock, and provide the generated start pulse and shift clock to the shift register of the gate driver 120 .

FIG. 3 is a plan view illustrating an example in which a plurality of drive ICs DIC are attached to the display panel 100 . 4 is a diagram schematically showing an example of ESD wiring and ESD elements.

Referring to FIGS. 3 and 4 , each of the drive ICs DIC may include a data driver 110 or a data driver 110 and a touch sensor driver. Each of the drive ICs (DIC) is mounted on a COF (Chip on Film) film substrate, and the COF may be adhered to the substrate of the display panel 100 using an anisotropic conductive film (ACF). Input terminals of the COFs are connected to a printed circuit board (PCB). At least one COF includes an output terminal electrically connected to data lines on the display panel 100 and an output terminal electrically connected to touch sensor lines on the display panel 100 .

At least one of the COFs includes dummy lines to which a start pulse for driving the gate driver 120, a shift clock, and gate voltages VGH and VGL are applied. The dummy wires are connected to the GIP wires 32 on the display panel through the output terminal of the COF and electrically connected to the gate driver 120 . The GIP wires 32 include clock wires to which start pulses and shift clocks are applied, and power supply wires to which gate voltages VGH and VGL are applied.

Power lines commonly connected to pixels, for example, a VDD line, a VSS line, a REF line, an INIT line, etc. are connected to pixels within the pixel array AA. VSS lines (or EVSS auxiliary lines) 38 to which the pixel reference voltage EVSS is applied are VSS shorting bars 34 formed at the top and bottom of the display panel 100, as shown in FIG. 38) is connected.

The VSS lines 38 may be formed of wires having a long stripe shape along a direction Y parallel to the data lines 102 . The VSS shorting bars 34 and 36 connecting the VSS lines 38 in common are long stripe-shaped wires along the direction X parallel to the gate lines 103 at the top and bottom of the display panel 100. can be formed as

Since the VSS lines 38 are not disposed in the left and right bezel areas BZ of the display panel 100 where the gate driver 120 is disposed, the left and right bezel areas BZ of the display panel 100 are reduced. In the case of a pixel circuit implemented with an n-channel oxide TFT, a rising pixel reference voltage (EVSS) due to an IR drop of a VSS line greatly affects luminance of pixels. Therefore, it is desirable that the combined resistance of the VSS lines 38 be designed as small as possible, for example, 4Ω or less.

The display panel 100 further includes an electrostatic discharge (ESD) wire 40 formed in a closed loop in a bezel area outside the pixel array AA. A ground voltage (GND) or a pixel reference voltage (EVSS) is applied to the ESD wire 40 . A plurality of ESD elements 42 are connected to the ESD wire 40 as shown in FIG. 4 . Each of the ESD elements 42 includes one or more n-channel oxide TFTs and operates as a diode. The ESD elements 42 include ESD elements 42 connected between the data lines 102 and the ESD wiring 40, and ESD elements 42 connected between the gate lines 103 and the ESD wiring 40. ). The ESD elements are turned on when static electricity is applied to the pixel array AA, and discharge the static electricity to the ESD wire 40 to protect the pixel array AA from static electricity.

There may be differences in electrical characteristics of driving elements between pixels due to process variation and element characteristic variation resulting from the manufacturing process of the display panel 100 , and such differences may increase as the driving time of the pixels elapses. An internal compensation circuit may be embedded in the pixel circuit or an external compensation circuit may be connected to the pixel circuit in order to compensate for a deviation in electrical characteristics of a driving element between pixels. The internal compensation circuit samples the electrical characteristics of the driving element for each sub-pixel using the internal compensation circuit implemented in each pixel circuit, and compensates for the gate-source voltage (Vgs) of the driving element by the electrical characteristic. The external compensation circuit generates a compensation value based on a result of sensing the electrical characteristics of the driving element using the external compensation circuit connected to the pixel circuit to compensate for the electrical specific change of the driving element.

The external compensation circuit includes a REF line (or sensing line, RL) connected to the pixel circuit, and an analog to digital converter (ADC) that converts the sensing voltage stored in the REF line RL into digital data. The sensing voltage may include, for example, threshold voltage and/or mobility of the driving element. An integrator may be connected to the input terminal of the ADC. The timing controller 130 to which the external compensation circuit is applied generates a compensation value for compensating for a change in the electrical characteristics of the driving element according to the sensing data input from the ADC, and adds or multiplies the compensation value to the pixel data of the input image to determine the value of the driving element. Changes in electrical characteristics can be compensated for. ADC may be built into the data driver 110 .

5 is a circuit diagram showing an example of a pixel circuit applicable to the display panel of the present invention. It should be noted that the pixel circuit of the present invention is not limited to FIG. 5 .

Referring to FIG. 5 , the pixel circuit is turned on/off according to voltages of a light emitting element EL, a driving element DT supplying current to the light emitting element EL, and voltages of gate pulses SCAN, SENSE, INIT, and EM. It includes a plurality of switch elements T01 to T03 and a capacitor Cst. In this pixel circuit, the driving element DT and the switch elements T01 to T03 may be implemented as n-channel oxide TFTs.

The gate signal includes a scan pulse (SCAN), a sensing pulse (SENSE), an initialization pulse (INIT), and an EM pulse (EM). The gate driver 120 includes a first shift register that sequentially outputs scan pulses SCAN, a second shift register that sequentially outputs sensing pulses SENSE, and a third shift register that sequentially outputs initialization pulses INIT. , and a fourth shift register sequentially outputting EM pulses EM.

Constant voltages such as a pixel driving voltage EVDD, a pixel reference voltage EVSS, a reference voltage Vref, and an initialization voltage Vinit are applied to the pixel circuit. The pixel driving voltage EVDD is higher than the low potential power supply voltage EVDD. The initialization voltage Vinit may be set within a data voltage range. The reference voltage Vref may be set to a low voltage similar to the pixel reference voltage EVSS.

The light emitting element EL may be implemented as an OLED. An OLED includes an organic compound layer formed between an anode electrode and a cathode electrode. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer, EIL), but is not limited thereto. The anode electrode of the light emitting element EL is connected to the third node n3, and the cathode electrode is connected to the VSS node to which the pixel reference voltage EVSS is applied. The VSS node is connected to the VSS line. The light emitting element EL includes a capacitor formed between an anode electrode and a cathode electrode. A capacitor of the light emitting element EL is omitted from the drawings.

When a voltage is applied to the anode electrode and the cathode electrode of the light emitting element EL, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL move to the light emitting layer EML to form excitons. In this case, visible light may be emitted from the light emitting layer EML.

The driving element DT includes a gate electrode connected to the second node n2, a first electrode connected to the first node n1, and a third electrode connected to the third node n3. The capacitor Cst is connected between the second node n2 and the third node n3 to store the gate-source voltage Vgs of the driving element DT. The driving element DT may be implemented as a 4-terminal element further including a second gate electrode (or bottom gate electrode) for applying a back gate bias.

The first switch element T01 is turned on according to the gate-on voltage VGH of the scan pulse SCAN to supply the pixel data data voltage Vdata to the second node n2. The first switch element T01 is connected to a gate electrode connected to a first gate line to which a scan pulse SCAN is applied, a first electrode connected to a data line to which a data voltage Vdata is applied, and a second node n2. It includes a second electrode.

The second switch element T02 is turned on according to the gate-on voltage VGH of the sensing pulse SENSE and supplies the reference voltage Vref to the third node n3. The second switch element T02 has a gate electrode connected to the second gate line to which the sensing scan pulse SENSE is applied, a first electrode connected to the REF line to which the reference voltage Vref is applied, and a second node n2. It includes a second electrode connected to it.

The third switch element T03 is turned on according to the gate-on voltage VGH of the initialization pulse INIT to apply the initialization voltage Vinit to the second node n2. The third switch element T03 includes a gate electrode connected to a third gate line to which an initialization pulse INIT is applied, a first electrode connected to an INIT line to which an initialization voltage Vinit is applied, and a second node n2 to which an initialization voltage Vinit is applied. It includes a second electrode.

The fourth switch element T04 is turned off according to the gate-on voltage VEL of the EM pulse EM1 and supplies the pixel driving voltage EVDD to the first node n1. The fourth switch element T04 includes a gate electrode connected to a fourth gate line to which an EM pulse EM is applied, a first electrode connected to a VDD line to which a pixel driving voltage EVDD is applied, and a first node n1. It includes a second electrode connected to it.

6A and 6B are cross-sectional views showing a cross-sectional structure of the display panel 100 according to an exemplary embodiment of the present invention. The display panel 100 shown in FIGS. 6A and 6B has a top emission panel structure in which light is emitted to the opposite side of the substrate GLS, that is, to the top.

Referring to FIGS. 6A and 6B , the substrate GLS may be made of a plate-shaped plastic substrate, alkali-free glass or non-alkali glass. The glass substrate GLS has greater impact resistance than the plastic substrate and is not easily deformed.

A circuit layer 12 is formed on the substrate GLS. The circuit layer 12 includes at least first and second TFTs TFT1 and TFT2, capacitors connected to the TFTs TFT1 and TFT2, and circuit wires.

The circuit layer 12 includes a plurality of metal layers, a semiconductor layer, and a plurality of insulating layers BUF1, BUF2, GI, ILD, PAC1, and PAC2.

A first metal layer is disposed on the substrate GLS. The first metal layer may be formed of a Cu/MoTi double metal layer, but is not limited thereto. The first metal layer includes a first light shield pattern LS1. The first light shield pattern LS1 includes a 1-1 light shield pattern overlapping the first semiconductor pattern ACT1 under the first TFT (TFT1) and a second semiconductor pattern under the first TFT (TFT2). A 1-2 light shield pattern overlapping (ACT2) is included. The first light shield pattern LS1 is disposed below the semiconductor patterns ACT1 and ACT2 of the TFTs TF1 and TFT2 to block light irradiated to the semiconductor patterns ACT1 and ACT2.

As shown in FIG. 6A , the first light shield pattern LS1 may be disposed below each of the first and second TFTs TFT1 and TFT2 . The 1-1 light shield pattern under the first TFT (TFT1) may be connected to the second electrode (or source electrode) SE1 of the first TFT (TFT1). In another embodiment, the 1-1 light shield pattern LS1 may not be disposed below the first TFT (TFT1) as shown in FIG. 6B.

The first insulating layer BUF1 is formed of an inorganic insulating material and covers the first light shield pattern LS1 of the first metal layer. The first insulating layer BUF1 may be formed of a structure in which an oxide film and a nitride film are stacked, for example, SiO ₂ /SiNx, but is not limited thereto. The first insulating layer BUF1 serves as a dielectric layer forming the capacitor Cst of the pixel circuit and serves as an insulating layer insulating the first metal layer and the second metal layer. The first insulating layer BUF1 is preferably set to 500 Å to 3000 Å in consideration of the capacitance of the capacitor Cst.

A second metal layer is disposed on the first insulating layer BUF1. The second metal layer may be formed of MoTi, but is not limited thereto. The second metal layer includes a second light shield pattern LS2.

The second light shield pattern LS2 is disposed under the semiconductor pattern ACT2 of the second TFT (TFT2) to block light irradiated to the semiconductor pattern ACT2. The second light shield pattern LS2 may overlap the semiconductor pattern ACT2 of the second TFT (TFT2) and at least partially overlap the first light shield pattern LS1 below the second TFT (TFT2).

A voltage may be applied to the first and second light shield patterns LS1 and LS2. For example, when the first TFT (TFT1) is a transistor of the gate driver 120, a predetermined constant voltage may be applied to the first light shield pattern LS1 under the first TFT (TFT1). When the second TFT (TFT2) is a transistor of the pixel circuit, a variable voltage may be applied in the driving phase of the pixel circuit. When the second TFT (TFT2) is implemented as a 4-terminal transistor, the second light shield pattern LS2 serves as a back bias for shifting the threshold voltage of the second TFT (TFT2) to a voltage higher than 0 [V]. It can be used as a second gate electrode (or bottom gate electrode) that applies (back bias).

The second insulating layer BUF2 includes an inorganic insulating material, such as SiO ₂ , and covers the second light shield pattern LS2 and the first insulating layer BUF1 of the second metal layer. The second insulating layer BUF2 insulates the second metal layer from the semiconductor layer. The second insulating layer BUF2 has a thickness equal to or different from that of the first insulating layer BUF2. For example, the first insulating layer BUF2 may be set to about 2500 Å, but is not limited thereto.

A semiconductor layer is disposed on the second insulating layer BUF2. The semiconductor layer may be formed of an oxide semiconductor, for example, indium gallium zinc oxide (IGZO), but is not limited thereto. The semiconductor layer includes semiconductor patterns ACT1 and ACT2 of each of the first and second TFTs TFT1 and TFT2 .

The semiconductor pattern ACT1 of the first TFT (TFT1) contacts the first and second electrodes DE1 and SE1 and overlaps the gate electrode GE1. When the first TFT (TFT1) is turned on, a channel current flows through the semiconductor pattern (ACT1). The semiconductor pattern ACT2 of the second TFT (TFT2) contacts the first and second electrodes DE2 and SE2 and overlaps the gate electrode GE2. When the second TFT (TFT2) is turned on, a channel current flows through the semiconductor pattern (ACT2).

The oxide semiconductor layer may be selectively conductive at least partially, for example, at a portion in contact with the first and second electrodes DE1 , SE1 , DE2 , and SE2 and at a portion MACT connected to the capacitor Cst. there is. In a dry etching process of a thin film layer positioned on the oxide semiconductor layer, an exposed portion of the oxide semiconductor layer may be made conductive. As another example, an oxide semiconductor may be made conductive by a doping method. In the channel portion below the gate electrodes GE1 and GE2 of the TFTs TFT1 and TFT2, the oxide semiconductor layer is not conductive.

The third insulating layer GI is an inorganic insulating material and is formed on the semiconductor layer and the second insulating layer BUF2 to cover the semiconductor layer and the second insulating layer BUF2. The third insulating layer GI may be formed of an oxide film (SiO ₂ ), but is not limited thereto. The third insulating layer GI covers the semiconductor layers ACT1, ACT2, and MACT. The third insulating layer GI insulates the semiconductor layer and the third metal layer. The third insulating layer GI may have a thickness smaller than that of the second insulating layer BUF2. For example, the thickness of the third insulating layer GI may be set to about 1500 Å, but is not limited thereto.

A third metal layer is disposed on the third insulating layer GI. The third metal layer may be formed of a Cu/MoTi double metal layer, but is not limited thereto. The third metal layer includes at least a gate line and gate electrodes GE1 and GE2 of the TFTs TFT1 and TFT2 connected to the gate line. The gate electrode GE1 of the first TFT (TFT1) overlaps the semiconductor pattern ACT1 with the third insulating layer GI interposed therebetween. The gate electrode GE2 of the second TFT (TFT2) overlaps the semiconductor pattern ACT2 with the third insulating layer GI interposed therebetween.

The fourth insulating layer ILD is an inorganic insulating material and is formed on the third metal layer and the third insulating layer GI to cover the third metal layer and the third insulating layer GI. The fourth insulating layer ILD may be formed of a structure in which a nitride film and an oxide film are stacked, for example, SiNx/SiO ₂ , but is not limited thereto.

A fourth metal layer is disposed on the fourth insulating layer ILD. The fourth metal layer includes at least a data line, first and second electrodes DE1 , DE2 , SE1 , SE2 of the first and second TFTs TFT1 and TFT2 connected to the data line, and a capacitor Cst. It includes a jumping pattern (CE) connected to.

The fourth metal layer may be formed of a double metal structure, for example, Ti/Al/Ti, including a hydrogen capture layer that blocks hydrogen penetrating into the semiconductor patterns ACT1 and ACT2 from the encapsulation layer 16, but is not limited thereto. don't Here, titanium (Ti) of the upper and lower layers of the fourth metal layer may serve as a hydrogen capture layer. When hydrogen permeates the oxide semiconductor, the oxide semiconductor may become a conductor. The fourth metal layer blocks hydrogen emitted from the encapsulation layer 16 to prevent an unwanted portion of the oxide semiconductor, for example, a phenomenon in which a channel portion of the TFTs TFT1 and TFT2 becomes conductive.

The first and second electrodes DE1 and SE1 of the first TFT TFT1 are connected to the semiconductor through first and second contact holes penetrating the third and fourth insulating layers GI and ILD. It comes into contact with the pattern ACT1. As shown in FIG. 6A , the second electrode SE1 of the first TFT (TFT1) transmits the first light through the third contact hole passing through the first to fourth insulating layers BUF1, BUF2, GI, and ILD. It may contact the shield pattern LS1.

The first and second electrodes DE2 and SE2 of the second TFT TFT2 are connected to the semiconductor pattern ACT2 through the fourth and fifth contact holes penetrating the third and fourth insulating layers GI and ILD. come into contact The second electrode SE2 of the second TFT (TFT2) may contact the second light shield pattern LS2 through the sixth contact hole passing through the second to fourth insulating layers BUF2, GI, and ILD. there is.

The jumping pattern CE is in contact with the conductive semiconductor pattern MACT through the 7-1 contact hole passing through the third and fourth insulating layers GI and ILD, and the first to fourth insulating layers GI and ILD. It contacts the first light shield pattern LS1 through the 7-2 contact hole passing through (BUF1, BUF2, GI, ILD).

The fifth insulating layer PAC1 is a thick organic film and is placed on the fourth insulating layer ILD to cover the fourth metal layer and the fourth insulating layer ILD. The fifth insulating layer PAC1 may be formed of polyimide (PI), but is not limited thereto. The fifth insulating layer PAC1 covers the fourth metal layer and flattens the surface. The fifth insulating layer PAC1 has a thickness greater than that of each of the first to fourth insulating layers BUF1, BUF2, GI, and ILD. Since the fifth insulating layer PAC1 is formed of a thick organic film having a low dielectric constant, parasitic capacitance between the fourth metal layer and the fifth insulating layer is minimized, allowing patterns of the fourth and fifth metal layers to overlap. . Accordingly, the fifth insulating layer PAC1 reduces the load of the display panel 100 and enables high-resolution design.

A fifth metal layer is disposed on the fifth insulating layer PAC1. The fifth metal layer includes at least the 5-1st metal pattern SD21 disposed on the first TFT (TFT1), the 5-2nd metal pattern SD22 disposed on the second TFT (TFT2), and the light emitting element EL. A 5-3 metal pattern SD23 connecting the anode electrode ANO to the second electrode SE2 of the second TFT TFT2 is included.

The 5-1st metal pattern SD21 overlaps the first and second electrodes DE1 and SE1 of the first TFT (TFT1) to block the hydrogen permeation path from the encapsulation layer 16, thereby blocking the hydrogen permeation path from the first TFT (TFT1). ) of the semiconductor pattern ACT1 is prevented from conducting. The 5-1st metal pattern SD21 may expose the gate electrode GE1 of the first TFT (TFT1). The 5-2 metal pattern SD22 overlaps the first and second electrodes DE2 and SE2 of the second TFT (TFT2) to block the hydrogen penetration path from the encapsulation layer 16, thereby blocking the second TFT (TFT2). ) of the semiconductor pattern ACT2 is prevented from conducting.

The 5-3rd metal pattern SD23 contacts the second electrode SE2 of the second TFT (TFT2) through an eighth contact hole penetrating the fifth insulating layer PAC1.

The fifth metal layer may be formed of, for example, Ti/Al/Ti, a double metal structure including a hydrogen capture layer that blocks hydrogen penetrating into the semiconductor patterns ACT1 and ACT2 from the encapsulation layer 16, but is not limited thereto. don't Here, the upper and lower layers of titanium (Ti) of the fifth metal layer may serve as a hydrogen capture layer. Accordingly, the fourth and fifth metal layers function as dual hydrogen capture layers to block hydrogen penetrating into the semiconductor patterns ACT1 and ACT2.

The power lines of the display panel 100 may be formed of one or more metal patterns of the first to fifth metal layers.

Transistors of the gate driver 120 may be implemented as a first TFT (TFT1). A signal for controlling the shift register, such as a start pulse and a shift clock, may be applied to the shift register of the gate driver 120 through wires formed from the third and fourth metal layers. In addition, a start pulse and a shift clock may be applied above the shift register through wires formed from the fourth and fifth metal layers.

The sixth insulating layer PAC2 is a thick organic film and is disposed on the fifth insulating layer PAC1 to cover the fifth metal layer and the fifth insulating layer PAC1. The sixth insulating layer PAC2 may be formed of polyimide (PI), but is not limited thereto. The sixth insulating layer PAC2 covers the fifth metal layer and flattens the surface. The sixth insulating layer PAC2 has a thickness greater than that of each of the first to fourth insulating layers BUF1, BUF2, GI, and ILD. Since the sixth insulating layer PAC2 is formed of a thick organic film having a low dielectric constant, parasitic capacitance between the fifth metal layer and the anode electrode ANO of the light emitting element EL is minimized. The sixth insulating layer PAC2 reduces the load of the display panel 100 and enables high-resolution design.

The light emitting element layer 14 includes an anode electrode (ANO) of the light emitting element EL, a seventh insulating layer, an organic compound layer (OE) including a light emitting layer, a spacer (SPC), and a cathode electrode (CAT) of the light emitting element EL. ), and a plurality of dams DAM disposed in the bezel area BZ.

The anode electrode ANO of the light emitting element EL is formed on the sixth insulating layer PAC2. The anode electrode ANO may have a triple structure of ITO/Ag/ITO including indium tin oxide (ITO) and silver (Ag), but is not limited thereto. The anode electrode ANO contacts the second electrode SE2 of the second TFT (TFT2) through the ninth contact hole penetrating the sixth insulating layer PAC2 and has a wide pattern overlapping the second TFT (TFT2). patterned.

The seventh insulating layer is a thick organic film and is formed on the anode electrode ANO of the light emitting element EL and the sixth insulating layer PAC2. The seventh insulating layer may be formed of polyimide (PI), but is not limited thereto. The seventh insulating layer includes a bank pattern BNK. The bank pattern BNK covers an edge of the anode electrode ANO and exposes most of the other anode electrode ANO to define a light emitting area in each of the pixels.

The spacer SPC is formed by patterning an eighth insulating layer made of a thick organic film. The spacer SPC is disposed on the bank pattern BNK. The spacer SPC may be formed of polyimide (PI), but is not limited thereto.

The organic compound layer OE of the light emitting element EL covers the bank pattern BNK and the spacer SPC. The cathode electrode CAT of the light emitting element EL covers the organic compound layer OE. In each of the pixels, a portion where the anode electrode ANO and the cathode electrode CAT overlap with the organic compound layer OE interposed therebetween is a light emitting area emitting light.

The dam DAM is thickly disposed at the edge of the display panel 100 to prevent the organic film from overflowing when the organic film of the encapsulation layer 16 is applied. The dam has a thickness in which the sixth insulating layer PAC2 , the seventh insulating layer, and the eighth insulating layer are stacked.

A concave trench may be formed on a top surface of the light emitting device layer 14 at a boundary between pixels. Trench structures are omitted from the drawings. The trench structure lengthens the path of a lateral current flowing between pixels, thereby preventing a phenomenon in which luminance of the pixels varies due to an interaction between pixels due to the leakage current.

The encapsulation layer 16 is formed as a stacked structure of a thick first organic layer EPAC1 , a thin inorganic layer PCL, and a thick second organic layer EPAC2 to cover the light emitting device layer 14 . The touch sensor layer formed on the encapsulation layer 16 is omitted in FIGS. 15A and 15B.

The display panel 100 includes many transistors used for various purposes. The present invention improves the S-factor (subthreshold slope factor) characteristics of transistors in order to functionally optimize each of the transistors.

The S-factor may be adjusted according to the capacitor transmission rate determined according to the capacities of the second and third capacitors C1 and C2. Cross-sectional structures of the second and third capacitors C1 and C2 may be changed according to the set value of the capacitor transmission factor.

로 표현될 수 있다. 에스-팩터가 커질수록 트랜지스터의 I-V 전달 커브의 기울기가 낮아진다. 따라서, 에스-팩터가 큰 트랜지스터는 작은 게이트 전압의 변화량에서 전류가 크게 변하지 않는 반면, 에스-팩터가 작은 트랜지스터는 작은 게이트 전압의 변화량에도 전류가 크게 변한다. 이러한 트랜지스터의 에스-팩터는 도 6a 및 도 6b에서 반도체 패턴(ACT1, ACT2)을 덮는 제3 절연층(GI)을 포함한 커패시터 용량(Cgi)과, 반도체 패턴(ACT1, ACT2) 아래의 제4 절연층(BUF1, BUF2)을 포함한 커패시터 용량(Cbuf)의 비율로 제어될 수 있다. 에스-팩터는 Cbuf에 비례하고 Cgi에 반비례한다. The S-factor is defined as a gate voltage value for increasing the drain current of a transistor by a factor of 10. The S-factor (S) is the reciprocal of the slope value of the IV transfer curve in the region below the threshold voltage (Vth) of the driving element (DT), that is,

can be expressed as The larger the S-factor, the lower the slope of the transistor's IV transfer curve. Accordingly, the current of a transistor with a large S-factor does not change significantly with a small change in gate voltage, whereas the current of a transistor with a small S-factor varies greatly even with a small amount of change in gate voltage. The S-factor of this transistor is the capacitor capacitance Cgi including the third insulating layer GI covering the semiconductor patterns ACT1 and ACT2 in FIGS. 6A and 6B and the fourth insulating layer below the semiconductor patterns ACT1 and ACT2. The ratio of the capacitor capacitance Cbuf including the layers BUF1 and BUF2 may be controlled. The S-factor is proportional to Cbuf and inversely proportional to Cgi.

Since the first TFT (TFT1) has a smaller Cgi than the second TFT (TFT2), the S factor is small. In the case of the first TFT (TFT1), as shown in FIGS. 6A, 6B, 7A and 7B, the dielectric layer of Cbuf includes the first and second insulating layers BUF1 and BUF2 so that the capacitance of Cbuf is small or does not exist. The switch elements T01 to T04 of the pixel circuit, the ESD element, the switch element of the demultiplexer 112, the transistor of the gate driver, and the like require fast switching response characteristics. Therefore, it is preferable that these transistors are implemented in the same stacked structure as the first TFT (TFT1). Since the first TFT (TFT1) has a fast switching response characteristic, the driving voltage of the transistor can be reduced, so power consumption is reduced and the size of the transistor is reduced, so that the bezel area of the display panel can be reduced.

The gate driver includes one or more transistors implemented by the first TFT (T1) and having a threshold voltage (Vth) of 0 [V] or near, and a gate-to-source voltage (Vgs) controlled to a voltage smaller than 0 [V]. can include

In the case of the second TFT (TFT2), as shown in FIGS. 6A, 6B, and 8 , the dielectric layer of Cbuf includes only the second insulating layer BUF2, so the capacitance of Cbuf is relatively large. The current of the second TFT (TFT2) does not change sensitively according to the change amount of the gate voltage. Therefore, it is preferable that the driving element DT of the pixel circuit has the same stacked structure as that of the second TFT (TFT2). The second TFT (TFT2) can improve image quality by improving low grayscale stains caused by threshold voltage deviations according to process deviations of the display panel 100 and accumulation of usage time.

Since the content of the specification described in the problem to be solved, the problem solution, and the effect above does not specify the essential features of the claim, the scope of the claim is not limited by the matters described in the content of the specification.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and may be variously modified and implemented without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed according to the claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

10, GLS: substrate of display panel 12: circuit layer
14: light emitting element layer 16: encapsulation layer
34, 36: VSS shorting bar 38: VSS wiring (EVSS auxiliary wiring)
40: ESD wiring 42: ESD element
100: display panel 101: pixel
102: data line 103: gate line
110: data driver 120: gate driver
130: timing controller 140: power supply
BZ: bezel area EL: light emitting element
DT: driving element of pixel circuit T01 to T04: switch element of pixel circuit
Cst: capacitor of pixel circuit TFT1: first TFT
TFT2: second TFT ACT1, ACT2: semiconductor pattern
LS1: first light shield pattern LS2: second light shield pattern
GE1, GE2: gate electrode DE1, DE2: first electrode
SE1, SE2: second electrode BUF: first insulating layer
BUF2: second insulating layer GI: third insulating layer
ILD: 4th insulating layer PAC1: 5th insulating layer
PAC2: sixth insulating layer DAM: dam

Claims (20)

a circuit layer disposed on a substrate including a plurality of transistors;
a light emitting element layer including a plurality of light emitting elements disposed on the circuit layer; and
Including an encapsulation layer covering the light emitting element layer,
All transistors of the circuit layer are n-channel oxide transistors,
the circuit layer includes at least a first transistor and a second transistor;
The first transistor,
A first oxide semiconductor pattern, a gate electrode overlapping the first oxide semiconductor on the first oxide semiconductor pattern, a first electrode contacting one side of the first oxide semiconductor pattern on the first oxide semiconductor pattern, the first oxide A second electrode contacting the other side of the first oxide semiconductor pattern on a semiconductor pattern, and a 1-1 light shield pattern disposed on the substrate and overlapping the first oxide semiconductor pattern,
The second transistor,
A second oxide semiconductor pattern, a gate electrode overlapping the second oxide semiconductor on the second oxide semiconductor pattern, a first electrode contacting one side of the second oxide semiconductor pattern on the second oxide semiconductor pattern, and the second oxide A second electrode on a semiconductor pattern and in contact with the other side of the second oxide semiconductor pattern, a first-second optical shield pattern disposed on the substrate and overlapping the second oxide semiconductor pattern, and the second oxide semiconductor pattern and the second oxide semiconductor pattern. A display panel including a second light shield pattern disposed between 1-2 light shield patterns. According to claim 1,
Further comprising a fifth metal layer disposed on the first and second transistors,
The fifth metal layer,
a 5-1st metal pattern disposed on the first transistor;
a 5-2 metal pattern disposed on the second transistor; and
A display panel comprising a 5-3 metal pattern connecting anode electrodes of the light emitting elements to the second electrode of the second transistor. According to claim 2,
The display panel of claim 1 , wherein the fifth metal layer includes titanium. According to claim 3,
The first and second electrodes of the first and second transistors include titanium. According to claim 2,
a first insulating layer disposed on the substrate and covering the first-first and first-second light shield patterns;
a second insulating layer disposed on the first insulating layer and covering the second light shield pattern and the first insulating layer;
a third insulating layer disposed on the second insulating layer and covering the first and second oxide semiconductor patterns and the second insulating layer;
a fourth insulating layer disposed on the third insulating layer and covering gate electrodes of the first and second transistors and the third insulating layer;
a fifth insulating layer disposed on the fourth insulating layer and covering the first and second electrodes of the first and second transistors and the fourth insulating layer; and
A sixth insulating layer disposed on the fifth insulating layer and covering the fifth metal layer and the fifth insulating layer,
Each of the first to fourth insulating layers is an inorganic film,
Each of the fifth and sixth insulating layers is an organic film having a thickness greater than that of each of the first to fourth insulating layers. According to claim 5,
The display panel of claim 1 , wherein the first insulating layer has a thickness between 500 Å and 3000 Å. According to claim 1,
The circuit layer,
data lines to which data voltages are applied and gate lines to which gate pulses are applied; and pixels connected to power lines to which a constant voltage is applied. and
A gate driver generating the gate pulse;
each of the pixels includes a pixel circuit;
The pixel circuit,
a driving element for driving the light emitting element; and
A switch element turned on/off in response to the gate pulse;
The gate driver includes a plurality of transistors,
The display panel of claim 1 , wherein each of the driving element, the switch element, and the transistors of the gate driving part is the n-channel oxide transistor. According to claim 7,
The display panel of claim 1 , wherein the switch element and the transistors of the gate driver have the same stacked structure as the first transistor. According to claim 1,
A display panel in which the second electrode of the first transistor contacts the 1-1 light shield pattern. According to claim 7,
The drive element,
A display panel having the same stacked structure as the second transistor. According to claim 1,
A display panel in which a second electrode of the second transistor contacts the second light shield pattern. According to claim 5,
It is disposed on the same layer as the first and second electrodes of the first and second transistors, and is in contact with a conductive semiconductor pattern through a contact hole penetrating the third and fourth insulating layers, and The display panel further includes a jumping pattern contacting the first-second light shield pattern through a contact hole penetrating the fourth insulating layers. According to claim 7,
At least a portion of the gate driver is disposed in a bezel area outside a pixel array in which the pixels are disposed in the display panel;
The circuit layer,
a plurality of VSS lines arranged in the pixel array to which a pixel reference voltage is applied; and
A display panel comprising a shorting bar connecting the VSS lines. According to claim 13,
The circuit layer,
a closed-loop electrostatic discharge wire disposed in the bezel area;
a plurality of electrostatic discharge elements connected between the data lines and the electrostatic discharge wire;
a plurality of electrostatic discharge elements connected between the gate lines and the electrostatic discharge wiring;
The display panel of claim 1 , wherein the electrostatic discharge elements have a stacked structure of the first transistor. According to claim 7,
The circuit layer,
a demultiplexer coupled to the data lines;
The display panel of claim 1 , wherein the switch elements of the demultiplexer have a stacked structure of the first transistors. a circuit layer disposed on a substrate including a plurality of transistors;
a light emitting element layer including a plurality of light emitting elements disposed on the circuit layer; and
Including an encapsulation layer covering the light emitting element layer,
All transistors of the circuit layer are n-channel oxide transistors,
the circuit layer includes at least a first transistor and a second transistor;
The first transistor,
A first oxide semiconductor pattern, a gate electrode overlapping the first oxide semiconductor on the first oxide semiconductor pattern, a first electrode contacting one side of the first oxide semiconductor pattern on the first oxide semiconductor pattern, and the first oxide semiconductor pattern. A second electrode contacting the other side of the first oxide semiconductor pattern over the oxide semiconductor pattern;
The second transistor,
A second oxide semiconductor pattern, a gate electrode overlapping the second oxide semiconductor on the second oxide semiconductor pattern, a first electrode contacting one side of the second oxide semiconductor pattern on the second oxide semiconductor pattern, and the second oxide A second electrode contacting the other side of the second oxide semiconductor pattern on a semiconductor pattern, a first light shield pattern disposed on the substrate and overlapping the second oxide semiconductor pattern, and the second oxide semiconductor pattern and the first A display panel including a second light shield pattern disposed between the light shield patterns. a display device on which an input image is reproduced; and
A host system transmitting pixel data of an input image to the display device;
The display panel of the display device,
a circuit layer disposed on a substrate including a plurality of transistors;
a light emitting element layer including a plurality of light emitting elements disposed on the circuit layer; and
Including an encapsulation layer covering the light emitting element layer,
All transistors of the circuit layer are n-channel oxide transistors,
the circuit layer includes at least a first transistor and a second transistor;
The first transistor,
A first oxide semiconductor pattern, a gate electrode overlapping the first oxide semiconductor on the first oxide semiconductor pattern, a first electrode contacting one side of the first oxide semiconductor pattern on the first oxide semiconductor pattern, and the first oxide semiconductor pattern. A second electrode contacting the other side of the first oxide semiconductor pattern over the oxide semiconductor pattern;
The second transistor,
A second oxide semiconductor pattern, a gate electrode overlapping the second oxide semiconductor on the second oxide semiconductor pattern, a first electrode contacting one side of the second oxide semiconductor pattern on the second oxide semiconductor pattern, and the second oxide semiconductor pattern. A second electrode contacting the other side of the second oxide semiconductor pattern over the oxide semiconductor pattern;
A 1-1 light shield pattern is disposed under the first transistor or there is no light shield pattern under the first transistor;
An electronic device in which a 1-2 light shield pattern and a second light shield pattern overlapping with an insulating layer interposed therebetween are disposed under the second transistor. 18. The method of claim 17,
The display panel,
a fifth metal layer disposed on the first and second transistors;
a first insulating layer disposed on the substrate and covering at least the first and second optical shield patterns;
a second insulating layer disposed on the first insulating layer and covering the second light shield pattern and the first insulating layer;
a third insulating layer disposed on the second insulating layer and covering the first and second oxide semiconductor patterns and the second insulating layer;
a fourth insulating layer disposed on the third insulating layer and covering gate electrodes of the first and second transistors and the third insulating layer;
a fifth insulating layer disposed on the fourth insulating layer and covering the first and second electrodes of the first and second transistors and the fourth insulating layer; and
A sixth insulating layer disposed on the fifth insulating layer and covering the fifth metal layer and the fifth insulating layer,
The fifth metal layer is an electronic device including titanium. 18. The method of claim 17,
The circuit layer,
data lines to which data voltages are applied and gate lines to which gate pulses are applied; and pixels connected to power lines to which a constant voltage is applied. and
A gate driver generating the gate pulse;
each of the pixels includes a pixel circuit;
The pixel circuit,
a driving element for driving the light emitting element; and
A switch element turned on/off in response to the gate pulse;
The gate driver includes a plurality of transistors,
Each of the transistors of the driving element, the switch element, and the gate driving part is the n-channel oxide transistor,
The switch element and the transistors of the gate driver have the same stacked structure as the first transistor,
The drive element,
It has the same stacked structure as the second transistor,
The second electrode of the first transistor is in contact with the 1-1 light shield pattern;
An electronic device in which a second electrode of the second transistor is in contact with the second light shield pattern. According to claim 19,
At least a portion of the gate driver is disposed in a bezel area outside a pixel array in which the pixels are disposed in the display panel;
The circuit layer,
a plurality of VSS lines arranged in the pixel array to which a pixel reference voltage is applied; and
a shorting bar connecting the VSS lines;
a closed-loop electrostatic discharge wire disposed in the bezel area;
a plurality of electrostatic discharge elements connected between the data lines and the electrostatic discharge wire;
a plurality of electrostatic discharge elements connected between the gate lines and the electrostatic discharge wiring;
The electronic device of claim 1 , wherein the electrostatic discharge elements have a stacked structure of the first transistor.

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