KR20230034827A - Electroluminescent display device - Google Patents

Abstract

In accordance with one embodiment of the present invention, an electroluminescent display device includes: a substrate divided into a display area and a non-display area; a first light blocking layer and a data line disposed on the substrate of the display area; a first buffer layer disposed on the first light blocking layer and the data line; a semiconductor layer disposed in an upper part of the first buffer layer, and composed of an oxide semiconductor; a gate insulating layer disposed on the semiconductor layer; a gate electrode disposed on the gate insulating layer; a protective layer and a first planarization layer disposed in an upper part of the gate electrode; a drain electrode disposed on the protective layer exposed by the removal of a part of the first planarization layer; a second planarization layer disposed on the drain electrode and the first planarization layer; and a light emitting element disposed in an upper part of the second planarization layer, and comprising an anode, a light emitting unit, and a cathode. In accordance with the present invention, since the number of mask processes required for the manufacture of an oxide thin film transistor is reduced, productivity can be increased and process and material costs can be reduced.

Description

Electroluminescent display device {ELECTROLUMINESCENT DISPLAY DEVICE}

The present invention relates to an electroluminescence display device, and more particularly, to an electroluminescence display device using an oxide thin film transistor.

Currently, as we enter the information age in earnest, the field of display devices that visually display electrical information signals is rapidly developing, and research is continuing to develop performance such as thinning, lightening, and low power consumption for various display devices.

Representative display devices include a liquid crystal display device (LCD), an electro-wetting display device (EWD), and an organic light emitting display device (OLED).

Among them, the electroluminescent display device including the organic light emitting display device is a self-emissive display device, and unlike the liquid crystal display device, it does not require a separate light source and can be manufactured in a lightweight and thin shape. In addition, the electroluminescent display is not only advantageous in terms of power consumption due to low voltage driving, but also has excellent color reproduction, response speed, viewing angle, and contrast ratio (CR), so it is expected to be used in various fields. It is becoming.

An electroluminescent display device is configured by disposing a light emitting layer using an organic material between two electrodes called an anode and a cathode. Then, when holes from the anode are injected into the light emitting layer and electrons from the cathode are injected into the light emitting layer, the injected electrons and holes recombine with each other to form excitons in the light emitting layer and emit light. do.

An object to be solved by the present invention is to provide an electroluminescent display device using an oxide thin film transistor in which the number of mask processes is reduced.

Another problem to be solved by the present invention is to provide an electroluminescent display device using an oxide thin film transistor with improved characteristics by blocking hydrogen from the outside or from an encapsulation layer.

Another problem to be solved by the present invention is to provide an electroluminescent display device using an oxide thin film transistor in which a charge rate of a storage capacitor is increased by reducing parasitic capacitance.

The tasks of this specification are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the description below.

In order to solve the above problems, an electroluminescent display device according to an embodiment of the present invention includes a substrate divided into a display area and a non-display area, a first light blocking layer and data lines disposed on the substrate of the display area, A first buffer layer disposed on the first light blocking layer and the data line, a semiconductor layer disposed on the first buffer layer and composed of an oxide semiconductor, a gate insulating layer disposed on the semiconductor layer, and a gate disposed on the gate insulating layer electrode, a protective layer and a first planarization layer disposed on the gate electrode, a drain electrode disposed on the protective layer exposed by removing a partial region of the first planarization layer, and disposed on the drain electrode and the first planarization layer It may include a second planarization layer and a light emitting element disposed on the second planarization layer and composed of an anode, a light emitting unit, and a cathode.

In order to solve the above problems, an electroluminescent display device according to another embodiment of the present invention includes a substrate divided into a display area and a non-display area, a first light blocking layer disposed on the substrate of the display area, and data lines. , a first buffer layer disposed on the first light blocking layer and the data wire, a semiconductor layer disposed on the first buffer layer and composed of an oxide semiconductor, a gate insulating layer disposed on the semiconductor layer, and a gate insulating layer disposed on the gate insulating layer A gate electrode, a first planarization layer disposed on the gate electrode, a drain electrode disposed on the protective layer exposed by removing a partial region of the first planarization layer, and a second planarization layer disposed on the drain electrode and the first planarization layer. It is disposed on the planarization layer and the second planarization layer, and may include a light emitting element composed of an anode, a light emitting unit, and a cathode.

Details of other embodiments are included in the detailed description and drawings.

The present invention can increase productivity and reduce process and material costs by reducing the number of mask processes required to manufacture an oxide thin film transistor.

According to the present invention, the characteristics and reliability of the thin film transistor can be improved by forming a drain electrode serving as a hydrogen trap on the oxide thin film transistor to prevent hydrogen from entering the oxide thin film transistor.

According to the present invention, the light blocking layer contact hole and the drain contact hole are overlapped, and the same type of electrode is formed to have a top and bottom step, thereby reducing parasitic capacitance and increasing the charging rate of the storage capacitor. do.

Effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the present invention.

1 is a schematic configuration diagram of an electroluminescent display device according to a first embodiment of the present invention.
FIG. 2 is a plan view of the electroluminescent display of FIG. 1 .
FIG. 3 is a cross-sectional view including a cross section taken along line III-III′ of FIG. 2 .
FIG. 4 is an enlarged view of portion A of FIG. 3 .
FIG. 5 is an enlarged view of part B of FIG. 3 .
6 is a plan view of an electroluminescent display device according to a second exemplary embodiment of the present invention.
7 is a plan view of an electroluminescent display device according to a third exemplary embodiment of the present invention.

The advantages and features of the present invention, and how to achieve them, will become clear with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different shapes, only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention pertains. It is provided to completely inform the person who has the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative, and the present invention is not limited thereto. Like reference numbers designate like elements throughout the specification. In addition, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. In the case where 'includes', 'has', 'consists of', etc. mentioned above is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, when the positional relationship of two parts is described with '~ above', '~ above', '~ below', 'next to', etc., 'directly' or Unless 'directly' is used, one or more other parts may be placed between two parts.

When an element or layer is referred to as being “on” another element or layer, it includes all cases where another element or layer is directly on top of another element or another layer or other element intervenes therebetween.

In addition, although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may also be the second component within the technical spirit of the present invention.

Like reference numbers designate like elements throughout the specification.

The area and thickness of each component shown in the drawings is shown for convenience of description, and the present invention is not necessarily limited to the area and thickness of the illustrated component.

Each feature of the various embodiments of the present invention can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment can be implemented independently of each other or can be implemented together in a related relationship. may be

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic configuration diagram of an electroluminescent display device according to a first embodiment of the present invention.

Referring to FIG. 1 , the electroluminescence display device 100 according to the first embodiment of the present invention includes a display panel PN including a plurality of sub-pixels SP and a gate supplying various signals to the display panel PN. It may include a driver GD, a data driver DD, and a timing controller TC controlling the gate driver GD and the data driver DD.

The gate driver GD may supply a plurality of scan signals to the plurality of scan wires SL according to the plurality of gate control signals GCS provided from the timing controller TC. The plurality of scan signals may include a first scan signal SCAN1 and a second scan signal SCAN2.

The data driver DD converts the image data RGB input from the timing controller TC into the data signal Vdata using the reference gamma voltage according to the plurality of data control signals DCS provided from the timing controller TC. can do. Also, the data driver DD may supply the converted data signal Vdata to the plurality of data lines DL.

The timing controller TC aligns image data RGB input from the outside and supplies it to the data driver DD, and generates a gate control signal GCS and data control signal DCS using a synchronization signal SYNC input from the outside. ) can be created.

Hereinafter, the pixel structure of the electroluminescent display according to the first embodiment of the present invention will be described in detail with reference to FIGS. 2 and 3 .

FIG. 2 is a plan view of the electroluminescent display of FIG. 1 .

FIG. 3 is a cross-sectional view including a cross-section taken along line III-III′ of FIG. 2 .

FIG. 4 is an enlarged view of portion A of FIG. 3 .

FIG. 5 is an enlarged view of part B of FIG. 3 .

FIG. 2 shows a pixel structure of one sub-pixel SP, and FIG. 3 shows a part of a non-display area NA including a display area AA and a pad part.

In FIG. 2, only the anode 121 of the light emitting element 120 is shown for convenience.

First of all, the electroluminescent display according to the first embodiment of the present invention may include a display panel, a flexible film, and a printed circuit board.

The display panel is a panel for displaying an image to a user.

The display panel may include a display element for displaying an image, a driving element for driving the display element, and wires for transmitting various signals to the display element and the driving element. The display element may be defined differently depending on the type of display panel. For example, when the display panel is an electroluminescent display panel, the display element may be a light emitting element including an anode, an organic light emitting layer, and a cathode.

Hereinafter, it is assumed that the display panel is an electroluminescence display panel, but the display panel is not limited to the electroluminescence display panel.

Referring to FIGS. 2 and 3 , the display panel may include a display area AA and a non-display area NA.

The display area AA is an area where an image is displayed on the display panel.

A plurality of sub-pixels SP constituting a plurality of pixels and a circuit for driving the plurality of sub-pixels SP may be disposed in the display area AA. The plurality of sub-pixels SP is a minimum unit constituting the display area AA, a display element may be disposed in each of the plurality of sub-pixels SP, and the plurality of sub-pixels SP may constitute a pixel. there is. For example, a light emitting element 120 including an anode 121 , a light emitting part 122 , and a cathode 123 may be disposed in each of the plurality of sub-pixels SP, but is not limited thereto. Also, a circuit for driving the plurality of sub-pixels SP may include a driving element and wiring. For example, the circuit may include thin film transistors T1 and T4, a storage capacitor, a scan line SL, and a data line DL, but is not limited thereto.

The plurality of sub-pixels SP may include a first sub-pixel, a second sub-pixel, and a third sub-pixel emitting light of different colors. For example, the first sub-pixel may be a green sub-pixel, the second sub-pixel may be a red sub-pixel, and the third sub-pixel may be a blue sub-pixel. However, the present invention is not limited thereto.

The arrangement, number, and color combination of the plurality of sub-pixels SP may be variously changed according to design, but are not limited thereto.

The non-display area NA is an area in which an image is not displayed.

The display area AA and the non-display area NA may have shapes suitable for the design of an electronic device equipped with an electroluminescent display device.

Various wires and circuits for driving the light emitting devices 120 of the display area AA may be disposed in the non-display area NA. For example, in the non-display area NA, a pad wiring PAD for transmitting signals to a plurality of sub-pixels SP and circuits of the display area AA, a link wiring, a gate driver IC, a data driver IC, and the like A driving IC or the like may be disposed, but is not limited thereto.

In this case, the gate driver IC may be formed independently of the display panel and electrically connected to the display panel in various ways, but is mounted in the display panel using a Gate In Panel (GIP) method. may consist of

The electroluminescent display device may include various additional elements for generating various signals or driving pixels in the display area AA. Additional elements for driving the pixel may include an inverter circuit, a multiplexer, an electro static discharge (ESD) circuit, and the like. The electroluminescent display device may also include additional elements related to functions other than pixel driving. For example, the electroluminescent display may include additional elements providing a touch sensing function, a user authentication function (eg, fingerprint recognition), a multi-level pressure sensing function, and a tactile feedback function. These additional elements may be located in the non-display area NA and/or an external circuit connected to the connection interface.

The flexible film is a film for supplying signals to the plurality of sub-pixels SP and circuits of the display area AA, and may be electrically connected to the display panel. The flexible film may be disposed at one end of the non-display area NA of the display panel to supply power voltages and data voltages to a plurality of sub-pixels SP and circuits in the display area. A driving IC such as a data driver IC may be disposed on the flexible film.

The printed circuit board may be disposed on one end of the flexible film and connected to the flexible film. The printed circuit board is a component that supplies signals to the driving IC. The printed circuit board may supply various signals such as driving signals and data signals to the driving IC.

Describing the pixel structure in detail, the substrate 110 may be divided into a display area AA and a non-display area NA outside the display area AA.

The thin film transistors T1 and T4, the light emitting element 120, and an encapsulation layer (not shown) may be disposed on the substrate 110 in the display area AA.

A pad line PAD and an encapsulation layer may be disposed on the substrate 110 in the non-display area NA.

The substrate 110 serves to support and protect components of the electroluminescent display device disposed thereon.

Recently, the flexible substrate 110 can be used as a flexible material having flexible characteristics such as plastic.

The flexible substrate 110 may be in the form of a film containing one of the group consisting of polyester-based polymers, silicone-based polymers, acrylic-based polymers, polyolefin-based polymers, and copolymers thereof.

First light blocking layers 118 and 119 may be disposed on the substrate 110 .

The first light blocking layers 118 and 119 may be disposed in the display area AA under the thin film transistors T1 and T4.

The first light blocking layers 118 and 119 may be formed of a metal material having a light blocking function to block external light from being introduced into the semiconductor layers ACT1 and ACT4 of the thin film transistors T1 and T4.

The first light-blocking layers 118 and 119 may be formed of a single layer, but for convenience, they will be referred to as the first light-blocking layer 118 on the right side and the first light-blocking layer 119 on the left side.

The first light blocking layers 118 and 119 may include aluminum (Al), chromium (Cr), tungsten (W), titanium (Ti), nickel (Ni), neodymium (Nd), molybdenum (Mo), copper (Cu), or the like. It may be formed in a single-layer or multi-layer structure made of any one of the opaque metals or alloys thereof.

A data line DL, a high potential power line HPPL, and a low potential power line LPPL may be disposed on the substrate 110 in the display area AA.

In addition, a pad wiring PAD may be disposed on the substrate 110 in the non-display area NA.

The data line DL, the high potential power line HPPL, the low potential power line LPPL, and the pad line PAD may be formed of the same metal on the same layer as the first light-blocking layers 118 and 119. Not limited.

The first buffer layer 111 is on the substrate 110 on which the first light blocking layers 118 and 119, data lines DL, high potential power lines HPPL, low potential power lines LPPL, and pad lines PAD are disposed. ) can be placed.

The first buffer layer 111 may be formed in a structure in which a single insulating layer or a plurality of insulating layers are stacked in order to block foreign substances including moisture or oxygen introduced from the substrate 110 . In this case, the first buffer layer 111 may be formed of an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or aluminum oxide (AlOx) in a single-layer or multi-layer structure. The first buffer layer 111 may be eliminated according to the type of the thin film transistors T1 and T4.

Second light blocking layers 128 and 129 may be disposed on the first buffer layer 111 .

The second light blocking layers 128 and 129 may be disposed in the display area AA under the thin film transistors T1 and T4.

The second light blocking layers 128 and 129 may be formed of a metal material having a light blocking function to block external light from being introduced into the semiconductor layers ACT1 and ACT4 of the thin film transistors T1 and T4.

The second light-blocking layers 128 and 129 may be composed of one layer, but for convenience, they will be referred to as the right-side second light-blocking layer 128 and the left-side second light-blocking layer 129 .

The second light-blocking layer 128 on the right side and the second light-blocking layer 129 on the left side may be disposed on the first light-blocking layer 118 on the right side and the first light-blocking layer 119 on the left side, respectively, to form a storage capacitor. there is.

The second light blocking layers 128 and 129 may include aluminum (Al), chromium (Cr), tungsten (W), titanium (Ti), nickel (Ni), neodymium (Nd), molybdenum (Mo), copper (Cu), or the like. It may be formed in a single-layer or multi-layer structure made of any one of the opaque metals or alloys thereof.

Meanwhile, the first light-blocking layers 118 and 119 and the second light-blocking layers 128 and 129 may be formed of a metal capable of collecting hydrogen such as Ti or a Ti alloy such as Ti/Al/Ti.

Sc, V, Mn, Fe, Pd, Nb, Zr, Y, Ta, Ce with excellent hydrogen collection ability other than Ti , La, Sm, U, and the like.

A second buffer layer 112 may be disposed on the second light blocking layers 128 and 129 .

The second buffer layer 112 may have a structure in which a single insulating layer or a plurality of insulating layers are stacked in order to block foreign substances including moisture or oxygen introduced from the substrate 110 . The second buffer layer 112 may be formed of a single-layer or multi-layer structure of an inorganic insulating material such as silicon oxide, silicon nitride, or aluminum oxide. The second buffer layer 112 may be eliminated according to the type of the thin film transistors T1 and T4.

Partial regions of the first and second buffer layers 111 and 112 may be removed to form a first contact hole 140a exposing a portion of the first light blocking layer 118 on the right side.

In addition, partial regions of the first and second buffer layers 111 and 112 may be removed to form the second contact hole 140b exposing a portion of the data line DL.

Partial regions of the first and second buffer layers 111 and 112 may be removed to form a third contact hole 140c exposing a portion of the left first light blocking layer 119 .

A portion of the first and second buffer layers 111 and 112 may be removed to form a fourth contact hole 140d exposing a portion of the high potential power line HPPL.

Partial regions of the first and second buffer layers 111 and 112 may be removed to form a fifth contact hole exposing a portion of the low potential power line LPPL.

Partial regions of the first and second buffer layers 111 and 112 may be removed to form a sixth contact hole exposing a portion of the pad wiring PAD.

The thin film transistors T1 and T4 may be disposed on the second buffer layer 112 .

The first thin film transistor T1 of the display area AA may be a switching transistor, and the fourth thin film transistor T4 may be a driving transistor, but is not limited thereto. Other sensing transistors and compensation circuits may also be included in the electroluminescent display device of the present invention.

The first thin film transistor T1 is turned on by the gate pulse supplied to the scan line SL, and the data voltage supplied to the data line DL is applied to the fourth gate electrode GE4 of the driving transistor T4. send. To this end, the first thin film transistor T1 may include a first gate electrode GE1, a first semiconductor layer ACT1, a first source electrode, and a first drain electrode DE1.

The fourth thin film transistor T4 transfers the current transmitted through the high potential power supply line HPPL to the anode 121 by the signal received from the switching transistor T1, and transmits the current transmitted to the anode 121. Illumination can be controlled. To this end, the fourth thin film transistor T4 may include a fourth gate electrode GE4, a fourth semiconductor layer ACT4, a fourth source electrode, and a fourth drain electrode DE4.

The semiconductor layers ACT1 and ACT4 may be formed of an oxide semiconductor. Excellent characteristics of a display panel can be secured by using an oxide thin film transistor having high mobility and low off current characteristics. In particular, when the thin film transistors of the GIP area are formed of oxide thin film transistors in the same way as the display area AA, there is an advantage in that the number of processes and costs are reduced.

Oxide semiconductors have excellent mobility and uniformity. The oxide semiconductor is a quaternary metal oxide, indium tin gallium zinc oxide (InSnGaZnO)-based material, a ternary metal oxide, indium gallium zinc oxide (InGaZnO)-based material, indium tin zinc oxide (InSnZnO)-based material, aluminum zinc oxide (InAlZnO) based material, tin gallium zinc oxide (SnGaZnO) based material, aluminum gallium zinc oxide (AlGaZnO) based material, indium tin aluminum zinc oxide (SnAlZnO) based material, binary metal oxide indium zinc oxide (InZnO) based material, tin zinc Oxide (SnZnO) material, aluminum zinc oxide (AlZnO) material, zinc magnesium oxide (ZnMgO) material, tin magnesium oxide (SnMgO) material, indium magnesium oxide (InMgO) material, indium oxide (InO) material , tin oxide (SnO)-based material, indium gallium oxide (InGaO)-based material, zinc oxide (ZnO)-based material, etc., and the composition ratio of each element is not limited.

Among them, a part of the first semiconductor layer ACT1 is electrically connected to the first light blocking layer 118 on the right side through the first contact hole 140a, and the other part is electrically connected to data through the second contact hole 140b. It can be electrically connected to the wiring DL. In this case, a storage capacitor may be formed between the first semiconductor layer ACT1 / the first light blocking layer 118 on the right side and the second light blocking layer 128 on the right side.

In addition, a portion of the fourth semiconductor layer ACT4 is electrically connected to the second light blocking layer 129 on the left side through the third contact hole 140c, and the other portion has a high potential through the fourth contact hole 140d. It can be electrically connected to the power supply wiring (HPPL). In this case, a capacitor may be additionally formed between the fourth semiconductor layer ACT4 / the second light blocking layer 129 on the left side and the first light blocking layer 119 on the left side.

The semiconductor layers ACT1 and ACT4 may include a source region including p-type or n-type impurities, a drain region, and a channel region between the source region and the drain region, and a source region adjacent to the channel region and A lightly doped region may be further included between the drain regions, but is not limited thereto.

The source region and the drain region are regions doped with impurities at a high concentration, and may be connected to the source and drain electrodes DE1 and DE4 of the thin film transistors T1 and T4, respectively.

As the impurity ion, a p-type impurity or an n-type impurity may be used. The p-type impurity may be one of boron (B), aluminum (Al), gallium (Ga), and indium (In), and the n-type impurity may be phosphorus ( P), arsenic (As) and antimony (Sb).

The channel region may be doped with an n-type impurity or a p-type impurity according to the NMOS or PMOS thin film transistor structure.

Meanwhile, a first connection electrode 125 electrically connected to the low potential power line LPPL through a fifth contact hole may be disposed on the low potential power line LPPL. In addition, a second connection electrode 126 electrically connected to the pad wire PAD through a sixth contact hole may be disposed on the pad wire PAD.

The first connection electrode 125 and the second connection electrode 126 may be formed of a conductive semiconductor layer, but are not limited thereto. If necessary, the first connection electrode 125 and the second connection electrode 126 may be omitted. The conductorized semiconductor layer may be composed of a doped layer in which impurity ions are doped into the semiconductor layer, or may be composed of an oxide semiconductor layer conductorized by plasma treatment.

In addition, a portion of the first semiconductor layer ACT1 may extend in a direction crossing the data line DL and be connected to the initialization voltage supply line Vini. Meanwhile, a reference voltage line RVL may be disposed on the second buffer layer 112 in a direction parallel to the initialization voltage supply line Vini. A portion of the reference voltage line RVL may extend in parallel with the high potential power line HPPL, but is not limited thereto.

A gate insulating layer 113 may be disposed on the semiconductor layers ACT1 and ACT4 and the first connection electrode 125 and the second connection electrode 126 .

The gate insulating layer 113 is composed of a single layer of silicon oxide (SiOx) or silicon nitride (SiNx) or multiple layers thereof, and the current flowing through the semiconductor layers ACT1 and ACT4 flows into the gate electrodes GE1 and GE4. It may be disposed between the gate electrodes GE1 and GE4 and the semiconductor layers ACT1 and ACT4 so as not to fall. Silicon oxide is inferior in ductility to metal, but superior in ductility to silicon nitride, and can be formed as a single layer or multiple layers depending on its characteristics. For example, the gate insulating layer 113 is preferably made of silicon oxide, but is not limited thereto.

A portion of the gate insulating layer 113 may be removed to form a seventh contact hole exposing a portion of the first connection electrode 125 .

In addition, an eighth contact hole exposing a portion of the second connection electrode 126 may be formed by removing a portion of the gate insulating layer 113 .

Gate electrodes GE1 and GE4 may be disposed on the gate insulating layer 113 .

A scan line SL and an emission control signal line EML may be disposed on the gate insulating layer 113 in a direction crossing the data line DL. In addition, a sensing line SSL and an initialization signal line ISL may be disposed on the gate insulating layer 113 in a direction parallel to the scan line SL.

The gate electrodes GE1 and GE4 are made of conductive metals such as copper (Cu), aluminum (Al), chromium (Cr), molybdenum (Mo), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). ), etc., but may be composed of a single layer or multiple layers as an alloy thereof, but is not limited thereto.

A protective layer 114 may be disposed on the gate electrodes GE1 and GE4.

The protective layer 114 may serve to prevent unnecessary electrical connections between components disposed above and below the protective layer 114 and prevent contamination or damage from the outside. The protective layer 114 may be formed of a single layer of silicon oxide (SiOx) or silicon nitride (SiNx) or multiple layers thereof.

At this time, partial regions of the gate insulating layer 113 and the protective layer 114 may be removed to form a ninth contact hole 140i exposing a portion of the first semiconductor layer ACT1.

In addition, a portion of the protective layer 114 may be removed to form a tenth contact hole 140j exposing a portion of the fourth gate electrode GE4 .

Also, partial regions of the gate insulating layer 113 and the protective layer 114 may be removed to form an eleventh contact hole 140k exposing a portion of the fourth semiconductor layer ACT4 .

In addition, a twelfth contact hole exposing a portion of the first connection electrode 125 may be formed by removing a portion of the gate insulating layer 113 and the protective layer 114 .

In addition, a thirteenth contact hole exposing a portion of the second connection electrode 126 may be formed by removing portions of the gate insulating layer 113 and the protective layer 114 .

In particular, the present invention overlaps the ninth contact hole 140i on the top of the first contact hole 140a and overlaps the eleventh contact hole 140k on the top of the third contact hole 140c, thereby increasing the margin. Parasitic capacitance with the peripheral data line DL or the high potential power line HPPL can be reduced, thereby increasing the charging rate of the storage capacitor (see FIG. 4 ). 4 omits the illustration of the first drain electrode DE1 formed in the ninth contact hole 140i for convenience of explanation. Referring to FIG. 4 , it can be seen that the ninth contact hole 140i is formed overlapping the upper portion of the first contact hole 140a based on the dotted line.

A first planarization layer 115 may be disposed on the protective layer 114 .

The first planarization layer 115 is made of acrylic resin, epoxy resin, phenolic resin, polyamides resin, polyimide resin, or unsaturated polyester. It may be formed of one or more of unsaturated polyesters resin, polyphenylene resin, polyphenylene sulfides resin, and benzocyclobutene, but is not limited thereto. .

In this case, a partial area of the first planarization layer 115 may be removed to form an open area exposing portions of the ninth contact hole 140i and the tenth contact hole 140j and the protective layer 114 .

In addition, a 14th contact hole exposing the 11th contact hole 140k may be formed by removing a partial region of the first planarization layer 115 .

A fifteenth contact hole exposing the twelfth contact hole may be formed by removing a portion of the first planarization layer 115 .

A portion of the first planarization layer 115 in the non-display area NA may be removed to expose the 13th contact hole.

Source and drain electrodes DE1 and DE4 may be disposed on the protective layer 114 and the first planarization layer 115 . However, in the case of the present invention, when the source electrode is configured as a part of the data line DL or the high potential power line HPPL, the source electrode may be omitted.

At this time, the first drain electrode DE1 is disposed on the protective layer 114 in the open area, and a part of the first drain electrode DE1 is electrically connected to the first semiconductor layer ACT1 through the ninth contact hole 140i, and the other part is the first drain electrode DE1. It may be electrically connected to the fourth gate electrode GE4 through the 10 contact hole 140j.

The fourth drain electrode DE4 is disposed on the first planarization layer 115 and may be electrically connected to the fourth semiconductor layer ACT4 through a fourteenth contact hole.

In this way, as the first drain electrode DE1 is disposed on the first planarization layer 115 in the open area, a short-circuit defect between the same type electrodes is prevented by forming an upper and lower step with the same type electrode, that is, the fourth drain electrode DE4. It can be improved, and parasitic capacitance is reduced so that the spacing between homogeneous electrodes can be reduced (see FIG. 5). In addition, areas of the first drain electrode DE1 and the fourth drain electrode DE4 may be increased, and thus inspection accuracy may be improved due to an increase in charge amount. In addition, a high mobility oxide thin film transistor may be very vulnerable to hydrogen in the encapsulation layer. Referring to FIG. 5, in the case of the first embodiment of the present invention, the first planarization layer 115 is removed in the open area OA. By arranging the first and fourth drain electrodes DE1 and DE4 as hydrogen absorbing layers, the hydrogen absorbing effect can be improved. That is, by opening a part of the first drain electrode DE1 and disposing the first and fourth drain electrodes DE1 and DE4 on the protective layer 114 closer to the oxide thin film transistors T1 and T4, the hydrogen collecting effect can be achieved. can be further improved.

An additional low potential power wire 135 may be disposed on the protective layer 114 . The additional low potential power wire 135 may be electrically connected to the first connection electrode 125 through a fifteenth contact hole. Accordingly, the additional low potential power line 135 may be electrically connected to the low potential power line LPPL.

The additional low-potential power line 135 supplies a low-potential power signal together with the low-potential power line LPPL, so that uniform power can be maintained in the large-area display panel.

The additional low potential power line 135 may be disposed around the data line DL in a direction parallel to the data line DL, but is not limited thereto.

A pad electrode 136 may be disposed on the protective layer 114 . The pad electrode 136 may be electrically connected to the second connection electrode 126 through the exposed thirteenth contact hole.

The additional low potential power wiring 135, the pad electrode 136, and the first and fourth drain electrodes DE1 and DE4 are made of conductive metal such as aluminum (Al), molybdenum (Mo), chromium (Cr), and gold (Au). , Titanium (Ti), nickel (Ni), copper (Cu) and neodymium (Nd), such as metal materials or alloys thereof, may be composed of a single layer or multiple layers, but is not limited thereto.

In particular, the first and fourth drain electrodes DE1 and DE4 may be formed of a metal capable of collecting hydrogen such as Ti or a Ti alloy such as Ti/Al/Ti.

Materials constituting the first and fourth drain electrodes DE1 and DE4 include Sc, V, Mn, Fe, Pd, Nb, Zr, Y, Ta, Ce, La, Sm, U, etc., which have excellent hydrogen collection ability in addition to Ti. can include

For reference, the hydrogen solubility of TiH is superior to that of AlH, NiH, AgH, CuH, and ZnH.

Looking at metal hydrides, for example, the hydride of Ti is TiH _2.00 , which means that 2 H can be stored in one Ti, and the hydrogen adsorption capacity for AlH _<2.5x10-8 , the hydride of Al. It can be seen that this is 1 million times better.

The hydrides of Sc, V, Pd, Nb, Zr, Y, Ta, Ce, La, Sm, and U have ScH _>1.86 , VH _1.00 , PdH _0.724 , NbH _1.1 , ZrH _>1.70 , YH _>2.85 , TaH _0.79 , It can be seen that CeH _>2.5 , LaH _>2.03 , SmH _3.00 , and UH _>3.00 .

As described above, the present invention prevents hydrogen from entering the oxide thin film transistors T1 and T4 by forming the drain electrodes DE1 and DE4 serving as a hydrogen trap on the oxide thin film transistors T1 and T4, thereby preventing the oxide thin film transistors T1 and T4. The characteristics and reliability of T4) can be improved.

Meanwhile, an additional high potential power line HPPL' may be disposed on the first planarization layer 115 . The additional high-potential power line HPPL' supplies a high-potential power signal together with the high-potential power line HPPL, so that uniform power can be maintained in the large-area display panel.

The additional high potential power line HPPL' may be disposed around the high potential power line HPPL in a direction parallel to the high potential power line HPPL, but is not limited thereto.

The thin film transistors T1 and T4 may be classified into a coplanar structure and an inverted staggered structure according to positions of components constituting the thin film transistors T1 and T4. At this time, for example, in the inverted staggered thin film transistor, the gate electrode may be located on the opposite side of the source electrode and the drain electrode with respect to the semiconductor layer. As shown in FIG. 3, the thin film transistors T1 and T4 of the coprana structure have gate electrodes GE1 and GE4 with the semiconductor layers ACT1 and ACT4 as a reference, the same as the first and fourth drain electrodes DE1 and DE4. can be located on the side.

In FIG. 3 , the coprana structure thin film transistors T1 and T4 are shown as examples, but the electroluminescent display device according to the first embodiment of the present invention may include an inverted staggered structure thin film transistor.

Also, some of the thin film transistors T1 and T4 may have a coprana structure, and some of the thin film transistors T1 and T4 may have an inverted staggered structure. In addition, the thin film transistors T1 and T4 of the present invention may have a structure in which a coprana structure and an inverted staggered structure are mixed.

A protective layer may be additionally disposed on the thin film transistors T1 and T4.

The protective layer may serve to prevent unnecessary electrical connections between components disposed above and below the protective layer, and to prevent contamination or damage from the outside.

A second planarization layer 116 may be disposed on the thin film transistors T1 and T4. The second planarization layer 116 protects the thin film transistors T1 and T4 and alleviates the step difference generated thereby, and the thin film transistors T1 and T4, the scan line SL and the data line DL, and the light emitting element ( 120) may be disposed above the thin film transistors T1 and T4 to reduce parasitic capacitance generated between them.

The second planarization layer 116 is made of acrylic resin, epoxy resin, phenolic resin, polyamides resin, polyimides resin, or unsaturated polyester. It may be formed of one or more of unsaturated polyesters resin, polyphenylene resin, polyphenylene sulfides resin, and benzocyclobutene, but is not limited thereto. .

The first and second planarization layers 115 and 116 may extend to and extend to a part of the non-display area NA. In addition, the first and second planarization layers 115 and 116 may extend and extend to a part of the non-display area NA to expose the pad electrode 136 .

A portion of the second planarization layer 116 may be removed to form a sixteenth contact hole 140o exposing a portion of the fourth drain electrode DE4 .

A light emitting device 120 including an anode 121 , a light emitting unit 122 , and a cathode 123 may be disposed on the second planarization layer 116 .

The anode 121 may be disposed on the second planarization layer 116 .

The anode 121 is an electrode serving to supply holes to the light emitting unit 122 and may be electrically connected to the fourth thin film transistor T4 through the sixteenth contact hole 140o.

In the case of a bottom emission method in which light is emitted to a lower portion where the anode 121 is disposed, the anode 121 is made of transparent conductive materials such as indium tin oxide (ITO) or indium zinc oxide (Indium Zinc Oxide). Zin Oxide; IZO), etc., but is not limited thereto.

On the other hand, when the display panel is a top emission method in which light is emitted to the top where the cathode 123 is disposed, the emitted light is reflected from the anode 121 more smoothly. A reflective layer may be further included so that the light is emitted upward.

That is, the anode 121 may have a two-layer structure in which a transparent conductive layer made of a transparent conductive material and a reflective layer are sequentially stacked, or a three-layer structure in which a transparent conductive layer, a reflective layer, and a transparent conductive layer are sequentially stacked, and the reflective layer is silver ( Ag) or an alloy containing silver.

A bank 150 may be disposed on the anode 121 and the second planarization layer 116 .

The bank 150 disposed on the anode 121 and the second planarization layer 116 may define a sub-pixel SP by dividing an area actually emitting light, that is, a light emitting area.

After forming a photoresist on the anode 121 , the bank 150 may be formed through a photolithography process. A photoresist refers to a photosensitive resin whose solubility in a developing solution is changed by the action of light, and a specific pattern can be obtained by exposing and developing the photoresist. Photoresists can be classified into positive photoresists and negative photoresists. In this case, the positive photoresist refers to a photoresist in which the solubility of the exposed portion in the developing solution is increased by exposure, and when the positive photoresist is developed, a pattern in which the exposed portion is removed is obtained. A negative photoresist refers to a photoresist in which the solubility of an exposed portion in a developing solution is reduced by exposure, and when the negative photoresist is developed, a pattern in which the unexposed portion is removed is obtained.

In order to form the light emitting part 122 of the light emitting device 120, a deposition mask, a fine metal mask (FMM) may be used.

In addition, in order to prevent damage that may occur due to contact with the deposition mask disposed on the bank 150 and to maintain a constant distance between the bank 150 and the deposition mask, polyimide, which is a transparent organic material, is placed on the upper part of the bank 150. , a spacer 156 composed of one of photo acrylic and benzocyclobutene.

A portion of the bank 150 of the emission region may be removed to form an opening OP exposing a portion of the anode 121 .

Meanwhile, a plurality of trench patterns 155 may be formed by removing a partial region of the bank 150 between the sub-pixels SP.

A plurality of trench patterns 155 may be disposed between the plurality of sub-pixels SP. The trench pattern 155 may be formed by removing a portion of the upper thickness of the bank 119, but the present invention is not limited thereto and may be formed by removing the entire thickness of the bank 119.

By thinning the thickness of the light emitting part 122 between neighboring sub-pixels SP by the trench pattern 155 or lengthening a path, or by making the light emitting part 122 between neighboring sub-pixels SP Leakage current by the light emitting unit 122 between neighboring sub-pixels SP can be minimized by disconnecting (disconnecting) a part of the wire.

The trench pattern 155 may minimize side leakage current generated in a multi-stack structure.

That is, in order to improve the quality and productivity of the electroluminescent display device, various light emitting device structures have been proposed to improve the efficiency and lifespan of the light emitting device and reduce power consumption.

Accordingly, a plurality of stacks, that is, a plurality of light emitting units, in order to realize improved efficiency and lifetime characteristics, as well as a light emitting device structure in which one stack, that is, one light emitting unit (EL unit) is applied, A light emitting device having a tandem structure using stacking has been proposed.

In such a tandem structure, that is, a light emitting device having a two-stack structure using a stack of a first light emitting unit and a second light emitting unit, the light emitting region in which light emission occurs through recombination of electrons and holes is the first light emitting unit and the second light emitting unit. Located in each light emitting unit, light emitted from the first light emitting layer of the first light emitting unit and the second light emitting layer of the second light emitting unit may generate constructive interference and provide higher luminance than light emitting devices having a single stack structure.

In addition, the distance between a plurality of sub-pixels constituting one pixel in the light emitting device becomes smaller as the electroluminescent display device has a higher resolution. HTL), charge generation layer (CGL), electron injection layer (EIL), electron transport layer (ETL), etc. are deposited to correspond to all of a plurality of sub-pixels using a common mask (common mask). The light-emitting layers in a plurality of sub-pixels, each of which emits light of different wavelengths, may be individually deposited and formed to correspond to each sub-pixel using a fine metal mask.

In the case of the above light emitting device, when a voltage is applied between the anode and the cathode, lateral leakage current occurs in the horizontal direction of the light emitting device through the common layer formed in the light emitting device as described above, and light emission is required. In addition to the desired sub-pixel, a color mixture defect occurs when an adjacent undesirable sub-pixel emits light.

The above color mixing defect may appear more severely in a light emitting device having a two-stack structure using a stack of a first light emitting unit and a second light emitting unit using constructive interference of light compared to a light emitting device having a single stack structure.

Accordingly, as shown in FIGS. 2 and 3 , the trench pattern 155 is formed between a plurality of sub-pixels SP to increase the thickness of the light emitting portion 122 between neighboring sub-pixels SP. Minimizing leakage current by the light emitting part 122 between neighboring sub-pixels (SP) by thinning or lengthening the path, or by disconnecting (disconnecting) a part of the light emitting part 122 between neighboring sub-pixels (SPs). characterized by

The bank 150 may be extended and disposed to a part of the non-display area NA, but is not limited thereto.

A light emitting unit 122 may be disposed between the anode 121 and the cathode 123 .

The light emitting unit 122 serves to emit light, including a hole injection layer (HIL), a hole transport layer (HTL), a light emitting layer, an electron transport layer (ETL), and an electron injection layer. (Electron Injection Layer; EIL), and some components may be omitted depending on the structure or characteristics of the EL display device. Here, as the light emitting layer, it is also possible to apply an electroluminescent layer and an inorganic light emitting layer.

The hole injection layer is disposed on the anode 121 to facilitate hole injection.

The hole transport layer is disposed on the hole injection layer to smoothly transfer holes to the light emitting layer.

The light emitting layer is disposed on the hole transport layer and may emit light of a specific color by including a material capable of emitting light of a specific color. In addition, the light emitting material may be formed using a phosphorescent material or a fluorescent material.

An electron injection layer may be further disposed on the electron transport layer. The electron injection layer is an organic layer that facilitates electron injection from the cathode 123 and may be omitted depending on the structure and characteristics of the electroluminescent display.

Meanwhile, by further disposing an electron blocking layer or a hole blocking layer to block the flow of holes or electrons adjacent to the light emitting layer, when electrons are injected into the light emitting layer, they move in the light emitting layer and move to the adjacent hole transport layer. Or, when holes are injected into the light emitting layer, the light emitting efficiency may be improved by preventing a phenomenon in which holes move from the light emitting layer and pass to the adjacent electron transport layer.

The cathode 123 is disposed above the light emitting part 122 and serves to supply electrons to the light emitting part 122 . In the bottom emission method, since the cathode 123 needs to supply electrons, it may be made of a metal material such as magnesium or silver-magnesium, which is a conductive material having a low work function, but is not limited thereto.

On the other hand, in the case of the top emission method, the cathode 123 includes indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), and It can be composed of tin oxide (TO)-based transparent conductive oxide.

An encapsulation layer (not shown) may be disposed on the cathode 123 .

Specifically, the encapsulation layer is formed on the upper surface of the substrate 110 on which the light emitting element 120 is formed, and a first protective film, an organic film, and a second protective film are sequentially formed thereon to form an encapsulation layer serving as an encapsulation means. make up However, the number of inorganic layers and organic layers constituting the encapsulation layer is not limited thereto.

In the case of the first passivation layer, since it is composed of an inorganic insulating layer, stack coverage is not good due to the lower step, but since the organic layer serves as a planarization, the second passivation layer is not affected by the step due to the lower layer. In addition, since the thickness of the organic layer made of polymer is sufficiently thick, cracks caused by foreign substances can be compensated for.

For encapsulation, a multi-layered protective film may be positioned opposite to the front surface of the substrate 110 including the secondary protective film, and a transparent adhesive having adhesive properties may be interposed between the encapsulation layer and the protective film.

A polarizing plate for preventing reflection of light incident from the outside may be attached on the protective film, but is not limited thereto.

Meanwhile, the present invention can increase productivity and reduce process and material costs by reducing the number of mask processes required to manufacture an oxide thin film transistor. That is, in the past, a total of 13 mask processes were required to form the first light blocking layer to the light emitting element, but in the present invention, the data wiring is formed on the same layer as the first light blocking layer, and the intermediate electrode for electrical connection with the anode is provided. removed, and by deleting the protective layer, it can be manufactured with a total of 11-12 mask processes.

Meanwhile, as described above, the second connection electrode of the non-display area may be omitted if necessary, and this will be described with reference to FIG. 6 .

6 is a plan view of an electroluminescent display device according to a second exemplary embodiment of the present invention.

The second embodiment of FIG. 6 differs from the first embodiment of FIGS. 2 and 3 described above only in that the pad wiring PAD is directly electrically connected to the pad electrode 236 without the second connection electrode. Since other configurations are substantially the same, redundant description is omitted. The same reference numerals will be used for the same components.

Referring to FIG. 6 , the thin film transistors T1 and T4, the light emitting element 120, and an encapsulation layer (not shown) may be disposed on the substrate 110 of the display area AA.

A pad line PAD and an encapsulation layer may be disposed on the substrate 110 in the non-display area NA.

The first light blocking layers 118 and 119 and the second light blocking layers 128 and 129 may be disposed in the display area AA under the thin film transistors T1 and T4 .

The first light-blocking layers 118 and 119 and the second light-blocking layers 128 and 129 may be formed of a metal capable of collecting hydrogen such as Ti or a Ti alloy such as Ti/Al/Ti.

Sc, V, Mn, Fe, Pd, Nb, Zr, Y, Ta, Ce with excellent hydrogen collection ability other than Ti , La, Sm, U, and the like.

The thin film transistors T1 and T4 may be disposed on the second buffer layer 112 .

The first thin film transistor T1 may include a first gate electrode GE1, a first semiconductor layer ACT1, a first source electrode, and a first drain electrode DE1.

The fourth thin film transistor T4 may include a fourth gate electrode GE4, a fourth semiconductor layer ACT4, a fourth source electrode, and a fourth drain electrode DE4.

The thin film transistors T1 and T4 of the present invention may include semiconductor layers ACT1 and ACT4 made of an oxide semiconductor.

Drain electrodes DE1 and DE4 may be disposed on the protective layer 114 and the first planarization layer 115 .

In this way, as the first drain electrode DE1 is disposed on the first planarization layer 115 in the open area, a short-circuit defect between the same type electrodes is prevented by forming an upper and lower step with the same type electrode, that is, the fourth drain electrode DE4. In addition, the parasitic capacitance is reduced so that the spacing between the same type of electrodes can be reduced. In addition, areas of the first drain electrode DE1 and the fourth drain electrode DE4 may be increased, and thus inspection accuracy may be improved due to an increase in charge amount.

In addition, a pad electrode 236 may be disposed on the protective layer 114 .

The pad electrode 236 according to the second embodiment of the present invention can be electrically connected to the pad wire PAD without the second connection electrode like the first embodiment described above. That is, the pad electrode 236 may be electrically connected to the pad wire PAD under the pad electrode 236 through at least one contact hole.

The pad electrode 236 and the first and fourth drain electrodes DE1 and DE4 may be formed of a metal capable of collecting hydrogen such as Ti or a Ti alloy such as Ti/Al/Ti.

Materials constituting the pad electrode 236 and the first and fourth drain electrodes DE1 and DE4 include Sc, V, Mn, Fe, Pd, Nb, Zr, Y, Ta, Ce, may include La, Sm, U, and the like.

The first planarization layer 115 and the second planarization layer 116 may extend and extend to a part of the non-display area NA to expose the pad electrode 236 .

In addition, the bank 150 covers the first planarization layer 115 and the second planarization layer 116 and extends to a portion of the non-display area NA to cover a portion of the upper surface of the pad electrode 236 and is disposed. can

In the case of the first and second embodiments of the present invention, it is possible to form the first light-blocking layer to the light emitting element through a total of 12 mask processes, so that one mask process can be reduced compared to the previous one. As a result, productivity can be increased and process and material costs can be reduced. In particular, in the case of the second embodiment, as the pad electrode 236 is electrically connected to the pad wire PAD without the second connection electrode, the process of forming and conducting the second connection electrode can be omitted, thereby shortening the process. there is

On the other hand, in the present invention, the protective layer on the gate electrode can be omitted except when the gate electrode is composed of Cu or the upper layer is composed of Cu, so that one mask process can be further reduced. Explain.

7 is a plan view of an electroluminescent display device according to a third exemplary embodiment of the present invention.

The third embodiment of FIG. 7 is different from the first embodiment of FIGS. 2 and 3 described above only in that the protective layer on the first and fourth gate electrodes GE1 and GE4 is omitted, and other configurations are Since they are substantially the same, redundant descriptions are omitted. The same reference numerals will be used for the same components.

Referring to FIG. 7 , the thin film transistors T1 and T4, the light emitting element 120, and an encapsulation layer (not shown) may be disposed on the substrate 110 in the display area AA.

A pad line PAD and an encapsulation layer may be disposed on the substrate 110 in the non-display area NA.

The first light blocking layers 118 and 119 and the second light blocking layers 128 and 129 may be disposed in the display area AA under the thin film transistors T1 and T4 .

For example, the first light blocking layers 118 and 119 may be made of Cu/MoTi, and the second light blocking layers 128 and 129 may be made of MoTi or ITO, but are not limited thereto.

In addition, the first light-blocking layers 118 and 119 and the second light-blocking layers 128 and 129 may be formed of a metal capable of collecting hydrogen such as Ti or a Ti alloy such as Ti/Al/Ti.

Sc, V, Mn, Fe, Pd, Nb, Zr, Y, Ta, Ce with excellent hydrogen collection ability other than Ti , La, Sm, U, and the like.

A first buffer layer 111 may be disposed on the first light blocking layers 118 and 119 , and a second buffer layer 112 may be disposed on the second light blocking layers 128 and 129 .

In this case, the first buffer layer 111 and the second buffer layer 112 may be composed of a single layer of silicon oxide (SiOx) or silicon nitride (SiNx) or multiple layers thereof, but are not limited thereto.

First and fourth semiconductor layers ACT1 and ACT4 may be disposed on the second buffer layer 112 .

The first and fourth semiconductor layers ACT1 and ACT4 may be formed of an oxide semiconductor.

A second connection electrode 126 formed of a conductive semiconductor layer on the same layer as the first and fourth semiconductor layers ACT1 and ACT4 and electrically connected to the pad wiring PAD may be disposed. However, the second connection electrode 126 may be omitted if necessary.

A gate insulating layer 113 made of silicon oxide (SiOx) may be disposed on the first and fourth semiconductor layers ACT1 and ACT4 and the second connection electrode 126 .

First and fourth gate electrodes GE1 and GE4 may be disposed on the gate insulating layer 113 .

For example, the first and fourth gate electrodes GE1 and GE4 may be made of Mo, MoTi, or Ti/Al/Ti, but are not limited thereto. In particular, the first and fourth gate electrodes GE1 and GE4 according to the third embodiment of the present invention are composed of a single layer of a conductive material or multiple layers thereof, except for the case where the upper layer is composed of Cu or the upper layer is composed of Cu. It can be.

Accordingly, a first planarization layer 115 of an organic layer may be disposed on the first and fourth gate electrodes GE1 and GE4 .

The first planarization layer 115 is made of acrylic resin, epoxy resin, phenolic resin, polyamides resin, polyimide resin, or unsaturated polyester. It may be composed of one or more materials of unsaturated polyesters resin, polyphenylene resin, polyphenylene sulfides resin, and benzocyclobutene, but is not limited thereto. .

In the case of the third embodiment of the present invention, since the first and fourth gate electrodes GE1 and GE4 are made of a conductive material other than Cu, the first planarization layer 115 of an organic film may be directly disposed thereon. . That is, when the organic film is deposited on Cu, interface characteristics are not good, so when the gate electrode is made of Cu, the first planarization layer is disposed after the protective layer of the inorganic film is disposed.

In the case of the third embodiment of the present invention, the drain electrodes DE1 and DE4 may be disposed on the gate insulating layer 113 and the first planarization layer 115 .

That is, the first drain electrode DE1 is disposed on the gate insulating layer 113 in the open area, and a part of the first drain electrode DE1 is electrically connected to the first semiconductor layer ACT1 through a contact hole, and the other part is a fourth gate electrode ( GE4) can be directly connected.

In addition, the fourth drain electrode DE4 is disposed on the first planarization layer 115 and can be electrically connected to the fourth semiconductor layer ACT4 through a contact hole.

In this way, as the first drain electrode DE1 is disposed on the gate insulating layer 113 in the open region, a short defect between the same type electrodes is improved by forming a step difference between the top and bottom of the same type electrode, that is, the fourth drain electrode DE4. In addition, parasitic capacitance is reduced, so that the spacing between homogeneous electrodes can be reduced. In addition, areas of the first drain electrode DE1 and the fourth drain electrode DE4 may be increased, and thus inspection accuracy may be improved due to an increase in charge amount.

The first and fourth drain electrodes DE1 and DE4 may be formed of a metal capable of collecting hydrogen such as Ti or a Ti alloy such as Ti/Al/Ti.

In addition, materials constituting the first and fourth drain electrodes DE1 and DE4 include Sc, V, Mn, Fe, Pd, Nb, Zr, Y, Ta, Ce, La, Sm, U and the like.

In particular, in the case of the third embodiment, since the protective layer is omitted, the distance between the first and fourth drain electrodes DE1 and DE4 and the oxide thin film transistors T1 and T4 is closer, so that the hydrogen trapping effect can be maximized.

In addition, in the case of the third embodiment of the present invention, it is possible to form the light emitting element from the first light-shielding layer through a total of 11 mask processes by omitting the protective layer, so that one mask process is required compared to the first and second embodiments. can be further reduced. As a result, productivity can be further increased and process and material costs can be further reduced.

An electroluminescent display device according to embodiments of the present invention can be described as follows.

An electroluminescent display device according to an exemplary embodiment of the present invention includes a substrate divided into a display area and a non-display area, a first light-blocking layer and data lines disposed on the substrate in the display area, and the first light-blocking layer and the data lines. A first buffer layer disposed above, a semiconductor layer disposed above the first buffer layer and composed of an oxide semiconductor, a gate insulating layer disposed above the semiconductor layer, a gate electrode disposed above the gate insulating layer, and a semiconductor layer disposed above the gate electrode A passivation layer and a first planarization layer, a drain electrode disposed on the passivation layer exposed by removing a partial region of the first planarization layer, a second planarization layer disposed on the drain electrode and the first planarization layer, and the second planarization layer. It is disposed on the planarization layer, and may include a light emitting element composed of an anode, a light emitting part, and a cathode.

An electroluminescent display device according to another embodiment of the present invention includes a substrate divided into a display area and a non-display area, a first light-blocking layer and data lines disposed on the substrate of the display area, the first light-blocking layer and the data line. A first buffer layer disposed on the wiring, a semiconductor layer disposed on the first buffer layer and composed of an oxide semiconductor, a gate insulating layer disposed on the semiconductor layer, a gate electrode disposed on the gate insulating layer, and a semiconductor layer disposed on the gate electrode A first planarization layer, a drain electrode disposed on the passivation layer from which a partial region of the first planarization layer is removed and exposed, a second planarization layer disposed on the drain electrode and the first planarization layer, and an upper portion of the second planarization layer It is disposed on, and may include a light emitting element consisting of an anode, a light emitting unit and a cathode.

According to another feature of the present invention, the electroluminescent display device further includes a second light blocking layer disposed over the first buffer layer to overlap the first light blocking layer and a second buffer layer disposed over the second light blocking layer, The semiconductor layer may be disposed on the second buffer layer.

According to another feature of the present invention, the first light blocking layer and the second light blocking layer may be composed of Ti or a Ti alloy.

According to another feature of the present invention, a portion of the semiconductor layer may be electrically connected to the data line and another portion may be electrically connected to the first light blocking layer.

According to another feature of the present invention, the semiconductor layer is connected to the first light blocking layer through a first light blocking layer contact hole, the drain electrode is connected to the semiconductor layer through a drain contact hole, and the first light blocking layer is connected to the first light blocking layer through a drain contact hole. The layer contact hole and the drain contact hole may overlap.

According to another feature of the present invention, an electroluminescent display device includes a high potential power line disposed on the substrate, a second light blocking layer disposed on the first buffer layer, and the oxide semiconductor on the same layer as the semiconductor layer. A semiconductor layer may be further included.

According to another feature of the present invention, the electroluminescent display device further includes a driving gate electrode disposed on the driving semiconductor layer, and the drain electrode may be electrically connected to the driving gate electrode through a contact hole.

According to another feature of the present invention, the electroluminescent display device may further include a driving drain electrode disposed on the passivation layer and the first planarization layer and electrically connected to the driving semiconductor layer.

According to another feature of the present invention, an electroluminescent display device includes a high potential power line disposed on the substrate, a second light blocking layer disposed on the first buffer layer, and the oxide semiconductor on the same layer as the semiconductor layer. A semiconductor layer may be further included.

According to another feature of the present invention, the electroluminescent display device further includes a driving gate electrode disposed on the driving semiconductor layer, and the drain electrode may be directly connected to the driving gate electrode.

According to another feature of the present invention, the electroluminescent display device may further include a driving drain electrode disposed on the first planarization layer and electrically connected to the driving semiconductor layer.

According to another feature of the present invention, a portion of the driving semiconductor layer may be electrically connected to the high potential power supply wire, and a portion of the driving semiconductor layer may be electrically connected to the second light blocking layer.

According to another feature of the present invention, the drain electrode and the driving drain electrode may be composed of Ti or a Ti alloy.

According to another feature of the present invention, the driving semiconductor layer is connected to the second light blocking layer through a second light blocking layer contact hole, and the driving drain electrode is connected to the driving semiconductor layer through a driving drain contact hole; The second light blocking layer contact hole and the driving drain contact hole may overlap.

According to another feature of the present invention, the electroluminescent display device may further include a pad wire disposed on the substrate in the non-display area.

According to another feature of the present invention, the electroluminescent display device further includes a connection electrode disposed on the second buffer layer and electrically connected to the pad wiring, wherein the connection electrode is a semiconductor made of a conductor of the oxide semiconductor. can be configured.

According to another feature of the present invention, the electroluminescent display device further includes a pad electrode disposed on the passivation layer and electrically connected to the connection electrode, wherein the pad electrode is on the same layer as the drain electrode. It may be made of the same conductive material as

According to another feature of the present invention, the electroluminescent display device further includes a pad electrode disposed on the passivation layer and electrically connected to the pad wiring, wherein the pad electrode is on the same layer as the drain electrode. It may be made of the same conductive material as

According to another feature of the present invention, the electroluminescent display device further includes a bank disposed on the second planarization layer and including an opening exposing a portion of the anode, and a trench pattern formed by removing a portion of the bank. can include

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and may be variously modified and implemented without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed according to the following claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: electroluminescent display device
110: substrate
111: first buffer layer
112: second buffer layer
113: gate insulating layer
114: protective layer
115: first planarization layer
116: second planarization layer
118, 119: first light blocking layer
120: light emitting element
121 anode
122: light emitting part
123: cathode
125: first connection electrode
126: second connection electrode
135 additional low potential power wiring
136, 236: pad electrode
150: bank
155: trench pattern
156: spacer
AA: display area
ACT1, ACT4:
DL: data wire
DE1, DE4: drain electrode
EML: light emission control signal wiring
GE1, GE4: gate electrode
HPPL: High Potential Power Wiring
HPPL': additional high-potential power wiring
ISL: initialization signal wiring
LPPL: Low Potential Power Wiring
NA: non-display area
OA: open area
OP: opening
PAD: pad wiring
PN: display panel
SL: scan wiring
SP: sub pixel
SSL: sensing wiring
T1, T4: thin film transistor

Claims (20)

a substrate divided into a display area and a non-display area;
a first light blocking layer and data lines disposed on the substrate of the display area;
a first buffer layer disposed on the first light blocking layer and the data line;
a semiconductor layer disposed on the first buffer layer and made of an oxide semiconductor;
a gate insulating layer disposed over the semiconductor layer;
a gate electrode disposed on the gate insulating layer;
a protective layer and a first planarization layer disposed on the gate electrode;
a drain electrode disposed on the passivation layer exposed by removing a portion of the first planarization layer;
a second planarization layer disposed on the drain electrode and the first planarization layer; and
and a light emitting element disposed on the second planarization layer and including an anode, a light emitting part, and a cathode. a substrate divided into a display area and a non-display area;
a first light blocking layer and data lines disposed on the substrate of the display area;
a first buffer layer disposed on the first light blocking layer and the data line;
a semiconductor layer disposed on the first buffer layer and made of an oxide semiconductor;
a gate insulating layer disposed over the semiconductor layer;
a gate electrode disposed on the gate insulating layer;
a first planarization layer disposed on the gate electrode;
a drain electrode disposed on the gate insulating layer exposed by removing a portion of the first planarization layer;
a second planarization layer disposed on the drain electrode and the first planarization layer; and
and a light emitting element disposed on the second planarization layer and including an anode, a light emitting part, and a cathode. According to claim 1 or 2,
a second light blocking layer disposed on the first buffer layer and overlapping the first light blocking layer; and
Further comprising a second buffer layer disposed on the second light blocking layer,
wherein the semiconductor layer is disposed on the second buffer layer. According to claim 3,
The first light blocking layer and the second light blocking layer are made of Ti or a Ti alloy. According to claim 2,
The semiconductor layer, wherein a part is electrically connected to the data line, and another part is electrically connected to the first light blocking layer. According to claim 5,
The semiconductor layer is connected to the first light blocking layer through a first light blocking layer contact hole;
The drain electrode is connected to the semiconductor layer through a drain contact hole;
The electroluminescent display device of claim 1 , wherein the first light blocking layer contact hole and the drain contact hole overlap each other. According to claim 1,
a high-potential power wiring disposed over the substrate;
a second light blocking layer disposed on the first buffer layer; and
and a driving semiconductor layer made of the oxide semiconductor on the same layer as the semiconductor layer. According to claim 7,
Further comprising a driving gate electrode disposed on the driving semiconductor layer,
wherein the drain electrode is electrically connected to the driving gate electrode through a contact hole. According to claim 8,
and a driving drain electrode disposed on the passivation layer and the first planarization layer and electrically connected to the driving semiconductor layer. According to claim 2,
a high-potential power wiring disposed over the substrate;
a second light blocking layer disposed on the first buffer layer; and
and a driving semiconductor layer made of the oxide semiconductor on the same layer as the semiconductor layer. According to claim 10,
Further comprising a driving gate electrode disposed on the driving semiconductor layer,
The drain electrode is directly connected to the driving gate electrode. According to claim 11,
and a driving drain electrode disposed on the first planarization layer and electrically connected to the driving semiconductor layer. According to claim 9 or 12,
The driving semiconductor layer, wherein a part is electrically connected to the high-potential power supply wire, and another part is electrically connected to the second light blocking layer. According to claim 13,
The drain electrode and the driving drain electrode are made of Ti or a Ti alloy. According to claim 13,
The driving semiconductor layer is connected to the second light blocking layer through a second light blocking layer contact hole;
The driving drain electrode is connected to the driving semiconductor layer through a driving drain contact hole;
The electroluminescent display device of claim 1 , wherein the second light blocking layer contact hole overlaps with the driving drain contact hole. According to claim 3,
The electroluminescent display device further comprises a pad wire disposed on the substrate in the non-display area. 17. The method of claim 16,
Further comprising a connection electrode disposed on the second buffer layer and electrically connected to the pad wiring,
The electroluminescent display device of claim 1 , wherein the connection electrode is formed of a semiconductor formed by conducting the oxide semiconductor. 18. The method of claim 17,
Further comprising a pad electrode disposed on the protective layer and electrically connected to the connection electrode,
wherein the pad electrode is formed of the same conductive material as the drain electrode and the same layer as the drain electrode. 17. The method of claim 16,
Further comprising a pad electrode disposed on the protective layer and electrically connected to the pad wiring,
wherein the pad electrode is formed of the same conductive material as the drain electrode and the same layer as the drain electrode. According to claim 3,
a bank disposed on the second planarization layer and including an opening exposing a portion of the anode; and
and a trench pattern formed by removing a portion of the bank.

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