KR20230034137A - Command address control circuit, a semiconductor apparatus, and a semiconductor system including the same - Google Patents

Abstract

A semiconductor device may include a command address control circuit. The command address control circuit receives a row command address signal and a column command address signal. The row command address signal and the column command address signal may be selectively inverted based on the logic level of at least one bit of the row command address signal.

Description

Command address control circuit, semiconductor device and semiconductor system including the same

The present invention relates to integrated circuit technology, and more particularly, to a command address control circuit, a semiconductor device and a semiconductor system including the same.

An electronic device includes many electronic components, and among them, a computer system may include many semiconductor devices made of semiconductors. Semiconductor devices constituting a computer system may include a processor or memory controller operating as a master device and a memory device or storage device operating as a slave device. The master device may provide a command address signal to the slave device, and the slave device may perform various operations based on the command address signal. For example, the slave device may perform an active operation, a read operation, and a write operation based on the command address signal. The master device may provide the command address signal to the slave device in synchronization with a clock signal. As semiconductor device designs are integrated and functions of semiconductor devices are diversified, the number of pins or pads for transmitting and receiving the command address signal tends to decrease. Accordingly, in recent semiconductor systems, command address signal sets are transmitted and received through limited command address pins or pads during a plurality of clock cycles.

An embodiment of the present invention includes a command address control circuit capable of receiving a command address signal set including a row command address signal and a column command address signal, and performing an inversion operation and an error correction operation on the command address signal set; A semiconductor device and a semiconductor system including the same may be provided.

An embodiment of the present invention provides a command address control circuit capable of performing an inversion operation of a row command address signal and a column command address signal based on at least one bit of a row command address signal, a semiconductor device and a semiconductor system including the same. can provide

An embodiment of the present invention provides a command address control circuit capable of correcting errors in a row command address signal and a column command address signal based on at least one bit of column command address signals, a semiconductor device and a semiconductor system including the same. can

According to an embodiment of the present invention, one of a row command signal and a row address signal is generated based on a row command signal received during a next unit cycle according to a type of a row command signal generated based on a row command address signal received during a current unit cycle. A command address control circuit that can be generated, and a semiconductor device and a semiconductor system including the same can be provided.

According to an embodiment of the present invention, one of a column command signal and a column address signal is selected based on a column command signal received during the next unit cycle according to the type of the column command signal generated based on the column command address signal received during the current unit cycle. A command address control circuit that can be generated, and a semiconductor device and a semiconductor system including the same can be provided.

A semiconductor device according to an embodiment of the inventive concept receives a row command address signal and a column command address signal, and outputs the row command address signal and the column command address signal based on a logic level of at least one bit of the row command address signal. It may include a command address control circuit that selectively inverts .

A semiconductor device according to an embodiment of the present invention receives a row command address signal and a column command address signal, and detects an error in the row command address signal and the column command address signal based on at least one bit of the column command address signal. A command address control circuit for correcting may be included.

A semiconductor device according to an embodiment of the present invention generates a row command address signal including one bit including inversion information and a column command address signal including one bit including parity, and generates the row command address signal and and a command generation circuit configured to transmit the column command address signal in synchronization with a clock signal.

A semiconductor system according to an embodiment of the present invention generates a row command address signal including one bit including inversion information and a column command address signal including one bit including parity, and the row command signal and the a first semiconductor device that transmits column address signals to a set of command address signals; and receiving the set of command address signals, selectively inverting the set of command address signals based on one bit including the inversion information, and inverting the set of command address signals based on one bit including the parity. A second semiconductor device for correcting errors may be included.

A command address control circuit according to an embodiment of the present invention receives a row command address signal and a column command address signal, and selectively selects the row command address signal and the column command address signal based on one bit of the row command address signal. an inversion circuit for generating an internal row command address signal and an internal column command address signal by inverting to ; a row control circuit configured to generate a row command signal and a row address signal based on the internal row command address signal; and a column control circuit generating a column command signal and a column address signal based on the internal column command address signal.

A command address control circuit according to an embodiment of the present invention receives a row command address signal and a column command address signal, and based on one bit of the column command address signal, an error of the row command address signal and the column command address signal is detected. an error correcting circuit for generating an internal row command address signal and an internal column command address signal by correcting ; a row control circuit configured to generate a row command signal and a row address signal based on the internal row command address signal; and a column control circuit generating a column command signal and a column address signal based on the internal column command address signal.

According to an exemplary embodiment of the inventive concept, a configuration of a command address control circuit may be simplified, and operation speed of a semiconductor device and a semiconductor system may be improved.

1 is a diagram showing the configuration of a semiconductor system according to an embodiment of the present invention.
2A is a diagram showing the configuration of a command address signal according to the prior art.
2B is a table showing the configuration of a command address signal generated according to an embodiment of the present invention.
3 is a diagram showing the configuration of a command control circuit according to an embodiment of the present invention.

1 is a diagram showing the configuration of a semiconductor system 100 according to an embodiment of the present invention. In FIG. 1 , the semiconductor system 100 may include a first semiconductor device 110 and a second semiconductor device 120 . The first semiconductor device 110 may provide various control signals necessary for the operation of the second semiconductor device 120 . The first semiconductor device 110 may include various types of devices. For example, the first semiconductor device 110 may include a central processing unit (CPU), a graphic processing unit (GPU), a multi-media processor (MMP), and a digital signal processor. , an application processor (AP) and a host device such as a memory controller. The second semiconductor device 120 may be, for example, a memory device, and the memory device may include a volatile memory and a non-volatile memory. The volatile memory may include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM), and the non-volatile memory may include read only memory (ROM), programmable ROM (PROM), electrically erase and Programmable ROM), EPROM (Electrically Programmable ROM), flash memory, PRAM (Phase change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), FRAM (Ferroelectric RAM), and the like.

The second semiconductor device 120 may be connected to the first semiconductor device 110 through a plurality of buses. The plurality of buses may be signal transmission paths, links, or channels for transmitting signals. The plurality of buses may include a clock bus 101, a command address bus 102, and a data bus 103. The clock bus 101 and the command address bus 102 may be unidirectional buses from the first semiconductor device 110 to the second semiconductor device 120, and the data bus 103 may be a bidirectional bus. there is. The second semiconductor device 120 may be connected to the first semiconductor device 110 through a clock bus 101 and receive a clock signal WCK through the clock bus 101 . The clock signal WCK may include one or more clock signal pairs. The second semiconductor device 120 is connected to the first semiconductor device 110 through the command address bus 102 and receives a command address from the first semiconductor device 110 through the command address bus 102 . A signal (CA<0:4>) can be received. The command address signals CA<0:4> may include a plurality of bits. The second semiconductor device 120 may receive the command address signal CA<0:4> based on the clock signal WCK. The second semiconductor device 120 is connected to the first semiconductor device 110 through a data bus 103, and receives data DQ from the first semiconductor device 110 through the data bus 103. Data DQ may be received or transmitted to the first semiconductor device 110 . An operation in which the data DQ is transmitted from the first semiconductor device 110 to the second semiconductor device 120 may be defined as a data input operation and/or a write operation, and the data DQ may be transmitted to the second semiconductor device 120 . An operation transmitted from the second semiconductor device 120 to the first semiconductor device 110 may be defined as a data output operation and/or a read operation.

The first semiconductor device 110 may include a clock generation circuit 111 , a command address control circuit 112 , and a data input/output circuit 113 . The clock generation circuit 111 may generate the clock signal WCK and transmit the clock signal WCK to the second semiconductor device 120 through the clock bus 101 . The clock generation circuit 111 may provide the clock signal WCK to the command address generation circuit 112 and the data input/output circuit 113 . The clock generation circuit 111 may generate the clock signal WCK having a frequency corresponding to the operating speed of the semiconductor system 100 . In one embodiment, the clock generation circuit 111 may generate the clock signal WCK having a frequency lower or higher than a frequency corresponding to the operating speed of the semiconductor system 100 . The clock generation circuit 111 includes various clocks such as a ring oscillator, a delay locked loop circuit, and a phase locked loop circuit to generate the clock signal WCK. It may contain at least one of the generators. In one embodiment, the clock generation circuit 111 adjusts the frequency and/or phase of the clock signal WCK, and transmits the frequency and/or phase-adjusted clock signal to the command address generation circuit 112 and / or may be provided to the data input/output circuit 113.

The command address generation circuit 112 may generate a command address signal set based on the request REQ. The command address generating circuit 112 may generate a command address signal set including different information based on various requests REQ. The command address generating circuit 112 transmits the command address signals CA<0:4> through the command address bus 102 for a plurality of cycles to transmit the command address signal set to the second semiconductor device ( 120) can be transmitted. Although the command address bus 102 is illustrated as being able to transmit the command address signal CA<0:4> of 5 bits, the number of bits of the command address signal CA<0:4> varies. will be able to change The command address signal set may include a row command address signal and a column command address signal. The row command address signal may be a signal used by the second semiconductor device 120 to generate a row command signal RCMD and a row address signal RADD, and the column command address signal may be a signal used to generate a row command signal RCMD and a row address signal RADD. ) may be a signal used to generate the column command signal CCMD and the column address signal CADD.

The command address generating circuit 112 receives the clock signal WCK from the clock generating circuit 111 and generates the command address signals CA<0:4> in synchronization with the clock signal WCK. It can be output to the command address bus 102. The command address generating circuit 112 may output a command address signal set including the row command address signal and the column command address signal to the command address bus 102 during one or more unit cycles. The unit cycle may be, for example, 4 cycles of the clock signal WCK. The row command address signal and the column command address signal may include two types. The row command address signal of the first type and the column command address signal of the first type may be a set of command address signals transmitted during 4 cycles of the clock signal WCK. The row command address signal of the second type and the column command address signal of the second type may be a set of command address signals transmitted during 8 cycles of the clock signal WCK. For example, a 5-bit command address signal CA<0:4> may be transmitted through the command address bus 102 during one cycle of the clock signal WCK, and 3 bits CA< 0:2>) may be allocated as a row command address signal, and two bits (CA<3:4>) may be allocated as a column command address signal. Accordingly, the first-type row command address signal may include a total of 12 bits, and the second-type row command address signal may include a total of 24 bits. The second-type column command address signal may include a total of 8 bits, and the second-type column command address signal may include a total of 16 bits.

The command address generation circuit 112 generates the command address signal CA during 4 cycles of the clock signal WCK when the row command address signal or the column command address signal generated according to the request REQ is of the first type. <0:4>) may transmit the row command address signal or the column command address signal. When the row command address signal or the column command address signal generated according to the request REQ is of the second type, the command address generation circuit 112 generates the command address signal CA during 8 cycles of the clock signal WCK. <0:4>) may transmit the row command address signal or the column command address signal. At least one bit of the row column address signal transmitted during the unit cycle may include inversion information used to perform an inversion operation on the row column address signal and the column command address signal transmitted during the unit cycle. there is. At least one bit of the column address signal transmitted during the unit cycle may include parity to detect and correct errors in the row column address signal and the column command address signal transmitted during the unit cycle.

The data input/output circuit 113 is connected to the second semiconductor device 120 through the data bus 103 and may transmit or receive the data DQ through the data bus 103 . The data input/output circuit 113 may receive the clock signal WCK from the clock generation circuit 111 . The data input/output circuit 113 may output internal data of the first semiconductor device 110 as the data DQ through the data bus 103 based on the clock signal CLK during the write operation. there is. The data input/output circuit 113 receives the data DQ transmitted through the data bus 103 based on the clock signal WCK during the read operation, and receives the first data DQ based on the data DQ. Internal data of the semiconductor device 110 may be generated.

The second semiconductor device may include a memory cell array 121 , an internal clock generation circuit 122 , the command address control circuit 123 , and a data input/output circuit 124 . Although not shown, the memory cell array 121 may include a plurality of memory banks. A plurality of word lines WL may be disposed in a row direction and a plurality of bit lines BL may be disposed in a column direction for each of a plurality of memory banks. A plurality of memory cells MC may be connected to points where the plurality of word lines WL and the plurality of bit lines BL intersect. When a specific word line is selected from among the plurality of word lines (WL) based on a row address signal (RADD) and a specific bit line is selected from among the plurality of bit lines (BL) based on a column address signal (CADD), the A target memory cell connected between a selected word line and the selected bit line may be accessed.

The internal clock generation circuit 122 is connected to the clock bus 101 and may receive the clock signal WCK transmitted from the first semiconductor device 110 through the clock bus 101 . The internal clock generation circuit 122 may generate a plurality of internal clock signals based on the clock signal WCK. The internal clock generation circuit 122 provides the plurality of internal clock signals to the command address control circuit 123 and the data input/output circuit 124 so that the command address control circuit 123 and the data input/output circuit 124 ) to operate based on the clock signal WCK. The internal clock generation circuit 122 may generate a plurality of internal clock signals having various frequencies and/or various phases. The internal clock generation circuit 122 may generate a command clock signal CCLK and a data clock signal DCLK based on the clock signal WCK. The internal clock generation circuit 122 may generate the command clock signal CCLK and the data clock signal DCLK by adjusting the frequency and/or phase of the clock signal WCK. The internal clock generation circuit 122 may include a frequency divider, a frequency multiplier, a delay locked loop circuit, etc. to adjust the frequency and/or phase of the clock signal WCK. .

The command address control circuit 123 is connected to the command address bus 102 and may receive the command address signals CA<0:4> transmitted from the first semiconductor device 110 . The command address control circuit 123 may receive the internal clock signal from the internal clock generation circuit 122 . The command address control circuit 123 may receive the command address signals CA<0:4> in synchronization with the command clock signal CCLK. The command address control circuit 123 may generate a row command signal RCMD and a row address signal RADD based on the row command address signal included in the command address signals CA<0:4>. Although not limited to, for example, the low command signal RCMD may include an active signal, a precharge signal, a refresh signal, and the like. The low command signal RCMD may include a first type low command signal and a second type low command signal. The first type low command signal may be a low command signal generated based on the first type low command address signal, and the second type low command signal may be generated based on the second type low command address signal. It may be a generated raw command signal. The command address control circuit 123 may generate a column command signal CCMD and a column address signal CADD based on column command address signals included in the command address signals CA<0:4>. Although not limited thereto, the column command signal CCMD may include the read signal, the write signal, a read training signal, a write training signal, and the like. The column command signal CCMD may include a first type column command signal and a second type column command signal. The first-type column command signal may be a column command signal generated based on the first-type column command address signal, and the second-type column command signal may be generated based on the second-type column command address signal. It may be a generated raw command signal. The command address control circuit 123 may perform an inversion operation and/or an error correction operation based on specific bits included in the command address signals CA<0:4>. The command address control circuit 123 receives the command address signals CA<0:4> during the unit cycle and outputs the row command address signal and the column command through the command address bus 102 for each unit cycle. The command address signal set including an address signal may be received. The command address control circuit 123 may selectively invert the row command address signal and the column command address signal based on at least one bit of the row command address signal received during the unit cycle. The command address control circuit 123 may correct errors in the row command address signal and the column command address signal based on at least one bit of the column command address signal received during the unit cycle.

The data input/output circuit 124 is connected to the data bus 103 and transmits the data DQ to the first semiconductor device 110 through the data bus 103 or the first semiconductor device 110 ), the transmitted data DQ may be received. The data input/output circuit 124 may receive the internal clock signal from the internal clock generation circuit 122 . The data input/output circuit 124 may receive the data DQ transmitted from the first semiconductor device 110 in synchronization with the data clock signal DCLK, and may receive the data DQ transmitted from the first semiconductor device 110 in synchronization with the data clock signal DCLK. The data DQ may be transmitted to the first semiconductor device 110 . During the write operation, the data input/output circuit 124 receives the data DQ from the first semiconductor device 110 to generate internal data of the first semiconductor device 110, and transfers the internal data to the memory. It may be provided as a cell array 121 . During the read operation, the data input/output circuit 124 receives the internal data output from the memory cell array 121 and transmits the internal data to the first semiconductor device 110 as the data DQ. can

The second semiconductor device 120 may further include a row circuit 125 and a column circuit 126 . The row circuit 125 may select a specific word line based on a row address signal RADD to access a target memory cell among the plurality of memory cells when an active signal among the row command signals RCMD is enabled. . The column circuit 126 is configured to access a specific bit line based on a column address signal CADD to access the target memory cell among the plurality of memory cells when a read signal and a write signal of the column command signal CCMD are enabled. can choose During the read operation, the column circuit 126 reads the internal data stored in the target memory cell connected between the selected word line and the selected bit line based on the read signal, and converts the internal data to the data input/output circuit. (124) can be output. During the write operation, the column circuit 126 receives the internal data provided from the data input/output circuit 124 based on the write signal, and transfers the internal data to the target memory cell connected between the selected word line and the selected bit line. Data can be written.

2A is a diagram showing the configuration of command address signals CA<0:4> according to the prior art, and FIG. 2B shows the configuration of command address signals CA<0:4> according to an embodiment of the present invention. it is a drawing 2A and 2B representatively show the second type of row command address signal and the second type of column command address signal. The row command address signal of the second type is to be generated as an active signal (ACT) among the row command signals, and the column command address signal of the second type is to be generated as a write signal (WR) among the column command signals. exemplify that The second type row command address signal includes command information (H or L) used to generate the row command signal and row address signal, bank address information (BA0, BA1, BA2, BA3) and row address information (R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13 V(R16), V(R15), V(R14)) may be included. The second type of column command address signal includes command information (H, L, or AP) used to generate a column command signal and column address signal, bank address information (BA0, BA1, BA2, BA3), and column address information (C0). , C1, C2, C3, C4, C5, V(C6)).

Referring to FIG. 2A , the row command address signal and the column command address signal may independently include inversion information CABI and a parity bit PAR. In other words, the low command address signal generated from the command address signals CA<0:2> transmitted during 8 cycles of the clock signal (WCK0-WCK7) includes at least one signal for selectively inverting the low command address signal. and at least one bit for detecting and correcting an error of the row command address signal. The column command address signal generated from the command address signal (CA<3:4>) transmitted during 8 cycles (WCK0-WCK7) of the clock signal includes at least one bit (for selectively inverting the column command address signal) CABI) and at least one bit PAR for detecting and correcting an error of the column command address signal. For example, the second bit CA<1> of the low command address signal transmitted during the first cycle WCK0 corresponds to the low command address signal transmitted during the first to eighth cycles WCK0-WCK7. It may include reversal information (CABI) for selectively inverting . A third bit (CA<2>) of the low command address signal transmitted during the eighth cycle (WCK7) detects an error in the low command address signal transmitted during the first to eighth cycles (WCK0-WCK7) and may be a parity bit (PAR) for correcting. The second bit CA<4> of the column command address signal transmitted during the first cycle WCK0 selectively inverts the column command address signal transmitted during the first to eighth cycles WCK0-WCK7. It may include reverse information (CABI) for The second bit CA<4> of the column command address signal transmitted during the eighth cycle WCK7 detects an error in the column command address signal transmitted during the first to eighth cycles WCK0-WCK7. and may be a parity bit (PAR) for correcting. As in the prior art, when a row command address signal and a column command address signal independently include bits for performing an inversion operation and an error correction operation, a circuit for receiving a command address signal becomes complicated and it is difficult to perform a high-speed operation. can be disadvantageous

Accordingly, in an embodiment of the present invention, a command address signal may be configured as follows. Referring to FIG. 2B , an embodiment of the present invention may include bits for performing an inversion operation and an error correction operation in a command address signal set transmitted in one unit cycle. A low command address signal transmitted during one unit cycle may include one bit including inversion information CABI to perform the inversion operation. The column command address signal transmitted during the one unit cycle may include one bit corresponding to a parity bit (PAR) to perform the error correction operation. For example, the second bit CA<1> of the low command address signal transmitted during the first cycle WCK0 corresponds to the low command address signal transmitted during the first to fourth cycles WCK0-WCK3. and inversion information CABI for selectively inverting the column command address signal transmitted during the first to fourth cycles WCK0 to WCK3. The second bit CA<4> of the column command address signal transmitted during the fourth cycle WCK3 corresponds to the row command address signal transmitted during the first to fourth cycles WCK0-WCK3 and the first bit CA<4>. It may be a parity bit (PAR) for detecting and correcting an error of the column command address signal transmitted during cycles WCK0 to WCK3 to fourth. The second bit CA<1> of the low command address signal transmitted during the fifth cycle WCK4 corresponds to the low command address signal transmitted during the fifth to eighth cycles WCK4-WCK7 and the fifth bit CA<1>. and inversion information CABI for selectively inverting the column command address signals transmitted during the to eighth cycles WCK4 to WCK7. The second bit CA<5> of the column command address signal transmitted during the eighth cycle WCK7 corresponds to the row command address signal transmitted during the fifth to eighth cycles WCK4-WCK7 and the fifth bit CA<5>. It may be a parity bit (PAR) for detecting and correcting an error of the column command address signal transmitted during the through eighth cycles (WCK4 to WCK7). When comparing the embodiment of the present invention with the prior art, since the row command address signal of the embodiment of the present invention may not include a parity bit (PAR) for performing an error correction operation, in the prior art, the 5th cycle (WCK4) The second bit (CA<1>) of the low command address signal transmitted during the 8th cycle (WCK7) in the embodiment of the present invention is the third bit (CA<2>) of the low command address signal transmitted during the eighth cycle (WCK7). can be transmitted Since the column command address signal according to the embodiment of the present invention may not include inversion information (CABI) for performing an inversion operation, the second column command address signal transmitted during the fourth cycle (WCK3) in the prior art The bit CA<4> may be transmitted as the second bit CA<4> of the column command address signal transmitted during the first cycle WCK0 in an embodiment of the present invention.

3 is a diagram showing the configuration of a command address control circuit 300 according to an embodiment of the present invention. The command address control circuit 300 may be applied as the command address control circuit 123 shown in FIG. 1 . Referring to FIG. 3 , the command address control circuit 300 may receive command address signals CA<0:2> and CA<3:4>. The command address control circuit 300 receives the command address signals CA<0:2> and CA<3:4> during a unit cycle, thereby controlling the row command address signal CAR<0:11> and the column command. Address signals CAC<0:7> may be received. The command address control circuit 300 generates the row command address signal CAR<0:11> and the column command based on a logic level of at least one bit of the row command address signal CAR<0:11>. The address signals (CAC<0:7>) can be selectively inverted. The command address control circuit 300 controls the row command address signals CAR<0:11> and the column command address signals (CAC<0:7>) based on at least one bit of the column command address signals CAC<0:7>. CAC<0:7>) errors can be detected and corrected. The command address control circuit 300 generates a row command signal RCMD and a row address signal RADD based on the row command address signals CAR<0:11>, and the column command address signal CAC< 0:7>), the column command signal CCMD and the column address signal CADD may be generated.

The command address control circuit 300 may include a command address buffer 310 , an inversion circuit 320 , an error correction circuit 330 , a row control circuit 340 and a column control circuit 350 . The command address buffer 310 may receive the command address signals CA<0:4>. The command address buffer 310 receives the command address signal CA<0:4> and generates the row command address signal CAR<0:11> and the column command address signal CAC<0:7>. can create The command address buffer 310 may receive a set of command address signals by receiving the command address signals CA<0:4> during a unit cycle. The command address buffer CA<0:4> may generate the command address signal set by latching the command address signal CA<0:4> received during the unit cycle. The command address signal set may include the row command address signal CAR<0:11> and the column command address signal CAC<0:7>.

The inversion circuit 320 may receive the row command address signals CAR<0:11> and the column command address signals CAC<0:7> from the command address buffer 310 . The inversion circuit 320 outputs the row command address signal CAR<0:11> and the column command address signal CAC based on at least one bit of the row command address signal CAR<0:11>. <0:7>) can be optionally inverted. The inversion circuit 320 outputs the row command address signal CAR<0:11> and the column command address signal CAC based on at least one bit of the row command address signal CAR<0:11>. <0:7>) can be optionally inverted. The inversion circuit 320 converts the row command address signal CAR<0:11> and the column when at least one bit of the row command address signal CAR<0:11> has a first logic level. Logic levels of the command address signals CAC<0:11> may be inverted. The inversion circuit 320 converts the row command address signal CAR<0:11> and the column when at least one bit of the row command address signal CAR<0:11> has a second logic level. The logic level of the command address signals CAC<0:7> may not be inverted. The inversion circuit 320 generates inversion row command address signals 321 by selectively inverting the row command address signals CAR<0:11>, and generates the column command address signals CAC<0:7 >) can be selectively inverted to generate the inversion column command address signal 322 .

The error correction circuit 330 may detect and correct errors in the row command address signal CAR<0:11> and the column command address signal CAC<0:7>. It is connected to the inversion circuit 320 and may receive the inversion row command address signal 321 and the inversion column command address signal 322 from the inversion circuit 320 . The error correction circuit 330 may detect and correct errors of the inversion row command address signal 321 and the inversion column command address signal 322 . The error correction circuit 330 detects errors in the inversion row command address signal 321 and the inversion column command address signal 322 based on at least one bit of the inversion column command address signal 322. Correction can be made to generate an internal row command address signal 331 and an internal column command address signal 332 .

In one embodiment, the error correction circuit 330 may be disposed in front of the inversion circuit 320 . The error correction circuit 330 receives the row command address signal CAR<0:11> and the column command address signal CAC<0:7>, and receives the column command address signal CAC<0:7 a row command address signal whose error is corrected by correcting an error of the row command address signal CAR<0:11> and the column command address signal CAC<0:7> based on at least one bit of >) And a column command address signal may be provided to the inversion circuit 330 . The inversion circuit 320 receives error-corrected row command address signals and column command address signals from the error correction circuit 330, and based on at least one bit of the error-corrected row command address signals, The internal row command address signal 331 and the internal column command address signal 332 may be generated by selectively inverting the error-corrected row command address signal and column command address signal. In one embodiment, the command address control circuit 300 may include only one of the inversion circuit 320 and the error correction circuit 330 . When the error correction circuit 330 is not provided, the inversion circuit 320 receives the row command address signal CAR<0:11> and the column command address signal CAC<0:7> and the row command address signal (CAR<0:11>) and the column command address signal (CAC<0:7>) based on at least one bit of the row command address signal (CAR<0:11>). The internal row command address signal 331 and the internal column command address signal 332 may be generated by selectively inverting . When the inversion circuit 320 is not provided, the error correction circuit 330 receives the row command address signal CAR<0:11> and the column command address signal CAC<0:7> and the row command address signal (CAR<0:11>) and the column command address signal (CAC<0:7>) based on at least one bit of the row command address signal (CAR<0:11>). The internal row command address signal 331 and the internal column command address signal 332 may be generated by correcting errors in .

The row control circuit 340 receives the internal row command address signal 331 from the error correction circuit 330, and generates a row command signal RCMD and a row address signal ( RADD). The row control circuit 340 generates a low command signal RCMD based on the internal low command address signal 331 generated from the low command address signal CAR<0:7> received during a current unit cycle. can do. The row control circuit 340 detects the type of the low command signal RCMD, and receives the low command address signal CAR<0:11> during the next unit cycle according to the type of the low command signal RCMD. One of the row command signal RCMD and the row address signal RADD may be generated based on the internal row command address signal 331 generated from . For example, when the low command signal RCMD generated based on the low command address signal CAR<0:11> received during the current unit cycle is of the first type, the row control circuit 340 performs the next The low command signal RCMD may be generated based on the low command address signal CAR<0:11> received during a unit cycle. When the low command signal RCMD generated based on the low command address signal CAR<0:11> received during the current unit cycle is of the second type, the row control circuit 340 receives it during the next unit cycle. The row address signal RADD may be generated based on the row command address signal CAR<0:11>.

The column control circuit 350 receives the internal column command address signal 332 from the error correction circuit 330, and receives a column command signal CCMD and a column address signal (from the internal column command address signal 332). CADD) can be created. The column control circuit 350 generates a column command signal CCMD based on the internal column command address signals 332 generated from the column command address signals CAC<0:7> received during a current unit cycle. can do. The column control circuit 350 detects the type of the column command signal CCMD, and the column command address signals CAC<0:7> received during the next unit cycle according to the type of the column command signal CCMD. One of the column command signal CCMD and the column address signal CADD may be generated based on the internal column command address signal 332 generated from . For example, when the column command signal CCMD generated based on the column command address signal CAC<0:7> received during the current unit cycle is of the first type, the column control circuit 350 performs the next The column command signal CCMD may be generated based on the column command address signals CAC<0:7> received during a unit cycle. When the column command signal CCMD generated based on the column command address signals CAC<0:7> received during the current unit cycle is of the second type, the column control circuit 350 receives the column command signal CCMD during the next unit cycle. The column address signals CADD may be generated based on the column command address signals CAC<0:7>.

The row control circuit 340 may include a row command decoder 341 , a row address decoder 342 and a first command type detection circuit 343 . The low command decoder 341 may receive the internal row command address signal 331 . The low command decoder 341 may decode the internal low command address signal 331 to generate the low command signal RCMD. The low command decoder 341 may receive a first mask signal M1. The low command decoder 341 may be selectively activated based on the first mask signal M1. For example, the low command decoder 341 may be activated when the first mask signal M1 is disabled and deactivated when the first mask signal M1 is enabled. When activated, the low command decoder 341 decodes the internal low command address signal 331 to generate the low command signal RCMD, and when deactivated, decodes the low command signal RCMD without performing a decoding operation. may not be created.

The row address decoder 342 may receive the internal row command address signal 331 . The row address decoder 342 may generate the row address signal RADD based on the internal row command address signal 331 . The row address decoder 342 may receive the row command signal RCMD generated from the row command decoder 341 . The row address decoder 342 may generate the row address signal RADD by decoding the internal row command address signal 331 based on the row command signal RCMD. The row address decoder 342 may generate the row address signal RADD by decoding the internal row command address signal 331 when the row command signal RCMD is of the second type. The row address decoder 342 may not decode the internal row command address signal 331 and may not generate the row address signal RADD when the row command signal RCMD is of the first type.

The first command type detecting circuit 343 may receive the low command signal RCMD generated from the low command decoder 341 . The first command type detection circuit 343 may detect the type of the low command signal RCMD and generate the first mask signal M1 according to a detection result. The first command type detection circuit 343 may maintain the first mask signal M1 in a disabled state when the low command signal RCMD is of the first type. The first command type detection circuit 343 may enable the first mask signal M1 when the low command signal RCMD is of the second type. The first command type detecting circuit 343 may receive the command clock signal CCLK shown in FIG. 1 and operate in synchronization with the command clock signal CCLK. The first command type detection circuit 343 maintains the logic level of the first mask signal M1 according to the type of the low command signal RCMD for each unit cycle in synchronization with the command clock signal CCLK. or can be changed.

The column control circuit 350 may include a column command decoder 351 , a column address decoder 352 and a second command type detection circuit 353 . The column command decoder 351 may receive the internal column command address signal 332 . The column command decoder 351 may decode the internal column command address signal 332 to generate the column command signal CCMD. The column command decoder 351 may receive the second mask signal M2. The column command decoder 351 may be selectively activated based on the second mask signal M2. For example, the column command decoder 351 can be activated when the second mask signal M2 is disabled and deactivated when the second mask signal M2 is enabled. When activated, the column command decoder 351 decodes the internal column command address signal 332 to generate the column command signal CCMD, and when deactivated, the column command decoder 351 decodes the column command signal CCMD without performing a decoding operation. may not be created.

The column address decoder 352 may receive the internal column command address signal 332 . The column address decoder 352 may generate the column address signal CADD based on the internal column command address signal 332 . The column address decoder 352 may receive the column command signal CCMD generated by the column command decoder 351 . The column address decoder 351 may generate the column address signal CADD by decoding the internal column command address signal 332 based on the column command signal CCMD. The column address decoder 352 may generate the column address signal CADD by decoding the internal column command address signal 332 when the column command signal CCMD is of the second type. The column address decoder 352 may not decode the internal column command address signal 332 and not generate the column address signal CADD when the column command signal CCMD is of the first type.

The second command type detecting circuit 353 may receive the column command signal CCMD generated by the column command decoder 351 . The second command type detection circuit 353 may detect the type of the column command signal CCMD and generate the second mask signal M2 according to a detection result. The second command type detection circuit 353 may maintain the second mask signal M2 in a disabled state when the column command signal CCMD is of the first type. The second command type detection circuit 353 may enable the second mask signal M2 when the column command signal CCMD is of the second type. The second command type detecting circuit 353 may receive the command clock signal CCLK shown in FIG. 1 and operate in synchronization with the command clock signal CCLK. The second command type detection circuit 353 maintains the logic level of the second mask signal M2 according to the type of the column command signal CCMD per unit cycle in synchronization with the command clock signal CCLK. or can be changed.

Those skilled in the art to which the present invention pertains should understand that the embodiments described above are illustrative in all respects and not limiting, since the present invention can be embodied in other specific forms without changing the technical spirit or essential characteristics thereof. only do The scope of the present invention is indicated by the following claims rather than the detailed description above, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention. do.

Claims (20)

a command address control circuit which receives a row command address signal and a column command address signal and selectively inverts the row command address signal and the column command address signal based on a logic level of at least one bit of the row command address signal; A semiconductor device comprising: According to claim 1,
wherein the command address control circuit receives the row command address signal and the column command address signal by receiving command address signals during a plurality of cycles of a clock signal. According to claim 1,
The semiconductor device of claim 1 , wherein the command address control circuit corrects errors in the row command address signal and the column command address signal based on at least one bit of the column command address signal. a command address control circuit receiving row command address signals and column command address signals and correcting errors in the row command address signals and column command address signals based on at least one bit of the column command address signals; Device. According to claim 4,
wherein the command address control circuit receives the row command address signal and the column command address signal by receiving command address signals during a plurality of cycles of a clock signal. According to claim 4,
The semiconductor device of claim 1 , wherein the command address control circuit selectively inverts the row command address signal and the column command address signal based on at least one bit of the row command address signal. generating a row command address signal including one bit including inversion information and a column command address signal including one bit including parity, and synchronizing the row command address signal and the column command address signal with a clock signal A semiconductor device comprising a command generation circuit for transmitting a command by According to claim 7,
wherein the command generating circuit transmits the row command address signal and the column command address signal by transmitting a command address signal during a plurality of cycles of the clock signal. generating a row command address signal including one bit including inversion information and a column command address signal including one bit including parity, and transmitting the row command signal and the column address signal as a set of command address signals a first semiconductor device; and
Receiving the command address signal set, selectively inverting the command address signal set based on one bit including the inversion information, and error of the command address signal set based on the one bit including the parity A semiconductor system including a second semiconductor device for correcting . According to claim 9,
wherein the first semiconductor device transmits the set of command address signals by transmitting command address signals during a plurality of cycles of a clock signal. Receiving a row command address signal and a column command address signal, and selectively inverting the row command address signal and the column command address signal based on one bit of the row command address signal to obtain an internal row command address signal and an internal column command an inversion circuit that generates an address signal;
a row control circuit configured to generate a row command signal and a row address signal based on the internal row command address signal; and
and a column control circuit generating a column command signal and a column address signal based on the internal column command address signal. According to claim 11,
The inversion circuit generates the internal row command address signal and the internal column command address signal by inverting the row command address signal and the column command address signal when the one bit is at a first logic level, and A command address control circuit configured to generate the internal row command address signal and the internal column command address signal by non-inverting the row command address signal and the column command address signal when a bit of is at a second logic level. According to claim 11,
The row control circuit includes: a row command decoder selectively activated based on a first mask signal and decoding the internal row command address signal to generate the row command signal;
a row address decoder configured to generate the row address signal from the internal row command address signal based on the row command signal; and
and a first command type detecting circuit configured to detect whether the low command signal is of a first type or a second type and generate the first mask signal. According to claim 13,
The column control circuit includes: a column command decoder selectively activated based on a second mask signal and generating the column command signal by decoding the internal column command address signal;
a column address decoder configured to generate the column address signal from the internal column command address signal based on the column command signal; and
and a second command type detecting circuit configured to detect whether the column command signal is of a first type or a second type and generate the second mask signal. According to claim 11,
and an error correction circuit correcting errors in the row command address signal and the column command address signal based on one bit of the column command address signal. Receives a row command address signal and a column command address signal, corrects an error in the row command address signal and the column command address signal based on one bit of the column command address signal, and obtains an internal row command address signal and an internal column command an error correction circuit for generating an address signal;
a row control circuit configured to generate a row command signal and a row address signal based on the internal row command address signal; and
and a column control circuit generating a column command signal and a column address signal based on the internal column command address signal. 17. The method of claim 16,
The row control circuit includes: a row command decoder selectively activated based on a first mask signal and decoding the internal row command address signal to generate the row command signal;
a row address decoder configured to generate the row address signal from the internal row command address signal based on the row command signal; and
and a first command type detecting circuit configured to detect whether the low command signal is of a first type or a second type and generate the first mask signal. 17. The method of claim 16,
The column control circuit includes: a column command decoder selectively activated based on a second mask signal and generating the column command signal by decoding the internal column command address signal;
a column address decoder configured to generate the column address signal from the internal column command address signal based on the column command signal; and
and a second command type detecting circuit configured to detect whether the column command signal is of a first type or a second type and generate the second mask signal. 17. The method of claim 16,
and an inversion circuit selectively inverting the row command address signal and the column command address signal based on one bit of the row command address signal. According to claim 19,
The inversion circuit inverts the row command address signal and the column command address signal when one bit of the row command address signal is at a first logic level, and one bit of the row command address signal is at a second logic level. A command address control circuit for non-inverting the row command address signal and the column command address signal when the level is the same.

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