KR20230029168A - Decoder, operating method thereof and memory system including the decoder for decoding non-binary low-density parity check code - Google Patents

Abstract

The present invention relates to a non-binary low-density parity check code decoder, an operating method thereof, and a memory system, which can improve error rate performance while reducing decoding complexity. According to one embodiment of the present invention, the method for decoding a non-binary low-density parity check code comprises: a step of receiving codewords consisting of N hard decision symbols from a semiconductor memory, and generating similarity soft decision information becoming larger as the Hamming distances for the hard decision symbols making up the received codewords and symbols remaining after excluding the hard decision symbols in a Galois field decrease based on the hard decision symbols; and a step of determining a corrected codeword based on the similarity soft decision information.

Description

Non-binary low density parity check code decoder, its operating method and memory system

The present invention relates to a technique for decoding a nonbinary low-density parity-check (NB-LDPC) code, and more particularly, to a non-binary low-density parity check using pseudo soft decision information for a NAND flash memory. It relates to a code decoder, its operating method and memory system.

The present invention relates to low density parity check codes, and more particularly to techniques for decoding non-binary low density parity check codes.

Low Density Parity Check Codes (LDPC Codes) are error correction codes first proposed in 1962, and are forward error correction codes belonging to linear block codes. ) is a type of At the time this code was proposed, it was at a time when vacuum tubes began to be replaced by transistors, and at that time, this code was not practically commercially available due to the enormous amount of calculation required for simulation to verify this code and the difficulty of its implementation. However, thanks to the development of information communication technology for more than 30 years, the recent emergence of high-performance processors, and the need to provide high-quality services in the field of multimedia mobile communication, the utilization of this code has recently been re-recognized, and the characteristics of this code and its encoding have been recognized. /Research on decryption methods is gaining momentum. This code is also being proposed as a channel coding method in a 4th generation mobile communication system to replace turbo codes.

LDPC codes are known to show excellent performance approaching Shannon's channel capacity (Shannon Limit) like turbo codes. The LDPC code has superior performance compared to the turbo code, the implementation of the decoder is not very complicated, parallel operation is possible, high-speed processing is possible, and a stochastic iterative decoding technique like the turbo code can be applied, resulting in low error rate and low error rate. It is known to be suitable for mobile communication systems requiring high-speed data processing. These LDPC codes include binary LDPC codes in which the components of the H matrix corresponding to the parity check matrix are binary elements, and non-binary LDPC codes in which the components of the H matrix are not binary elements. It can be divided into codes (Non-Binary LDPC Codes). Binary LDPC codes show weakness in terms of bit error rate for short or medium-length codewords, whereas non-binary LDPC codes outperform even for short-length codewords. It shows generally superior performance to binary LDPC code, such as not showing an error floor phenomenon even at a low error rate.

However, the non-binary LDPC code has a disadvantage in that its complexity increases as the row weight of the H matrix or the order q of a Galois Field (GF) increases in the decoding process. Accordingly, research on a method for reducing the amount of computation in the decoding process by simplifying the decoding process without significantly degrading the performance of the LDPC decoder has recently been actively conducted.

An object of the present invention is to provide a method for decoding a non-binary LDPC code that enables high-speed decoding while minimizing performance degradation of a non-binary LDPC decoder.

Another object of the present invention is to provide a non-binary LDPC code decoding method capable of reducing the amount of computation and computation delay at check nodes of a non-binary LDPC decoder.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. Therefore, a decoding method capable of reducing decoding complexity and preventing deterioration of error rate performance is required.

An object of the present invention is to provide a decoding method and apparatus capable of improving error rate performance while reducing decoding complexity.

The problem to be solved by the present invention is not limited to the above-mentioned problem (s), and another problem (s) not mentioned will be clearly understood by those skilled in the art from the following description.

To achieve the above object, a method of decoding a non-binary low density parity check code according to an embodiment of the present invention includes receiving codewords composed of hard decision symbols from a semiconductor memory; generating similar soft decision information that increases as the Hamming distance decreases for each hard decision symbol and the remaining symbols excluding hard decision symbols in a Galois field based on N hard decision symbols constituting the received codeword; It is characterized by including the step of performing a variable node and check node operation, and the step of determining an error correction codeword (corrected codeword) by comparing the similar soft decision information with a preset threshold value.

In an embodiment, the generating of the similar soft decision information may include multiplying a value considering a hamming distance between the hard decision symbol and the remaining symbols excluding the hard decision symbol among the codewords received at all times by a column weight to obtain similar soft decision information. It is characterized by generating.

In one embodiment, the step of determining the error correction codeword may include M check nodes having a connection relationship with the N variable nodes, determined by a parity check matrix (H) of the low density parity check code, and the It is characterized in that the received codeword is decoded by repetitive message exchange between N variable nodes.

In one embodiment, it is characterized in that the non-binary low density parity check code is a code defined for a Galois field GF(q) of order q.

In one embodiment, the step of determining the codeword (corrected codeword) is characterized in that a syndrome check, a check node update, and a variable node update are set as one set, and the set is repeatedly executed a preset number of times.

In one embodiment, the check node update performs an Extrinsic Information Sum (EXI) operation each time, and when updating similar soft decision information of a symbol obtained as a result of the EXI operation, a weight coefficient calculated based on a Hamming distance is used. characterized by use.

In one embodiment, the update of the check node is characterized by updating similar soft decision information for a hard decision symbol received from a variable node without performing an EXI operation when the result value of the i-th syndrome check is 0 each time. do.

A non-binary low density parity check code decoder according to another embodiment of the present invention receives a codeword consisting of N hard decision symbols from a semiconductor memory, and receives the hard decision symbols and the remaining symbols in the GF excluding the hard decision symbols. an initialization module for generating similar soft decision information that increases as the Hamming distance decreases for ; and a node processor for determining an error correction codeword from symbols having the largest value among the similar soft decision information.

A semiconductor memory system according to an embodiment of the present invention includes a semiconductor memory for storing codewords that are encoded data; a decoder generating decoded data by decoding the codeword stored in the semiconductor memory through a parity check matrix composed of sub-matrices; and a channel connecting the semiconductor memory and the decoder and providing the codeword of the semiconductor memory device to the decoder.

The semiconductor memory according to an embodiment of the present invention is characterized in that it is a NAND flash memory.

The present invention has an effect of improving BER (Bit Error Rate) performance and reducing the amount of calculation.

The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

1 is a diagram for explaining the configuration of a decoder for a non-binary low density parity check (NB-LDPC) code according to an embodiment of the present invention.
2 is an exemplary diagram for explaining a parity check matrix according to an embodiment of the present invention.
FIG. 3 is a diagram showing the parity check matrix shown in FIG. 2 as a Tanner graph.
4 is a diagram illustrating an algorithm for decoding according to an embodiment of the present invention.
5 is a diagram for explaining reliability of hard decision information according to an embodiment of the present invention.
6 is a diagram showing an algorithm for decoding according to another embodiment of the present invention.
7 is a flowchart illustrating a method of decoding a non-binary low density parity check code according to an embodiment of the present invention.
8 is a configuration diagram showing a schematic configuration of a semiconductor memory system according to an exemplary embodiment of the present invention.

Since the present invention can make various changes and have various embodiments, specific embodiments will be illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the present invention to specific embodiments, and should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Like reference numerals have been used for like elements throughout the description of each figure.

Terms such as first, second, A, and B may be used to describe various components, but the components should not be limited by the terms. These terms are only used for the purpose of distinguishing one component from another. For example, a first element may be termed a second element, and similarly, a second element may be termed a first element, without departing from the scope of the present invention. The terms and/or include any combination of a plurality of related recited items or any of a plurality of related recited items.

It is understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, but other elements may exist in the middle. It should be. On the other hand, when an element is referred to as “directly connected” or “directly connected” to another element, it should be understood that no other element exists in the middle.

Terms used in this application are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, the terms "include" or "have" are intended to designate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, but one or more other features It should be understood that the presence or addition of numbers, steps, operations, components, parts, or combinations thereof is not precluded.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related art, and unless explicitly defined in the present application, they should not be interpreted in an ideal or excessively formal meaning. don't

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

A decoder according to an embodiment of the present invention may receive a signal corresponding to a codeword from a channel and perform error correction decoding on the received signal.

A decoder according to an embodiment of the present invention may perform error correction decoding using various algorithms employing an iterative decoding scheme. A decoder according to an embodiment of the present invention may perform error correction decoding using a message passing algorithm (MPA), also referred to as a belief propagation algorithm (BPA). As a message transfer algorithm, a bit flipping algorithm, a symbol flipping algorithm, a min-sum algorithm, or a sum-product algorithm may be used.

A decoder according to an embodiment of the present invention may perform error correction decoding within a set maximum iteration number (I). Here, I may be a natural number. The error correction decoder converts the generated valid codeword into a decoded code when a valid codeword that satisfies the constraints of the parity check matrix of the error correction code is generated within the maximum number of iterations (I). It can be output as a word (decoded codeword).

In the decoder according to an embodiment of the present invention, when a valid codeword that satisfies the constraints of the parity check matrix of the error correction code is not generated within the maximum number of iterations (I), the decoder fails indicating that error correction decoding has failed. ) signal can be output.

1 is a diagram for explaining the configuration of a decoder for a non-binary low density parity check (NB-LDPC) code according to an embodiment of the present invention, and FIG. It is an exemplary diagram for explaining a parity check matrix according to an embodiment.

Referring to FIG. 1 , the decoder 200 may include an initialization module 210, a variable node processing module 220, a check node processing module 230, and a syndrome check module 240. The variable node processing module 220, the check node processing module 230, and the syndrome check module 240 may all be referred to as a node processor.

The initialization module 210 may receive a read vector corresponding to a codeword from a channel. The initialization module 210 may configure initial symbols to be allocated to variable nodes by grouping read values included in the read vector.

Also, the initialization module 210 may generate soft decision information (also referred to as reliability) based on initial symbols. Similar soft decision information may be generated using Hamming distance based on hard decision values. In one embodiment, the similar soft decision information is calculated by multiplying the hamming distance by the column weight dv.

The initialization module 210 may initialize variable nodes using initial symbols received from the initialization module 210 before the first iteration is performed. That is, the initialization module 210 may generate similar soft decision values of variable nodes based on each of the initial symbols constituting the codeword and allocate them to each of the variable nodes.

The variable node processing module 220 and the check node processing module 230 exchange messages between variable nodes and check nodes. Through this, it is possible to generate a result that converges to the codeword.

More specifically, the variable node processing module 220 generates a variable to check (V2C) message transmitted from the variable node to the check node and transfers it to the check node processing module 230.

The check node processing module 230 generates a check-to-variable (C2V) message transmitted from the check node to the variable node and transfers it to the variable node processing module 220.

In the first iteration, the variable node processing module 220 generates V2C messages so that similar soft decision values of the variable nodes can be transmitted to the check nodes, and each of the variable nodes is based on the C2V messages received from the check nodes. The pseudo soft decision value of can be updated.

In one embodiment, an output of the variable node processing module 220 becomes an input value corresponding to columns having non-zero element values (variable nodes) of each row of each parity check matrix.

The check node processing module 230 generates C2V messages based on V2C messages received from variable nodes in each repetition except for the first repetition.

In one embodiment, the output of the check node processing module 230 is similar to the output of the variable node processing module 220, the value of a row having a non-zero value in each column based on the column of the parity check matrix (H). are output, which are input to the variable node processing module 220.

In another embodiment, the check node processing module 230 may update the next confidence level with a value obtained by adding the weight coefficient θ based on the Hamming distance to the confidence level. This will be described in detail with reference to FIG. 6 to be described later.

The syndrome check module 240 may perform a syndrome check on the hard decision values of the variable node in response to the i-th iteration. For example, the syndrome check may be performed by checking whether a value calculated by Equation 1, which is a syndrome check equation, is 0.

[Equation 1]

Here, z ^(k) is a hard decision value correspondingly generated in the kth iteration, and H is a parity check matrix of an error correction code.

은 j번째 변수 노드에서 이웃하는 채널 노드로 전달된다. Hard decision symbol at kth iteration

is transferred from the j-th variable node to a neighboring channel node.

로 표기되고,

는 수학식 2와 같이 연산된다.The extrinsic information sum (EXI) passed from the i-th channel node to the j-th variable node is

is denoted by

Is calculated as in Equation 2.

[Equation 2]

는 Ni의 부분집합으로, Ni에서 j번째 변수 노드(0≤i<M, 0≤j<N)를 제외한 집합을 의미한다.Here, Ni connected to the i-th channel node means a set of variable nodes,

is a subset of Ni, and means a set excluding the j-th variable node (0≤i<M, 0≤j<N) from Ni.

에 기초하여, 변수노드는 경판정 벡터 z^(k)를 수학식 3과 같이 갱신한다. derived

Based on , the variable node updates the hard decision vector z ^(k) as shown in Equation 3.

[Equation 3]

In another embodiment, the syndrome check module 240 outputs, as a codeword, a decision value of a variable node in which all result values of the syndrome check become 0.

Referring to FIG. 2, an example of a parity check matrix H defining (n, k) codes is shown. (n, k) codes may be defined as a parity check matrix having a size of (n-k)×n. In one embodiment, a 3×4 parity check matrix is illustrated for convenience of description, but is not limited thereto. Each entry of the parity check matrix may be represented by elements belonging to a Galois field.

A Galois field (GF(q)) is a finite field of q elements, where q=2 ^p and p is a positive integer.

The elements of the Galois field (GF(q)) can be expressed as {0, α ⁰ , α ¹ , ..., α ^q-2 }.

If all entries calculated by Equation 1, which is the syndrome check equation, are 0, it means that the syndrome check has passed, and if there is a non-zero entry among all entries of the syndrome vector (S _i ), the syndrome check has failed. (failed).

If the syndrome check passes, the syndrome check module 240 may output the hard decision vector as a decoded codeword.

If the syndrome check does not pass within the maximum number of iterations Imax, the node processor 220 may output a fail signal indicating that error correction decoding has failed.

A codeword consisting of N symbols received by repetitive message exchange between M check nodes having connection relationships with N variable nodes and the N variable nodes is decoded.

FIG. 3 is a diagram showing the parity check matrix shown in FIG. 2 as a Tanner graph.

The parity check matrix shown in FIG. 2 can be expressed as a Tanner graph, which is an equivalent bipartite graph representation. A Tanner graph can be represented by check nodes, variable nodes, and edges. Check nodes correspond to rows of the parity check matrix, and variable nodes correspond to columns of the parity check matrix. Each edge connects one check node and one variable node, and corresponds to a non-zero entry in the parity check matrix.

The degree of a node, the number of adjacent nodes in a Tanner graph, corresponds to the number of non-zero elements in a column or row and is called the weight of a matrix. This NB-LDPC code has column weights dv and row weights dc.

,

, ...,

]라 한다. 따라서, z⁽⁰⁾은 채널 출력의 경판정 심볼로 구성되며, 디코더의 입력이다. 디코딩 반복의 목표는 z^(k)가 신드롬 체크 방정식인 수학식 1의 계산결과 0을 충족하도록 하는 것이다. 신드롬 체크 방정식을 0으로 하는 z^(k)가 코드워드임을 의미한다. For an NB-LDPC code with a length of N, when the codewords of C are c=[c ₀ , c ₁ , c ₂ ,..., c _N-1 ], the channel input vector and the received vector are x=[x ₀ , x ₁ , x ₂ ,..., x _N-1 ] and y=[y ₀ , y ₁ , y ₂ ,..., y _N-1 ]. Here, the vector y is a vector obtained by adding noise to x. Based on Y, the hard decision vector of the kth decoded received symbol is z ^(k) = [

,

, ...,

]. Thus, z ⁽⁰⁾ consists of the hard decision symbols of the channel output and is the input of the decoder. The goal of decoding iteration is to make z ^(k) satisfy 0 as a result of calculation of Equation 1, which is a syndrome check equation. This means that z ^(k), which sets the syndrome check equation to 0, is a codeword.

4 is a diagram illustrating an algorithm for decoding according to an embodiment of the present invention, and FIG. 5 is a diagram for explaining reliability of hard decision information according to an embodiment of the present invention.

As can be seen with reference to FIG. 4, the algorithm for decoding is largely divided into 1. Initialization step 2. Syndrome check 3. Check node update 4. Variable node update.

The above algorithm is repeatedly executed a preset number of times (Imax). Accordingly, it can be seen that the channel node update (CN update) and variable update (VN update) are also repeated.

More specifically, in the initialization step, dv × p represents the highest reliability among all symbols during initialization. where p is calculated as log ₂ q. The reliability of all other symbols is set as in Equation 4.

[Equation 4]

The closer the Hamming distance is from the hard decision symbol, the higher the reliability of the symbol. The Hamming distance can be easily calculated by binary XOR operation between symbols.

은 다음 반복에서 투표될 것이고,

=

+1로 나타낼 수 있다. If EXI (extrinsic information) operation is performed from the i-th CN adjacent to the j-th VN and the calculated value σ _i,j is a1,

will be voted on in the next iteration,

=

It can be represented as +1.

Referring to FIG. 5, unlike the case in which reliability is assigned only to hard decision symbols and symbols having a hamming distance of 1, in one embodiment, reliability values are differentially assigned to all symbols according to the hamming distance and multiplied by dv to determine reliability according to the hamming distance. Reliability values (R) differ by the column weight dv. By multiplying by dv, we can prevent the occurrence of a change in the symbol with the maximum confidence in one vote in the next iteration.

The syndrome check is performed based on Equation 1, which is the syndrome check equation using the transposition matrix of the parity check matrix H. If the calculated syndrome check equation becomes less than the selected value or repeats the selected number of times.

Codewords can be decoded by repeating check node updates and variable node updates through repetitive message exchanges between the check node and the variable node.

6 is a diagram showing an algorithm for decoding according to another embodiment of the present invention.

는 채널 출력으로부터의 경판정 정보와 다른 갈루아 체 요소 사이의 해밍 거리를 기반으로 초기화된다. The j-th confidence of the received symbol

is initialized based on the Hamming distance between the hard decision information from the channel output and other Galois field elements.

As can be seen with reference to FIG. 6, the algorithm for decoding is largely divided into 1. Initialization step 2. Syndrome check 3. Check node update 4. Variable node update.

Since the initialization step of the algorithm of FIG. 6 is similar to that of FIG. 4, a detailed description thereof will be omitted.

를 초기화에 사용하는 것과 같은 이유로 가중치 계수를 결정하기 위하여 해밍거리

를 연산한다. Looking at the check node update,

Hamming distance to determine the weight coefficients for the same reason as using

calculate

가 작을 수록

의 신뢰도가 더 높기 때문에 상응하는 가중 계수 θ

도 커진다.

the smaller

Since the reliability of is higher, the corresponding weighting factor θ

also grows

Looking at the VN update step, in the soft decision decoding algorithm, channel information is used in each iteration of the VN update. Hard decision symbols in the channel output are updated by voting in each VN.

In the syndrome check step of iterative decoding, syndrome s ^(k) is iteratively calculated by Equation 5 at each VN update end point.

[Equation 5]

s ^(k) = z ^(k) H ^T

Here, when syndrome s ^(k) is 0, decoding is ended and z ^(k) is output as a codeword.

In the syndrome s ^(k) operation, z ^(k) H ^T is matrix multiplication and the length of the output vector of matrix multiplication becomes M. Each element of the output vector is calculated by Equation (6).

[Equation 6]

Here, Equation 6 can be expressed as Equation 7.

[Equation 7]

In Equation 5, when syndrome s ^(k) is 0, as in [Equation 8], it is equal to the EXI of the i-th channel node.

[Equation 8]

가 0일 때

가

와 같다는 것을 알 수 있다. 이것은,

가 0일 때 CN 업데이트에서 EXI 연산을 건너뛸 수 있음을 의미한다. Here, addition and multiplication operations are Galois field operations. Referring to Equation 6,

is 0

go

It can be seen that it is the same as this is,

When is 0, it means that the EXI operation can be skipped in the CN update.

가 0인지 여부를 나타내는 1비트 정보를 저장한다. After checking the syndrome, each channel node

Stores 1-bit information indicating whether is 0.

값이 0인 체크 노드 CN을 CN_SAT라고 하고, 그 외의 체크 노드 CN은 CN_UNSAT라고 한다. CN_SAT의 경우, CN 업데이트 단계에서 EXI 연산은 건너 뛰고,

와

사이의 해밍거리만을 계산하여 가중치 계수를 설정한다. 따라서, 디코더의 오류율 성능에는 영향을 주지 않고, EXI의 연산량을 줄일 수 있다.

The check node CN whose value is 0 is called CN _SAT , and the other check node CNs are called CN _UNSAT . In the case of CN _SAT , EXI operation is skipped in the CN update step,

and

Weight coefficients are set by calculating only the Hamming distance between Therefore, the amount of operation of EXI can be reduced without affecting the error rate performance of the decoder.

7 is a flowchart illustrating a method of decoding a non-binary low density parity check code according to an embodiment of the present invention.

Decoding of the non-binary low density parity check code of FIG. 7 is performed by the decoder described based on FIGS. 1 to 6 .

In step S100, the decoder receives a read vector corresponding to the codeword from the channel.

In step S110, the read values included in the received read vector are assigned to variable nodes, and based on the assigned values, the reliability of the hard decision is calculated using the Hamming distance to generate similar soft decision information. The hard decision information may be provided from the outside, and the similar soft decision information is initialized by calculating the hamming distance between the hard decision symbol and other symbols by multiplying the column weight. During initialization, you can set the number of executions of one iteration consisting of check node update, variable node update, and syndrome check.

In step S120, syndrome values are calculated for all test nodes.

If the calculated syndrome value is 0, the process proceeds to step S160, the decision value of the variable node is output as a code word, and decoding is terminated.

Proceeding to step S130, if the calculated syndrome value is not 0, it is checked whether the number of iterations is a preset execution number, and if it is not the preset execution number, check node update and variable node update are performed in step S140.

The check node update performs an Extrinsic Information Sum (EXI) operation each time, and when updating similar soft decision information of a symbol obtained as a result of the EXI operation, a weight coefficient calculated based on the Hamming distance may be used.

In one embodiment, the check node update performs an EXI operation each time, and when the result value of the i-th syndrome check is 0, the EXI operation is not performed and the similar soft decision information is received for the hard decision symbol received from the variable node. can be updated.

In step S130, if the number of iterations is the same as the preset number of executions, the process proceeds to step S170, it is determined that decoding of the hard decision data has failed and a fail is output.

In step S150, the number of iterations is increased by 1, and in step S120, the decoding operation of step S150 is repeatedly performed.

One iteration consisting of check node update, variable node update, and syndrome check is performed multiple times.

8 is a configuration diagram showing a schematic configuration of a semiconductor memory system according to an exemplary embodiment of the present invention.

A semiconductor memory system may include a semiconductor memory 100 , a decoder 200 and a channel 300 .

The semiconductor memory 100 stores codewords that are encoded data. The semiconductor memory 100 may be a NAND flash memory.

The decoder 200 decodes the codeword stored in the semiconductor memory 100 through a parity check matrix to generate decoded data. Since the decoder 200 includes the functions of the decoder 200 described with reference to FIGS. 1 to 6, a detailed description thereof will be omitted.

The channel 300 connects the semiconductor memory 100 and the decoder 200 .

In one embodiment, the channel 300 may obtain a hard decision value based on a codeword read from the semiconductor memory 100 .

Channel 300 provides the hard decision value to decoder 200 .

As described above, since the decoder according to an embodiment of the present invention can perform decoding at a high processing speed while having good error rate performance, it can be applied to NAND flash memories with relatively small memory space allowed for parity bits. .

So far, the present invention has been looked at with respect to its preferred embodiments. Those of ordinary skill in the art to which the present invention pertains will understand that the present invention can be implemented in a modified form without departing from the essential characteristics of the present invention. Therefore, the disclosed embodiments should be considered from an illustrative rather than a limiting point of view. The scope of the present invention is shown in the claims rather than the foregoing description, and all differences within the equivalent scope will be construed as being included in the present invention.

Claims (15)

A method of decoding a non-binary low density parity check code, comprising:
Receiving codewords consisting of N hard decision symbols from a semiconductor memory;
generating similar soft decision information that increases as the Hamming distance decreases for each hard decision symbol and remaining symbols except for each hard decision symbol in the Galois field based on the hard decision symbols constituting the received codeword; and
determining a corrected codeword based on the similar soft decision information;
Non-binary low density parity check code decoding method comprising a.
According to claim 1,
Generating the similar soft decision information,
Non-binary low-density parity check code decoding method characterized by generating pseudo soft decision information by multiplying a value considering the hamming distance between each hard decision symbol and the remaining symbols excluding each hard decision symbol in the Galois field by a column weight.
According to claim 1,
Determining the error correction codeword,
Decrypt the codeword by repetitive message exchange between M check nodes having a connection relationship with the N variable nodes and the N variable nodes, determined by the parity check matrix (H) of the low density parity check code Non-binary low density parity check code decoding method, characterized in that.
According to claim 1,
The non-binary low density parity check code is a code defined for a Galois field GF(q) of order q.
According to claim 4,
Determining the codeword (corrected codeword)
A non-binary low density parity check code decoding method comprising a syndrome check, a check node update, and a variable node update as one set, wherein the set is repeatedly executed a preset number of times.
According to claim 5,
The check node update performs an Extrinsic Information Sum (EXI) operation each time, and when updating similar soft decision information of a symbol obtained as a result of the EXI operation, a weight coefficient calculated based on a Hamming distance is used. A non-binary low-density parity check code decoding method.
According to claim 5,
The check node update is characterized by updating similar soft decision information for the hard decision symbol received from the variable node without performing EXI (Extrinsic Information Sum) operation when the result value of the ith syndrome check is 0 each time. A non-binary low-density parity check code decoding method.
Codewords composed of N hard decision symbols are received from the semiconductor memory, and based on the hard decision symbols constituting the received codewords, each hard decision symbol and the remaining symbols except for each hard decision symbol in the Galois field are generated. an initialization module for generating similar soft decision information that increases as the Hamming distance decreases; and
a node processor determining an error correction codeword based on the similar soft decision information;
A non-binary low density parity check code decoder comprising a.
According to claim 8,
The initialization module,
A non-binary low-density parity check code decoder characterized by generating pseudo soft decision information by multiplying a value considering the Hamming distance between each hard decision symbol and the remaining symbols excluding each hard decision symbol in the Galois field by a column weight.
According to claim 8,
The node processor,
The received codeword by repetitive message exchange between the N variable nodes and M check nodes having a connection relationship with the N variable nodes, determined by the parity check matrix (H) of the low density parity check code. Non-binary low density parity check code decoder, characterized in that for decoding.
According to claim 8,
The node processor,
A non-binary low density parity check code decoder comprising a syndrome check, a check node update and a variable node update as one set, wherein the set is repeatedly executed a preset number of times.
According to claim 11,
The check node update performs an Extrinsic Information Sum (EXI) operation each time, and when updating similar soft decision information of a symbol obtained as a result of the EXI operation, a weight coefficient calculated based on a Hamming distance is used. A non-binary low density parity check code decoder.
According to claim 12,
The check node update is characterized by updating similar soft decision information for the hard decision symbol received from the variable node without performing EXI (Extrinsic Information Sum) operation when the result value of the ith syndrome check is 0 each time. A non-binary low density parity check code decoder.
a semiconductor memory that stores codewords that are encoded data;
a decoder generating decoded data by decoding the codeword stored in the semiconductor memory through a parity check matrix composed of sub-matrices; and
A channel connecting the semiconductor memory and the decoder and providing the codeword of the semiconductor memory device to the decoder
including,
The decoder
Codewords composed of N hard decision symbols are received from the semiconductor memory, and the remaining symbols except for each hard decision symbol in each hard decision symbol and the Galois field are based on the hard decision symbols constituting the received codeword. an initialization module for generating similar soft decision information that increases as the Hamming distance decreases for ; and
a node processor determining an error correction codeword based on the similar soft decision information;
A semiconductor memory system comprising a.
15. The semiconductor memory system according to claim 14, wherein the semiconductor memory is a NAND flash memory.

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