KR20230021140A - Neurons using Posit - Google Patents

Abstract

Systems, devices, and methods related to neurons using posits are described. An example device may include a memory array including a plurality of memory cells configured to store data. Data may include a plurality of bit strings. An exemplary device may include neuronal components coupled to a memory array. A neuron component may include neuron circuitry configured to perform neuromorphic operations on at least one of a plurality of bit strings.

Description

Neurons using Posit

The present disclosure relates generally to semiconductor memory and methods, and more specifically to devices, systems, and methods for neurons using positrons.

Memory devices are typically provided as internal semiconductor, integrated circuitry within computers or other electronic systems. Many different types of memories include volatile and non-volatile memory. Volatile memory can require power to hold its data (e.g., host data, error data, etc.) and, among other things, random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM). Non-volatile memory can provide permanent data by retaining stored data when power is not supplied, and can provide permanent data, in particular NAND flash memory, NOR flash memory, variable memory such as phase change random access memory (PCRAM), resistive random access memory. (RRAM), and magnetic random access memory (MRAM), such as rotational torque transfer random access memory (STT RAM).

Memory devices may be coupled to a host (eg, host computing device) to store data, commands, and/or instructions for use by the host while the computer or electronic system is operating. For example, data, commands, and/or instructions may be transferred between a host and memory device(s) during operation of a computing or other electronic system.

1 is a functional block diagram in the form of a computing system that includes an apparatus that includes a host and a memory device in accordance with multiple embodiments of the present disclosure.
2A is another functional block diagram in the form of a computing system that includes an apparatus that includes a host and a memory device in accordance with multiple embodiments of the present disclosure.
2B is a functional block diagram in the form of a computing system that includes a host, a memory device, an application specific integrated circuit, and a field programmable gate array in accordance with multiple embodiments of the present disclosure.
3 is an example of an n-bit positive with es exponent bits.
4A is an example of positive values for a 3-bit posit.
4B is an example of a posit configuration using two exponent bits.
5A is a functional block diagram in the form of peripheral sense amplifiers, a memory array, and a plurality of arithmetic logic units (ALUs) in accordance with multiple embodiments of the present disclosure.
5B is a functional block diagram of a neuron type including a multiplier, an accumulator, an internal ALU, and registers in accordance with multiple embodiments of the present disclosure.
5C is a functional block diagram of sense amplifiers and a memory array of neurons in accordance with multiple embodiments of the present disclosure.
6 is a functional block diagram in the form of control circuitry in accordance with multiple embodiments of the present disclosure.
7 is a flow diagram illustrating an example method for performing neuromorphic operations using neurons in accordance with multiple embodiments of the present disclosure.

Systems, devices, and methods related to neurons using posits are described. An example device may include a memory array including a plurality of memory cells configured to store data. Data may include a plurality of bit strings. An exemplary device may include neuronal components coupled to a memory array. A neuron component may be configured to perform neuromorphic operations on at least one of a plurality of bit strings.

The memory array can be within a memory device. The memory device may include control circuitry. Control circuitry may include memory resources and processing resources. Control circuitry may be coupled to the memory array. A memory array may include a plurality of neurons (eg, neuronal elements). A memory array may store data including a plurality of bit strings. The control circuitry may control performance of neuromorphic operations on at least one of a plurality of bit strings. In this way, the neuromorphic memory array can act as a neural network. Analog weights may be input to computation of the neural network to train the neural network. In response to the data being stored in a neural network that caused neuromorphic operations to be performed on the data comprising the points, the data may simulate learning and may be tested or analyzed to determine the degree of learning that has occurred. The data may have a format including a universal number (unum) format, such as a Type III unum or positive format.

A neural network can include a set of instructions that can be executed to recognize patterns in data. Some neural networks can be used to recognize underlying relationships in a set of data in a way that mimics the way the human brain operates. A neural network can adapt to variable or changing inputs such that the neural network can produce the best possible result without redesigning the output criteria.

A neural network may consist of multiple neurons, which may be expressed in one or more expressions. With respect to neural networks, a neuron can receive as inputs a quantity of numbers or vectors and, based on properties of the neural network, generate an output. For example, a neuron may receive X _k inputs, where k corresponds to the index of the input. For each input, a neuron can assign a weight vector W _k to the input. Weight vectors may, in some embodiments, differentiate neurons in a neural network from one or more different neurons in the neural network. In some neural networks, each input vector is multiplied with each weight vector to yield a value, as shown by Equation 1, which shows an example of a linear combination of input vectors and weight vectors.

Equation 1

In some neural networks, a nonlinear function (eg, an activation function) may be applied to the resulting value f ( x ₁ , x ₂ ) from Equation 1. An example of a non-linear function that can be applied to the resulting value from Equation 1 is the rectified linear unit function (ReLU). Application of the ReLU function shown in Equation 2 yields a value input to the function if the value is greater than zero, or zero if the value input to the function is less than zero. The ReLU function is used herein only as an illustrative example of an activation function and is not intended to be limiting. Other non-limiting examples of activation functions that can be applied in connection with neural networks include, among others, sigmoid functions, binary step functions, linear activation functions, hyperbolic functions, Leaky ReLU functions, parametric ReLU functions, Softmax functions, and/or Swish functions.

Equation 2

During the process of training a neural network, the input vectors and/or weight vectors may be changed to “tune” the neural network. In one example, the neural network may be initialized with random weights (eg, analog weights). Over time, the weights can be adjusted to improve the accuracy of the neural network. Over time, this can result in a neural network with high accuracy.

Neural networks have a wide range of applications. For example, neural networks are used, among others, for system identification and control (vehicle control, trajectory prediction, process control, natural resource management), quantum chemistry, general game play, pattern recognition (radar systems, face identification, signal classification, 3D reconstruction, object recognition), sequence recognition (gesture, speech, handwritten and printed text recognition), medical diagnostics, finance (e.g. automated trading systems), data mining, visualization, machine translation, social network filtering and/or email spam. Can be used for filtering.

Due to the computing resources some neural networks require, in some approaches, neural networks are deployed in a computing system, such as a host computing system (eg, desktop computer, supercomputer, etc.) or a cloud computing environment. In these approaches, as part of the operation to train the neural network, data to be subjected to the neural network can be stored in a memory resource, such as a NAND storage device, and a processing resource, such as a central processing unit, can access the data and use the neural network to It can execute commands to process data. Some approaches may also use specialized hardware such as field programmable gate arrays or application specific integrated circuits as part of neural network training. In other approaches, storage and training of one or more neural networks may occur within a non-volatile memory device, such as a dynamic random access memory (DRAM) device.

Data that may be used to perform neural network (or neuromorphic) operations may be stored in specific formats. For example, data may be stored in analog or digital formats to increase the accuracy of the data. One such format may include a format referred to as a "universal number" (unum) format. There are several types of unum formats—Type I unum, Type II unum, and Type III unum—that can be referred to as “positive” and/or “valid.” Type I unum is a superset of the IEEE 754 standard floating-point format that uses "ubit" at the end of a fraction to indicate whether a real number is an exact float, or in an interval between adjacent floats. The sign, exponent, and fraction bits of type I unum take their definition from the IEEE 754 floating point format, but the length of the exponent and fraction fields of type I unum can vary dramatically from a single bit to a maximum user-definable length. . By taking the sign, exponent, and fraction bits from the IEEE 754 standard floating-point format, a Type I unum can behave similarly to floating-point numbers, but the variable bit lengths represented by the exponent and fraction bits of a Type I unum represent floats. may require additional management.

Referring to the floating point standard, bit strings (e.g., strings of bits that can represent numbers), such as strings of binary digits, are integers or three sets of bits - referred to as a "base". It is expressed in terms of a set of bits, a set of bits referred to as an "exponent", and a set of bits referred to as a "mantissa" (or significand). The integers or sets of bits that define the format in which a string of binary numbers is stored may be referred to herein as a "number format" or "format" for simplicity. For example, the aforementioned integers or three sets of bits (e.g., radix, exponent, and mantissa) that define a floating-point bit string may be referred to as a format (e.g., a first format) . As will be described in more detail below, a positive bit string may include integers or four sets of bits (e.g., sign, regime, exponent, and mantissa), which may also be referred to as a "number format" or may be referred to as a “format” (eg, a second format). Also, under the floating point standard, there are two infinities (e.g., +∞ and -∞) and/or two kinds of "NaN" (not a number): qNaN (quiet NaN) and signaling NaN (signaling NaN). can be included in the string.

The floating point standard has been used in computing systems for many years and defines arithmetic formats, interchange formats, rounding rules, operations, and exception handling for calculations performed by many computing systems. Arithmetic formats may include binary and/or decimal floating point data, which may include finite numbers, infinities, and/or special NaN values. Interchange formats may include encodings (eg, bit strings) that may be used to exchange floating point data. Rounding rules may include a set of properties that may be satisfied when rounding numbers during arithmetic operations and/or conversion operations. Floating point operations may include arithmetic operations and/or other computational operations such as trigonometric functions. Exception handling may include indications of exceptional conditions such as division by zero, overflow, and the like.

Referring back to universal number formats, Type II unums are generally incompatible with floats, which allow clean mathematical designs based on projective real numbers. A Type II unum can contain n bits and can be described in terms of a " u -lattice" in which the quadrants of the circular projection are filled with an ordered set of 2 ^n-3 - 1 real numbers. Values of Type II unum can be reflected about the axis that bisects the circular projection such that positive values are in the upper right quadrant of the circular projection, while their negative counterparts are in the upper left quadrant of the circular projection. The lower half of the circular projection representing the Type II unum may contain the reciprocal of the values in the upper half of the circular projection. Type II unums generally rely on lookup tables for most operations. For example, the size of the lookup table can limit the effectiveness of a Type II unum in some situations. However, Type II unums can provide improved computational capabilities compared to floats under some conditions.

The Type III unum format is referred to herein as a "positive format" or, for brevity, as a "positive". In contrast to floating point bit strings, posits can, under certain conditions, enable a wider dynamic range and higher accuracy (precision) than floating point numbers with the same bit width. This may allow operations performed by the computing system to be performed at a higher rate (eg, faster) when using positions than using floating point numbers, which in turn may, for example, perform such operations The performance of a computing system may be improved by reducing the number of clock cycles used to perform it, thereby reducing processing time and/or power consumed performing these operations. In addition, the use of posits in computing systems may enable higher accuracy and/or precision than floating point numbers, which may also allow some approaches (e.g., ones that rely on floating point format bit strings). approaches) may improve the functionality of the computing system. However, performing neural network or neuromorphic operations on data stored in a Type III unum format can be more difficult than performing such operations on data stored in an analog format.

Embodiments herein relate to hardware circuitry (eg, control circuitry, digital-to-analog converters, analog-to-digital converters, etc.) configured to perform various operations on bit strings to improve the overall functionality of a computing device. For example, embodiments herein relate to hardware circuitry configured to perform neuromorphic operations to train a neural network or to cause a neural network to simulate learning using posi- tions.

In some embodiments, by performing operations in this manner, hardware circuitry may enable improved performance of neuromorphic operations for such neural network purposes, while for data in unum or posit format a memory device and/or or before improved accuracy and/or precision of performance of operations performed outside of a neuromorphic memory array, improved speed in performing unum or positive operations, and/or performance of arithmetic and/or logical operations; It is possible to still maintain a reduced required storage space for bit strings during or after execution.

As used herein, the term “resident on” refers to being physically located on a particular component. Neuron circuitry, such as, for example, neuron circuitry 552 shown in FIG. 5B residing on array portion 132 of memory array 130 shown in FIG. , circuitry, logic, or other hardware components) are physically contained within an array portion and/or memory array (ie, within the same die or package) described below. The term “resident on” may be used interchangeably herein with other terms such as “disposed on” or “located on”.

By performing neuromorphic operations using neurons within a memory array (e.g., a DRAM memory array) and/or performing arithmetic operations using hardware circuitry, these operations can be performed outside the memory array or in a positive format. It may enable neural network training and/or learning using data in positive format in an improved manner to increase the efficiency of neural network processing of the data, compared to approaches performed without the use of data in . For example, performing neuromorphic operations on devices external to the memory array or on data that does not use a positive format reduces the efficiency of the neuromorphic operations and reduces the performance of the memory array and/or memory device. can reduce

In the following detailed description of the present disclosure, reference is made to the accompanying drawings, which form a part of this disclosure and are shown as examples of how one or more embodiments of the disclosure may be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice embodiments of the present disclosure, and other embodiments may be utilized and process, electrical, and structural changes may be made without departing from the scope of the present disclosure. should be understood as possible.

As used herein, designations such as "N", "M", etc., particularly for reference numerals in the drawings, indicate that a number of specific features so designated may be included. Also, it should be understood that the terminology used herein is merely for describing specific embodiments and is not intended to be limiting. As used herein, singular expressions are used unless the context clearly dictates otherwise. It may include both singular and plural objects. Also, "a number of", "at least one", and "one or more" (e.g., multiple memory banks) can refer to one or more memory banks, whereas "a plurality of" means that these are more than one. It is intended to refer to many things.

Further, the words "may" and "may" are used throughout this application in a permissive sense (ie, likely to, capable of), rather than a mandatory (ie, should) meaning. is used as The term "comprises", and its derivatives, means "including but not limited to". The terms “coupled” and “coupling” are contextually appropriate, directly or indirectly connected to or physically accessing and moving (transmitting) commands and/or data. means The terms “bit strings,” “data,” and “data values” may be used interchangeably and have the same meaning herein, as appropriate in the context.

The drawings herein follow a numbering convention in which the first digit or digits correspond to a figure number and the remaining digits identify elements or components in the figure. Similar elements or components between different figures may be identified by the use of like numbers. For example, 120 may refer to element “20” in FIG. 1 and a similar element may be referenced as 220 in FIG. 2A. A plurality of similar elements or components or a group of similar elements or components may be referred to herein collectively by a single element number. For example, the plurality of reference elements 431-1, 431-2, and 431-3 may be collectively referred to as 431. As will be appreciated, elements presented in various embodiments herein may be added, exchanged, and/or removed to provide many additional embodiments of the present disclosure. Further, the proportions and relative scale of elements provided in the drawings are intended to illustrate particular embodiments of the present disclosure and should not be taken in a limiting sense.

1 is a functional block diagram in the form of a computing system 100 that includes an apparatus that includes a host 102 and a memory device 104 in accordance with multiple embodiments of the present disclosure. As used herein, “apparatus” refers to any of various structures or combinations of structures, such as, for example, a circuit or circuitry, die or dies, module or modules, device or devices, or system or systems. may refer to, but is not limited thereto. Also, components (e.g., host 102, control circuitry 120, processing resources (or logic circuitry) 122, memory resources 124, and/or neuromorphic memory array 130) Each may be separately referred to herein as a “device”.

The memory device 104 may include one or more memory modules (eg, single inline memory modules, dual inline memory modules, etc.). The memory device 104 may include volatile memory and/or non-volatile memory. In some embodiments, memory device 104 may include a multi-chip device. A multi-chip device can include a number of different memory types and/or memory modules. For example, memory device 104 may include non-volatile or volatile memory on any type of module.

Memory device 104 may provide main memory for memory system 100 , or may be used as additional memory or storage throughout memory system 100 . The memory device 104 can include one or more neuromorphic memory arrays 130 (eg, an array of memory cells) that can include volatile and/or non-volatile memory cells. The neuromorphic memory array 130 may be, for example, a flash memory array having a NAND architecture. Although embodiments are not limited to a particular type of memory device, memory device 104 may include RAM, ROM, DRAM, SDRAM, PCRAM, RRAM, and flash memory, among others.

In embodiments where memory device 104 includes non-volatile memory, memory device 104 may include flash memory devices, such as NAND or NOR flash memory devices. However, embodiments suggest that the memory device 104 is compatible with other non-volatile memory devices such as non-volatile random access memory devices (e.g., NVRAM, ReRAM, FeRAM, MRAM, PCM), 3-D cross point (3D XP ) memory devices, “recently made” memory devices, etc., or combinations thereof. A 3D XP array of non-volatile memory, along with a stackable cross-grid data access array, can perform bit storage based on changes in bulk resistance. Also, unlike many flash-based memories, 3D XP non-volatile memory can perform write in-place operations, in which non-volatile memory cells can be programmed without the non-volatile memory cells being previously erased. there is.

As shown in FIG. 1 , host 102 can be coupled to memory device 104 . In many embodiments, host 102 may be coupled to memory device 104 via one or more channels 103 (eg, a bus, interface, communication path, etc.). In addition, control circuitry 120 of memory device 104 may be coupled to neuromorphic memory array 130 via channel 107 . Channel(s) 103 may be used to transfer data between memory system 104 and host 102 and may be in the form of a standardized interface. For example, when the memory system 104 is used for data storage in the computing system 100, the channel(s) 103 are serial advanced technology attachment (SATA), peripheral (PCIe), among other physical connectors and interfaces. component interconnect express), or a universal serial bus (USB) or double data rate (DDR) interface. In general, however, channel(s) 103 are used for conveying control, address, data, and other signals between a host 102 and memory system 104 having compatible receptors for host interface 103. interfaces can be provided.

Host 102 may be a personal laptop computer, desktop computer, digital camera, mobile phone, internet-of-things (IoT) enabled device, or memory card reader, graphics processing unit (e.g., video card). Host 102 may include a system motherboard and/or backplane, and may include multiple memory access devices, such as multiple processing devices (e.g., one or more processors, microprocessors, or some other type of the control circuit) may be included. Those skilled in the art will understand that "processor" can mean one or more processors, such as parallel processing systems, multiple co-processors, and the like.

System 100 may include separate integrated circuits, or host 102 , memory device 104 , and neuromorphic memory array 130 may be on the same integrated circuit. System 100 may be, for example, a server system and/or a high-performance computing (HPC) system and/or a portion thereof. 1 shows a system with a von Neumann architecture, embodiments of the present disclosure may be used for non-von Neumann architectures - one or more components normally associated with a von Neumann architecture (e.g., CPU , ALU, etc.) may not be included.

In some embodiments, host 102 may be responsible for running an operating system for computing system 100 that includes memory device 104 . Accordingly, in some embodiments, host 102 may be responsible for controlling the operation of memory device 104 . For example, host 102 may execute instructions (eg, in the form of an operating system) that manage hardware of computing system 100, such as scheduling tasks, running applications, controlling peripherals, and the like.

The memory device 104 , shown herein in more detail in FIGS. 2A and 2B , may include control circuitry 120 , which may include a processing resource 122 and a memory resource 124 . Processing resource 122 may be received from an application specific integrated circuit (ASIC), field programmable gate array (FPGA), system-on-chip, or host 102 and/or other external devices, as described in more detail herein. may be provided in the form of an integrated circuit, such as another combination of hardware and/or circuitry configured to perform arithmetic and/or logic operations on a bit string. In some embodiments, processing resource 122 may include an arithmetic logic unit (ALU). The ALU is used to perform operations such as those described above (e.g., arithmetic operations, logical operations, bitwise operations, etc.) on integer binary bit strings, such as bit strings in positive format. may include circuitry (eg, hardware, logic, one or more processing devices, etc.). However, embodiments are not limited to an ALU, and in some embodiments, processing resource 122 may be a state machine and/or in addition to or instead of an ALU, as described in more detail herein with respect to FIG. 5 . instruction set architecture (or combinations thereof).

For example, processing resource 122 may receive one or more bit strings (e.g., a plurality of bits) in positive format and/or perform arithmetic and/or logical operations using the bit strings in positive format. It can be configured to cause the performance of operations. In contrast to bit strings in floating point format, there are three sets of integers or bits - the set of bits referred to as the "radix", the set of bits referred to as the "exponent", and the "mantissa" (or mantissa) A set of bits, referred to as , where the bit string(s) in positive format are four sets of bits - at least one bit, referred to as "sign", set of bits referred to as "regime", " a set of bits referred to as the "exponent", and a set of bits referred to as the "mantissa" (or mantissa). As used herein, set of bits is intended to refer to a subset of bits included in a bit string. Examples of sets of sign, regime, exponent, and mantissa of bits are described in more detail herein with respect to FIGS. 3 and 4A-4B.

In some embodiments, processing resource 122 performs addition, subtraction, multiplication, division, fused multiplicative addition, multiplication-accumulation, dot product unit, absolute value (e.g., FABS()) using positive bit strings. over or under, fast Fourier transform, inverse fast Fourier transform, sigmoid function, convolution, square root, exponential, and/or logarithmic operations, and/or logical operations such as AND, OR, XOR, NOT, etc., as well as It may be configured to perform (or cause the performance of) arithmetic operations such as trigonometric operations such as sine, cosine, tangent, and the like. As will be appreciated, the foregoing list of operations is not intended to be exhaustive, nor is the foregoing list of operations intended to be limiting, and processing resource 122 may perform (or cause to perform) other arithmetic and/or logical operations. ) can be configured.

After control circuitry 120 performs arithmetic and/or logical operations on the bit string(s), control circuitry 120 outputs the resulting bit string (e.g., a result representing the result of the arithmetic operation and/or logical operation). bit string) to be passed to the host 102 and/or the neuromorphic memory array 130 . In some embodiments, the resulting bit string may be sent to the neuromorphic memory array 130 and the data of the resulting bit string may be input into a neural network of the neuromorphic memory array 130 . For example, the resulting bit string may be a plurality of neurons (eg, neuronal elements) 125-1, 125-2, 125-3, 125-4, 125-5, 125-6 (hereafter, referred to as neuronal elements 125). In some embodiments, control circuitry 120 may transmit the resulting bit string(s) to host 102 and/or neuromorphic memory array 130, for example in positive format. The neuronal components 125 can be coupled to each other and to other elements within the neuromorphic memory array 130, which will be further described below in connection with FIGS. 5A-5C.

Control circuitry 120 may further include a memory resource 124 , which may be communicatively coupled to processing resource 122 . Memory resource 124 may include volatile memory resources, non-volatile memory resources, or a combination of volatile and non-volatile memory resources. In some embodiments, memory resource 124 may be random access memory (RAM), such as static random access memory (SRAM). However, embodiments are not so limited, and memory resources 124 may be "recently made" such as caches, one or more registers, NVRAM, ReRAM, FeRAM, MRAM, PCM), 3-D Crosspoint (3D XP) memory devices. memory device, etc., or combinations thereof.

Control circuitry 120 may be communicatively coupled to neuromorphic memory array 130 via one or more channels 107 . Neuromorphic memory array 130 may be, for example, a DRAM array, SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash array, and/or NOR flash array. Array 130 has rows connected by access lines, which may be referred to herein as word lines or select lines, and columns connected by sense lines, which may be referred to herein as digit lines or data lines. It may include memory cells arranged in . Although a single array 130 is shown in FIG. 1, embodiments are not so limited. For example, memory device 104 may include multiple memory arrays 130 (eg, multiple banks of DRAM cells, NAND flash cells, etc.). Array 130 may also include neurons 125 arranged in rows and columns and coupled to memory cells, as will be further described below with respect to FIG. 5C.

The embodiment of FIG. 1 may include additional circuitry not shown in order not to obscure embodiments of the present disclosure. For example, the memory device 104 may include address circuitry for latching address signals provided over I/O connections through the I/O circuitry. Address signals may be received and decoded by a row decoder and a column decoder to access memory device 104 and/or neuromorphic memory array 130 . Those skilled in the art will appreciate that the number of address input connections may vary depending on the density and architecture of memory device 104 and/or neuromorphic memory array 130 .

2A is another functional block diagram in the form of a computing system that includes an apparatus 200 that includes a host 202 and a memory device 204 in accordance with multiple embodiments of the present disclosure. The memory device 204 may include control circuitry 220 , which may be similar to the control circuitry 120 shown in FIG. 1 . Similarly, host 202 can be similar to host 102 shown in FIG. 1 , memory device 204 can be similar to memory device 104 shown in FIG. 1 , and neuromorphic memory Array 230 may be similar to neuromorphic memory array 130 shown in FIG. 1 . Each of the components (e.g., host 202, control circuitry 220, processing resource 222, memory resource 224, and/or neuromorphic memory array 230, etc.) is referred to herein as a "device can be referred to separately as ".

Host 202 may be communicatively coupled to memory device 204 via one or more channels 203 and 205 . Channels 203 and 205 may be interfaces, buses, communication paths, or other physical connections through which data and/or commands may be transferred between host 202 and memory device 204 . Channels 203 and 205 may be used to transfer data between memory system 204 and host 202 and may be in the form of a standardized interface.

When memory system 204 is used for data storage in computing system 200, channels 203 and 205 are serial advanced technology attachment (SATA), peripheral component interconnect express (PCIe), among other physical connectors and interfaces. , or a universal serial bus (USB) or double data rate (DDR) interface. In general, however, channels 203 and 205 carry control, address, data, and other signals between a host 202 and memory system 204 having compatible receptors for channels 203 and 205. An interface can be provided to do this. In some embodiments, to cause initiation of an operation to be performed by the control circuitry 220 (e.g., an operation to perform arithmetic and/or logical operations on bit string(s) in positive format). Commands may be transmitted over channels 203 and 205 from the host.

In some embodiments, control circuitry 220 performs arithmetic and arithmetic operations in response to an initiate command sent from host 202 over one or more of channels 203, 205 in the absence of an intervening command from host 202. Note that/or it can perform logical operations. That is, if control circuitry 220 receives a command from host 202 to initiate performance of an operation, the operation may be performed by control circuitry 220 in the absence of additional commands from host 202. . However, in some embodiments, control circuitry 220 may, in the absence of a command from host 202 specifying that an operation is to be performed (eg, a start command), generate a bit string (eg, in positive format). bit string) to perform operations in response to receiving it. For example, control circuitry 220 may be configured to self-initiate performance of arithmetic and/or logical operations on the received bit string(s) in response to receiving the bit string(s). However, in some embodiments, in response to receiving a command to perform neuromorphic operations on the data, the data may be converted to an analog format as it is sent to the neuromorphic memory array 230 .

As used herein, “first precision level” and “second precision level” generally refer to the accuracy of a bit string and/or the resultant bit string representing the result of an operation performed using one or more bit strings. For example, floating point format bit strings may be described herein as having a "first level of precision," while unum bit strings (eg, positive format bit strings) may have a particular precision or "second level of precision." 2 levels of precision" because unum bit strings can provide a higher level of precision under certain conditions than numbers in floating point formats, as described in more detail herein.

In some embodiments, a floating point format or unum format may refer to a digital format, while the additional format may include an analog format. A digital format may use discrete values such as "0" or "1", while an analog format may use more continuous values and represent physical measurements along that continuum.

2A, memory device 204 includes register access component 206, high-speed interface (HSI) 208, controller 210, one or more peripheral sense amplifiers (PSAs) 212, main memory input/output (I/O) circuitry 214, row address strobe (RAS)/column address strobe (CAS) chain control circuitry 216, RAS/CAS chain components 218, control circuitry 220, and A neuromorphic memory array 230 may be included. As shown in FIG. 2A , the control circuitry 220 is located in a region of the memory device 204 that is physically separate from the neuromorphic memory array 230 . That is, in some embodiments, the control circuitry 220 is located at a location around the neuromorphic memory array 230 .

The register access component 206 can enable transferring and fetching data from the host 202 to the memory device 204 and from the memory device 204 to the host 202 . For example, register access component 206 may store addresses, such as memory addresses corresponding to data to be transferred from memory device 204 to host 202 or from host 202 to memory device 204. (or enable lookup of addresses). In some embodiments, register access component 206 may enable transferring and fetching data to be operated on by control circuitry 220 and/or register access component 206 may enable transmission of data to host 202. It may be possible to transmit or fetch data that has been calculated by the control circuitry 220 for transmission.

HSI 208 may provide an interface between host 202 and memory device 204 for commands and/or data traversing channel 205 . HSI 208 may be a double data rate (DDR) interface, such as a DDR3, DDR4, DDR5 interface. However, embodiments are not limited to a DDR interface, and HSI 208 can be a Quad Data Rate (QDR) interface, a Peripheral Component Interconnect (PCI) interface (e.g., Peripheral Component Interconnect Express (PCIe)), or a channel There may be other suitable interfaces for transferring commands and/or data between host 202 and memory device 204 via (s) 203 , 205 .

Controller 210 may be responsible for executing instructions from host 202 and accessing control circuitry 220 and/or neuromorphic memory array 230 . Controller 210 may be a state machine, sequencer, or some other type of controller. Controller 210 receives commands from host 202 (eg, via HSI 208) and, based on the received commands, controls circuitry 220 and/or neuromorphic memory array 230 ) can be controlled. In some embodiments, controller 210 may receive a command from host 202 to cause the performance of arithmetic and/or logical operations on received bit strings using control circuitry 220 . In response to receiving such a command, controller 210 may instruct control circuitry 220 to begin performing the arithmetic and/or logical operation(s).

In some embodiments, controller 210 may be a global processing controller and may provide power management functions to memory device 204 . Power management functions may include control over power consumed by memory device 204 and/or neuromorphic memory array 230 . For example, the controller 210 may control the various banks of the neuromorphic memory array 230 to control which banks of the neuromorphic memory array 230 are active at different times during operation of the memory device 204. The power provided to them can be controlled. This may include shutting down certain banks of the neuromorphic memory array 230 to optimize power consumption of the memory device 230 while providing power to other banks of the neuromorphic memory array 230. there is. In some embodiments, the controller 210 controlling the power consumption of the memory device 204 controls the various cores of the memory device 204 and/or control circuitry 220, neuromorphic memory array 230, etc. This may include controlling power.

PSAs 212 sense (eg, read, store, cache) data values of memory cells in neuromorphic memory array 230 and perform additional functions separate from neuromorphic memory array 230 (eg, read, store, cache). eg, peripheral amplifiers). PSAs 212 may include latches and/or registers. For example, additional latches may be included in PSAs 212 . The latches of the PSAs 212 may be located on the periphery of the neuromorphic memory array 230 of the memory device 204 (eg, on the periphery of one or more banks of memory cells).

Main memory input/output (I/O) circuitry 214 may enable transfer of data and/or commands to and from neuromorphic memory array 230 . For example, main memory I/O circuitry 214 may transmit bit strings, data, and/or commands from host 202 and/or control circuitry 220 to and from neuromorphic memory array 230. transmission of them can be made possible. In some embodiments, main memory I/O circuitry 214 transfers bit strings (e.g., positive bit strings stored as blocks of data) from control circuitry 220 to neuromorphic memory array 230. It may include one or more direct memory access (DMA) elements that can transfer to and from the computer and vice versa.

In some embodiments, main memory I/O circuitry 214 may enable transfer of bit strings, data, and/or commands from neuromorphic memory array 230 to control circuitry 220, such that Control circuitry 220 may perform arithmetic and/or logic operations on bit strings. Similarly, main memory I/O circuitry 214 may enable transfer of bit strings on which one or more operations have been performed by control circuitry 220 to neuromorphic memory array 230 . In this way, data in unum or positive format can be operated on by control circuitry 220 to perform arithmetic and/or logic operations while the data is stored in an array or other location other than neuromorphic memory array 230. can; While data is stored in the neuromorphic memory array 230, it may be used to perform neuromorphic operations. As described in more detail herein, the operations are arithmetic operations performed on bit strings in positive format, logical operations performed on bits in positive format, and bit strings performed on bit strings in positive format. bit-by-bit operations, etc., and neuromorphic operations performed on bitstreams in positive format.

Row Address Strobe (RAS)/Column Address Strobe (CAS) chain control circuitry 216 and RAS/CAS chain components 218 use neuromorphic to latch row addresses and/or column addresses to initiate memory cycles. It can be used with memory array 230 . In some embodiments, RAS/CAS chain control circuitry 216 and/or RAS/CAS chain component 218 determines whether read and write operations associated with neuromorphic memory array 230 are to be initiated or terminated. Row and/or column addresses of memory array 230 may be resolved. For example, upon completion of an operation using control circuitry 220, RAS/CAS chain control circuitry 216 and/or RAS/CAS chain component 218 may perform neuromorphic operations to control circuitry ( A specific location in the neuromorphic memory array 230 where the bit strings operated by 220 should be stored may be latched and/or resolved. Similarly, the RAS/CAS chain control circuitry 216 and/or the RAS/CAS chain component 218 may perform the bit string prior to the control circuitry 220 performing neuromorphic operations on the bit string(s) in the analog format. The strings may latch and/or resolve a specific location in the neuromorphic memory array 230 to be transmitted to the control circuitry 220 .

As described above with respect to FIG. 1, neuromorphic memory array 230 may include, for example, a DRAM array, an SRAM array, an STT RAM array, a PCRAM array, a TRAM array, an RRAM array, a NAND flash array, and/or a NOR array. It may be a flash array, but embodiments are not limited to these specific examples. The neuromorphic memory array 230 may serve as main memory for the computing system 200 shown in FIG. 2 . In some embodiments, neuromorphic memory array 230 may be configured to store bit strings operated on by control circuitry 220 and/or to store bit strings to be transmitted to control circuitry 220 . The neuromorphic memory array 230 may include an array portion 232 . Array portion 232 includes a plurality of neurons (e.g., neuronal elements) 225-1, 225-2, 225- , which are used to perform a number of neuromorphic operations, as described below. 3) (hereinafter collectively referred to as neurons 225). Neurons 225 may be coupled to a plurality of arithmetic logic units (ALUs) 226 - 1 , 226 - 2 , and 226 - 3 (hereafter collectively referred to as ALUs 226 ).

Control circuitry 220 includes logic circuitry (eg, processing resource 122 shown in FIG. 1 ) and/or memory resource(s) (eg, memory resource 124 shown in FIG. 1 ). can do. As described above with respect to FIG. 1 and described in more detail below with respect to FIG. 6 , control circuitry 220 receives one or more bit strings in positive format and, by neuromorphic memory array 230 , It can be configured to cause the performance of neuromorphic operations using one or more bit strings in positive format.

For example, bit strings (e.g., data, a plurality of bits, etc.) may be sent to host 202, e.g., in a first format (e.g., positive format), and/or in a first format (e.g., For example, a positive format) may be received by the control circuitry 220 from the neuromorphic memory array 230, and may be received by the control circuitry 220, for example, a memory resource of the control circuitry 220 (eg, shown herein). It can be stored by the control circuitry 220 in the memory resource 624 shown in FIG. Control circuitry 220 performs arithmetic and/or logical operations on (or causes arithmetic and/or logical operations to be performed on) the bit string(s), as described herein in more detail with respect to FIG. 6 . can do.

As described in more detail with respect to FIGS. 3 and 4A-4B , the posits may provide improved accuracy (e.g., precision) over corresponding bit strings represented in floating point format, and more May require less storage space. Accordingly, by using the control circuitry 220 to use positive bit strings to perform neuromorphic operations using neurons of a neural network, the performance of the computing system 200 can be improved by performing neuromorphic operations outside the memory array. It can be improved over approaches that use positivebit strings to perform because neuromorphic operations can be performed faster inside a memory array (e.g., neuromorphic operations can be performed within a memory array). because it is more efficient).

As described above, when control circuitry 220 receives positive bit strings from host 202 and/or neuromorphic memory array 230, control circuitry 220 performs It may perform (or cause the performance of) arithmetic and/or logical operations. For example, control circuitry 220 may perform addition, subtraction, multiplication, division, fused multiplier-add, multiply-accumulate, dot product unit, absolute value (e.g., FABS()) for the received positive bit strings. over or under, fast Fourier transform, inverse fast Fourier transform, sigmoid function, convolution, square root, exponential, and/or logarithmic operations, and/or logical operations such as AND, OR, XOR, NOT, etc., as well as It may be configured to perform (or cause the performance of) arithmetic operations such as trigonometric operations such as sine, cosine, tangent, and the like. As will be appreciated, the foregoing list of operations is not intended to be exhaustive, nor is the foregoing list of operations intended to be limiting, and the control circuitry 220 may perform other arithmetic and/or logical operations on the positive bit strings. may be configured to perform (or cause the performance of)

In some embodiments, control circuitry 220 may perform the operations listed above in conjunction with the execution of one or more machine learning algorithms. For example, the control circuitry 220 may perform operations related to one or more neural networks such as those used in the neuromorphic memory array 230 . Neural networks allow an algorithm to be trained over time to determine an output response based on input signals. For example, over time, a neural network can inherently learn to better maximize its chances of completing a particular goal. This can be desirable in machine learning applications because a neural network can be trained over time with new data to achieve a better maximization of the chance of completing a particular goal. A neural network can be trained to improve the computation of specific goals and/or specific tasks over time. However, in some approaches, machine learning (eg, neural network training) can be processing intensive (eg, consume large amounts of computer processing resources) when transferring data into and out of a memory array for processing by external devices. may be) and/or may be time intensive (eg, may require long calculations to be performed that consume many cycles). In contrast, by using neurons 225 to perform these neuromorphic operations on bit strings, the amount of processing resources and/or time spent performing the operations is less than the amount of such operations. may be reduced compared to approaches performed using elements outside the memory array.

2B shows functionality in the form of a computing system 200 that includes a host 202, a memory device 204, an application specific integrated circuit 223, and a field programmable gate array 221 in accordance with multiple embodiments of the present disclosure. It is a block diagram. Each of the components (eg, host 202, memory device 204, FPGA 221, ASIC 223, etc.) may be separately referred to herein as an “apparatus.”

As shown in FIG. 2B , host 202 can be coupled to memory device 204 via channel(s) 203, which can be similar to channel(s) 103 shown in FIG. there is. A field programmable gate array (FPGA) 221 may be coupled to the host 202 via channel(s) 217 and an application specific integrated circuit (ASIC) 223 may be coupled to the host via channel(s) 219 (202). In some embodiments, channel(s) 217 and/or channel(s) 219 may include a peripheral serial interconnect express (PCIe) interface, although embodiments are not limited thereto, and channel(s) 217 and/or channel(s) 219 may include other types of interfaces, buses, communication channels, etc. to communicate between host 202 and FPGA 221 and/or ASIC 223 Enables the transmission of data.

As noted above, non-limiting examples of arithmetic and/or logic operations that may be performed by FPGA 221 and/or ASIC 223 include addition, subtraction, multiplication, division, fusion using positive bit strings. multiplicative addition, multiplication-accumulation, dot product unit, absolute value (e.g., FABS()) above or below, fast Fourier transform, inverse fast Fourier transform, sigmoid function, convolution, square root, exponential, and/or logarithmic operations, and/or logical operations such as AND, OR, XOR, NOT, etc., as well as arithmetic operations such as trigonometric operations such as sine, cosine, tangent, etc.

FPGA 221 may include state machine 227 and/or register(s) 229 . State machine 227 may include one or more processing devices configured to perform operations on inputs and generate outputs. For example, FPGA 221 may receive positive bit strings from host 202, perform arithmetic and/or logical operations on the positive bit strings, and perform operations on the received positive bit strings. may be configured to generate result positive bit strings representing the result of FPGA 221 may also be configured to cause performance of neuromorphic operations in neuromorphic memory array 230 using neurons, as will be further described below with respect to FIGS. 5A-5C . .

Register(s) 229 of FPGA 221 buffers and/or stores the positive bit strings received from host 202 before state machine 227 performs operations on the received positive bit strings. can be configured to In addition, the register(s) 229 of the FPGA 221 transmits the results of operations performed on the received positive bit strings to circuitry outside the ASIC 233, such as the host 202 or memory device 204. It may be configured to buffer and/or store the result posit bit string representing the result prior to transmission.

ASIC 223 may include logic 241 and/or cache 243 . Logic 241 may include circuitry configured to perform operations on inputs and generate outputs. In some embodiments, ASIC 223 receives positive bit strings from host 202 and performs arithmetic and/or logical operations on the positive bit strings to perform may be configured to generate result post bit strings representing the result of the operation performed. Likewise, ASIC 223 may enable performance of subsequent neuromorphic operations to be performed on the bit strings.

Cache 243 of ASIC 223 may be configured to buffer and/or store positive bit strings received from host 202 before logic 241 performs operations on the received positive bit strings. there is. In addition, the cache 243 of the ASIC 223 transmits the result of the operation performed on the received positive bit strings to circuitry outside the ASIC 233, such as the host 202 or memory device 204. buffer and/or store a result positive bit string representing the result.

Although FPGA 227 is shown as including state machine 227 and register(s) 229, in some embodiments, FPGA 221 may include state machine 227 and/or register(s) ( In addition to or instead of 229 , logic such as logic 241 , and/or cache such as cache 243 , may be included. Similarly, ASIC 223 may, in some embodiments, in addition to or instead of logic 241 and/or cache 243, a state machine, such as state machine 227, and/or register(s) 229 ).

3 is an example of an n-bit universal number with es exponent bits, or "unum". In the example of FIG. 3 , the n-bit unum is the positive bit string 331 . As shown in FIG. 3, n bit position 331 is a set of sign bit(s) (e.g., sign bit 333), a set of regime bits (e.g., regime bits 335) ), a set of exponent bits (eg, exponent bits 337), and a set of mantissa bits (eg, mantissa bits 339). The mantissa bits 339 may alternatively be referred to as a “fractional part” or “fractional bits” and may represent the portion (eg, number) of the bit string following the decimal point.

The sign bit 333 can be zero (0) for positive numbers and one (1) for negative numbers. The regime bits 335 are described with respect to Table 1 below, which presents (binary) bit strings and their associated numeric meaning (k). In Table 1, the numerical meaning (k) is determined by the length of the string of bits. The letter x in the binary part of Table 1 indicates that the bit value is independent of the determination of the regime, since the (binary) bit string is terminated in response to successive bit flips or when the end of the bit string is reached. Because. For example, in the (binary) bit string 0010, the bit string is terminated in response to a 0 being changed to a 1 and back to a 0 again. Thus, the last 0 is independent of the regime, all that is considered for regimes is the leading identical bits and the first opposite bit that terminates the bit string (if the bit string contains these bits).

binary number 0000 0001 001X 01XX 10XX 110X 1110 1111 number ( k ) -4 -3 -2 -One 0 One 2 3

은 비트 스트링을 종결시키는 반대 비트에 대응한다. 예를 들어, 표 1에 도시된 숫자(k) 값 -2에 대해, 레짐 비트들 r은 처음 두 선두의 0들에 대응하는 한편, 레짐 비트(들)

은 1에 대응한다. 위에서 언급된 바와 같이, 표 1에서 X로 표현되는 숫자(k)에 대응하는 최종 비트는 레짐과 무관하다. 3, regime bits 335 r correspond to the same bits in the bit string, while regime bits 335

corresponds to the opposite bit that terminates the bit string. For example, for the number k value -2 shown in Table 1, the regime bits r correspond to the first two leading zeros, while the regime bit(s)

corresponds to 1. As mentioned above, the last bit corresponding to the number k represented by X in Table 1 is independent of the regime.

이다. 사용될 몇 가지 예시적인 값들이 아래 표 2에서 제시된다.If m corresponds to the same number of bits in the bit string, and the bits are zero, then k = -m . If the bits are 1, then k = m - 1. This is illustrated in Table 1, in which case, for example, the (binary) bit string 10XX has one 1 and k = m - 1 = 1 -1 = 0. Similarly, the (binary) bit string 0001 contains three zeros, so k = -m = -3. The regime can represent a scale factor of used ^k , where used =

am. Some exemplary values to be used are presented in Table 2 below.

es 0 One 2 3 4 used 2 2 ² = 4 4 ² = 16 16 ² = 256 256 ² = 65536

The exponent bits 337 correspond to the exponent e as an unsigned number. In contrast to floating point numbers, the exponent bits 337 described herein may not have a bias associated with them. As a result, the exponent bits 337 described herein may represent scaling by a factor of ^2e . As shown in FIG. 3, es exponent bits ( e ₁ , e ₂ , e ₃ , . . . , e _es ). In some embodiments, this may enable tapered accuracy of the n bit posit 331 where numbers closer to one in magnitude have higher accuracy than very large or very small numbers. However, because very large or very small numbers may be used less frequently in certain kinds of operations, the n shown in FIG. The tapered accuracy behavior of bit position 331 may be desirable in a wide range of situations.

Mantissa bits 339 (or fraction bits) represent any additional bits that may be part of n-bit positions 331 lying to the right of exponent bits 337 . Similar to floating point bit strings, the mantissa bits 339 represent the fraction 1. f, which can be analogous to the fraction f, where f includes one or more bits to the right of the decimal point following the 1. However, in contrast to floating point bit strings, in the n bit position 331 shown in Figure 3, the "hidden bit" (e.g. 1) is always one (e.g. 1) , whereas floating point bit strings may contain a subnormal number for which the “hidden bit” is zero (eg, 0. f ).

4A is an example of positive values for a 3-bit position 431. In Fig. 4a, there are only the right half of the projected real numbers, but negative projected real numbers corresponding to the positive counterparts shown in Fig. 4a can exist on the curve representing the transformation of the curves shown in Fig. 4a with respect to the y-axis. It will be understood.

= 16이다. 포지트(431)의 정밀도는 도 4b에 도시된 바와 같이, 비트 스트링에 비트들을 덧붙임으로써 증가될 수 있다. 예를 들어, 포지트(431-1)의 비트 스트링들에 일(1)의 값을 갖는 비트를 덧붙이면 도 4b의 포지트(431-2)에 의해 도시된 바와 같이 포지트(431)의 정확도를 증가시킨다. 유사하게, 도 4b의 포지트(431-2)의 비트 스트링들에 일의 값을 갖는 비트를 덧붙이면 도 4b에 도시된 포지트(431-3)에 의해 도시된 바와 같이 포지트(431-2)의 정확도를 증가시킨다. 도 4b에 도시된 포지트들(431-2, 431-3)을 얻기 위해 도 4a에 도시된 포지트들(431-1)의 비트 스트링들에 비트들을 덧붙이는 데 사용될 수 있는 보간 규칙들의 예는 다음과 같다.In the example of Fig. 4a, since es = 2, used =

= 16. The precision of the posit 431 can be increased by appending bits to the bit string, as shown in FIG. 4B. For example, appending a bit with a value of one (1) to the bit strings of position 431-1 results in position 431 as shown by position 431-2 in FIG. 4B. increase accuracy. Similarly, appending a bit with a value of one to the bit strings of position 431-2 in Figure 4b results in position 431-3 as shown by position 431-3 shown in Figure 4b. 2) increases the accuracy. Example of interpolation rules that can be used to append bits to the bit strings of positions 431-1 shown in Figure 4A to obtain positions 431-2 and 431-3 shown in Figure 4B. is as follows

와 같을 수 있다. maxpos와 ±∞ 사이에서, 새로운 비트 값이

일 수 있고, 제로와 minpos 사이에서, 새로운 비트 값이

일 수 있다. 이러한 새로운 비트 값들은 새로운 레짐 비트(335)에 대응할 수 있다. 기존 값들 x = 2 ^m 과 y = 2 ⁿ (여기서, m 및 n은 1보다 크게 상이함) 사이에서, 새로운 비트 값은 기하 평균:

으로 주어질 수 있으며, 이는 새로운 지수 비트(337)에 대응한다. 새로운 비트 값이 이 다음의 기존 x와 y 값들 사이의 중간에 있다면, 새로운 비트 값은 산술 평균

를 나타낼 수 있으며, 이는 새로운 가수 비트(339)에 대응한다. maxpos is the largest positive value of the bit string of the positions 431-1, 431-2, and 431-3 shown in FIG. For the smallest value of the bit string in 3), maxpos can be equal to used and minpos is

can be equal to Between maxpos and ±∞, the new bit value is

, and between zero and minpos , the new bit value is

can be These new bit values may correspond to the new regime bit 335 . Between the old values x = 2 ^m and y = 2 ⁿ (where m and n differ by more than 1), the new bit value is the geometric mean:

, which corresponds to the new exponent bit 337. If the new bit value is midway between these next existing x and y values, the new bit value is the arithmetic mean

, which corresponds to the new mantissa bit 339.

= 16이고, 포지트 431-2는 es = 3을 가지므로, useed =

= 256이며, 포지트 431-3는 es = 4를 가지므로, useed =

= 4096이다.4B is an example of a posit configuration using two exponent bits. In FIG. 4b, there are only the right half of the projected real numbers, but negative projected real numbers corresponding to the positive counterparts shown in FIG. 4b can exist on the curve representing the transformation of the curves shown in FIG. 4b with respect to the y-axis. It will be understood. The positions 431-1, 431-2, and 431-3 shown in FIG. 4B each have only two exception values: zero when all bits of the bit string are zero, and zero when the bit string is equal to 1. A one (1) followed by all zeros includes ±∞. Note that the numerical values of the positions 431-1, 431-2, and 431-3 shown in FIG. 4 are exactly used ^k . That is, the numerical values of the positions 431-1, 431-2, and 431-3 shown in FIG. 4 are exactly used to the power of k (the value of k is the regime (eg, the regime described above with reference to FIG. 3) bits 335). In FIG. 4B, post 431-1 has es = 2, so used =

= 16, and position 431-2 has es = 3, so used =

= 256, and position 431-3 has es = 4, so used =

= 4096.

)를 가진다. 상술한 바와 같이, 대응하는 비트 스트링들은 기존 값들 사이에서, 이에 덧붙는 추가적인 지수 비트를 가진다. 예를 들어, 숫자 값들 1/16, ¼, 1, 및 4는 이에 덧붙는 지수 비트를 가질 것이다. 즉, 숫자 값 4에 대응하는 최종 일은 지수 비트이고, 숫자 값 1에 대응하는 최종 제로는 지수 비트인 등이다. 이 패턴은 또한, 4 비트 포지트(431-2)로부터 상기한 규칙들에 따라 생성된 5 비트 포지트인 포지트(431-3)로 보여질 수 있다. 또 다른 비트가 도 4b의 포지트(431-3)에 추가되어 6 비트 포지트를 생성한다면, 1/16과 16 사이의 숫자 값들에 가수 비트들(339)이 덧붙을 것이다. As an illustrative example of adding bits to the 3-bit position 431-1 to produce the 4-bit position 431-2 of FIG. 4B, since used = 256, the bit string corresponding to used of 256 is thus With an additional regime bit appended, the previous used 16 is appended with the termination regime bit (

) has As described above, the corresponding bit strings have an additional exponent bit appended to, between and existing values. For example, the numeric values 1/16, ¼, 1, and 4 will have an exponent bit appended to them. That is, the last day corresponding to the numeric value 4 is the exponent bit, the last zero corresponding to the numeric value 1 is the exponent bit, and so on. This pattern can also be seen as position 431-3, which is a 5-bit position generated according to the rules described above from 4-bit position 431-2. If another bit is added to the position 431-3 of Figure 4b to create a 6-bit position, the mantissa bits 339 will be added to numeric values between 1/16 and 16.

에서

에 이르는 무부호 정수이고, k는 레짐 비트들(335)에 대응하는 정수이며, e는 지수 비트들(337)에 대응하는 무부호 정수이다. 가수 비트들의 집합(339)이 {f ₁ f ₂ . . . f _fs }로서 표현되고 f가 1. f ₁ f ₂ . . . f _fs 로(예를 들어, 일 다음 소수점 다음 가수 비트들(339)로) 표현된다면, p는 아래 식 1로 주어질 수 있다.A non-limiting example of decoding a position (e.g. position 431) to obtain its equivalent number is as follows. In some embodiments, the bit string corresponding to posit p has the range

at

is an unsigned integer leading to , k is an integer corresponding to the regime bits 335, and e is an unsigned integer corresponding to the exponent bits 337. The set of mantissa bits 339 is { f ₁ f ₂ . . . f _fs } where f is 1. f ₁ f ₂ . . . If expressed as f _fs (eg, one followed by the decimal point followed by mantissa bits 339), p may be given by Equation 1 below.

Equation 1

A further illustrative example of decoding a positive bit string is provided below with respect to the positive bit string 0000110111011101 set forth in Table 3 below.

sign regime jisoo singer 0 0001 101 11011101

이다. 이들 값들 및 식 1을 사용하면, 표 3에 주어진 포지트 비트 스트링에 대응하는 숫자 값은

이다.In Table 3, the positive bit string 0000110111011101 is the set of bits that make up it (e.g., sign bit 333, regime bits 335, exponent bits 337, and mantissa bits 339) is decomposed into Since es = 3 in the positive bit string shown in Table 3 (eg, because there are three exponent bits), used = 256. Since the sign bit 333 is zero, the value of the expression corresponding to the positive bit string shown in Table 3 is positive. Regime bits 335 correspond to a value of -3 followed by three consecutive zeros (as described above with respect to Table 1). As a result, the scale factor contributed to the regime bits 335 is 256 ^-3 (eg, used ^k ). The exponent bits 337 represent five (5) as an unsigned integer, thus contributing to an additional scale factor 2 ^e = 2 ⁵ = 32. Finally, since the mantissa bits 339 given as 11011101 in Table 3 represent two hundred and twenty-one 221 as an unsigned integer, the mantissa bits 339 given as f above are

am. Using these values and Equation 1, the numeric value corresponding to the positive bit string given in Table 3 is

am.

5A is a diagram in the form of peripheral sense amplifiers 512, a memory array 530, a plurality of muxes 545, and a plurality of arithmetic logic units (ALUs) 526 in accordance with multiple embodiments of the present disclosure. Functional block diagram 550 . The neuromorphic memory array 530 can receive data from a host (eg, hosts 102 and 202 in FIGS. 1, 2A, and 2B) or other external devices. Data may include bit strings in a specific format (eg, unum number or positive format). Data in positive format may be stored in peripheral sense amplifiers (PSAs) 512 and/or other locations within a memory device (such as memory device 104 in FIG. 1). PSAs 512 may be coupled to a plurality of multiplexers ("MUXs") 545-1, 545-2, 545-3 (hereafter collectively referred to as MUXs 545); Positive format data is transmitted through the MUXs 545 to the neuron components 525-1, 525-2, 525-3, 525-4, 525-5, 525-6, 525-7, 525-8, 525-8) (hereinafter collectively referred to as neuronal elements 525). Neuron components 525 can perform a number of neuromorphic operations on data. Neuron components 525 can also send data and/or results of performing neuromorphic operations on data to additional devices. For example, neuron components 525 may be coupled to a plurality of arithmetic logic units (ALUs) 526-1, 526-2, and 526-3 (hereinafter referred to as ALUs 526). can Neuron components 525 may send data or results to the ALUs for performance of additional operations (eg, RELU operations, sigma operations, etc.).

In one embodiment, neuromorphic operations may be performed using neuronal elements 525 as a neural network. Some neuromorphic systems may use resistive RAM (RRAM), such as PCM devices or self-selecting memory devices, to store synaptic values (or weights) (eg, synaptic weights). Such a variable resistance memory can include memory cells that can be configured to store multiple levels and/or have wide sensing windows. These types of memory may be configured to perform training operations by pulse (eg, spike) control. These training operations may include spike-timing-dependent plasticity (STDP). STDP may have a form of Hebbian learning derived by correlation between spikes transmitted between nodes (eg, neurons). STDP can be an example of a process that adjusts the strength of connections between nodes (eg, neurons).

In neural networks, synaptic weight refers to the strength or amplitude of a connection between two nodes (eg, neurons). The nature and content of information transmitted through a neural network may be based in part on properties of connections representing synapses formed between nodes. For example, an attribute of connections may be synaptic weights. In particular, neuromorphic systems and devices can be designed to achieve results that may not be possible with traditional computer architectures. For example, neuromorphic systems can be used to achieve results more commonly associated with biological systems, such as learning, vision or visual processing, auditory processing, advanced computing, or other processes, or combinations thereof. By way of example, synaptic weights and/or connections between at least two memory cells may represent a synapse, or strength or degree of synaptic connectivity, associated with each short-term connection or long-term connection corresponding to the biological occurrence of short-term and long-term memory. It can be. As will be explained below, a series of neural network operations can be performed to increase the synaptic weight between at least two memory cells in a short-term or long-term manner, depending on which type of memory cell is used.

The learning event of neural network operation can represent the causal propagation of spikes between neurons, enabling weight gain on connecting synapses. An increase in synapse weight can be expressed as an increase in conductivity of a memory cell. A variable resistance memory array (eg, a 3D cross point or self-selecting memory (SSM) array) can emulate an array of synapses, each characterized by a weight, or memory cell conductance. The larger the conductance, the larger the synaptic weight and the higher the degree of memory learning. Short-term memory learning can be fast and/or reversible memory learning in which analog weights of synapses are enhanced, ie, their electrical conductivity is increased by a reversible mechanism. Long-term memory learning can be slow and/or irreversible memory learning in which cell conductance is irreversibly increased for a particular state (e.g., SET or RESET), resulting in longer, non-forgetting memory that comes from experience-dependent learning. cause

Neuromorphic operations may be used to mimic neuro-biological architectures that may exist in the nervous system and/or to store synaptic weights associated with long-term and short-term learning or relationships. The memory device may include a memory array including a first portion and a second portion. The first portion of the memory array may include a first plurality of variable resistance memory cells, and the second portion may include a second plurality of variable resistance memory cells. The second portion may be deteriorated through forced write cycling. The degradation mechanism may include damage to the chalcogenide material. In some embodiments involving memory cells composed of a material other than a chalcogenide material, the degradation mechanism may be a thermal relationship between the memory cells, control through a control gate coupling between the memory cells, a charge loss corresponding to the memory cells, a signal or a threshold of temperature induced losses and the like.

These neuromorphic operations may be performed on data received by neuromorphic memory array 530 . In anticipation that the neural network will be used to detect a particular event represented by the data or patterns in the data, the neural network can be used to train the neural network (e.g., using data sent to neuron elements 525). may receive a large amount of data (what may be referred to as analog weights 559 in FIG. 5B, described below) used for In one embodiment, when data comprising bit strings is received, analog weights may be added to the data values to train a neural network for subsequent neuromorphic processing. Training may include large amounts of data that enable the neural networks of neuromorphic memory array 530 to accurately interpret the data and provide desired or helpful results. Using the neural network processing described above, large amounts of data can train the neural networks of the neuromorphic memory array 530 to detect events or patterns and become more effective and efficient in doing so.

The resulting value of the neuromorphic operation may be sent out of the neuromorphic memory array 530 for further processing to the ALUs 526 and/or to other storage locations. In this way, multiple levels of processing can occur on the same piece of data. For example, a command to perform both arithmetic/logic operations and neuromorphic operations on a set of data may be sent from the host.

Depending on the order of processing, arithmetic operations may be performed while the data is outside the neuromorphic memory array 530 . The result of the arithmetic operation may be sent to the neuromorphic memory array 530 for performing neuromorphic operations. Subsequent to the neuromorphic operations being performed, data can be sent from the neuron elements 525 to other locations within the memory device. The result of the neuromorphic operation can be sent out of the neuron elements 525, and subsequent arithmetic operations can be performed. Results of neuromorphic operations and/or arithmetic operations may be sent back to the host.

As used herein, neural network operations or neuromorphic operations may include operations performed to determine one or more hidden layers of at least one of the neural networks. In general, a neural network may include at least one input layer, at least one hidden layer, and at least one output layer. Layers can include multiple neurons, each capable of receiving input and generating a weighted output. In some embodiments, neurons in the hidden layer(s) calculate weighted sums and/or averages of the inputs received from the input layer(s) and their respective weights, and pass this information to the output layer(s). can

In some embodiments, neural network or neuromorphic operations may be performed by using knowledge learned by trained neural networks to train untrained neural networks. This can reduce the amount of time and resources spent training untrained neural networks by reducing retraining of information already learned by trained neural networks. Additionally, embodiments herein may enable a neural network trained under a particular training methodology to train a neural network that has not been trained with a different training methodology. For example, a neural network can be trained under the TensorFlow methodology, and then an untrained neural network can be trained under the MobileNet methodology. However, embodiments are not limited to these specific examples, and other training methodologies are contemplated as being within the scope of this disclosure.

5B is a functional block diagram in the form of a neuron component 525 that includes a multiplier 557, an accumulator 559, an internal ALU 551, and a register 555 in accordance with multiple embodiments of the present disclosure. Neuron component 525 may include neuron circuitry 552 configured to operate multiplier 557, accumulator 559, internal ALU 551, and register 555 to perform neuromorphic operations. there is. Neuron circuitry 552 may include hardware, logic, or one or more processing devices used to perform neuromorphic operations. As an example, neuron component 525 can receive data from a multiplexer (eg, MUX 545 in FIG. 5A ), and neuron circuitry 552 of neuron component 525 can transmit data to multiplier 557 As an input, it can cause the outgoing of data. Neuron circuitry 552 can cause multiplier 557 to perform a multiplication operation on received data values and send the result of the multiplication operation to adder 559 as an output. An adder 559 may be coupled to the bit string register 555. The bit string register 555 can store a data value representing the overflow of the result of neuromorphic operations using digits. An internal ALU (eg, “mini-ALU”) 551 may provide an input with data that multiplier 557 receives. An accumulator ("ACCUM") 553 may also accumulate the output of adder 559 and provide it to adder 559 as an input.

In this way, neuron component 525 uses neuron circuitry 552 to operate multiplier 557, adder 559, accumulator 553, and internal ALU 551 to perform neuromorphic operations on data. and store the result in the bit string register 555. The output of bit string register 555 can be sent to an ALU (such as ALU 526 in FIG. 5A) for additional operations to be performed on the data (RELU operation, sigma operation, etc.).

5C is a functional block diagram of a portion of a memory array 530 in accordance with multiple embodiments of the present disclosure. Array 530 includes access lines 554-0, 554-1, 554-2, 554-3, 554-4, 554-5, 554-6, ..., 554-R (access lines 554 (collectively referred to as and a plurality of memory cells 501-0 through 501-J (collectively referred to as cells 501) coupled to columns of (collectively referred to as sense lines 556). Memory array 330 is not limited to a particular number of access lines and/or sense lines, and use of the terms "rows" and "columns" refers to the specific physical structure and/or Orientation is not intended. Although not shown, each column of memory cells may be associated with a corresponding pair of complementary sense lines (eg, complementary sense lines 205-1 and 205-2 in FIG. 2A).

The memory array 530 may include a plurality of neurons 525 - 1 and 525 - 2 composed of a plurality of memory cells 501 . For example, as shown in FIG. 5C , sixteen memory cells may constitute a neuron. However, examples are not limited to this. Any number of memory cells may constitute a neuron. Each of the memory cells 501 may constitute components of a neuron, as shown in FIG. 5B.

Each column of memory cells may be coupled to sense circuitry (eg, sense amplifiers 547). In this example, the sensing circuitry includes each of the sensing lines 556-0, 556-1, 556-2, 556-3, 556-4, 556-5, 556-6, 556-7, ..., 556-S A plurality of sense amplifiers (547-0, 547-1, 547-2, 547-3, 547-4, 547-5, 547-6, 547-7, ..., 547-U) coupled to (sense amplifier s 547). Sense amplifiers 547 are connected to access devices (e.g., transistors) 549-0, 549-1, 549-2, 549-3, 549-4, 549-5, 549-6, 549-7 , ..., 549-V) to an input/output (I/O) line 334 (e.g., a local I/O line). In this example, the sense circuitry also includes a number of compute elements 331-0, 331-1, 331-2, 331-0, 331-1, 331-2, 331-, corresponding to respective sense amplifiers 547 and coupled to respective sense lines 556. 3, 331-4, 331-5, 331-6, 331-7, ..., 331-X). Column decode lines 558-1 through 558-W are coupled to the gates of transistors 549-1 through 549-V, respectively, and are sensed by respective sense amplifiers 547-0 through 547-U and / or may be selectively activated to transmit data stored in each of the compute elements 331-0 to 331-X to the secondary sense amplifier 561. In some embodiments, the compute elements 331 may be formed in pitch with their corresponding columns of memory cells and/or corresponding sense amplifiers 547 .

In some embodiments, sense circuitry (eg, compute components 331 and sense amplifier 547 ) is configured to perform signed division operations on the elements stored in array 330 . As an example, a plurality of elements each comprising four data units (eg, four bit elements) may be stored in a plurality of memory cells. A first 4-bit element of the plurality of elements is connected to a first sense line (e.g., 556-0) and to multiple access lines (e.g., 554-0, 554-1, 554-2, 554-0). 3), the second element to a second sense line (eg, 556-1) and to a plurality of access lines (eg, sense lines ( 554-0, 554-1, 554-2, 554-3)). As such, the first element and the second element are stored in the first and second columns of memory cells, respectively.

6 is a functional block diagram in the form of a device 600 that includes control circuitry 620 in accordance with multiple embodiments of the present disclosure. Control circuitry 620 may include logic circuitry 622 and memory resources 624 , which may be similar herein to processing resources 122 and memory resources 124 shown in FIG. 1 . Logic circuitry 622 and/or memory resource 624 may individually be considered a “device.”

Control circuitry 620 may be configured to receive a bit string in positive format from a host (eg, host 102/202 shown herein in FIGS. 1, 2A, and 2B). In some embodiments, the pause bit string may be stored in memory resource 624 . Once a bit string has been received by control circuitry 620, arithmetic and/or logical operations may be performed on the positive bit string in the absence of intervening commands from the host and/or controller. For example, control circuitry 620 may have sufficient processing resources to perform arithmetic and/or logical operations on bit strings stored in memory resource 624 without receiving additional commands from circuitry external to control circuitry 620. s and/or instructions.

Logic circuitry 622 may be an arithmetic logic unit (ALU), state machine, sequencer, controller, instruction set architecture (ISA), or other type of control circuitry. As described above, the ALU performs operations such as those described above (e.g., arithmetic operations, logical operations, bitwise operations, etc.) on integer binary numbers, such as bit strings in positive format. It may include circuitry to perform. An instruction set architecture (ISA) may include a reduced instruction set computing (RISC) device. In embodiments where logic circuitry 622 includes a RISC device, the RISC device may include processing resources that may employ an instruction set architecture (ISA), such as a RISC-V ISA, although embodiments It is not limited to ISAs and other processing devices and/or ISAs may be used.

In some embodiments, logic circuitry 622 may be configured to execute instructions (eg, instructions stored in INSTR 625 portion of memory resource 624) to perform the above operations. For example, logic circuitry 624 has processing resources sufficient to enable it to perform arithmetic and/or logical operations on data received by control circuitry 620 (e.g., on bit strings). .

When arithmetic and/or logic operation(s) are performed by logic circuitry 622, the resulting bit strings are stored in memory resource 624 and/or a memory array (eg, herein, the neuromorphic data shown in FIG. 2A). may be stored in the memory array 230 . Stored result bit strings may be addressed such that they are accessible for performance of operations. For example, bit strings may be stored at specific physical addresses (which may have corresponding logical addresses) in memory resource 624 and/or a memory array such that the bit strings may be accessed in performing operations. there is.

In some embodiments, memory resource 624 may be a memory resource such as random access memory (eg, RAM, SRAM, etc.). However, embodiments are not so limited, and memory resource 624 may include various registers, caches, buffers, and/or memory arrays (eg, DRAM arrays such as 1T1C, 2T2C, 3T, etc.). can do. Memory resource 624 may be, for example herein, a host such as host 102/202 shown in FIGS. 1 and 2A, and/or a memory such as neuromorphic memory array 230 shown in FIG. 2A. It may be configured to receive a bit string (eg, a bit string in positive format) from the array. In some embodiments, memory resource 638 may have a size of approximately 256 kilobytes (KB), although embodiments are not limited to this particular size, and memory resource 624 may have a size greater than or less than 256 KB. can have

Memory resources 624 may be partitioned into one or more addressable memory regions. As shown in FIG. 6, memory resource 624 may be partitioned into addressable memory areas so that various types of data may be stored therein. For example, one or more memory areas may store instructions ("INSTR") 625 used by memory resource 624 and/or one or more memory areas may store data 626-1, ..., 626-N) (e.g., data such as bit strings retrieved from the host and/or a memory array), and/or one or more memory areas may be local memory ("LOCAL MEM") ( 628) can serve as a part. Although twenty distinct memory regions are shown in FIG. 6, it will be appreciated that the memory resource 624 may be partitioned into any number of distinct memory regions.

As noted above, the bit string(s) may represent messages and/or commands generated by a host, a controller (e.g., controller 210 shown herein in FIG. 2A), or logic circuitry 622. In response, it can be retrieved from the host and/or memory array. In some embodiments, commands and/or messages may be processed by logic circuitry 622. Once the bit string(s) are received by control circuitry 620 and stored in memory resource 624, they may be processed by logic circuitry 622. Processing the bit string(s) by logic circuitry 622 may include performing arithmetic operations and/or logical operations on the received bit string.

In a non-limiting neural network training application, control circuitry 620 may receive a floating analog bit string converted from an 8-bit position with es = 0. In contrast to some approaches that use an 8-bit positive bit string with es = 0, an analog bit string can provide faster neural network training results than an 8-bit positive bit string.

7 is a flow diagram illustrating an exemplary method 770 for neuromorphic operations on positions in accordance with multiple embodiments of the present disclosure. At block 772 , method 770 may include receiving data values at the neuron element of the memory array from the multiplexer. A data value may include a bit string in a format that supports arithmetic operations with a particular level of precision. The format may be a positive format. Also, the format may include mantissa, regime, sign, and exponent. The memory array may be similar to the memory array ( 130 shown in FIG. 1 and 230 shown in FIG. 2A ).

At block 774, method 770 may include performing neuromorphic operations on the data values at the neuron component. The neuron component may be similar to the neuron component ( 125 in FIG. 1 , 225 in FIG. 2A , and 525 in FIGS. 5A-5C ).

At block 776, the method 770 may include performing a multiply-accumulate (MAC) operation on the neuron component to generate a MAC resultant value. In some embodiments, performing the operation may include performing a neuromorphic operation on data written to a memory cell. In some examples, performance of an operation on data occurs in a shorter amount of time or in fewer sub-operations than if the operation were performed on the same data represented in the first format. In some embodiments, method 770 may further include performing a second MAC operation on the MAC result value to generate an additional MAC result value.

At block 778, method 770 provides the MAC result value to a bit string register in the neuron component. and generating additional data in a second format by performing an operation using the data written in the memory cell. Method 770 can further include sending the MAC result value to a device external to the memory device. A device external to the memory device may be a host.

In some embodiments, method 770 further comprises performing an additional neuromorphic operation on an additional data value, the additional data value being related to the data value, in the additional neuron component to generate an additional MAC result value. can include The method may further include providing an additional MAC result value to an additional bit string register in the additional neuron element, and providing an additional MAC result value to an additional bit string register in the additional neuron element. In some embodiments, combining the MAC result value and the additional MAC result value may increase the precision of the neuron component and the result of the additional neuron component.

In some embodiments, method 770 may further include performing a plurality of MAC operations within each of a plurality of individual neuronal elements. A quantity of the plurality of individual neuron elements may correspond to a precision of data values stored across a plurality of individual bit string registers within each of the plurality of individual neuron elements. Data values stored across multiple individual bit string registers can be combined to create larger values resulting in precision. In some embodiments, method 770 may further include performing at least a portion of the MAC operation in an internal ALU within the neuron component.

Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may be substituted for the specific embodiments presented. This disclosure is intended to cover adaptations or variations of one or more embodiments of the disclosure. It should be understood that the foregoing description has been made in an exemplary manner and not in a restrictive manner. Combinations of the above embodiments, and other embodiments not specifically described herein, will become apparent to those skilled in the art upon review of the above description. The scope of one or more embodiments of the present disclosure includes other applications in which the structures and processes described above are used. Accordingly, the scope of one or more embodiments of the present disclosure should be determined with reference to the appended claims, along with the full scope of equivalents accorded to those claims.

In the foregoing specifics for practicing the invention, several features are grouped together in an embodiment to simplify the present disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of this disclosure must use more features than are expressly recited in each claim. More precisely, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Accordingly, the following claims are hereby incorporated into the specific content to practice the invention, with each claim standing alone as a separate embodiment.

Claims (20)

As a device,
A memory array comprising:
a plurality of memory cells configured to store data comprising a plurality of bit strings; and
and a processing device residing on the memory array and configured to perform neuromorphic operations using at least one bit string of the plurality of bit strings in an input layer of the neuron component. device, which does. The apparatus of claim 1, wherein the plurality of bit strings are in a format supporting arithmetic operations with different levels of precision, respectively. 3. The apparatus of claim 2, wherein the format supporting the arithmetic operations is a universal number format. 3. The apparatus of claim 2, wherein the format supporting the arithmetic operation is a Type III universal number format or a posit format. 3. The apparatus of claim 2, wherein the format supporting the arithmetic operations includes a mantissa, sign, regime, and exponent part. 6. The neuronal component according to any one of claims 1 to 5, wherein:
an internal ALU component configured to perform at least some of the MAC operations within the neuron component;
accumulator; and
contains a bit string register;
wherein the bit string register is configured to determine a particular level of precision. 7. The apparatus of claim 6, wherein the internal ALU component is configured to perform MAC operations that are performed with a specific frequency or performed with a specific number of times. According to any one of claims 1 to 5,
the neuromorphic operations include neural network operations or machine learning operations;
the neuron component is configured to transmit an output from a result of performing at least one of the neuromorphic operations to external circuitry;
wherein the external circuitry is an arithmetic logic unit (ALU). As a method,
receiving data values at the neuron element of the memory array from the multiplexer;
Using a processing device of the neuron component, performing a neuromorphic operation at the neuron component on the data value including at least one bit string of a plurality of bit strings in an input layer of the neuron component It includes the step of performing the neuromorphic operation:
Generating a MAC result value by performing a multiply accumulate (MAC) operation in the neuron component; and
and providing the MAC result value to a bit string register in the neuron component. 10. The method of claim 9, further comprising generating an additional MAC result value by performing a second MAC operation on the MAC result value. According to claim 9,
performing an additional neuromorphic operation on an additional data value in an additional neuron component, the additional data value being related to the data value, to generate an additional MAC result value; and
providing the additional MAC result value to an additional bit string register in the additional neuron component; and
further comprising combining the MAC result value and the additional MAC result value. 12. The method of claim 11, wherein combining the MAC result value and the additional MAC result value comprises increasing precision of the neuron component and the result of the additional neuron component. 12. The method of claim 11, further comprising performing a plurality of MAC operations within a plurality of individual neuronal elements, respectively;
the quantity of the plurality of individual neuron elements corresponds to a precision of data values stored across a plurality of individual bit string registers within each of the plurality of individual neuron elements;
wherein the data values stored across the plurality of individual bit string registers are combined to produce a larger value resulting in the precision. 14. The method of any one of claims 9-13, wherein at least part of the MAC operations are performed in an internal ALU within the neuron component. As a system,
a plurality of peripheral sense amplifiers (PSAs);
a plurality of neuronal components coupled to the plurality of PSAs through a plurality of multiplexers, each of the plurality of neuronal components including neuronal circuitry; and
a plurality of arithmetic logic units (ALUs) coupled to each of a plurality of discrete neuronal elements;
The plurality of neuronal components use individual neuronal circuitry to:
receive a data value from the PSAs via the plurality of multiplexers, the data value comprising at least one bit string;
perform neuromorphic operations on the data values;
and output a result of performing the neuromorphic operation, wherein the output indicates a degree of neural network learning. 16. The method of claim 15, wherein each of the plurality of neuronal components:
multiplier;
accumulator;
an internal arithmetic logic unit (ALU); and
A system comprising a bit string register. According to claim 16,
the neuromorphic operation is performed within one of the plurality of neuronal components using separate multipliers, accumulators, and internal ALUs;
each bit string register is configured to be used for storing an overflow of the output as a positive value;
wherein the neuron circuitry is configured to cause the overflow of the output to be sent to the internal ALU to perform an additional neuromorphic operation in response to a threshold number of neuromorphic operations being performed. 18. The system of any one of claims 15-17, wherein the neuron circuitry is configured to send the output to an external ALU, and the external ALU is configured to perform additional operations on the output. 19. The system of claim 18, wherein the external ALU is configured to perform a RELU operation or a sigma operation on the output. 19. The system of claim 18, wherein the neuron circuitry is configured to direct the output to the external ALU in response to a threshold number of neuromorphic operations being performed.

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