KR20230020904A - Pixel array accumulating photocharges in each unit frame, and image sensor including the same - Google Patents

Abstract

As a pixel array including a plurality of pixels, each of the plurality of pixels comprising: a photo diode configured to generate photo charges in a frame including a plurality of unit frames; a floating diffusion node configured to receive photo charges; a first storage capacitor configured to receive and store first photo charges generated by the photo diode during a first unit accumulation time in each of a plurality of unit frames through the floating diffusion node; and a second storage capacitor configured to receive and store second photo charges generated by the photo diode during a second unit accumulation time in each of the plurality of unit frames through the floating diffusion node. Accordingly, the present invention can generate an HDR image and perform the LFM function at the same time.

Description

A pixel array accumulating photoelectric charges per unit frame and an image sensor including the same

The technical idea of the present disclosure relates to an image sensor, and more particularly, to an image sensor including a pixel array accumulating photocharges for each unit frame and the same.

An image sensor is a device that captures a two-dimensional or three-dimensional image of an object. An image sensor generates an image of an object using a photoelectric conversion element that reacts according to the intensity of light reflected from the object. Recently, with the development of the computer and communication industries, demand for image sensors with improved performance has increased in various electronic devices such as digital cameras, camcorders, PCS (Personal Communication System), game devices, security cameras, medical micro cameras, and mobile phones. are doing

The image sensor may generate a high dynamic range (HDR) image by generating image data of high or low intensity by receiving photocharges corresponding to a plurality of exposure times.

An object to be solved by the technical concept of the present disclosure is to provide an image sensor that generates an HDR image from photocharges generated in at least one photodiode and simultaneously performs an LED Flicker Mitigation (LFM) function.

According to one aspect of the technical idea of the present disclosure, a pixel array including a plurality of pixels, wherein each of the plurality of pixels receives photocharges from a photodiode configured to generate photocharges in a frame including a plurality of unit frames. a floating diffusion node configured to receive and store first photocharges generated by the photodiode during a first unit accumulation time in each of a plurality of unit frames through the floating diffusion node; and a plurality of unit frames. and a second storage capacitor configured to receive and store second photocharges generated by the photodiode during a second unit accumulation time through a floating diffusion node in each of the first storage capacitors.

An image sensor according to one aspect of the technical idea of the present disclosure may include a pixel array including a plurality of pixels, and each of the plurality of pixels is a first unit accumulation in each of a plurality of unit frames included in the frame. A first photodiode configured to generate first photo-charges during time, in each of a plurality of unit frames, to generate second photo-charges during a second unit accumulation time and generate third photo-charges during a third unit accumulation time configured second photodiode, at least one floating diffusion node configured to receive at least one of first photocharges, second photocharges, and third photocharges, and receive and store second photocharges through at least one floating diffusion node and a second storage capacitor configured to receive and store third photocharges through at least one floating diffusion node.

The technical concept of the present disclosure is that an image sensor generates photocharges in at least one photodiode during an exposure time, and accumulates only the photocharges generated during a unit accumulation time, which is a partial time interval among unit frames divided into a plurality of units with respect to the entire frame. By doing so, it is possible to perform the LFM function at the same time as generating the HDR image.

Effects obtainable in the exemplary embodiments of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned are common knowledge in the art to which exemplary embodiments of the present disclosure belong from the following description. can be clearly derived and understood by those who have That is, unintended effects according to the implementation of the exemplary embodiments of the present disclosure may also be derived by those skilled in the art from the exemplary embodiments of the present disclosure.

1 is a block diagram showing a schematic configuration of an image sensor according to an exemplary embodiment of the present disclosure.
2 is a graph illustrating an example of generating image data for an LED light source by accumulating light charges for each of a plurality of unit frames according to an embodiment.
3A to 3E are circuit diagrams illustrating configurations of pixels according to a plurality of exemplary embodiments.
4 is a graph illustrating levels of pixel control signals generated for each unit frame in an accumulation step of one frame according to an exemplary embodiment.
5A is a diagram illustrating an example in which photocharges are accommodated in a floating diffusion node according to an embodiment, and FIG. 5B is a diagram illustrating an example in which photocharges received in a floating diffusion node are stored in a storage capacitor according to an embodiment. am.
FIG. 6 is a graph illustrating levels of signals generated when an image sensor reads accumulated photocharges after the accumulation step of FIG. 4 , according to an exemplary embodiment.
7 is a circuit diagram illustrating a configuration of a pixel having one photodiode according to another exemplary embodiment.
FIG. 8 is a graph illustrating levels of pixel control signals generated for each unit frame according to the exemplary embodiment of FIG. 7 .
9 is a block diagram illustrating an image sensor according to another exemplary embodiment.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a schematic configuration of an image sensor according to an exemplary embodiment of the present disclosure.

The pixel PX described in FIG. 1 is for explaining an example of a pixel including a capacitor therein, and is a digital pixel capable of performing a global shutter function.

The image sensor 10 may be mounted in an electronic device having an image or light sensing function. For example, the image sensor 10 may be a camera, a smart phone, a wearable device, the Internet of Things (IoT), a tablet PC (Personal Computer), a PDA (Personal Digital Assistant), a PMP (portable multimedia player), It can be mounted on an electronic device such as a navigation device. In addition, the image sensor 10 may be mounted on electronic devices provided as parts, such as vehicles, furniture, manufacturing facilities, doors, and various measuring devices.

The image sensor 10 includes a pixel array 100, a row driver 200, a ramp generator 300, a controller 400, a digital signal processor 500, and an interface circuit 600. can do. The pixel array 100 may include a plurality of pixels PX, and each of the plurality of pixels PX senses an external light signal and generates a digital output signal DOUT corresponding to the sensed light signal. It can be configured to output.

The plurality of pixels PX may detect an optical signal by using a light sensing element and convert the optical signal into a digital output signal DOUT, which is an electrical signal. Each of the plurality of pixels PX may sense light in a specific spectrum range. For example, the plurality of pixels PX include a red pixel for converting light in a red spectral range into an electrical signal, a green pixel for converting light in a green spectral range into an electrical signal, and a blue pixel for converting light in a green spectral range into an electrical signal. ) may include a blue pixel for converting light in a spectral range into an electrical signal. A color filter for transmitting light in a specific spectral range may be disposed above each of the plurality of pixels PX, and a microlens for condensing light may be disposed.

The pixel PX may include an optical detection circuit 110 , an analog-to-digital converter (ADC) 120 , and a memory 130 . In some embodiments, the pixel array 100 may include a first semiconductor substrate and a second semiconductor substrate that are stacked. For example, the photodetector circuit 110 of the pixel PX may be formed on a first semiconductor substrate, and the ADC 120 converting a signal generated by the photodetector circuit 110 into a digital signal may be configured on the first semiconductor substrate. It may be formed on a second semiconductor substrate different from the substrate. The photodetection circuits formed on the first semiconductor substrate may be respectively connected to the ADCs formed on the second semiconductor substrate through an electrical connection means so that detection signals may be transmitted. In some embodiments, the electrical connection means may include Through Silicon Via (TSV) penetrating the first semiconductor substrate and/or a metal-to-metal connection structure respectively formed on the first semiconductor substrate and the second semiconductor substrate. In some embodiments, memory 130 may be formed in the second semiconductor substrate. The photodetection circuit 110 may include a photodetection element and convert an optical signal sensed from the outside into an electrical signal, that is, a detection signal that is an analog signal. For example, the photo-sensing device may include a photo diode, a photo transistor, a port gate, or a pinned photodiode. The detection signal may include a detection signal according to a reset operation of the pixel PX and may include a detection signal according to a light detection operation of the pixel PX.

The ADC 120 may convert the detection signal output from the photodetection circuit 110 into a digital signal. In some embodiments, the ADC 120 may convert the detection signal into a digital signal by comparing the detection signal with the ramp signal RAMP. The memory 130 may store the converted digital signal. The memory 130 may output the digital output signal DOUT to the digital signal processing unit 500 .

The image sensor 10 according to the present disclosure may accumulate photocharges during a unit accumulation time of a predetermined ratio of a unit frame for each of a plurality of unit frames divided into one frame, and may accumulate photocharges during a plurality of unit accumulation times. Image data can be generated based on the photoelectric charge. In this case, the image sensor 10 according to an exemplary embodiment may generate an HDR image by accumulating charges for unit accumulation times having different time lengths in one unit frame.

The pixel driver 200 may output control signals CTRL for controlling the plurality of pixels PX included in the pixel array 100 . In response to the control signals CTRL generated from the pixel driver 200, each of the plurality of pixels PX generates a detection signal, converts the detection signal into a digital signal using the ramp signal RAMP, A digital signal may be stored, and the stored digital signal may be output as a digital output signal DOUT.

The ramp signal generator 300 may generate and output the ramp signal RAMP to the pixel array 100 . The ramp signal RAMP is provided to the pixel array 100 (eg, the ADC 120 of the pixel PX) and may be used as a reference signal to be compared with the detection signal. In an exemplary embodiment, the ramp signal RAMP may be a constant decreasing or increasing signal (eg, an increasing/decreasing signal having a single and/or linear slope).

The controller 400 may control overall operations of the image sensor 10 . For example, the controller 400 may be configured based on control information received from an external device (eg, an image signal processor (ISP), an application processor (AP), etc.) through the interface circuit 600. operation timing of the image sensor 10 may be controlled by using the control signal CTRL and the ramp signal RAMP based on timing signals provided from the controller 400. ) can be created.

The digital signal processing unit 500 may perform digital signal processing on the digital output signals DOUT received from the pixel array 100 and provide final image data ID to an external device. The digital output signal DOUT may include a reset value according to a reset operation of the pixel PX and may include an image signal value according to a light detection operation of the pixel PX. The digital signal processing unit 500 may determine a final digital value corresponding to the light signal sensed by one pixel PX by performing an operation on the reset value and the image signal value. Final image data ID may be generated by combining the final digital values determined in each of the plurality of pixels PX. That is, the correlated double sampling operation may be implemented through the digital output signal DOUT generated by the digital signal processing operation of the digital signal processing unit 500 and the operation of the ADC 120 included in the pixel PX.

The interface circuit 600 may be configured to receive control information from an external device or output final image data ID. In an exemplary embodiment, the interface circuit 600 may exchange the above-described information with an external device based on a predetermined protocol.

FIG. 2 is a graph illustrating an example of generating image data ID for an LED light source by accumulating light charges for each of a plurality of unit frames according to an embodiment.

Referring to FIG. 2 , the image sensor 10 of the present disclosure may accumulate photocharges for a plurality of unit accumulation times to generate image data ID for an LED light source. The LED light source may be turned on and off at regular intervals, and exemplarily, turned on and off at a frequency of 90 Hz or higher. At this time, the period in which the LED light source is turned on for energy efficiency may be shorter than the period in which the LED light source is turned off. In some embodiments, the period in which the LED light source is turned off may be longer than the period in which the LED light source is turned on. Illustratively, when turned on and off at a period of 10 ms, the period in which the LED light source is turned on may be about 1 ms.

When the image sensor 10 acquires an HDR image in a multi-exposure method according to a comparative embodiment, the photodiode may generate photoelectric charges during a plurality of exposure times in one frame. For example, the photodiode may generate light charges for a short exposure time to generate a high-illuminance image, and the photodiode may generate light charges for a long exposure time to generate a low-illuminance image.

Therefore, when the image sensor 10 acquires an HDR image of the LED light source in a multiple exposure method, a short exposure time for generating a high-illuminance image may be included in a period in which the LED light source is turned off, and at this time, the LED light source will not be able to produce high-contrast images.

A photodiode of the present disclosure generates photocharges corresponding to a frame, and a floating diffusion node connected to the photodiode generates photocharges generated during a unit accumulation time corresponding to a partial time interval among a plurality of unit frames for one frame. can accommodate At this time, the length of the unit frame may be formed shorter than the period in which the LED light source is turned on. Accordingly, since the image sensor 10 may generate light charges corresponding to when the LED light source is turned on, an HDR image may be appropriately generated from the LED light source that flickers periodically.

Hereinafter, a circuit configuration for generating an HDR image by the image sensor 10 of the present disclosure will be described.

3A to 3E are circuit diagrams illustrating a configuration of a pixel PX according to a plurality of embodiments.

The embodiment according to FIGS. 3A to 3E is a circuit capable of generating an HDR image for an LED light source by accommodating photocharges generated by a plurality of photodiodes PD1 and PD2 in floating diffusion nodes FD1 and FD2. can be 3A to 3E , examples of generating photocharges by two photodiodes PD1 and PD2 are described, but the number of photodiodes of the present disclosure is not limited thereto.

The light detection circuit 110 of the pixel PX according to FIGS. 3A to 3E may include a first photodiode PD1 and a second photodiode PD2 . According to an embodiment, the sensitivity of the first photodiode PD1 and the sensitivity of the second photodiode PD2 may be different from each other in order to generate an HDR image. It can be determined by size. The first photodiode PD1 may be a high-sensitivity photodiode for generating a low-illuminance image, and the second photodiode PD2 may be a low-sensitivity photodiode for generating a high-illuminance image.

Referring to FIG. 3A , the photodetection circuit 110a may include a first transfer transistor TX1 and a second transfer transistor TX2. When activated, the first transfer transistor TX1 connected to the first photodiode PD1 may transfer photocharges generated in the first photodiode PD1 to the first floating diffusion node FD1. When the second transfer transistor TX2 is connected to the second photodiode PD2 and activated, it may transfer photocharges generated by the second photodiode PD2 to the second floating diffusion node FD2.

The first floating diffusion node FD1 and the second floating diffusion node FD2 may include a first capacitor C _FD1 and a second capacitor C _FD2 , respectively. The first capacitor C _FD1 and the second capacitor C _FD2 may receive photocharges transferred from the first photodiode PD1 and the second photodiode PD2 , respectively. In some embodiments, each of the first capacitor C _FD1 and the second capacitor C _FD2 may be a parasitic capacitor having a parasitic capacitance.

The first floating diffusion node FD1 and the second floating diffusion node FD2 of the photodetection circuit 110a may be connected to each other, and the first floating diffusion node FD1 and the second floating diffusion node FD2 share charge. It can be connected to transistor CSX. As the charge sharing transistor CSX is activated in each unit frame, charges may be shared between the first capacitor C _FD1 and the second capacitor C _FD2 with the storage capacitor Cs.

The photodetection circuit 110a may further include a reset transistor RX, and when activated with the reset transistor RX, the first floating diffusion node FD1 and the second floating diffusion node FD2 may be reset. . According to an embodiment, after the charge is shared by the storage capacitor Cs, the charge of the first floating diffusion node FD1 and the second floating diffusion node FD2 is discharged by the reset transistor RX to generate the first floating diffusion node FD1 and the second floating diffusion node FD2. The diffusion node FD1 and the second floating diffusion node FD2 may accommodate photocharges generated in subsequent unit frames.

The second transfer transistor TX2 according to an exemplary embodiment may transmit photocharges generated in the second photodiode PD2 to the second floating diffusion node FD2 in every unit frame shown in FIG. 2 and in every unit frame. Photoelectric charges generated in the second photodiode PD2 by the activated charge sharing transistor CSX may be accumulated with the storage capacitor Cs. The first transfer transistor TX1 is activated in a read step performed for each frame and provides photocharges generated in the first photodiode PD1 to the first floating diffusion node FD1 and the second floating diffusion node FD2. can do.

That is, photocharges generated in the second photodiode PD2 in the accumulation step may be stored in the storage capacitor Cs through the second floating diffusion node FD2, and in the read step after the accumulation step, the first photodiode Photocharges generated in (PD1) may be read through the first floating diffusion node (FD1). Also, in the reading step, photocharges generated by the second photodiode stored in the storage capacitor Cs may be read. Accordingly, the photocharges generated in the first photodiode PD1 and the photocharges generated in the second photodiode PD2 may be independently read.

In the reading step, the source follower SF may transmit a detection signal to the output node according to the potential of photocharges accommodated in the floating diffusion node (eg, FD1 and/or FD2). The source follower SF may amplify a voltage change of a floating diffusion node (eg, FD1 and/or FD2). The source follower SF may be connected to an output node and provide a current path through which current of the source follower SF flows according to a selection control signal output from the pixel driver 200 . The selection transistor may control a signal (eg, voltage change) amplified by the source follower SF to ADc based on the logic level of the selection signal.

The ADC may be, for example, a single slope ADC. The ADC may include a comparator (COMP), a first capacitor, and a second capacitor. The comparator COMP may include a differential amplifier, a first input terminal of the comparator COMP receives a detection signal as a first input signal through a first capacitor, and a second input terminal of the comparator COMP receives a second input signal. The ramp signal RAMP as a signal may be received through the second capacitor. The comparator COMP may compare the detection signal received through the capacitors and the ramp signal RAMP, and output a comparison result signal.

The image sensor 10 of the present disclosure may generate a digital signal corresponding to the light signal of the first photodiode PD1 and a digital signal corresponding to the light signal of the second photodiode PD2 according to the comparison result signal. and image data ID may be generated by combining the generated digital signals. At this time, the image sensor 10 may generate the image data ID of the first illuminance based on the comparison result signal output by the first photodiode PD1, and generate the image data ID of the second photodiode PD2. Image data ID of the second illuminance may be generated based on the output comparison result signal.

Referring to FIG. 3B , the photodetection circuit 110b may further include an overflow transistor OFX in the photodetection circuit 110a of FIG. 3A. The overflow transistor OFX may be connected to the first photodiode PD1 and, when activated, may discharge some of the photocharges generated in the first photodiode PD1.

Referring to FIG. 3C , the photodetection circuit 110c may further include a dual conversion transistor DCX in the photodetection circuit 110a of FIG. 3a. According to one embodiment, the dual conversion transistor (DCX) may also be referred to as a gain control transistor. When the dual conversion transistor DCX is activated (eg, by the dual conversion signal DCS), the first floating diffusion node FD1 and the second floating diffusion node FD2 may be connected. When the dual conversion transistor DCX is inactivated, the photocharges generated in the first photodiode PD1 can be transferred only to the first capacitor C _FD1 , and the photocharges generated in the second photodiode PD2 are transferred to the second capacitor. (C _FD2 ) can only be transmitted.

According to an exemplary embodiment, when the photoelectric charge generated in the first photodiode PD1 is read, when the dual conversion transistor DCX is inactivated, the first floating diffusion node FD1 is connected to the first photodiode PD1. Photocharges may be transferred, and a voltage level formed by the first capacitor C _FD1 may be input to the gate of the source follower SF. On the other hand, when the dual conversion transistor DCX is activated, the photoelectric charge of the first photodiode PD1 can be transferred to the first floating diffusion node FD1 and the second floating diffusion node FD2, and the second floating diffusion node connected in series can be transferred. A voltage level formed by the first capacitor C _FD1 and the second capacitor C _FD2 may be input to the gate of the source follower SF. Since the capacitances of the first capacitor C _FD1 and the second capacitor C _FD2 connected in parallel are greater than the capacitance of the first capacitor C _FD1 , when the dual conversion transistor DCX is activated, compared to when the dual conversion transistor DCX is inactivated, A lower level of voltage may be formed. That is, depending on whether the dual conversion transistor DCX is activated, the image sensor 10 may adjust the conversion gain of photocharges.

Referring to FIG. 3D , the photodetection circuit 110d may include a plurality of storage capacitors Cs (eg, Cs1, Cs2, etc.). Although FIG. 3D shows two storage capacitors Cs1 and Cs2, in some embodiments, the plurality of storage capacitors Cs may include three or more storage capacitors. According to an embodiment, the image sensor 10 may include unit accumulation times allocated as a plurality of different time lengths for each unit frame, and during the different unit accumulation times, the second photodiode PD2 generates Photoelectric charges may be stored in different storage capacitors Cs. For example, photocharges accumulated during the first unit accumulation time may be stored in the first storage capacitor Cs1, and photocharges accumulated during the second unit accumulation time may be stored in the second storage capacitor Cs2. A method of storing photocharges in the plurality of storage capacitors Cs by the photodetector circuit 110d according to the embodiment of FIG. 3D will be described later with reference to FIG. 8 .

Referring to FIG. 3E , the photodetector circuit 110e may further include a dual conversion transistor DCX than the photodetector circuit 110d of FIG. 3d. When the dual conversion transistor DCX is activated, the first floating diffusion node FD1 and the second floating diffusion node FD2 may be connected. When the dual conversion transistor DCX is inactivated, the photocharges generated in the first photodiode PD1 can be transferred only to the first capacitor C _FD1 connected to the first floating diffusion FD1, and the second photodiode PD2 ) may be transferred only to the second capacitor C _FD2 connected to the second floating diffusion FD2. In the pixel circuit of FIG. 3E, during the effective integration time (EIT) during the integration step, the first photodiode PD1 can generate photocharges, and the second photodiode PD2 can generate a plurality of sub-subs divided from EIT. Charge generated during each of the EITs may be stored in a plurality of storage capacitors. In the reading step, photocharges generated in the first photodiode PD1 may be read, and photocharges generated in the second photodiode PD2 may be read through charges stored in storage capacitors. A detailed description of the reading step will be described later with reference to FIG. 6 .

4 is a graph illustrating levels of pixel control signals generated for each unit frame in an accumulation step of one frame according to an exemplary embodiment.

Referring to FIG. 4 , the accumulation step of one frame may consist of a plurality of unit frames, and the image sensor 10 reads the photocharges accumulated during the plurality of unit frames in a reading step subsequent to the accumulation step. By doing so, image data (ID) can be generated. The accumulation step of the image sensor 10 will be described with reference to FIGS. 4 to 5B and the read step of the image sensor 10 will be described with reference to FIG. 6 .

According to an embodiment, when the image sensor 10 generates photocharges through a plurality of photodiodes, in the accumulation step, some photodiodes transmit photocharges to a floating diffusion node every unit frame and store the photocharges in a storage capacitor. , the remaining photodiodes may generate and accumulate photocharges for a plurality of unit frames. The generated photocharges may be transferred to the floating diffusion node in the reading step. 3A to 3E, the first photodiode PD1 may transmit photocharges generated during a plurality of unit frames in the accumulation step to the first floating diffusion node FD1 in the read step, and the second photodiode PD1 may The diode PD2 may transmit photocharges generated for each unit frame in the accumulation step to the second floating diffusion node FD2 and store them in a storage capacitor. However, the number of photodiodes in the embodiments of the present disclosure is not limited thereto.

According to an exemplary embodiment, a plurality of photodiodes may generate photocharges for the same exposure time during each frame. Hereinafter, a case of generating photocharges for a time corresponding to an entire frame will be described, but this embodiment The example exposure time is not limited thereto, and may also include a case in which photocharges are generated during a portion of the time corresponding to the frame.

The image sensor 10 may start an accumulation operation for a unit accumulation time INT by resetting photocharges generated in the photodiode. The photocharges generated in the photodiode before the unit accumulation time INT may be received in the floating diffusion node by activating the transfer transistor, and then, when the reset transistor RX is activated, the photocharges received in the floating diffusion node may be reset. can Illustratively, referring to FIGS. 3A to 4 , when the second transmission signal TS2 of a logic high level is input to the second transmission transistor TX2, photocharges generated in the second photodiode PD2 are transferred to the second transmission transistor TX2. After that, when the logic high level reset signal RS is input to the reset transistor RX, photocharges generated before the unit accumulation time INT can be reset. there is.

Thereafter, the photodiode may generate and accumulate photocharges again by inactivating the transfer transistor, and when the transfer transistor is activated, the photocharges generated during the unit accumulation time INT may be transferred to the floating diffusion node. At this time, the reset transistor RX connected to the floating diffusion node is inactivated so that the floating diffusion node can accommodate photocharges generated during the unit accumulation time INT.

For example, referring to FIGS. 3A to 4 , when the second transmission signal TS2 transitions to a logic low level, the second photodiode PD2 can generate and accumulate photocharges for a unit accumulation time INT. , when the second transmission signal TS2 transitions to the logic high level again, photocharges generated during the unit accumulation time INT may be transferred to the second floating diffusion node FD2.

According to an embodiment, the image sensor 10 may store the photocharges accumulated during the unit accumulation time INT in the storage capacitor Cs by activating the charge sharing transistor CSX for each unit frame. A time point at which the charge sharing transistor CSX is activated may be an arbitrary time point during a time period during which the reset transistor RX is deactivated. The point at which the charge sharing transistor CSX is inactivated is at any interval between the end point of the unit accumulation time INT after the charge sharing transistor CSX is activated and the point at which the reset transistor RX is activated. may be a point in time.

3A to 4 , as the charge sharing signal CSS transitions to a logic high level after the unit accumulation time INT, the image sensor 10 operates at a floating diffusion node during the unit accumulation time INT. The received photocharge may be stored in the storage capacitor Cs. Thereafter, when the charge sharing signal CSS transitions to the logic low level and the reset signal RS transitions to the logic high level, the photocharges of the floating diffusion node are reset so that the accumulation operation for the next unit frame can be performed. there is.

5A is a diagram illustrating an example in which photocharges are accumulated in a floating diffusion node according to an embodiment, and FIG. 5B is an example in which photocharges accumulated in a floating diffusion node are stored in a storage capacitor Cs according to an embodiment. It is a drawing showing

Referring to FIGS. 3A to 3D and FIGS. 5A and 5B , a potential barrier is formed according to voltage levels input to gates of the transfer transistor TX, the charge sharing transistor CSX, and the reset transistor RX. can be controlled For example, when a high-level voltage is input to a gate of a transistor, a potential barrier of the transistor is lowered, and charges trapped in a node of a high energy level may be transferred to a low energy level. On the other hand, when a low-level voltage is input to the gate of the transistor, the potential barrier of the transistor becomes high and charges may be trapped in each node.

Referring to FIG. 5A , the photodiode of the image sensor 10 may generate photoelectric charges in the first time period T1 . The first time period T1 may correspond to the unit accumulation time INT, and the image sensor 10 may reset photocharges generated in the photodiode prior to the unit accumulation time INT. When the transfer transistor TX is inactivated, charges may be generated in the photodiode by a potential barrier formed in the transfer transistor TX.

When the transfer transistor TX is activated in the second time interval T2 , a potential barrier of the transfer transistor TX is lowered so that charges can be transferred from the photodiode to the floating diffusion node. In this case, the charge sharing transistor CSX is inactivated, and the potential barrier of the charge sharing transistor CSX is increased so that the photocharges generated in the unit accumulation time INT can be accommodated in the floating diffusion node.

Referring to FIG. 5B , the transfer transistor TX is inactivated and the charge sharing transistor CSX is activated in the third time interval T3 so that the charge received in the floating diffusion node can be shared with the storage capacitor Cs. In this case, the energy level of the floating diffusion node and the energy level of the storage capacitor Cs may be the same, and the capacitance of the storage capacitor Cs may be greater than the capacitance of the parasitic capacitor of the floating diffusion node.

In the fourth time period T4 , the charge sharing transistor CSX may be inactivated, and a potential barrier may be formed between the storage capacitor Cs and the floating diffusion node. According to an embodiment, the amount of charge stored in each capacitor may be determined according to a ratio between the capacitance of the storage capacitor Cs and the capacitance of the parasitic capacitor, and when the capacitance of the storage capacitor Cs is greater than the capacitance of the parasitic capacitor, the storage capacitor More charge can be stored in (Cs).

Charges stored in the floating diffusion node may be reset by activating the reset transistor RX in the fifth time interval T5 . At this time, since the charge sharing transistor CSX is inactivated, the charge stored in the storage capacitor Cs is not reset, and only the charge stored in the floating diffusion node can be reset.

Some of the photocharges generated in the unit accumulation time INT for each unit frame may be shared and stored in the storage capacitor Cs, and after the charges are shared in the storage capacitor Cs, the floating diffusion node is reset to reset the image sensor ( 10) may accumulate and store photocharges generated during a plurality of unit frames. Illustratively, referring to FIG. 5A , the photoelectric charges generated during the first time period T1 in the first unit frame UF1 may be shared and preserved by the storage capacitor Cs. In each subsequent unit frame, the image sensor 10 may add and store the photoelectric charge generated in the photodiode to the charge stored in the previous unit frame. Accordingly, the image sensor 10 accumulates charges generated during the unit accumulation time INT in each unit frame from the first unit frame UF1 to the last unit frame (eg, the tenth unit frame UF10). and can be saved.

FIG. 6 is a graph illustrating levels of signals generated when the image sensor 10 reads the accumulated photocharges after the accumulation step of FIG. 4 according to an exemplary embodiment.

Referring to FIG. 6 , the image sensor 10 may perform a dual conversion operation on the charge generated and accumulated in the first photodiode PD1 in a sixth time interval T6 during the reading step, and In the time period T7 , charges stored in the second photodiode PD2 corresponding to the unit accumulation time INT of each unit frame may be read. That is, referring to FIGS. 3A to 3E , the image sensor 10 may read the photocharges generated in the first photodiode PD1 in the sixth time period T6 and in the seventh time period T7 The photoelectric charge generated in the second photodiode PD2 can be read from .

Referring to FIGS. 3C and 3E , in the dual conversion operation, the storage gain for photocharges generated in the first photodiode PD1 may be adjusted according to whether the dual conversion transistor DCX is activated. For example, when the dual conversion transistor DCX is activated, the first floating diffusion node FD1 and the second floating diffusion node FD2 are connected to form the first capacitor C _FD1 and the second capacitor C _FD2 . As a result, the accumulation conversion gain can be lowered. On the other hand, when the dual conversion transistor DCX is inactivated, charge is received only in the first floating diffusion node FD1, and thus the storage conversion gain may be increased.

In the sixth time interval T6 , according to FIGS. 3C and 3E , the image sensor 10 may perform a dual conversion operation on photocharges generated in the first photodiode PD1 . When the logic low level reset signal RS and the logic low level dual conversion signal DCS are input to the photodetection circuit 110, the image sensor 10 converts photocharges into electrical signals with a high storage conversion gain. can make it According to an embodiment, in order to perform Correlated Double Sampling (CDS), the image sensor 10 determines the amount of charge received in the first floating diffusion node FD1 after the first floating diffusion node FD1 is reset. After reading (R1), the amount of charge transferred from the first photodiode (PD1) to the first floating diffusion node (FD1) can be read (S1).

When receiving the dual conversion signal DCS transitioned from the logic low level to the logic high level, the photodetection circuit 110 may read the accumulated charge amount with a low storage conversion gain. At this time, the photodetection circuit 110 reads the amount of charge of the first floating diffusion node FD1 (S2) to perform correlated double sampling and reads the amount of charge after the first floating diffusion node FD1 is reset. (R2) can.

In the sixth time interval T6, when the amount of charge accumulated with a high accumulation gain is read, the amount of charge accumulated with a low accumulation gain is read, and the amount of charge is read with a high accumulation gain and a low accumulation gain, correlated double sampling is performed. For this purpose, the amount of charge in the reset state can be read at high and low accumulation gains, respectively. The photodetection circuit 110 may receive a low-level lamp signal to read (R1) and sample the amount of charge in the reset state at a high storage gain, and receive a high-level lamp signal to read (S1) and sample the amount of charge in the exposure state. A ramp signal of can be received. In addition, the photodetection circuit 110 may receive a low-level lamp signal to read (S2) and sample the amount of charge in the exposure state at a low accumulation gain, and to read (R2) and sample the amount of charge in the reset state. A high-level ramp signal can be received.

In the seventh time interval T7 , the image sensor 10 may read the amount of photocharges generated by the second photodiode PD2 stored in the storage capacitor Cs for each unit frame. Referring to FIGS. 3C and 3D , the photodetection circuit 110 detects charges stored in the storage capacitor Cs when receiving the logic high level charge sharing signal CSS and the logic high level dual conversion signal DCS. It may be provided to the first floating diffusion node FD1. To perform correlated double sampling, the image sensor 10 may read the amount of charge before the first floating diffusion node FD1 is reset ( S3 ) and read the amount of charge in the reset state ( R3 ).

The embodiments of FIGS. 3A, 3B, and 3D can sequentially read the amount of charge generated by each photodiode in a readout period without a dual conversion operation. When photocharges are stored in the plurality of storage capacitors Cs according to the embodiment of FIG. 3D , the amount of charge stored in each storage capacitor may be sequentially read in a readout period added after the seventh time period T7.

4 to 6, a method for the image sensor 10 to receive the photocharges generated by the plurality of photodiodes in the accumulation step and sequentially read the photocharges generated by the photodiodes without overlapping. explained. Hereinafter, a method of storing photocharges generated by one photodiode for a plurality of unit accumulation times (INT) in a plurality of storage capacitors (Cs) will be described with reference to FIGS. 7 and 8 .

7 is a circuit diagram illustrating a configuration of a pixel PX having one photodiode PD according to another exemplary embodiment.

Referring to FIG. 7 , the photodetection circuit 110 according to an exemplary embodiment may include one photodiode PD and a floating diffusion node FD. A plurality of storage capacitors (Cs) and a plurality of charge sharing transistors (CSX) may be connected in parallel to the floating diffusion node (FD), and photocharges generated in the photodiode (PD) during different unit accumulation times may have different charges. It can be stored in different storage capacitors Cs through the sharing transistor CSX. Although two storage capacitors are shown in FIG. 7 , in some embodiments, the plurality of storage capacitors Cs may include three or more storage capacitors.

FIG. 8 is a graph illustrating levels of pixel control signals generated for each unit frame according to the exemplary embodiment of FIG. 7 .

According to an embodiment, in the accumulation step, the image sensor 10 generates one photodiode (PD) during at least two unit accumulation times INT1 and INT2 having different lengths in each of a plurality of unit frames divided from one frame. ), the generated photocharges may be stored in the storage capacitors Cs1 and Cs2 corresponding to the unit accumulation times INT1 and INT2, respectively. Illustratively, referring to FIG. 8 , the image sensor 10 may store photocharges generated during the first unit accumulation time INT1 of each unit frame in the first storage capacitor Cs1 and Photoelectric charges generated during the second unit accumulation time INT2 may be stored in the second storage capacitor Cs2. 8, a case in which photocharges are generated at the first unit accumulation time INT1 and the second unit accumulation time INT2 will be described, but the unit accumulation time INT and storage capacitor Cs of the embodiment of the present disclosure will be described. ) is not limited to this number.

The image sensor 10 may start an accumulation operation corresponding to each of the unit accumulation times INT1 and INT2 by resetting photocharges generated in the photodiode PD. The photocharges generated in the photodiode PD before each unit accumulation time can be accommodated in the floating diffusion node FD by activating the transfer transistor TX, and at this time, when the reset transistor RX is activated, the floating diffusion node The photocharges accommodated in (FD) can be reset.

Thereafter, the photodiode PD can generate photocharges again by inactivating the transfer transistor TX, and when the transfer transistor TX is activated again, the photocharges generated during each unit accumulation time INT1 and INT2 It may be transmitted to a floating diffusion node (FD). Before the transfer transistor (TX) is re-activated, the reset transistor (RX) connected to the floating diffusion node (FD) is deactivated so that the floating diffusion node (FD) is connected to the photodiode (PD) for each unit accumulation time (INT1, INT2). It can accommodate the generated photocharge.

Illustratively, referring to FIG. 8 , when the transmission signal TS transitions to a logic low level, the image sensor 10 may generate photoelectric charges during the first unit accumulation time INT1 , and the transmission signal TS ) transitions to the logic high level, photocharges generated during the first unit accumulation time INT1 may be transferred to the floating diffusion node FD.

According to an embodiment, the image sensor 10 activates the charge sharing transistor CSX after each unit accumulation time INT1 and INT2, thereby accumulating the photocharges accumulated during each unit accumulation time INT1 and INT2 for each unit. It can be stored in the storage capacitors Cs1 and Cs2 allocated in correspondence to the times INT1 and INT2. 8, as the first charge sharing signal CSS1 transitions to a logic high level after the first unit accumulation time INT1, the image sensor 10 floats for the first unit accumulation time INT1. The photocharges received by the diffusion node FD may be stored in the first storage capacitor Cs1.

Thereafter, when the first charge sharing signal CSS1 transitions to the logic low level and the reset signal RS of the logic high level is input, the floating diffusion node FD is reset, thereby performing an accumulation operation for the next unit accumulation time. can be performed. Illustratively, referring to FIG. 7 , when the reset signal RS and the transmission signal TS of the logic high level are input to the photodetection circuit 110 before the second unit accumulation time INT2, the image sensor 10 ) may reset photocharges generated in the photodiode PD before the second unit accumulation time INT2 after the first unit accumulation time INT1. The photodiode PD of the image sensor 10 may generate light charges during the second unit accumulation time INT2, and when the transmission signal TS transitions to the logic high level, the second unit accumulation time ( The photocharges generated during INT2) may be transferred to the floating diffusion node FD. As the second charge sharing signal CSS2 transitions to the logic high level after the second unit accumulation time INT2, the image sensor 10 stores the photocharges received in the floating diffusion node FD during the second unit accumulation time INT2. may be stored in the second storage capacitor Cs2.

According to the embodiment of FIG. 8 , the image sensor 10 of FIG. 3D transfers photocharges generated in the second photodiode PD2 for a plurality of unit accumulation times INT1 and INT2 to different storage capacitors Cs1 and Cs2. can be stored in the field.

The image sensor of FIG. 7 activates the plurality of charge sharing transistors CSX at different points in time to store charges stored in the storage capacitors Cs in the reading step after the accumulation step consisting of a plurality of unit frames in FIG. The amount of charge stored in the storage capacitor Cs can be read. Illustratively, the image sensor 10 may read the amount of charge stored in the first storage capacitor Cs1 when the first charge sharing transistor CSX1 is activated at a first time point, and at a time point different from the first time point, a second time point. When the second charge sharing transistor CSX2 is activated at the second point in time, the amount of charge stored in the second storage capacitor Cs2 may be read.

According to an embodiment, the time lengths of the first unit accumulation time INT1 and the second unit accumulation time INT2 may be different from each other, and the time length of each unit accumulation time INT may be determined according to the illuminance level. . Exemplarily, the image sensor 10 may accumulate photocharges for a long unit accumulation time (INT) to generate a low-illuminance image, and store photocharges for a short unit accumulation time (INT) to generate a high-illuminance image. can accumulate.

9 is a block diagram illustrating an image sensor according to another exemplary embodiment.

The pixel PX′ described in FIG. 9 is for explaining an example of a pixel including a capacitor therein, and is a pixel capable of a global shutter operation. Compared to the image sensor 10 of FIG. 1 , the image sensor 10' of FIG. 9 does not include the ADC 510 inside each pixel PX', but instead includes the ADC 510 outside the pixel array 100'. ) may be included. In the description of FIG. 9 , redundant descriptions of the same symbols as in FIG. 1 will be omitted.

Referring to FIG. 9 , an image sensor 10' includes a pixel array 100', a pixel driver 200', a lamp signal generator 300', a controller 400', a readout circuit 500', and an interface. circuit 600'. The pixel array 100' may include a plurality of pixels PX', and each of the plurality of pixels PX' senses an external light signal and generates a pixel signal PXS corresponding to the sensed light signal. It can be configured to output.

In the pixel array 100', a plurality of pixels PX' may be arranged in a matrix form in which a plurality of rows and a plurality of columns are arranged. In the global shutter mode, the image sensor 10' can equally control the photo charge accumulation timing of the pixels PX' arranged in different rows, and eliminate image distortion caused by the difference in photo charge accumulation time. can

The pixel PX' may include a photodetection circuit 110' and a pixel signal generating circuit 120'. The photodetection circuit 110 may include a photodetection element and convert an optical signal sensed from the outside into an electrical signal, that is, a detection signal that is an analog signal. The detection signal may include a detection signal according to a reset operation of the photodetection circuit 110' and may include a detection signal according to a photodetection operation of the photodetection circuit 110'.

The pixel signal generating circuit 120 ′ may receive the detection signal, generate a pixel signal PXS corresponding to the detection signal, and output the pixel signal PXS through a column line.

The image sensor 10' according to the present disclosure may accumulate photoelectric charges during unit accumulation times of a predetermined ratio of unit frames for each of a plurality of unit frames divided into a plurality of units of one frame, and may accumulate photocharges during a plurality of unit accumulation times. Image data can be generated based on one photoelectric charge. In this case, the image sensor 10 ′ according to an exemplary embodiment may generate an HDR image by accumulating photocharges corresponding to unit accumulation times having different time lengths in one unit frame.

The pixel driver 200' may output a control signal CTRL' for controlling the plurality of pixels PX' included in the pixel array 100'. In response to the control signal CTRL' generated from the pixel driver 200', each of the plurality of pixels PX' may operate in a plurality of operation modes according to the illuminance. In an exemplary embodiment, the pixel driver 200' may determine a timing at which the control signals CTRL' output to each of the plurality of pixels PX' are activated or deactivated in order to operate in the global shutter mode. there is.

The ramp signal generator 300' may generate a ramp signal RAMP' and provide the ramp signal RAMP' to the readout circuit 500', for example, the ADC 510. The ramp signal RAMP' is a signal for converting an analog signal into a digital signal, and may be generated to have a triangular wave shape.

The readout circuit 500' may include an ADC 510 and a memory 520. The ADC 510 may sample and hold the pixel signal PXS provided from the pixel array 100', double-sample the reset signal and the image signal, and output a level corresponding to the difference therebetween. can be performed. The ADC 510 may receive the ramp signal RAMP', compare the reset signal and the image signal with the ramp signal RAMP', and output a comparison result signal. The ADC 510 may convert the comparison result signal into a digital signal. The memory 520 may latch the digital signal and sequentially output the latched image data ID.

As above, exemplary embodiments have been disclosed in the drawings and specifications. Although the embodiments have been described using specific terms in this specification, they are only used for the purpose of explaining the technical idea of the present disclosure, and are not used to limit the scope of the present disclosure described in the claims. . Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical scope of protection of the present disclosure should be determined by the technical spirit of the appended claims.

Claims (19)

As a pixel array including a plurality of pixels,
Each of the plurality of pixels,
a photo diode configured to generate photoelectric charges in a frame including a plurality of unit frames;
a floating diffusion node configured to receive the photocharge;
a first storage capacitor configured to receive and store first photocharges generated by the photodiode through the floating diffusion node during a first unit accumulation time in each of the plurality of unit frames; and
and a second storage capacitor configured to receive and store second photocharges generated by the photodiode through the floating diffusion node during a second unit accumulation time in each of the plurality of unit frames. . The method of claim 1,
Each of the first unit accumulation time and the second unit accumulation time corresponds to a period from a time when the reset of the floating diffusion node and the photodiode is released to a time when the floating diffusion node accepts photocharges. A pixel array with . The method of claim 1,
The first unit accumulation time is longer than the second unit accumulation time. The method of claim 1,
The first unit accumulation time is shorter than a period in which a light emitting diode (LED) light source is turned on. The method of claim 1,
Each of the plurality of pixels,
a source follower configured to read the first photocharges through the floating diffusion node in a first read interval after the frame, and to read the second photocharges through the floating diffusion node in a second read interval after the frame; A pixel array comprising: The method of claim 5,
Each of the plurality of pixels,
An analog-to-digital converter configured to convert a first detection signal corresponding to the read first photocharge into a first digital signal and convert a second detection signal corresponding to the read second photocharge into a second digital signal. A pixel array further comprising a. The method of claim 6,
The pixel array includes a first semiconductor substrate and a second semiconductor substrate that are stacked,
The first semiconductor substrate includes the photodiode, the floating diffusion node, the first storage capacitor, the second storage capacitor, and the source follower;
The second semiconductor substrate includes the analog-to-digital converter. A pixel array comprising a plurality of pixels;
Each of the plurality of pixels,
a first photodiode configured to generate a first photoelectric charge during a first unit accumulation time in each of a plurality of unit frames included in the frame;
a second photodiode configured to generate second photocharges for a second unit accumulation time and generate third photocharges for a third unit accumulation time in each of the plurality of unit frames;
at least one floating diffusion node configured to receive at least one of the first photocharge, the second photocharge, and the third photocharge;
a first storage capacitor configured to receive and store the second photocharge through the at least one floating diffusion node; and
and a second storage capacitor configured to receive and store the third photocharge through the at least one floating diffusion node. The method of claim 8,
The first unit accumulation time includes at least a portion overlapping at least one of the second unit accumulation time and the third unit accumulation time. The method of claim 8,
The image sensor, characterized in that the length of the second unit accumulation time is different from the length of the third unit accumulation time. The method of claim 8,
The first unit storage time corresponds to a period from a time when the reset of the photodiode is released to a time when the at least one floating diffusion node accepts photocharges. The method of claim 8,
Each of the plurality of pixels,
In a first read period after the frame, the first photocharges are read through the at least one floating diffusion node, and in a second read period after the frame, the second photocharges and the second photocharges stored in the first storage capacitor are read out through the at least one floating diffusion node. The image sensor of claim 1 , further comprising a source follower configured to read at least one of the third photocharges stored in a storage capacitor through the at least one floating diffusion node. The method of claim 12,
Each of the plurality of pixels further comprises an analog-to-digital converter configured to convert a detection signal corresponding to each of the read first photocharge, second photocharge, and third photocharge into a digital signal. image sensor with The method of claim 13,
The pixel array includes a first semiconductor substrate and a second semiconductor substrate that are stacked,
The first semiconductor substrate includes the first photodiode, the second photodiode, the at least one floating diffusion node, the first storage capacitor, the second storage capacitor, and the source follower;
The second semiconductor substrate may include the analog-to-digital converter. The method of claim 8,
The at least one floating diffusion node,
a first floating diffusion node configured to receive the first photocharge from the first photodiode; and
a second floating diffusion node configured to receive the second or third photocharges from the second photodiode;
Each of the plurality of pixels,
The image sensor of claim 1 , further comprising a dual conversion transistor configured to connect the first floating diffusion node and the second floating diffusion node when activated, and configured to be deactivated in the frame. The method of claim 15
The dual conversion transistor is deactivated during a first read period for reading the first photocharge after the frame, and activated during a second read period for reading the first photocharge after the first read period. image sensor to be. The method of claim 16
The second photocharges stored in the first storage capacitor are read during a third read period after the second read period;
The image sensor of claim 1 , wherein the third photocharges stored in the second storage capacitor are read during a fourth read period after the third read period. The method of claim 17
The dual conversion transistor is an image sensor, characterized in that activated during the third read period and the fourth read period. The method of claim 17
A digital signal processing unit configured to generate image data based on digital signals respectively corresponding to the photocharges read in the first read interval, the second read interval, the third read interval, and the fourth read interval. Including image sensor.

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