KR20230018972A - Neural network apparatus and processing method performed by the same - Google Patents

Abstract

Disclosed are a neural network device and a processing method performed by the neural network device. The neural network device may comprise: a random access memory that generates an analog output signal based on an input and weight, and has a crossbar array structure; an analog-to-digital converter circuit that generates a digital output signal based on a reference signal and an analog output signal of a resistance memory; a first ADC scaler that scales the reference signal of an ADC circuit; and a second ADC scaler that scales the digital output signal generated by the ADC circuit.

Description

Neural network device and processing method performed by the neural network device

Embodiments relate to an in-memory computing based neural network device and a processing method performed by the neural network device.

Due to the recent success of deep neural networks (DNNs), interest in efficient hardware for accelerating DNN algorithms is increasing. A resistive random-access memory (ReRAM) crossbar array (RCA) is a matrix-vector multiplication (MVM) operation that underlies many recently proposed RCA-based DNN accelerators. It allows efficient calculation of The RCA-based DNN accelerator has an architecture in which calculations are performed right where data is stored, and provides high throughput by implementing all synaptic elements with dedicated hardware.

A neural network device according to an embodiment includes a random access memory that generates an analog output signal based on inputs and weights and has a crossbar array structure; an analog-to-digital converter (ADC) circuit that generates a digital output signal based on a reference signal and the analog output signal of the random access memory; a first ADC scaler for scaling the reference signal of the ADC circuit; and a second ADC scaler for scaling the digital output signal generated by the ADC circuit.

The first ADC scaler and the second ADC scaler may have the same scale factor.

The first ADC scaler may adjust the reference voltage by dividing the reference voltage corresponding to the reference signal by a scale factor in the analog domain.

The second ADC scaler may adjust the digital output signal by multiplying the digital output signal by the scale factor in a digital domain.

A processing method performed by a neural network device according to an embodiment includes an operation of receiving an input and a weight; generating an analog output signal based on the input and the weight through a random access memory having a crossbar array structure; generating a digital output signal based on a reference signal scaled by a first ADC scaler and the analog output signal of the random access memory through an analog-to-digital converter circuit; and scaling the digital output signal generated by the ADC circuit through a second ADC scaler.

The processing method performed by the neural network device according to an embodiment may further include generating the scaled reference signal by dividing the reference signal by a scale factor in an analog domain by the first ADC scaler. can

1 is a block diagram showing configurations of a neural network device according to an embodiment.
2 is a diagram for explaining a processing process performed in a neural network device according to an exemplary embodiment.
3 is a diagram showing the structure of a neural network device including an RCA structure according to an embodiment.
4 is a diagram for explaining dividing weights according to an exemplary embodiment.
5 is a diagram illustrating an ADC circuit according to an embodiment.
6A and 6B are views for explaining deriving a scale factor based on a quantization technique according to an exemplary embodiment.
7 is a flowchart illustrating operations of a processing method performed by a neural network device according to an embodiment.

Specific structural or functional descriptions of the embodiments are disclosed for illustrative purposes only, and may be changed and implemented in various forms. Therefore, the form actually implemented is not limited only to the specific embodiments disclosed, and the scope of the present specification includes changes, equivalents, or substitutes included in the technical idea described in the embodiments.

Although terms such as first or second may be used to describe various components, such terms should only be construed for the purpose of distinguishing one component from another. For example, a first element may be termed a second element, and similarly, a second element may be termed a first element.

It should be understood that when an element is referred to as being “connected” to another element, it may be directly connected or connected to the other element, but other elements may exist in the middle.

Singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, terms such as "comprise" or "have" are intended to designate that the described feature, number, step, operation, component, part, or combination thereof exists, but one or more other features or numbers, It should be understood that the presence or addition of steps, operations, components, parts, or combinations thereof is not precluded.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related art, and unless explicitly defined in this specification, it should not be interpreted in an ideal or excessively formal meaning. don't

Embodiments described in this document are deep learning hardware devices based on in-memory computing or hardware devices using matrix-vector multiplication of an in-memory computing method (eg, artificial intelligence hardware application, signal processing chips, etc.). In the following description, an embodiment based on a resistive memory (ReRAM) is described for convenience of explanation, but the embodiments of this document are other types of memory (eg, analog addition) that has a crossbar array structure and performs analog operations (eg, analog addition). static RAM (SRAM), dynamic RAM (DRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FeRAM), etc.).

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. In the description with reference to the accompanying drawings, the same reference numerals are given to the same components regardless of reference numerals, and overlapping descriptions thereof will be omitted.

1 is a block diagram showing configurations of a neural network device according to an embodiment.

Referring to FIG. 1 , the neural network device 100 may be a hardware device implementing a neural network using an in-memory computing method. For example, the neural network device 100 may be a neural network accelerator optimized to handle a neural network workload. The neural network apparatus 100 may perform an operation using a random access memory (RAM) 110 having a crossbar array structure.

The neural network device 100 may include a random access memory 110 (RAM), an ADC circuit 120, a first ADC scaler 130, and a second ADC scaler 140.

The random access memory 110 may generate an analog output signal based on inputs and weights. A weight belongs to a parameter of a neural network implemented by the neural network device 100 . Each of the input and weight may be quantized (binarization may also be performed) and split to correspond to the crossbar array structure of the random access memory 110 . Each quantized and divided input and weight may be input to the random access memory 110, and partial sums of analog values generated by an operation between each quantized and divided input and weight may be generated.

The random access memory 110 may be, for example, a resistive memory (ReRAM), but the scope of the embodiment is not limited thereto, and may be another type of memory having a crossbar array structure. The resistance memory operates in a manner of storing '1' corresponding to a low resistance state or '0' corresponding to a high resistance state by using a resistance change phenomenon observed in a transition metal oxide, and a crossbar array structure can be implemented. In the case of the crossbar array structure, it can be driven using two electrodes of a bit line and a word line without a cell selection transistor to select a unit cell for storing data, so it has advantages in terms of integration. have

The ADC circuit 120 may convert an input analog signal into a digital signal. The ADC circuit 120 may generate a digital output signal based on the reference signal and the analog output signal of the random access memory 110 . The ADC circuit 120 converts partial sums of analog values output from the random access memory 110 into digital values to generate partial sums of digital values, and accumulates the partial sums of digital values to obtain a digital output signal. can create The ADC circuit 120 includes a plurality of comparators input to a corresponding analog output signal and a reference signal different from each other, and each of the comparators may output a binarized output value based on a comparison result between the analog output signal and the reference signal. .

The first ADC scaler 130 may scale the reference signal of the ADC circuit 120 . 'Scaling' means adjusting the amplitude of a signal. The first ADC scaler 130 may adjust the reference voltage by dividing the reference voltage (eg, Vref in FIG. 5 ) corresponding to the reference signal in the analog domain by a set scaling factor. The first ADC scaler 130 may scale a reference signal by adjusting a reference voltage applied to resistors connected in series. The second ADC scaler 140 may scale the digital output signal generated by the ADC circuit 120 . The second ADC scaler 140 may adjust a digital output signal by multiplying a corresponding digital output signal by a scale factor in a digital domain. The second ADC scaler 140 may include a digital multiplier and a digital adder that output a result obtained by multiplying a digital output signal of the ADC circuit 120 by a scale factor. The first ADC scaler 130 may also be referred to as a pre-ADC scaler, and the second ADC scaler 140 may also be referred to as a post-ADC scaler.

As described above, the first ADC scaler 130 can control the signal scale of the analog domain by controlling the reference voltage, and the second ADC scaler 140 can control the signal scale of the digital domain. Both the first ADC scaler 130 and the second ADC scaler 140 can be used to realize quantization parameters such as scale factors. The first ADC scaler 130 and the second ADC scaler 140 may have the same scale factor, thereby reducing overhead. The same value may be used as a parameter of the first ADC scaler 130 and the second ADC scaler 140 . The scale factor of the first ADC scaler 130 and the scale factor of the second ADC scaler 140 may be derived by quantization techniques (optimal values derived from quantization theory), and The scale factor, the scale factor of the second ADC scaler 140, and the weight input to the random access memory 110 may be optimized through the same learning process. In the learning process, optimal values of the scale factor of the first ADC scaler 130 and the scale factor of the second ADC scaler 140 are determined, and the weight applied to the neural network device 100 based on the determined optimal scale factor. can be learned.

Neural network hardware based on in-memory computing requires an ADC to perform the calculations. In the RCA-based neural network apparatus 100 proposed in this specification, a matrix-vector multiplication (MVM) operation is performed in an analog domain, and an ADC is required to convert an operation result in the analog domain into a digital signal. ADCs generally have a large overhead in terms of area, energy, and power. According to the proposed technology, it is possible to provide high accuracy while reducing the required area of the ADC through the first ADC scaler 130 and the second ADC scaler 140 without changing the hardware, and greatly reduce the overhead of the ADC. there is.

The neural network device 100 uses the optimal scale factor derived from the quantization technique as a parameter of the ADC circuit 120, thereby reducing the size of the ADC required in the in-memory computing-based neural network hardware and providing high calculation accuracy. and reduce power consumption and required area of peripheral circuits (eg, the ADC circuit 120). The neural network device 100 may be implemented in the form of a chip or mounted on a device such as a computer or mobile phone.

2 is a diagram for explaining a processing process performed in a neural network device according to an exemplary embodiment.

Referring to FIG. 2 , an input 210 of a neural network layer and a weight 230 of a neural network are given to a neural network device (eg, the neural network device 100 of FIG. 1 ). The input 210 and the weight 230 may have a tensor data structure, which is an n-dimensional array data structure.

Input 210 may be binarized and quantized to generate binarized and quantized input 215 . The binarized and quantized input 215 is divided 220 to correspond to the crossbar array structure of the random access memory (eg, the random access memory 110 of FIG. 1) included in the neural network device, and divided inputs 225 this can be created. Similarly, weights 230 may also be binarized and quantized to produce binarized and quantized weights 235 . The binarized and quantized weights 235 may be divided 240 to correspond to the crossbar array structure of the random access memory to generate divided weights 245 . In this way, the binarized and quantized input 215 and the binarized and quantized weights 235 may be divided according to the size of the crossbar array structure of the random access memory.

The divided inputs 225 and the divided weights 245 are input to the crossbar array structure of the random access memory, and an operation is performed based on the divided inputs 225 and the divided weights 245 in the random access memory. (250) may be performed. Operation 250 is performed in the analog domain and may correspond to, for example, a convolution operation. As a result of performing each operation 250, partial sums 260 of analog values are generated from the random access memory, and the partial sums 260 of analog values are transferred to an ADC circuit (eg, the ADC circuit 120 of FIG. 1). can be entered. The ADC circuit may generate partial sums 270 of digital values by converting each of the partial sums 260 of analog values into digital values. The partial sums 270 of the digital values generated in this way are accumulated (accumulation) 280, and a digital output signal 290 corresponding to a final output may be generated as an accumulation result.

3 is a diagram showing the structure of a neural network device including an RCA structure according to an embodiment.

Referring to FIG. 3 , a structure of a neural network apparatus 300 including a resistive memory crossbar array (RCA) structure is shown. The structure of the neural network device 300 may correspond to the structure in which the neural network device 100 of FIG. 1 has a resistive memory (ReRAM) 310 as a random access memory. The resistive memory 310 has advantages of being compact in size and fast in operation.

In one embodiment, resistive memory 310 includes digital-to-analog converters (DACs) 312 that convert inputs of digital values to analog values, a low resistance state or a high resistance state. ) crossbar array structure 314 for storing data based on whether or not in a resistance state, and sample and hold circuits 316 for sampling and holding analog values in the crossbar array structure 314 can include The resistive memory 310 performs an operation between an input input to the row lines of the resistive memory 310 and a weight input to the column lines of the resistive memory 310, You can create partial sums.

The partial sums of the analog values output from the resistance memory 310 are transferred to the analog multipliers 320, and the analog multipliers 320 may scale the partial sums of the analog values based on the set scale factor. The analog multipliers 320 may multiply partial sums of analog values in the analog domain by a scale factor (eg, 1/s). Analog-to-digital converter (ADC) circuits 330 may generate partial sums of digital values by converting each of the partial sums of analog values into digital values. Digital multipliers 340 may scale partial sums of digital values generated by ADC circuits 330 . The digital multipliers 340 may multiply partial sums of digital values by a scale factor (eg, s). The partial sums of the scaled digital values may be accumulated 350 to generate a final digital output signal.

4 is a diagram for explaining dividing weights according to an exemplary embodiment.

Referring to FIG. 4 , as an example, a weight 410 having a tensor data structure in a convolution layer is divided to correspond to a crossbar array structure of a random access memory.

There are various methods for mapping a convolutional layer to a crossbar array structure. Corresponding methods may vary depending on how to flatten the 3D structure of the weights 410 and how to map them to input rows of the crossbar array structure. When the convolution layer is mapped to the crossbar array structure, weights having a tensor data structure may be divided into several 1 X 1 convolutions having, for example, P or less input channels. The filter used may have, for example, a filter size of K X K (in the illustrated example, K=3). Each divided weight block 420 may have a shape of 1 X 1 X P. P represents the number of input rows of the crossbar array structure, and Cin represents the number of input channels. P X P may correspond to the size of the crossbar array structure.

5 is a diagram illustrating an ADC circuit according to an embodiment.

Referring to FIG. 5 , a flash ADC circuit is shown as an example of the ADC circuit (eg, the ADC circuit 120 of FIG. 1 ) 500 . The ADC circuit 500 may include a plurality of resistors 512 , 514 , 516 , and 518 , comparators 522 , 524 , and 526 , and an encoder 530 .

In the ADC circuit 500, different voltages are generated from a reference signal (eg, a reference voltage) Vref by resistors 512, 514, 516, and 518 connected in series, and each different voltage is generated by comparators 522, 524, 526) are input to each. Voltage values of the different voltages may be determined by a voltage division rule based on a connection relationship between the resistors 512 , 514 , 516 , and 518 .

The reference signal Vref may be adjusted by a first ADC scaler (eg, the first ADC scaler 130 of FIG. 1 ). The first ADC scaler may scale the reference signal Vref by applying a scale factor to the reference signal Vref. The scale factor of the first ADC scaler may be learned and determined together with the weights in the process of learning the weights of the neural network. In this way, by implementing the first ADC scaler, which is an analog domain scaler, by using the reference signal Vref, it is possible to replace the ADC circuit 500 with a quantizer without incurring area cost. Scaling in the analog domain can be implemented without using an analog multiplier by adjusting the reference signal Vref.

The comparators 522, 524, and 526 each generate an analog output signal (eg, an analog voltage signal) of an analog value output from a random access memory (eg, the random access memory 110 of FIG. 1) from Vin and a reference signal Vref. Different voltages are input. The comparators 522, 524, and 526 compare the input analog voltage signal, the reference signal Vref, and the reference voltage signal generated from the resistors 512, 514, 516, and 518, respectively, to a high level ( A high level or low level output value may be output.

The output values of the comparators 522, 524, and 526 are transmitted to the encoder 530, and the encoder 530 outputs a digital output signal of a digital value based on the output values of the comparators 522, 524, and 526. can The encoder 530 may be composed of, for example, a combination of a full adder and an adder, and may convert the output values of the comparators 522, 524, and 526 into binary codes and output them. . A final digital output signal of the ADC circuit 500 may be generated by outputting the corresponding binary code as a parallel output.

6A and 6B are views for explaining deriving a scale factor based on a quantization technique according to an exemplary embodiment.

A method for determining parameters (eg, scale factors) of a first ADC scaler and a second ADC scaler for optimizing the performance of a neural network (eg, a deep neural network (DNN)) implemented by a neural network apparatus is provided. By considering the problem of reducing the area of the ADC (ADC reduction problem, ADC reduction problem) as a quantization problem, the proposed technology can optimize the precision of the ADC in the neural network device having the RCA structure.

The first step is to convert the neural network graph. In the first step, as shown in FIG. 6A, the neural network (eg, DNN) graph is mapped to RCA blocks 610 and ADC blocks 620 and converted. do. Partitioning the weight matrix of a neural network into RCA matrices is called weight-to-RCA mapping, and weight-to-RCA mapping determines the precision of weights, cell precision of resistive memory, RCA It depends on the size, dimensions of the weight tensor and how the weights are processed. A fully-connected layer of the neural network may be mapped to RCA blocks 610 as shown in FIG. 6A. Since the RCA blocks 610 process and output analog values, the ADC blocks 620 are connected to the RCA blocks 610, and then the digital values output from the respective ADC blocks 620 are summed ( A summation block 630 for summation (or accumulation) is placed.

In the second step, as shown in FIG. 6B, the ADC blocks 620 are replaced with quantizer (Q) blocks 640. In the second step, parameters are optimized and quantization is applied to the neural network graph transformed in the first step. The quantizer blocks 640 function to simulate a first ADC scaler (eg, the first ADC scaler 130 of FIG. 1 ) and a second ADC scaler (eg, the second ADC scaler 140 of FIG. 1 ). can be done The quantizer blocks 640 quantize the output values of the RCA blocks 610 and restore the scale of the input values. In the quantizer blocks 640, for example, an operation such as Equation 1 below may be performed.

는 양자화의 대상이 되는 입력 값이고,

는 양자화된 입력 값을 나타낸다.

는 수학식 1 연산의 결과 값을 나타내고, s는 스케일 요소(또는 단계 크기)의 파라미터를 나타낸다. b는 ADC의 정밀도(비트 수)를 나타낸다.

는 라운드 연산(round operation)을 나타내고,clip(x, a, b) = min(max(x, a), b)의 연산을 나타낸다. 스케일 요소 s는 뉴럴 네트워크의 학습 과정 또는 다른 방법(예: 통계적인 방법)을 통해 결정될 수 있다. RCA 블록들(610)의 출력 신호(예: 아날로그 값의 출력 전압)에 대응하는

가 스케일 요소 s에 나누어진다. 이 과정은 제1 ADC 스케일러에 의해 ADC 회로의 기준 전압 Vref(예: 도 5의 기준 전압 Vref)을 1/s 배로 조정하는 것에 의해 구현될 수 있다. ADC 회로의 기준 전압 Vref을 조정함으로써, 아날로그 곱셈기를 사용하지 않고도 아날로그 영역에서의 스케일링을 구현할 수 있게 된다.here,

is an input value to be quantized,

represents a quantized input value.

denotes a resultant value of the calculation of Equation 1, and s denotes a parameter of a scale factor (or step size). b represents the precision (number of bits) of the ADC.

represents a round operation, and represents an operation of clip(x, a, b) = min(max(x, a), b). The scale factor s may be determined through a learning process of a neural network or another method (eg, a statistical method). Corresponding to the output signal (eg, the output voltage of the analog value) of the RCA blocks 610

is divided by the scale factor s. This process may be implemented by adjusting the reference voltage Vref (eg, the reference voltage Vref of FIG. 5 ) of the ADC circuit by a factor of 1/s by the first ADC scaler. By adjusting the reference voltage Vref of the ADC circuit, scaling in the analog domain can be implemented without using an analog multiplier.

In the third step, the quantized neural network is remapped to an RCA-based neural network (eg, an RCA-based accelerator). In the quantization blocks 640, there are two scaling operations performed before and after the round operation of Equation 1. A scaling operation in the analog domain performed before the round operation (performed by the first ADC scaler) and a scaling operation in the digital domain performed after the round operation (performed by the second ADC scaler). The parameters of the scale factor can be shared within the entire layer, output channel or each RCA structure of the neural network. Scaling overhead can be reduced if the same scale factor is used in all layers. Alternatively, the parameter of the scale factor may not be shared, and in this case, the scale factor of the first ADC scaler may have a unique value.

7 is a flowchart illustrating operations of a processing method performed by a neural network device according to an embodiment. Operations of the processing method may be performed by a neural network device (eg, the neural network device 100 of FIG. 1 ) described in this specification.

Referring to FIG. 7 , in operation 710, the neural network device may receive an input and a weight. Each input and weight may be quantized (binarization may also be performed) and divided to correspond to a crossbar array structure of a random access memory (eg, random access memory 110 of FIG. 1 ).

In operation 720, the neural network device may generate an analog output signal based on the input and the weight through the random access memory having a crossbar array structure. The random access memory may generate partial sums of analog values generated by operations between weights and inputs that are each quantized and divided.

In operation 730, the neural network device may generate a scaled reference signal by dividing the reference signal by a scale factor in the analog domain through a first ADC scaler (eg, the first ADC scaler 130 of FIG. 1). there is. Here, the reference signal may correspond to a reference voltage to be compared with the analog output signal in the ADC circuit.

In operation 740, the neural network device, via an analog-to-digital converter (ADC) circuit (e.g., ADC circuit 120 in FIG. 1), analogs the reference signal scaled by the first ADC scaler to the random access memory. A digital output signal may be generated based on the output signal. The ADC circuit may generate the partial sums of the digital values by converting the partial sums of the analog values into digital values, and may generate a digital output signal by accumulating the partial sums of the digital values.

In operation 750, the neural network device may perform scaling of the digital output signal generated by the ADC circuit through a second ADC scaler (eg, the second ADC scaler 140 of FIG. 1). The second ADC scaler may adjust the digital output signal by multiplying the digital output signal by a scale factor in the digital domain. In one embodiment, the first ADC scaler and the second ADC scaler may have the same scale factor.

The embodiments described above may be implemented as hardware components, software components, and/or a combination of hardware components and software components. For example, the devices, methods and components described in the embodiments may include, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate (FPGA). array), programmable logic units (PLUs), microprocessors, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and software applications running on the operating system. A processing device may also access, store, manipulate, process, and generate data in response to execution of software. For convenience of understanding, there are cases in which one processing device is used, but those skilled in the art will understand that the processing device includes a plurality of processing elements and/or a plurality of types of processing elements. It can be seen that it can include. For example, a processing device may include a plurality of processors or a processor and a controller. Other processing configurations are also possible, such as parallel processors.

Software may include a computer program, code, instructions, or a combination of one or more of the foregoing, which configures a processing device to operate as desired or processes independently or collectively. You can command the device. Software and/or data may be any tangible machine, component, physical device, virtual equipment, computer storage medium or device, intended to be interpreted by or provide instructions or data to a processing device. may be permanently or temporarily embodied in Software may be distributed on networked computer systems and stored or executed in a distributed manner. Software and data may be stored on computer readable media.

The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer readable medium. A computer readable medium may store program instructions, data files, data structures, etc. alone or in combination, and program instructions recorded on the medium may be specially designed and configured for the embodiment or may be known and usable to those skilled in the art of computer software. there is. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks and magnetic tapes, optical media such as CD-ROMs and DVDs, and magnetic media such as floptical disks. - includes hardware devices specially configured to store and execute program instructions, such as magneto-optical media, and ROM, RAM, flash memory, and the like. Examples of program instructions include high-level language codes that can be executed by a computer using an interpreter, as well as machine language codes such as those produced by a compiler.

The hardware device described above may be configured to operate as one or a plurality of software modules to perform the operations of the embodiments, and vice versa.

As described above, although the embodiments have been described with limited drawings, those skilled in the art can apply various technical modifications and variations based on this. For example, the described techniques may be performed in an order different from the method described, and/or components of the described system, structure, device, circuit, etc. may be combined or combined in a different form than the method described, or other components may be used. Or even if it is replaced or substituted by equivalents, appropriate results can be achieved.

Therefore, other implementations, other embodiments, and equivalents of the claims are within the scope of the following claims.

Claims (19)

In a neural network device using random-access memory (RAM),
the random access memory generating an analog output signal based on inputs and weights and having a crossbar array structure;
an analog-to-digital converter (ADC) circuit that generates a digital output signal based on a reference signal and the analog output signal of the random access memory;
a first ADC scaler for scaling the reference signal of the ADC circuit; and
A second ADC scaler for scaling the digital output signal generated by the ADC circuit
A neural network device comprising a.
According to claim 1,
The first ADC scaler and the second ADC scaler have the same scale factor,
Neural network device.
According to claim 1,
The first ADC scaler,
Adjusting the reference voltage by dividing the reference voltage corresponding to the reference signal in the analog domain by a scale factor.
Neural network device.
According to claim 3,
The second ADC scaler,
adjusting the digital output signal by multiplying the digital output signal by the scale factor in the digital domain;
Neural network device.
According to claim 1,
The first ADC scaler,
scaling the reference signal by adjusting a reference voltage applied to resistors connected in series;
Neural network device.
According to claim 1,
The second ADC scaler,
Including a digital multiplier for outputting a result of multiplying the digital output signal of the ADC circuit by a scale factor,
Neural network device.
According to claim 1,
The ADC circuit,
Includes a plurality of comparators input to the analog output signal and a different reference signal,
Each of the comparators outputs a binarized output value based on a comparison result between the analog output signal and a reference signal.
Neural network device.
According to claim 1,
The input and the weight are each quantized and split to correspond to the crossbar array structure of the random access memory,
Neural network device.
According to claim 8,
The random access memory,
Generating partial sums of analog values generated by the operation between the respective quantized and divided inputs and weights,
Neural network device.
According to claim 9,
The ADC circuit,
converting the partial sums of the analog values into digital values to generate partial sums of digital values, and generating the digital output signal by accumulating the partial sums of the digital values;
Neural network device.
According to claim 1,
The scale factor of the first ADC scaler and the scale factor of the second ADC scaler are derived by a quantization technique,
Neural network device.
According to claim 1,
The random access memory,
A neural network device, which is a resistive RAM.
In the processing method performed by the neural network device,
receiving inputs and weights;
generating an analog output signal based on the input and the weight through a random-access memory (RAM) having a crossbar array structure;
generating a digital output signal based on a reference signal scaled by a first ADC scaler and the analog output signal of the random access memory through an analog-to-digital converter (ADC) circuit; and
Scaling the digital output signal generated by the ADC circuit through a second ADC scaler.
A processing method comprising a.
According to claim 13,
The first ADC scaler and the second ADC scaler have the same scale factor,
processing method.
According to claim 13,
Generating the scaled reference signal by dividing the reference signal by a scale factor in an analog domain by the first ADC scaler
A processing method further comprising a.
According to claim 13,
The operation of scaling the digital output signal,
Adjusting the digital output signal by multiplying the digital output signal by the scale factor in the digital domain.
A processing method comprising a.
According to claim 13,
The operation of generating the analog output signal,
An operation of generating partial sums of analog values generated by an operation between each quantized and divided input and weights
A processing method comprising a.
According to claim 17,
The operation of generating the digital output signal,
converting the partial sums of the analog values into digital values to generate the partial sums of the digital values, and generating the digital output signal by accumulating the partial sums of the digital values;
A processing method comprising a.
A computer-readable recording medium storing one or more computer programs including instructions for performing the method of any one of claims 13 to 18.

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