KR20230017711A - Memory device, memory system having the same and operating method thereof - Google Patents

Abstract

A memory device of the present invention includes a first rank having first memory banks and a first quad skew control circuit, and a second rank having second memory banks and a second quad skew control circuit. Each of the first quad skew control circuit and the second quad skew control circuit may receive a 4-phase clock through first channels, detect an inner quad skew of the 4-phase clock, correct the skew of the 4-phase clock according to the detected quad skew, and output mode register information corresponding to the detected quad skew through a second channel.

Description

Memory device, memory system including the same and operating method thereof

The present invention relates to a memory device, a memory system including the same, and an operating method thereof.

Mobile-oriented semiconductor memory devices such as LPDDR (Low Power Double Data Rate) DRAM (Dynamic Random Access Memory) are mainly used in mobile electronic devices. When an application processor (AP) is installed as one of multi-cores in a mobile electronic device, a semiconductor memory device such as an LPDDR DRAM may be used as a working memory of the AP.

An object of the present invention is to provide a memory system that efficiently manages quad skew and an operating method thereof.

A memory device according to an embodiment of the present invention includes a first rank having first memory banks and a first quad skew control circuit; and a second rank having second memory banks and a second quad skew control circuit, wherein each of the first quad skew control circuit and the second quad skew control circuit generates a 4-phase clock through first channels. , detects an internal quad skew of the 4-phase clock, corrects the skew of the 4-phase clock according to the detected quad skew, and modulates a mode register corresponding to the detected quad skew through a second channel. Characterized in outputting information.

An operating method of a system including a multi-rank implemented memory device and a controller controlling the memory device according to an embodiment of the present invention includes a 4-phase clock received through first channels from the controller in each of the ranks. detecting an inner quad skew of ; correcting a first skew of the 4-phase clock according to the detected inner quad skew at each of the ranks; and adjusting, by the controller, a second skew of the 4-phase clock using mode register information corresponding to the internal quad skew output through a second channel from each of the ranks.

A memory system according to an embodiment of the present invention includes a memory device that adjusts a first quad skew of a 4-phase clock; and a controller for controlling the memory device and controlling a second quad skew of the 4-phase clock, wherein the memory device receives the 4-phase clock from the controller through first channels, and - a first method for detecting a first internal quad skew of the phase clock, storing first mode register information corresponding to the first internal quad skew, and outputting the first mode register information to the controller through a second channel; rank; and receiving the 4-phase clock from the controller through the first channels, detecting a second internal quad skew of the 4-phase clock, and storing second mode register information corresponding to the second internal quad skew. and a second rank for outputting the second mode register information to the controller through the second channel.

A memory device according to an embodiment of the present invention, a memory system including the same, and a method of operating the same, Quad skew may be detected in a memory device, and the detected quad skew may be efficiently removed inside/outside the memory device.

The accompanying drawings are provided to aid understanding of the present embodiment, and provide embodiments along with detailed descriptions.
1 is a diagram showing a memory system according to an exemplary embodiment of the present invention by way of example.
FIG. 2 is a diagram showing quad skew cancellation in the memory system 10 according to an exemplary embodiment of the present invention.
3A, 3B, and 3C are views exemplarily illustrating a quad skew method according to quad skew detection in the memory system 10 according to an embodiment of the present invention.
4A and 4B are diagrams showing an example of a quad skew monitor (QM) and its input clocks (CK, CKB).
5 is a diagram showing a quad skew corrector (QC) according to an embodiment of the present invention by way of example.
6 is a diagram showing a quad skew adjuster according to an embodiment of the present invention by way of example.
7 is a flowchart illustrating an operating method of a memory system according to an exemplary embodiment of the present invention.
8 is a ladder diagram exemplarily illustrating a clock training process of a memory system according to an embodiment of the present invention.
9 is a diagram showing a memory module according to an exemplary embodiment of the present invention by way of example.
FIG. 10 is a diagram showing the memory device shown in FIG. 9 .
11 is a block diagram illustrating a semiconductor package having a stacked structure including a plurality of layers according to an embodiment of the present invention.
12 is a diagram illustrating a semiconductor package including stacked semiconductor chips according to an embodiment of the present invention.

In the following, the content of the present invention will be described clearly and in detail to the extent that a person skilled in the art can easily practice using the drawings.

A memory system and its operating method according to an embodiment of the present invention is a multi-rank system supporting a 4-phase clock and can detect and adjust quad skew there is. In particular, the memory system and its operating method of the present invention enable efficient skew control by adjusting quad skew inside and outside the memory device.

1 is a diagram showing a memory system according to an exemplary embodiment of the present invention by way of example. Referring to FIG. 1 , a memory system 10 may include a memory device 100 and a memory controller 200 (CTRL).

The memory system 10 may be implemented to be included in a personal computer (PC) or a mobile electronic device. Mobile electronic devices include laptop computers, mobile phones, smart phones, tablet PCs, personal digital assistants (PDAs), enterprise digital assistants (EDAs), digital still cameras, digital video cameras, PMPs ( Portable Multimedia Player), PND (Personal Navigation Device or Portable Navigation Device), handheld game console, Mobile Internet Device (MID), wearable computer, IoT (Internet of Things) device, IoE ( It can be implemented as an Internet of Everything device or a drone.

The memory device 100 may be implemented as a volatile memory device. The volatile memory device may be implemented as random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), or low power double data rate (LPDDR) DRAM. In another embodiment, the memory device 100 may be implemented as a non-volatile memory device. Non-volatile memory devices include EPROM (electrically erasable programmable read-only memory), NORA flash memory, NAND flash memory, MRAM (Magnetoresistive Random Access Memory), STT (Spin Transfer Torque)-MRAM, FeRAM (Ferroelectric RAM), PRAM (Phase Phase change RAM), resistive RAM (RRAM), nanotube RRAM, polymer RAM (PoRAM), nano floating gate memory (NFGM), holographic memory ( holographic memory), a molecular electronics memory device (Molecular Electronics Memory Device), or an insulation resistance change memory (Insulator Resistance Change Memory).

Also, the memory device 100 may be implemented as a multi-rank having a plurality of ranks. Here, the rank means one block or area of data generated by using a part or the whole of a memory chip in one module. In an embodiment, one rank may input/output 64-bit or 72-bit data. In FIG. 1, two ranks are shown for convenience of explanation.

The memory device 100 may include a first rank 101 and a second rank 102 . In an embodiment, the first rank 101 and the second rank 102 may receive the 4-phase clock CK[3:0] from the controller 200 through the first channels 11. . In an embodiment, the first rank 101 and the second rank 102 may output mode register information MRR to the controller 200 through the second channel 12 . Here, the second channel 12 may be any one of a command/address bus and a data bus.

The first rank 101 may include a plurality of first memory banks and a first quad skew control circuit 110 . Each of the first memory banks may include a plurality of memory cells connected to word lines and bit lines therebetween. The first quad skew control circuit 110 may include a clock receiver 111 (CLK RX), a quad skew monitor 112 (QM), a quad skew corrector 113 (QC), and a mode register 114 (MR). . The clock receiver 111 (CLK RX) receives a 4-phase clock (CK[3:0]) through the first channels 11 and outputs a 1st bank 4-phase clock (CK_R0[3:0]) The quad skew monitor 112 (QM) may be implemented to receive the first bank 4-phase clock (CK_R0[3:0]) from the clock receiver 111 and monitor the quad skew. The skew compensator 113 (QC) may be implemented to adjust the skew of the first bank 4-phase clock (CK_R0[3:0]) output from the clock receiver 111 in response to the monitoring result of the quad skew monitor 112. The mode register 114 (MR) may be implemented to store information (MRR) corresponding to the monitoring result of the quad skew monitor 112. Here, the mode register information (MRR) stored in the mode register 114 is It can be output through the second channel 12 according to the request of the controller 200 .

The second rank 102 may include a plurality of second memory banks and a second quad skew adjusting circuit 120 . The second quad skew control circuit 120 may include a clock receiver 121 (CLK RX), a quad skew monitor 122 (QM), a quad skew corrector 123 (QC), and a mode register 124 (MR). . The clock receiver 121 may receive the 4-phase clock CK[3:0] of the first channels 11 and output the second bank 4-phase clock CK_R1[3:0]. Each of the clock receiver 121 (CLK RX), quad skew monitor 122 (QM), quad skew corrector 123 (QC), and mode register 124 (MR) of the second rank 102 is ) may be implemented identically to those of (111, 112, 113, 114).

The memory controller 200 may be implemented as an integrated circuit, a system on chip (SoC), an application processor (AP), a mobile AP, a chipset, or a set of chips. The memory controller 200 includes a random access memory (RAM), a central processing unit (CPU), a graphics processing unit (GPU), a neural network processing unit (NPU), or a modem. can include In an embodiment, the memory controller 200 may perform functions of a modem and an AP.

The memory controller 200 may be implemented to control the memory device 100 to read data stored in the memory device 100 or write data to the memory device 100 . The memory controller 200 provides a command CMD and an address ADD to the memory device 100 in synchronization with the 4-phase clock CK[3:0], thereby performing a write operation on the memory device 100 or Read operation can be controlled. Also, data DQ may be transmitted and received between the memory controller 200 and the memory device 100 in synchronization with the data transfer clock WCK.

The memory controller 200 may include a quad skew control circuit 210 that controls the quad skew of the memory device 100 . The quad skew control circuit 210 outputs a 4-phase clock (CK[3:0]) to the memory device 100 and obtains mode register information (MRR) corresponding to the result of the quad skew monitoring from the memory device 100. and adjust the skew of the 4-phase clock CK[3:0] in response to the mode register information MRR.

The quad skew control circuit 210 may include a clock transmitter 211 and a quad skew adjuster 212 (QA). The clock transmitter 211 may be implemented to output the 4-phase clock CK[3:0] to the memory device 100 through the first channels 11 . The quad skew adjuster 212 (QA) reads the mode register information (MRR) of the requested rank through the second channel 12, and generates a 4-phase clock (CK[3:0]) based on the mode register information (MRR). ) can be implemented to adjust the skew of

A typical memory system detects quad-skew inside a memory device and internally processes the detected skew. On the other hand, the memory system 10 according to an embodiment of the present invention may detect quad skew inside the memory device 100 of each rank and transmit detection information to the external controller 200 . In the memory system 10 according to an embodiment of the present invention, the common quad skew between the ranks 101 and 102 sharing the same clock is removed by the external controller 200, and the additional internal skew is removed by the memory device 100 It can be processed in the interior (110, 120) of. As a result, the memory system 10 implemented as an interface system that transmits and receives a 4-phase clock to an input/output pin detects an internal quad skew state and internally compensates according to the detection result or externally monitors and compensates for internal quad skew (Internal quad skew). Quad Skew) can be minimized. The memory system 10 according to an embodiment of the present invention can effectively manage skew in a multi-rank system.

FIG. 2 is a diagram showing quad skew cancellation in the memory system 10 according to an exemplary embodiment of the present invention.

In general, quad skew reduces the timing margin of the data sampling unit. Quad skew is an internal 4-phase clock in a data interface system that sends and receives a 4-phase clock (CLK0, CLK90, CLK180, CLK270; or CK[0], CK[1], CK[2], CK[3]) to the input and output pins. Means the skew between the phases. As shown in FIG. 2 , the memory system 10 of the present invention detects quad skew inside the memory device 100, processes all or part of the detected quad skew internally, or uses an external controller 200. ), the internal quad skew can be minimized by monitoring and processing the quad skew. Thus, the memory system 10 can secure a data timing margin as much as possible.

Meanwhile, the memory system 10 according to an embodiment of the present invention may remove the quad skew by using various combinations of an external skew removal method and an internal skew removal method according to the detected quad skew.

3A, 3B, and 3C are views exemplarily illustrating a quad skew method according to quad skew detection in the memory system 10 according to an embodiment of the present invention.

Referring to FIG. 3A , quad skew is generated only in the first rank 101 among the first rank 101 and the second rank 102 . For example, as shown in FIG. 3A , skew may occur in clocks CK_R0[1] and CK_R0[2] of the first rank 101 . Since quad skew occurs only inside the memory chip of the first rank 101, the first rank 101 may operate the first quad skew control circuit 110 to remove the internal quad skew.

Referring to FIG. 3B , quad skew in the same direction may occur in the first rank 101 and the second rank 102 . For example, as shown in FIG. 3B, received clocks (CK[1], CK[2]), first rank 101 clocks (CK_R0[1], CK_R0[2]), and Skew may occur in the same direction of the clocks CK_R1[1] and CK_R1[2] of the second rank 102 . When viewed from the outside (eg, the controller 200 shown in FIG. 1), it is confirmed that the quad skew of the clocks inside the memory chips of the first rank 101 and the second rank 102 are twisted in the same direction It can be. This skew in the same direction is a controller (200, external SOC) that commonly transmits clocks (CK[0], CK[1], CK[2], and CK[3]) to respective ranks (101, 102). side) can be removed. Meanwhile, it should be understood that the present invention is not limited thereto. The skew in the same direction can be eliminated by using the quad skew control circuit of each rank.

Referring to FIG. 3C , quad skew occurs in the first rank 101 and the second rank 102, and the skew in the same direction may partially exist. The common quad skew of the ranks 101 and 102 can be processed by the external controller 200 . At this time, the controller 200 may transmit each skew-free clock of the ranks 101 and 102 . The skew-free clock transmitted here may still have internal quad skew. This internal quad skew can be processed by each quad skew control circuit of ranks 101 and 102 . This skew removal method can effectively remove quad skew both inside and outside the memory device 100 .

4A and 4B are diagrams showing an example of a quad skew monitor (QM) and its input clocks (CK, CKB). Here, the input clocks CK and CKB are edge-to-edge by two of the 4-phase clocks CK[0], CK[1], CK[2], and CK[3]. These are clocks with phases opposite to each other generated using In an embodiment, each frequency of the input clocks CK and CKB is 2 of the respective frequencies of the 4-phase clocks CK[0], CK[1], CK[2], and CK[3]. it can be a boat The quad skew monitor QM accumulates duty through the charge pump 410 (LPF) in synchronization with the input clocks CK and CKB, and determines the duty of the newly generated clock through the comparator 420. can This allows the quad skew monitor (QM) to detect phase skew between two different phase clocks.

Meanwhile, it should be understood that the quad skew monitor (QM) of the present invention is not limited thereto. The quad skew monitor of the present invention can be implemented in various ways.

5 is a diagram showing a quad skew corrector (QC) according to an embodiment of the present invention by way of example. Referring to FIG. 5 , the quad skew corrector (QC) may include a skew correction unit 510 .

The skew correction unit 510 receives the 4-phase clocks CK[0], CK[1], CK[2], and CK[3], and generates 4 according to the detection result value of the quad skew monitor 520. -Adjust the skew of each of the phase clocks (CK[0], CK[1], CK[2], CK[3]), and adjust the 4-phase clocks (CK[0], CK[1] , CK[2], CK[3]) may be output.

The quad skew monitor 520 may include an XOR circuit 521 , a phase detector 522 , a duty cycle monitor 523 (DCM), and a skew detection unit 524 . The XOR circuit 521 selects two clocks (eg, CK[0]) for skew detection among the 4-phase clocks (CK[0], CK[1], CK[2], and CK[3]). ], CK[1]), XOR operation can be performed. The phase separator 522 may separate the phase from the output signal of the XOR circuit 521 . The duty cycle monitor 524 (DCM) may detect the duty cycle from the output of the phase separator 522 in response to the signal flip. In an embodiment, the duty cycle monitor 523 may include the circuit shown in FIG. 4A. The skew detection unit 524 may detect skew according to a result of the duty cycle monitor 523 and store skew information corresponding to the detected skew. This skew information may be output to the skew correction unit 510 .

6 is a diagram showing a quad skew adjuster according to an embodiment of the present invention by way of example. Referring to FIG. 6 , the quad skew adjuster 620 may adjust the skew of the 4-phase clock using duty information stored in the mode register MR of the memory device 610 .

The mode register MR may store either first duty information of a high level (H) or second duty information of a low level (L). Here, the first duty information is a value indicating that the duty ratio is 50% or more. Also, the second duty information is a value indicating that the duty ratio is less than 50%.

The quad skew controller 620 responds to the first duty information (H) output from the mode register (MR) of the memory device 610 from the rising of the first phase (x) to the second phase (x+90). ) may be equal to or greater than the second interval from the rising of the second phase to the falling of the first phase. Here, the second phase may be a quadrature phase of the first phase.

In addition, the quad skew controller 620 responds to the second duty information L from the mode register MR of the memory device 610 from the rising of the first phase (x) to the second phase (x+90). ) may be smaller than the second interval from the rising of the second phase to the falling of the first phase.

Meanwhile, the quad skew controller 620 may adjust the skew of the 4-phase clock in various ways using duty information output from the mode register MR of the memory device 610 .

7 is a flowchart illustrating an operating method of a memory system according to an exemplary embodiment of the present invention. Referring to FIGS. 1 to 7 , an operation of the memory system 10 may proceed as follows.

Each of the ranks of the memory device 100 receives the 4-phase clock CK[3:0] from the controller 200 and detects an internal quad skew of the 4-phase clock CK[3:0]. It can (S110). In an embodiment, the detected internal quad skew may be stored in a mode register of each rank. Each of the ranks may correct the internal skew of the 4-phase clock (CK[3:0]) according to the detected internal quad skew (S120). The controller 200 may read quad skew information stored in the mode register of the memory device 100 and adjust the second skew of the 4-phase clock CK[3:0] in response to the quad skew information (S130). .

In an embodiment, skew directions of ranks may be determined through quad skew detection. In an embodiment, when the skew directions of the ranks are not the same, the quad skew detected in each of the ranks may be internally adjusted. In an embodiment, when skew directions of the ranks are the same, the controller may receive mode register information from each of the ranks and control the skew of the 4-phase clock using the mode register information. In an embodiment, the second channel may include a data pin or a command/address pin.

8 is a ladder diagram exemplarily illustrating a clock training process of a memory system according to an embodiment of the present invention. Referring to FIGS. 1 to 8 , a training process for a clock of a memory system may proceed as follows.

The control chip SoC may transmit a 4-phase clock to the memory device MEM (S10). The control chip SoC may request training for the 4-phase clock from the memory device MEM (S11). The memory device MEM may detect the quad skew of the 4-phase clock in response to the training request for the 4-phase clock (S12). The memory device MEM may adjust the internal quad skew according to the detected quad skew (S13). At the same time, the memory device MEM may store information corresponding to the common skew of the 4-phase clock (S14). The control chip SoC may read common skew information from the memory device MEM (S15). The control chip (SoC) may adjust the 4-phase clock using the common skew information (S16). The control chip SoC may output the adjusted 4-phase clock to the memory device MEM (S17).

9 is a diagram showing a memory module 1000 according to an embodiment of the present invention by way of example. Referring to FIG. 9 , the memory module 1000 includes a plurality of memory chips (DRAM) each including a memory cell array, a memory controller and a buffer chip (RCD) for routing transmission/reception signals or managing memory operations for the memory chips. ), and a power management chip (PMIC). The RCD may control the memory chips (DRAM) and the power management chip (PMIC) according to the control of the memory controller. For example, the RCD may receive a command signal, a control signal and a clock signal from a memory controller.

The memory chips DRAM may be connected to corresponding data buffers among the data buffers DB through corresponding data transmission lines to exchange data signals DQ and data strobe signals DQS. The memory chips DRAM may be connected to the data buffer DB through corresponding data transmission lines to transmit and receive parity data PRT and data strobe signal DQS.

The SPD chip (not shown) may be a programmable read only memory (EEPROM). The SPD chip may include initial information or device information of the memory module 1000 . For example, the SPD chip 580 may include initial information or device information such as the module type, module configuration, storage capacity, module type, and execution environment of the memory module 500 . When a memory system including the memory module 1000 is booted, the memory controller may read device information from the SPD chip and recognize the memory module based on the read device information.

The memory module 1000 may include a plurality of ranks. In an embodiment, each of the plurality of ranks may include 8 bank groups. Each of the bank groups may include 4 banks. In an embodiment, the memory chips may be divided into memory chips dedicated to a first channel and memory chips dedicated to a second channel.

On the other hand, as described in FIGS. 1 to 8, each of the plurality of ranks receives a 4-phase clock, detects quad skew, stores information about the detected quad skew, and outputs the stored quad skew information It may include a quad skew control circuit that does.

FIG. 10 is a diagram showing the memory device 1100 shown in FIG. 9 . Referring to FIG. 10 , a memory device 1100 includes a memory cell array 1110, a row decoder 1120, a column decoder 1130, a sense amplifier circuit 1140, an address register 1150, and a bank control logic 1152. ), refresh counter 1154, row address multiplexer 1156, column address latch 1158, control logic 1160, repair control circuit 1166, timing control circuit 1164, input/output gating circuit 1170, error A correction circuit 1180 and an input/output buffer 1190 may be included.

The memory cell array 1110 may include first to eighth banks 1111 to 1118 . Meanwhile, it should be understood that the number of banks of the memory cell array 1110 is not limited thereto. Each of the first to eighth banks 1111 to 1118 may include a plurality of memory cells MCs connected between word lines WLs and bit lines BLs. Here, each of the plurality of memory cells may be implemented as a volatile memory cell or a non-volatile memory cell.

The row decoder 1120 may include first to eighth bank row decoders 1121 to 128 respectively connected to the first to eighth banks 1111 to 1118 . The column decoder 1130 may include first to eighth bank column decoders 1131 to 1138 respectively connected to the first to eighth banks 1111 to 1118 . The sense amplifier circuit 1140 may include first to eighth bank sense amplifiers 1141 to 148 respectively connected to the first to eighth banks 1111 to 1118 . Meanwhile, the first to eighth banks 1111 to 1118 include the first to eighth bank row decoders 1121 to 128, the first to eighth bank column decoders 1131 to 1138, and the first to eighth bank row decoders 1121 to 128. It can be composed of 8 bank sense amplifiers (1141 to 1148).

The address register 1150 may receive and store an address ADDR having a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from an external memory controller. The address register 1150 provides the received bank address BANK_ADDR to the bank control logic 1152, the received row address ROW_ADDR to the row address multiplexer 1156, and the received column address COL_ADDR. column address latch 1158.

The bank control logic 1152 may generate bank control signals in response to the bank address BANK_ADDR. A bank row decoder corresponding to the bank address BANK_ADDR among the first to eighth bank row decoders 1121 to 1128 may be activated in response to the bank control signals. A bank column decoder corresponding to the bank address BANK_ADDR among the first to eighth bank column decoders 1131 to 1138 may be activated in response to the bank control signals.

The row address multiplexer 1156 may receive the row address ROW_ADDR from the address register 1150 and receive the refresh row address REF_ADDR from the refresh counter 1154 . The row address multiplexer 1156 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 1156 may be applied to the first to eighth bank row decoders 1121 to 1128, respectively.

A bank row decoder activated by the bank control logic 1152 among the first to eighth bank row decoders 1121 to 1128 decodes the row address RA output from the row address multiplexer 1156 and corresponds to the row address You can activate the word line to For example, the activated bank row decoder may apply a word line driving voltage to a word line corresponding to a row address. Also, the activated bank row decoder may activate a redundancy word line corresponding to a redundancy row address output from the repair control circuit 1166 simultaneously with activating a word line corresponding to the row address.

The column address latch 1158 may receive the column address COL_ADDR from the address register 1150 and temporarily store the received column address COL_ADDR. Also, the column address latch 1158 may incrementally increase the received column address COL_ADDR in a burst mode. The column address latch 1158 may apply the temporarily stored or gradually increased column address COL_ADDR to the first to eighth bank column decoders 1131 to 1138, respectively.

A bank column decoder activated by the bank control logic 1152 among the first to eighth bank column decoders 1131 to 1138 corresponds to the bank address BANK_ADDR and the column address COL_ADDR through the input/output gating circuit 1170 can activate the sense amp. Also, the activated bank column decoder may perform a column repair operation in response to a column repair signal output from a repair control circuit.

The control logic 1160 may be implemented to control the operation of the memory device 1100 . For example, the control logic 1160 may generate control signals to allow the semiconductor memory device 1100 to perform a write operation or a read operation. The control logic 1160 may include a command decoder 1161 to decode a command CMD received from the memory controller and a mode register set 1162 to set an operation mode of the memory device 1100 . For example, the command decoder 1161 decodes a write enable signal (/WE), a row address strobe signal (/RAS), a column address strobe signal (/CAS), a chip select signal (/CS), etc. CMD) may generate operation control signals ACT, PCH, WE, and RD. The control logic 1160 may provide operation control signals ACT, PCH, WE, and RD to the timing control circuit 1164 . The control signals ACT, PCH, WR, and RD may include an active signal ACT, a precharge signal PCH, a write signal WR, and a read signal RD.

Each of the input/output gating circuits of the input/output gating circuit 1170 includes circuits for gating input/output data, input data mask logic, and read data for storing data output from the first to eighth banks 1111 to 1118. Latches and write drivers for writing data to the first to eighth banks 1111 to 1118 may be included. A codeword (CW) to be read from one of the first to eighth banks 1111 to 1118 may be sensed by a sense amplifier corresponding to one bank and stored in read data latches. The codeword CW stored in the read data latches may be provided to the memory controller through the input/output buffer 1190 after ECC decoding is performed by the error correction circuit 1180 . Data DQ to be written to one bank among the first to eighth banks 1211 to 1218 may be written to one bank through write drivers after performing ECC encoding in the error correction circuit 1180 .

The error correction circuit 1180 (ECC1) generates parity bits based on the data bits of the data DQ provided from the input/output buffer 1190 in a write operation, and generates a code word including the data DQ and the parity bits. (code word) to the input/output gating circuit 1170, and the input/output gating circuit 1170 may write the codeword to the bank. Also, the error correction circuit 1180 may receive the codeword CW read from one bank in the read operation from the input/output gating circuit 1170 . The error correction circuit 1180 corrects at least one error bit included in the data DQ by performing ECC decoding on the data DQ using the parity bits included in the read codeword CW to input/output buffer ( 1190) can be provided.

The input/output buffer 1190 provides data DQ to the error correction circuit 1180 based on the clock CLK provided from the memory controller in a write operation, and provides data provided from the error correction circuit 1180 in a read operation. (DQ) to the memory controller.

11 is a block diagram illustrating a semiconductor package having a stacked structure including a plurality of layers according to an embodiment of the present invention. Referring to FIG. 11 , a semiconductor package 2000 may include a plurality of layers LA1 to LAn. Each of the first layer LA1 to the n−1 th layer LAn may be a memory layer (or memory chip) including a plurality of memory cores MC. The memory core MC may include a memory cell array for storing data, a row decoder, a column decoder, a sense amplifier circuit, and an error correction circuit.

The nth layer LAn may be a buffer layer (or buffer chip). In the semiconductor package 2000 , the layers LA1 to LAn of the stack structure may be interconnected through through silicon vias (TSVs) 2300 . The buffer layer LAn may communicate with the external memory controller and the memory layers LA1 to LAn-1 and route transmission/reception signals between the memory layers LA1 to LAn-1 and the memory controller. Furthermore, the buffer layer LAn may queue signals received from the memory controller or the memory layers LA1 to LAn-1. Also, the buffer layer LAn may include a training block 2200 . The buffer layer LAn may perform a training operation on the memory layers LA1 to LAn−1 using the training block 2200 . The training block 2200 receives the 4-phase clock, detects quad skew, internally adjusts the first quad skew, and externally adjusts the second quad skew as described in FIGS. 1-8. A quad skew control circuit outputting mode register information may be included.

12 is a diagram illustrating a semiconductor package according to an embodiment of the present invention. Referring to FIG. 12 , a semiconductor package 3000 includes at least one stacked semiconductor chip 3300 mounted on a package substrate 3100 such as a printed circuit board and a system-on-chip (SOC). It may be a memory module including 3400. An interposer 3200 may be selectively further provided on the package substrate 3100 . The stacked semiconductor chip 3300 may be formed of CoC (Chip-on-Chip). The stack semiconductor chip 3300 receives a 4-phase clock, detects a quad skew, internally adjusts a first quad skew, and externally adjusts a second quad skew, as described with reference to FIGS. 1 to 8 . In order to do so, a quad skew control circuit for outputting mode register information may be included.

The stacked semiconductor chip 3300 may include at least one memory chip 3320 stacked on a buffer chip 3310 such as a logic chip. The buffer chip 3310 and at least one memory chip 3320 may be connected to each other by through silicon vias (TSVs). The buffer chip 3310 may perform a training operation on the memory chip 3320 . The stacked semiconductor chip 3300 may be, for example, 500 GB/sec to 1 TB/sec, or higher bandwidth memory (HBM).

A semiconductor device according to an embodiment of the present invention has an interface for sending and receiving a 4-phase clock to input/output pins, detects a quad skew of the 4-phase clock, and compensates for the skew of the clock internally or externally according to the result. By compensating for the skew of the clock in , it is possible to secure the maximum timing margin in a system using a 4-phase clock.

A memory system according to an embodiment of the present invention is a system that transmits and receives data in synchronization with a 4-phase clock, and may include a semiconductor device that outputs a clock and a semiconductor device that receives a clock. In an embodiment, a semiconductor device receiving a clock may include a circuit for detecting or monitoring a quad skew of a 4-phase clock. In an embodiment, the result of detecting the skew of the clock is fed back to a semiconductor device that outputs the clock, or the semiconductor device that receives the clock internally compensates for the skew, and thus, the skew of the 4-phase clock is measured in the semiconductor device. Errors can be minimized. Accordingly, in the present invention, by minimizing the quad skew of the 4-phase clock, it is possible to maximize the timing margin of the circuit for exchanging data.

In a general memory system, in a system in which data is transmitted and received using a 4-phase clock, a problem such as a decrease in timing margin of a circuit that transmits and receives data, for example, a data sampling circuit, may occur due to a skew between clocks. The memory system according to an embodiment of the present invention maximizes the timing margin of data by correcting a skew error between 4-phase clocks having different phases in a semiconductor device that receives the clock or a semiconductor device that transmits the clock. can be secured

A memory device according to an embodiment of the present invention may detect an internal quad skew in a multi-rank system that exchanges a 4-phase clock using an I/O pin. In an embodiment, the memory device may have a circuit for compensating quad skew inside a memory device of an individual rank using output information corresponding to the detected quad skew. In an embodiment, the memory system may send the output information to the outside through a memory device I/O pin and adjust a common quad skew of each rank using the information.

Meanwhile, quad skew control of a 4-phase clock has been described in FIGS. 1 to 12 . However, the present invention need not be limited thereto. In a semiconductor device having an interface for transmitting and receiving a 4-phase clock to input/output pins, the present invention detects the duty of a 4-phase clock, internally compensates for a duty error according to the result, or monitors the clock externally to determine the duty By compensating for the error, the duty error in the 4-phase clock may be minimized.

A multi-rank system according to an embodiment of the present invention may include a semiconductor device that can both externally and internally adjust skew/duty errors between 4-phase clocks.

On the other hand, the above-described content of the present invention is only specific embodiments for carrying out the invention. The present invention will include technical ideas, which are abstract and conceptual ideas that can be utilized as technology in the future, as well as concrete and practically usable means themselves.

10: memory system
11: first channels
12: second channel
100: memory device
101: first rank
102: second rank
200: memory controller
110, 120: quad skew control circuit
111, 121: clock receiver
112, 122: quad skew monitor
113, 123: quad skew corrector
114, 124: mode register
MRR: mode register information

Claims (20)

a first rank having first memory banks and a first quad skew adjusting circuit; and
a second rank having second memory banks and a second quad skew adjusting circuit;
Each of the first quad skew control circuit and the second quad skew control circuit receives a 4-phase clock through first channels, detects an internal quad skew of the 4-phase clock, and detects the detected quad skew. The memory device characterized in that the skew of the 4-phase clock is corrected according to, and mode register information corresponding to the detected quad skew is output through a second channel. According to claim 1,
The quad skew common to the first rank and the second rank that share the 4-phase clock is removed from an external device using the mode register information. According to claim 1,
The memory device, characterized in that the quad skew is adjusted in different ways according to the skew direction of the first rank and the skew direction of the second rank. According to claim 3,
When a skew direction of the first rank and a skew direction of the second rank are the same, the quad skew is removed from an external device using the mode register information. According to claim 3,
When a skew direction of the first rank and a skew direction of the second rank are not the same, a common quad skew is removed from an external device using the mode register information. According to claim 5,
The memory device, characterized in that the remaining quad skew except for the common quad skew is removed in a corresponding quad skew control circuit. According to claim 1,
Each of the first quad skew control circuit and the second quad skew control circuit,
a clock receiver receiving the 4-phase clock;
a quad skew monitor that detects quad skew of the 4-phase clock output from the clock receiver;
a quad skew corrector adjusting the skew of the 4-phase clock according to the detected quad skew; and
and a mode register storing the mode register information corresponding to the detected quad skew. According to claim 7,
The quad skew monitor groups the 4-phase clock by 2 phases, generates clocks having a frequency twice the frequency of the 4-phase clock and having opposite phases using edge-to-edge, and receiving them, accumulating a duty through a charge pump, comparing the accumulated duty to determine a duty of each of the clocks, and detecting a skew between corresponding phase clocks using the duty. memory device. According to claim 7,
The quad skew monitor,
a logic circuit for receiving a first phase clock and a second phase clock among the 4-phase clocks and performing an XOR operation on the first phase clock and the second phase clock;
a phase separator for phase separating the output signal of the logic circuit; and
a duty cycle monitor detecting duty cycles corresponding to the first phase clock and the second phase clock from the output signal of the phase separator; and
and a skew detection unit configured to detect a skew between the first phase clock and the second phase clock in response to an output value of the duty cycle monitor. According to claim 9,
The quad skew corrector includes a skew correction unit correcting a skew of the first phase clock and the second phase clock using the skew detected by the skew detection unit, wherein the second phase clock determines the first phase clock A memory device characterized in that the quadrature phase of the clock. A method of operating a system including a multi-rank implemented memory device and a controller controlling the memory device,
detecting an inner quad skew of a 4-phase clock received on first channels from the controller at each of the ranks;
correcting a first skew of the 4-phase clock according to the detected inner quad skew at each of the ranks; and
and adjusting, in the controller, a second skew of the 4-phase clock using mode register information corresponding to the inner quad skew output through a second channel from each of the ranks. According to claim 11,
The step of detecting the inner quad skew,
and determining skew directions of the ranks. According to claim 11,
In the step of correcting the first skew,
and adjusting the detected quad skew at each of the ranks when the skew directions of the ranks are not equal. According to claim 11,
In the step of correcting the second skew,
receiving the mode register information from each of the ranks at the controller when skew directions of the ranks are the same; and
and controlling the skew of the 4-phase clock using the mode register information. According to claim 11,
wherein the second channel comprises a data pin or a command/address pin. a memory device for adjusting the first quad skew of the 4-phase clock; and
a controller controlling the memory device and controlling a second quad skew of the 4-phase clock;
The memory device,
Receiving the 4-phase clock from the controller through first channels, detecting a first inner quad skew of the 4-phase clock, and storing first mode register information corresponding to the first inner quad skew; a first rank outputting the first mode register information to the controller through a second channel; and
Receiving the 4-phase clock from the controller through the first channels, detecting a second inner quad skew of the 4-phase clock, and storing second mode register information corresponding to the second inner quad skew; , a second rank outputting the second mode register information to the controller through the second channel. 17. The method of claim 16,
The controller includes a quad skew controller,
The quad skew controller,
a clock transmitter outputting the 4-phase clock through the first channels; and
and a quad skew adjuster controlling the 4-phase clock using the first mode register information or the second mode register information. 18. The method of claim 17,
The first mode register information and the second mode register information include duty information corresponding to a skew between a first phase clock and a second phase clock among the 4-phase clocks. According to claim 18,
When the duty information indicates 50% or more, the quad skew adjuster divides a first period from the rising of the first phase clock to the rising of the second phase clock to the rising of the first phase clock to the rising of the second phase clock. A memory system, characterized in that equal to or greater than the second period until polling of the clock. According to claim 18,
When the duty information indicates less than 50%, the quad skew adjuster divides a first interval from the rising of the first phase clock to the rising of the second phase clock to the rising of the first phase clock to the rising of the second phase clock. A memory system characterized in that it is smaller than the second period until polling of the clock.

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