KR20230014613A - Memory device, memory system and operating method of memory device - Google Patents

Abstract

According to a technological idea of the present invention, a memory device comprises: a memory bank including a plurality of memory cells; and a memory interface circuit storing data in the plurality of memory cells based on a command/address signal and a data signal. The memory interface circuit includes: a first buffer circuit sampling the command/address signal by responding to the activation timing of a first clock signal and a third clock signal with opposite phases to each other among a first to fourth signals received through a first to fourth pads; and a second buffer circuit sampling the data signal by responding to the activation timing of the first to fourth clock signals. Therefore, a small size of a memory device can be provided.

Description

Memory device, memory system and method of operating the memory device

The technical idea of the present disclosure relates to a memory system, and more particularly, to a memory system including a memory controller and a memory device interfacing based on multiple clock signals.

Electronic devices such as smart phones, graphic accelerators, and AI accelerators may process data using a memory device such as dynamic random access memory (DRAM).

The memory device may receive a clock from a system on chip (SoC) and sample a command/address signal according to the clock. The memory device may receive a write clock separately from the clock from the SoC for high-speed data input/output. In general, the frequency of the write clock is higher than the frequency of the clock, and during a write operation, a certain amount of time may be required for synchronization between the write clock and the clock.

Technical features of the present disclosure may provide a memory system including a memory device and a memory controller interfacing a data signal and a command/address signal based on multi-phase clock signals.

In order to achieve the above object, a memory device according to an aspect of the present disclosure includes a memory bank including a plurality of memory cells and a memory storing data in the plurality of memory cells based on a command/address signal and a data signal. An interface circuit, wherein the memory interface circuit samples a command/address signal in response to activation timings of first and third clock signals having opposite phases among first to fourth clock signals received through first to fourth pads and a second buffer circuit for sampling a data signal in response to activation timings of first to fourth clock signals.

A memory system according to another aspect of the present disclosure includes a memory controller generating first to fourth clock signals having the same frequency and outputting the first to fourth clock signals, a data signal, and a command/address signal, and first to fourth clock signals. and a memory device for sampling a command/address signal based on first and third clock signals having opposite phases among signals and sampling a data signal based on first to fourth clock signals.

A method of operating a memory device according to another aspect of the present disclosure includes receiving first to fourth clock signals having the same frequency, a data signal, and a command/address signal, and sampling the data signal based on the first to fourth clock signals. sampling a command/address signal based on first and third clock signals having opposite phases among the first to fourth clock signals; and sampling the sampled data in a memory cell identified by the sampled command/address signal. and lighting the signal.

In the memory system according to an exemplary embodiment of the present disclosure, synchronization time between a clock and a write clock may be omitted by performing interfacing of a data signal and a command/address signal based on synchronized multi-phase clock signals.

In the memory device according to an exemplary embodiment of the present disclosure, a separate circuit for clock division may be omitted and a small-sized memory device may be provided by receiving multi-phase clock signals from a memory controller.

1 is a diagram for describing a memory system 10 according to an exemplary embodiment of the present disclosure.
2 is a block diagram illustrating a method of controlling a termination resistance according to an exemplary embodiment of the present disclosure.
3 is a flowchart illustrating a method of operating a memory system according to an exemplary embodiment of the present disclosure.
4A and 4B are timing diagrams illustrating DQ operation and CA operation according to exemplary embodiments of the present disclosure.
5 is a diagram illustrating a memory controller according to an exemplary embodiment of the present disclosure.
6A and 6B are diagrams illustrating multi-clock generation according to exemplary embodiments of the present disclosure.
7 is a block diagram illustrating a memory device according to an exemplary embodiment of the present disclosure.
8 is a block diagram illustrating a clock regulator 743 according to an exemplary embodiment of the present disclosure.
9A and 9B are timing diagrams illustrating clock adjustment according to exemplary embodiments of the present disclosure.
10 is a timing diagram illustrating a process of changing a terminating resistor according to an exemplary embodiment of the present disclosure.
11 is a timing diagram according to a write command according to an exemplary embodiment of the present disclosure.

Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a diagram for describing a memory system 10 according to an exemplary embodiment of the present disclosure.

Referring to FIG. 1 , a memory system 10 may include a memory controller 100 and a memory device 200 . The memory controller 100 may control overall operations of the memory device 200 . For example, the memory controller 100 may control the memory device 200 to output data from the memory device 200 or to store data in the memory device 200 . For example, the memory controller 100 may be implemented as a part of a system-on-chip (SoC), but is not limited thereto.

The memory controller 100 may include a host interface circuit 110 . The host interface circuit 110 may transmit first to fourth clock signals CK1 to CK4, a data input/output signal (hereinafter referred to as a DQ signal), and a command/address signal (hereinafter referred to as a CA signal) to the memory device 200. . Although the CA signal is shown as being transmitted to the memory device 200 through one signal line, the embodiment is not limited thereto, and the command signal and the address signal may be transmitted to the memory device 200 through separate signal lines. there is.

일 수 있다. 구체적으로, 제1 클럭 신호(CK1)의 위상은

이고, 제2 클럭 신호(CK2)의 위상은

이고, 제3 클럭 신호(CK3)의 위상은

이고, 제4 클럭 신호(CK4)의 위상은

일 수 있다. 멀티 클럭 생성기(111)는 PLL(Phase-Locked Loop) 회로 또는 DLL(Delay Lock Loop) 회로를 포함할 수 있다. 제1 내지 4 클럭 신호들(CK1 내지 CK4) 각각은 주기적으로 하이 레벨 및 로우 레벨 사이를 토글하는 신호일 수 있다. 제1 내지 4 클럭 신호들(CK1 내지 CK4)은 4-위상 클럭 신호들(4-phased clock signals)또는 다중 위상 클럭 신호들(multi-phased clock signals)로 지칭될 수 있다.The host interface circuit 110 may include a multi-clock generator 111 . The multi-clock generator 111 may generate first to fourth clock signals CK1 to CK4 having different phases. The embodiment is not limited thereto, and the multi-clock generator 111 may generate a plurality of clock signals having different phases. In some embodiments, the phase difference between the first to fourth clock signals CK1 to CK4 is

can be Specifically, the phase of the first clock signal CK1 is

, and the phase of the second clock signal CK2 is

, and the phase of the third clock signal CK3 is

, and the phase of the fourth clock signal CK4 is

can be The multi-clock generator 111 may include a phase-locked loop (PLL) circuit or a delay lock loop (DLL) circuit. Each of the first to fourth clock signals CK1 to CK4 may be a signal that periodically toggles between a high level and a low level. The first to fourth clock signals CK1 to CK4 may be referred to as 4-phased clock signals or multi-phased clock signals.

The memory device 200 may operate under the control of the memory controller 100 . For example, the memory device 200 may output stored data under the control of the memory controller 100 or store data provided from the memory controller 100 .

The memory device 200 may include a memory interface circuit 210 and a memory bank 220 . The memory interface circuit 210 may receive first to fourth clock signals CK1 to CK4 from the memory controller 100 . The memory interface circuit 210 may receive the CA signal and the DQ signal from the memory controller 100 .

일 수 있다. 이에 따라, 메모리 인터페이스 회로(210)는 CA 신호에 포함된 커맨드(CMD) 및/또는 어드레스(ADDR)를 획득할 수 있다. 메모리 인터페이스 회로(210)는 CA 버퍼(211)를 포함할 수 있다. 예를 들어, 도 1을 참조하면, CA 신호는 제1 및 제3 클럭 신호(CK1 및 CK3)에 기초하여 CA 버퍼(211)에 저장될 수 있다. 제1 내지 4 클럭 신호들(CK1 내지 CK4) 중 2개의 클럭 신호는 하이 임피던스(High-Z) 상태이고, 2개의 클럭 신호는 정상 상태인 모드는 2-위상 클럭 모드(2-phase clock mode)로 지칭될 수 있다. 2-위상 클럭 모드에서, 하이 임피던스(High-Z) 상태인 2개의 클럭 신호들 간의 위상 차이는

일 수 있다. 2-위상 클럭 모드에서, 정상 상태인 2개의 클럭 신호들은 하이 레벨과 로우 레벨 사이에서 토글할 수 있다.The memory interface circuit 210 may sample the CA signal based on toggle timings (eg, a rising edge and/or a falling edge) of two clock signals among the first to fourth clock signals CK1 to CK4. there is. The phase difference between the two clock signals is

can be Accordingly, the memory interface circuit 210 may obtain the command CMD and/or address ADDR included in the CA signal. The memory interface circuit 210 may include a CA buffer 211 . For example, referring to FIG. 1 , the CA signal may be stored in the CA buffer 211 based on the first and third clock signals CK1 and CK3. Among the first to fourth clock signals CK1 to CK4, two clock signals are in a high-impedance (High-Z) state, and a mode in which two clock signals are in a normal state is a 2-phase clock mode. can be referred to as In the 2-phase clock mode, the phase difference between the two clock signals in the high-impedance (High-Z) state is

can be In 2-phase clock mode, the two clock signals in steady state can toggle between a high level and a low level.

In some embodiments, the host interface circuit 110 may include first to fourth controller pads C1 to C4 to which the first to fourth clock signals CK1 to CK4 are transferred. The first to fourth controller pads C1 to C4 may be connected to first to fourth controller termination resistors ODT_C1 to ODT_C4, respectively.

In some embodiments, the host interface circuit 110 controls the impedance values of the first to fourth controller termination resistors ODT_C1 to ODT_C4 so that the first to fourth clock signals CK1 to CK4 are in a high impedance state or It can switch to normal state. For example, the host interface circuit 110 may switch the state of the second clock signal CK2 to a high impedance state by changing the impedance value of the second controller terminating resistor ODT_C2 to a high impedance state. When the impedance value of the second controller terminating resistor ODT_C2 is high impedance, the second clock signal CK2 may not periodically toggle between a high level and a low level.

In some embodiments, the memory interface circuit 210 controls the impedance values of the first to fourth memory termination resistors ODT_M1 to ODT_M4 so that the first to fourth clock signals CK1 to CK4 are in a high impedance state or It can switch to normal state. For example, the memory interface circuit 210 may switch the state of the second clock signal CK2 to a high impedance state by changing the impedance value of the second memory termination resistor ODT_M2 to a high impedance state. When the impedance value of the second memory termination resistor ODT_M2 is high impedance, the second clock signal CK2 may not periodically toggle between a high level and a low level.

However, the embodiment is not limited thereto, and in the 2-phase clock mode, various control signals (not shown) (eg, data bus inversion (DBI) and data parity (DPAR)) may be transmitted/received.

일 수 있다.The memory interface circuit 210 may sample the DQ signal based on toggle timings (eg, rising edges and/or falling edges) of the first to fourth clock signals CK1 to CK4 . Accordingly, the memory interface circuit 210 may obtain data DATA included in the DQ signal. The memory interface circuit 210 may include a DQ buffer 212 . For example, referring to FIG. 1 , DQ signals may be stored in the DQ buffer 212 based on first to fourth clock signals CK1 to CK4 . A mode in which all of the first to fourth clock signals CK1 to CK4 are in a normal state may be referred to as a 4-phase clock mode. That is, in the 4-phase clock mode, all of the first to fourth clock signals CK1 to CK4 may toggle between a high level and a low level. The phase difference between the first to fourth clock signals CK1 to CK4 is

can be

In some embodiments, in the 4-phase clock mode, the host interface circuit 110 may transmit all of the first to fourth clock signals CK1 to CK4 to the memory device 200 . That is, in the 4-phase clock mode, all of the first to fourth clock signals CK1 to CK4 may toggle. In the 4-phase clock mode, the host interface circuit 110 may transmit a DQ signal to the memory device 200 . In some embodiments, in the 4-phase clock mode, the CA signal may be in a high impedance (Hi-Z) state. In some embodiments, in the 4-phase clock mode, the host interface circuit 110 may send a CA signal to the memory device 200 . That is, in the 4-phase clock mode, the CA signal may be selectively transmitted to the memory device 200 . However, the embodiment is not limited thereto, and in the 4-phase clock mode, various control signals (not shown) (eg, Data Bus Inversion (DBI) and Data Parity (DPAR)) may be transmitted/received. .

In some embodiments, the frequencies of the first to fourth clock signals CK1 to CK4 may be the same. For example, the frequencies of the first to fourth clock signals CK1 to CK4 may be 1.6 GHz or 3.2 GHz. However, the present invention is not limited thereto, and the frequencies of the first to fourth clock signals CK1 to CK4 may vary.

The memory interface circuit 210 generates a control signal iCTRL based on the command CMD and address ADDR received from the memory controller 100 and provides the control signal iCTRL to the memory bank 220 . can For example, the control signal iCTRL may include a row address and a column address.

인 클럭 신호들(예를 들어, 제1 및 3 클럭 신호(CK1 및 CK3)를 기초로 CA 신호를 샘플링함으로써 CA 버퍼(211)에 데이터를 저장할 수 있다. 메모리 인터페이스 회로(210)는 CA 버퍼(211)에 저장된 데이터를 커맨드(CMD) 및 어드레스(ADDR)로 디코딩할 수 있다. 메모리 인터페이스 회로(210)는 디코딩된 커맨드(CMD) 및 어드레스(ADDR)를 기초로 제어 신호(iCTRL)를 생성할 수 있다. 다만, 실시예는 이에 제한되지 않으며, 메모리 인터페이스 회로(210)는 위상 차이가

인 제2 및 4 클럭 신호(CK2 및 CK4)를 기초로 CA 신호를 샘플링함으로써 CA 버퍼(211)에 데이터를 저장할 수도 있다.Specifically, the memory interface circuit 210 has a phase difference

Data may be stored in the CA buffer 211 by sampling the CA signal based on the in clock signals (eg, the first and third clock signals CK1 and CK3). The memory interface circuit 210 may include the CA buffer ( Data stored in 211) may be decoded into the command CMD and the address ADDR The memory interface circuit 210 may generate the control signal iCTRL based on the decoded command CMD and address ADDR. However, the embodiment is not limited thereto, and the memory interface circuit 210 has a phase difference

Data may be stored in the CA buffer 211 by sampling the CA signal based on the second and fourth clock signals CK2 and CK4.

The host interface circuit 110 may include a fifth controller pad C5 to which the DQ signal is transmitted, and the memory interface circuit 210 may include a fifth memory pad M5 to which the DQ signal is transmitted. The number of pads transmitting the DQ signal is not limited thereto.

The host interface circuit 110 may include a sixth controller pad C6 to which a CA signal is transmitted, and the memory interface circuit 210 may include a sixth memory pad M6 to which a CA signal is transmitted. The embodiment is not limited thereto, and a command signal and an address signal may be transmitted through different pads.

In some embodiments, the host interface circuit 110 may include a seventh controller pad C7 to which a read data strobe (RDQS) signal is transmitted, and the memory interface circuit 210 may include the RDQS signal may include a seventh memory pad M7 to which is transferred. The memory interface circuit 210 may provide the RDQS signal to the host interface circuit 110, and the host interface circuit 110 may sample the DQ signal based on the RDQS signal. The RDQS signal may be a signal that periodically toggles between a high level and a low level.

The memory bank 220 may include a plurality of memory cells connected to word lines and bit lines. For example, each of the plurality of memory cells may be a dynamic random access memory (DRAM) cell. In this case, the host interface circuit 110 and the memory interface circuit 210 may include double data rate (DDR), low power double data rate (LPDDR), graphics double data rate (GDDR), wide I/O, and high bandwidth HBM. Memory), HMC (Hybrid Memory Cube), and the like.

The memory bank 220 may write data DATA to memory cells or read data DATA from memory cells in response to the control signal iCTRL. Although not shown in FIG. 1 , the memory bank 220 may further include a row decoder, a column decoder, a sense amplifier, a write driver, and the like for write and read operations. The memory interface circuit 210 may store data in the DQ buffer 212 by sampling the DQ signal based on the first to fourth clock signals CK1 to CK4 . The memory interface circuit 210 may provide data stored in the DQ buffer 212 to a write driver.

The memory controller 100 and the memory device 200 according to an exemplary embodiment of the present disclosure may transmit/receive a CA signal and a DQ signal based on multi-phase clock signals.

According to an exemplary embodiment of the present disclosure, the DQ signal may be rapidly sampled based on multi-phase clock signals. Since the memory device 200 may directly receive the multi-phase clock signals from the memory controller 100, a component for generating the multi-phase clock signals may be omitted. In addition, since the memory device 200 samples the CA signal based on two clock signals among the multi-phase clock signals and samples the DQ signal based on the multi-phase clock signals, the timing at which the CA signal and the DQ signal are sampled can be synchronized. Accordingly, the memory device 200 may omit a synchronization operation for synchronizing sampling timings of the CA signal and the DQ signal.

2 is a block diagram illustrating a method of controlling a termination resistance according to an exemplary embodiment of the present disclosure.

Referring to FIG. 2 , the host interface circuit 1100 may include a controller pad C, and the memory interface circuit 2110 may include a memory pad M. The controller pad (C) and the memory pad (M) may be interconnected. The controller pad C may correspond to at least one of the first to seventh controller pads C1 to C7 in FIG. 1 , and the memory pad M may correspond to one of the first to seventh memory pads M1 to M7 in FIG. 1 . It may correspond to at least one.

The host interface circuit 1100 may include a transmitter 1110, and an output of the transmitter 1110 may be connected to the controller pad C. A controller terminating resistor ODT_C may be connected between the output of the transmitter 1110 and the controller pad C. The controller termination resistor ODT_C may be configured as a pull-down circuit connected to the VSS voltage, but the embodiment is not limited thereto. For example, the controller termination resistor ODT_C may be configured as a pull-up circuit connected to the VDD voltage.

In some embodiments, the host interface circuit 1100 may block the output of the transmitter 1110 from toggling by changing the impedance value of the controller termination resistor ODT_C to a high impedance. When the impedance value of the controller terminating resistor ODT_C has a high impedance, the output of the transmitter 1110 may be considered to be in a high impedance state. In some embodiments, when the impedance value of the controller terminating resistor ODT_C has a high impedance, it may be understood that the controller terminating resistor ODT_C is disabled. When the impedance value of the controller terminating resistor ODT_C has a high impedance, it may be understood that the controller terminating resistor ODT_C is turned off.

In some embodiments, the host interface circuit 1100 may transfer the output of the transmitter 1110 to the receiver 2110 by changing the impedance value of the controller termination resistor ODT_C to a predetermined value. When the impedance value of the controller terminating resistor ODT_C has a predetermined value, it may be understood that the output of the transmitter 1110 is in a normal state. In some embodiments, when the impedance value of the controller terminating resistor ODT_C has a predetermined value, it may be understood that the controller terminating resistor ODT_C is enabled. When the impedance value of the controller terminating resistor ODT_C has a predetermined value, it may be understood that the memory terminating resistor ODT_M is turned on.

The memory interface circuit 2100 may include a receiver 2110, and an input of the receiver 2110 may be connected to the memory pad M. A memory termination resistor ODT_M may be connected between the input of the receiver 2110 and the memory pad M. The memory termination resistor ODT_M may be configured as a pull-down circuit connected to the VSS voltage, but the embodiment is not limited thereto. For example, the memory termination resistor ODT_M may be configured as a pull-up circuit connected to the VDD voltage.

In some embodiments, the memory interface circuit 2100 may block transmission of the output of the transmitter 1110 to the receiver 2110 by changing the impedance value of the memory termination resistor ODT_M to a high impedance. When the impedance value of the memory termination resistor ODT_M has a high impedance, the output of the transmitter 1110 may be understood as a high impedance state. When the impedance value of the memory terminating resistor ODT_M has a high impedance, it may be understood that the memory terminating resistor ODT_M is disabled. When the impedance value of the memory termination resistor ODT_M has a high impedance, it may be understood that the memory termination resistor ODT_M is turned off.

In some embodiments, the memory interface circuit 2100 may transfer the output of the transmitter 1110 to the receiver 2110 by changing the impedance value of the memory termination resistor ODT_M to a predetermined value. When the impedance value of the memory termination resistor ODT_M has a predetermined value, it may be understood that the output of the transmitter 1110 is in a normal state. In some embodiments, when the impedance value of the memory termination resistor ODT_M has a predetermined value, it may be understood that the memory termination resistor ODT_M is enabled. When the impedance value of the memory termination resistor ODT_M has a predetermined value, it may be understood that the memory termination resistor ODT_M is turned on.

The host interface circuit 1100 may provide the memory interface circuit 2100 with a command indicating a change in the impedance value of the memory termination resistor ODT_M. Illustratively, the host interface circuit 110 may provide a command for changing the mode register value to the memory interface circuit 2100 through the sixth controller pad C6 of FIG. 1 , and the memory interface circuit 2100 may The impedance value of the memory termination resistor ODT_M may be changed in response to a command.

3 is a flowchart illustrating a method of operating a memory system according to an exemplary embodiment of the present disclosure. The method of operating the memory system may include a plurality of steps S310 to S340. FIG. 3 may be described later with reference to FIG. 1 .

의 위상 차이를 가질 수 있다. 구체적으로, 제1 클럭 신호(CK1)의 위상은

이고, 제2 클럭 신호(CK2)의 위상은

이고, 제3 클럭 신호(CK3)의 위상은

이고, 제4 클럭 신호(CK4)의 위상은

일 수 있다. 제1 내지 4 클럭 신호들(CK1 내지 CK4)의 주파수는 동일할 수 있다.In step S310, the memory controller 100 may generate multi-phase clock signals based on the reference clock signal. For example, the multi-clock generator 111 included in the memory controller 100 may generate first to fourth clock signals CK1 to CK4. The first to fourth clock signals CK1 to CK4 are mutually

may have a phase difference of Specifically, the phase of the first clock signal CK1 is

, and the phase of the second clock signal CK2 is

, and the phase of the third clock signal CK3 is

, and the phase of the fourth clock signal CK4 is

can be The frequencies of the first to fourth clock signals CK1 to CK4 may be the same.

In step S320, the memory controller 100 may identify whether a DQ signal is to be transmitted. In some embodiments, the memory controller 100 determines whether data is stored in a data register, whether a write command or a read command is provided to the memory device 200, or whether a write command or a read command is sent to the memory device 200. Whether or not the DQ signal is transmitted may be identified based on whether a predetermined time has elapsed after being provided. When the DQ signal is scheduled to be transmitted, step S330 may be performed, and when the DQ signal is not scheduled to be transmitted, step S340 may be performed.

인 클럭 신호들(예를 들어, 제1 클럭 신호(CK1) 및 제3 클럭 신호(CK3))는 CA 신호를 샘플링하기 위해 사용될 수 있다. 제1 내지 4 클럭 신호들(CK1 내지 CK4)은 DQ 신호를 샘플링하기 위해 사용될 수 있다.In step S330, the memory system 10 may operate in the 4-phase clock mode. In the 4-phase clock mode, the first to fourth clock signals CK1 to CK4 may be in a normal state. That is, the first to fourth clock signals CK1 to CK4 may periodically toggle between a high level and a low level. In some embodiments, the memory system 10 may operate in a 4-phase clock mode by the memory controller 100 controlling the first to fourth controller terminating resistors ODT_C1 to ODT_C4 to have a predetermined impedance value. there is. In some embodiments, the memory system 10 may operate in a 4-phase clock mode by the memory controller 100 controlling the first to fourth memory termination resistors ODT_M1 to ODT_M4 to have a predetermined impedance value. . The phase difference among the first to fourth clock signals CK1 to CK4 is

In clock signals (eg, the first clock signal CK1 and the third clock signal CK3) may be used to sample the CA signal. The first to fourth clock signals CK1 to CK4 may be used to sample the DQ signal.

In step S340, the memory system 10 may operate in the 2-phase clock mode. In the 2-phase clock mode, two clock signals among the first to fourth clock signals CK1 to CK4 may be in a normal state, and two clock signals may be in a high impedance state. For example, the first and third clock signals CK1 and CK3 may be in a normal state, and the second and fourth clock signals CK2 and CK4 may be in a high impedance state. A clock signal that is in a high impedance state may not periodically toggle between a high level and a low level. In some embodiments, the memory controller 100 controls the first and third controller terminating resistors ODT_C1 and ODT_C3 to have a predetermined impedance value, and sets the second and fourth controller terminating resistors ODT_C2 and ODT_C4 high. By controlling the impedance to have a value, the memory system 10 can operate in the 2-phase clock mode. In some embodiments, the memory controller 100 controls the first and third memory termination resistors ODT_M1 and ODT_ M3 to have a predetermined impedance value, and controls the second and fourth memory termination resistors ODT_M2 and ODT_M4 to have a predetermined impedance value. By controlling to have a high impedance value, the memory system 10 can operate in the 2-phase clock mode. Clock signals (eg, the first clock signal CK1 and the third clock signal CK3 ) in a steady state may be used to sample the CA signal.

According to the method of operating a memory system according to an exemplary embodiment of the present disclosure, power consumption due to a toggled clock signal may be reduced by changing a phase clock mode depending on whether a DQ signal is transmitted.

4A and 4B are timing diagrams illustrating DQ operation and CA operation according to exemplary embodiments of the present disclosure. 4a and 4b may be described later with reference to FIG. 1 .

4A may show a timing diagram of a 4-phase clock mode. Referring to FIG. 4A , the first to fourth clock signals CK1 to CK4 may be in a normal state. That is, the first to fourth clock signals CK1 to CK4 may periodically toggle between a high level and a low level, and each may have a period T. The frequencies of the first to fourth clock signals CK1 to CK4 may be the same.

The DQ buffer 212 may sample the DQ signal based on the first to fourth clock signals CK1 to CK4. For example, the DQ buffer 212 samples the first data D1 based on the first clock signal CK1 at a first time point t11 and samples the second clock signal CK2 at a second time point t12. ), sample the third data D3 based on the third clock signal CK3 at the third time point t13, and sample the fourth data D3 at the fourth time point t14. The fourth data D4 may be sampled based on the clock signal CK4 , and the fifth data D5 may be sampled based on the first clock signal CK1 at the fifth time point t15 .

The CA buffer 211 may sample the CA signal based on the first and third clock signals CK1 and CK3. For example, the CA buffer 211 samples the first CA information CA1 based on the first clock signal CK1 at the first time point t11, and samples the third clock signal (CA1) at the third time point t13. The second CA information CA2 may be sampled based on CK3), and the third CA information CA3 may be sampled based on the first clock signal CK1 at the fifth time point t15.

일 수 있다. 제2 및 4 클럭 신호(CK2 및 CK4)는 하이 임피던스 상태일 수 있다. 즉, 제2 및 4 클럭 신호(CK2 및 CK4)는 토글하지 않을 수 있다.4B may show a timing diagram of a 2-phase clock mode. Referring to FIG. 4B , first and third clock signals CK1 and CK3 may be in a normal state. That is, the first and third clock signals CK1 and CK3 may periodically toggle between a high level and a low level, and each may have a period T. The frequencies of the first and third clock signals CK1 and CK3 may be the same. The phase difference between the first and third clock signals CK1 and CK3 is

can be The second and fourth clock signals CK2 and CK4 may be in a high impedance state. That is, the second and fourth clock signals CK2 and CK4 may not toggle.

The CA buffer 211 may sample the CA signal based on the first and third clock signals CK1 and CK3. For example, the CA buffer 211 samples the first CA information CA1 based on the first clock signal CK1 at the first time point t21 and samples the third clock signal (CA1) at the second time point t22. The second CA information CA2 may be sampled based on CK3), and the third CA information CA3 may be sampled based on the first clock signal CK1 at the third time point t23.

5 is a diagram illustrating a memory controller according to an exemplary embodiment of the present disclosure.

Referring to FIG. 5 , the memory controller 100' includes a command/address generator 121, a command/address transmission buffer 120, a command/address transmitter 131, a multi-clock generator 140, and a clock transmitter 132. , RDQS receiver 133, multiplexer 136, data register 150, phase controller 160, DQ receive buffer 171, DQ transmit buffer 172, DQ receiver 134 and DQ transmitter 135 can include 5 may be described later with reference to FIG. 1 .

The command/address generator 121 may generate a command CMD and an address ADDR and provide them to the command/address transmission buffer 120 . The command/address transmission buffer 120 may provide the command CMD and address ADDR to the command/address transmitter 131 in synchronization with the first and third clock signals CK1 and CK3. The command/address transmitter 131 may provide the command CMD and address ADDR to the memory device 200 through the sixth controller pad C6.

일 수 있다. 제1 내지 4 클럭 신호들(CK1 내지 CK4)의 주파수는 동일할 수 있다. 클럭 송신기(132)는 제1 내지 4 컨트롤러 패드(C1 내지 C4)를 통해 제1 내지 4 클럭 신호들(CK1 내지 CK4)을 메모리 장치(200)에 제공할 수 있다. 클럭 송신기(132)가 하나인 것으로 도시되었으나, 실시예는 이에 제한되지 않으며, 클럭 신호마다 별도의 클럭 송신기가 구비될 수도 있다.The multi-clock generator 140 may include an oscillator 141 , a phase locked loop circuit 142 , and a phase divider 143 . The oscillator 141 may generate an oscillation signal, and the phase locked loop circuit 142 may generate a reference clock signal RCK in response to the oscillation signal. The phase locked loop circuit 142 may provide the reference clock signal RCK to the phase divider 143 . The phase divider 143 may generate first to fourth clock signals CK1 to CK4 based on the reference clock signal RCK. The phase difference between the first to fourth clock signals CK1 to CK4 is

can be The frequencies of the first to fourth clock signals CK1 to CK4 may be the same. The clock transmitter 132 may provide the first to fourth clock signals CK1 to CK4 to the memory device 200 through the first to fourth controller pads C1 to C4. Although one clock transmitter 132 is shown, the embodiment is not limited thereto, and a separate clock transmitter may be provided for each clock signal.

In some embodiments, the memory controller 100 ′ may adjust states of the first to fourth clock signals CK1 to CK4 according to the phase clock mode. Specifically, the memory controller 100' may adjust the states of the first to fourth clock signals CK1 to CK4 to a normal state in the 4-phase clock mode, and the first to fourth clock signals CK1 to CK4 in the 2-phase clock mode. The states of CK1 to CK4 may be adjusted to a high impedance state. Although not shown, first to fourth controller terminating resistors ODT_C1 to C4 may be respectively connected to the first to fourth controller pads C1 to C4 as shown in FIG. 1 . In some embodiments, the memory controller 100 may switch states of the first to fourth clock signals CK1 to CK4 by controlling the values of the first to fourth controller termination resistors DT_C1 to C4.

인 제1 내지 4 클럭 신호들(CK1 내지 CK4)이 메모리 장치(200)에 제공될 수 있으므로, 메모리 장치(200)는 클럭 신호를 분주하지 않더라도 DQ 신호를 샘플링할 수 있다.According to an exemplary embodiment of the present disclosure, the phase difference is

Since the first to fourth clock signals CK1 to CK4 may be provided to the memory device 200, the memory device 200 may sample the DQ signal without dividing the clock signal.

The multiplexer 136 may provide the first to fourth clock signals CK1 to CK4 to the phase controller 160 during DQ writing, and provide a read strobe signal RDQS to the phase controller 160 during DQ reading. can The RDQS receiver 133 may receive the read strobe signal RDQS from the memory device 200 through the seventh controller pad C7 and provide the read strobe signal RDQS to the multiplexer 136 .

The phase controller 160 may adjust the phases of the first to fourth clock signals CK1 to CK4 or the read strobe signal RDQS. The phase controller 160 may provide the first to fourth clock signals CK1 to CK4 to the DQ transmit buffer 172 and a read strobe signal RDQS to the DQ receive buffer 171 .

The DQ receiving buffer 171 may sample the DQ signal provided from the DQ receiver 134 in synchronization with the read strobe signal RDQS during DQ reading. The DQ reception buffer 171 may provide the sampled DQ signal to the data register 150 .

The DQ transmit buffer 172 may sample data provided from the data register 150 in synchronization with the first to fourth clock signals CK1 to CK4 during DQ writing. The DQ transmit buffer 172 may provide sampled data to the DQ transmitter 135 .

6A and 6B are diagrams illustrating multi-clock generation according to exemplary embodiments of the present disclosure. Specifically, FIG. 6A is a circuit diagram illustrating a phase divider, and FIG. 6B is a timing diagram of a multi-clock signal generated by the phase divider.

Referring to FIG. 6A , the phase divider 143 may include a first flip flop 61 and a second flip flop 62 . However, the structure of the phase divider 143 according to an exemplary embodiment of the present disclosure is not limited thereto.

)를 통해 제3 클럭 신호(CK3)를 출력할 수 있다. 제1 플립 플롭(61)은 기준 클럭 신호(RCK)에 응답하여 입력 단자(D1)의 값을 출력 단자(Q1)로 출력할 수 있다. 출력 단자(Q1)의 값과 출력 단자(

)의 값은 서로 반전된 관계일 수 있다. 제1 플립 플롭(61)은 리셋 신호에 응답하여 출력 단자(Q1)의 값을 로우 레벨로 리셋할 수 있고, 출력 단자(

)의 값을 하이 레벨로 리셋할 수 있다.The first flip-flop 61 receives the fourth clock signal CK4 through the input terminal D1, outputs the first clock signal CK1 through the output terminal Q1, and outputs the fourth clock signal CK1 through the output terminal (Q1).

) through which the third clock signal CK3 can be output. The first flip-flop 61 may output the value of the input terminal D1 to the output terminal Q1 in response to the reference clock signal RCK. The value of the output terminal (Q1) and the output terminal (

) may have an inverted relationship with each other. The first flip-flop 61 may reset the value of the output terminal Q1 to a low level in response to the reset signal, and the output terminal (

) can be reset to a high level.

)를 통해 제4 클럭 신호(CK4)를 출력할 수 있다. 제2 플립 플롭(62)은 기준 클럭 신호(RCK)에 응답하여 입력 단자(D2)의 값을 출력 단자(Q2)로 출력할 수 있다. 출력 단자(Q2)의 값과 출력 단자(

)의 값은 서로 반전된 관계일 수 있다. 제2 플립 플롭(62)은 리셋 신호에 응답하여 출력 단자(Q2)의 값을 로우 레벨로 리셋할 수 있고, 출력 단자(

)의 값을 하이 레벨로 리셋할 수 있다.The second flip-flop 62 receives the first clock signal CK1 through the input terminal D2, outputs the second clock signal CK2 through the output terminal Q2, and outputs the output terminal (

) through which the fourth clock signal CK4 can be output. The second flip flop 62 may output the value of the input terminal D2 to the output terminal Q2 in response to the reference clock signal RCK. The value of the output terminal (Q2) and the output terminal (

) may have an inverted relationship with each other. The second flip-flop 62 may reset the value of the output terminal Q2 to a low level in response to the reset signal, and the output terminal (

) can be reset to a high level.

,

)를 리셋할 수 있다. 즉, 제1 시점(t31)에 제1 및 3 클럭 신호(CK1, CK3)는 로우 레벨이고, 제2 및 4 클럭 신호(CK2, CK4)는 하이 레벨일 수 있다.Referring to FIG. 6B, the first and second flip-flops 61 and 62 initially output terminals Q1 and Q2 in response to a reset signal.

,

) can be reset. That is, at the first time point t31, the first and third clock signals CK1 and CK3 may be at low levels, and the second and fourth clock signals CK2 and CK4 may be at high levels.

At the second time point t32, the first flip-flop 61 may output the value of the input terminal D1 to the output terminal Q1 in response to the reference clock signal RCK. Accordingly, at the second time point t32, the first clock signal CK1 may transition to a high level.

At the third time point t33, the second flip-flop 62 may output the value of the input terminal D1 to the output terminal Q2 in response to the reference clock signal RCK. Accordingly, the second clock signal CK2 may transition to a high level at the second time point t32.

At a fourth time point t34 , the first flip-flop 61 may output the value of the input terminal D1 to the output terminal Q1 in response to the reference clock signal RCK. Accordingly, at the fourth time point t34, the first clock signal CK1 may transition to a low level.

At the fifth time point t35, the second flip-flop 62 may output the value of the input terminal D1 to the output terminal Q2 in response to the reference clock signal RCK. Accordingly, at the fifth time point t35, the second clock signal CK2 may transition to a low level.

The timing diagram from the sixth time point t36 to the second to fifth time points t2 to t5 may be repeated.

7 is a block diagram illustrating a memory device according to an exemplary embodiment of the present disclosure.

Referring to FIG. 7, the memory device 200' includes a CA receiver 711, a CA buffer 712, a command/address decoder 713, a decoder 714, a mode register circuit 720, a terminating resistance control circuit ( 730), clock receiver circuit 741, clock buffer 742, clock regulator 743, RDQS transmitter 744, DQ receiver 751, DQ receive buffer 752, DQ transmitter 753, DQ transmit buffer 754, a memory bank 761, a write driver 762, and a sense amplifier 763. FIG. 7 may be described later with reference to FIG. 1 .

인 제2 클럭 신호(CK2) 및 제4 클럭 신호(CK4)를 기초로 CA 신호를 샘플링할 수도 있다. CA 버퍼(712)는 샘플링한 CA 데이터를 커맨드/어드레스 디코더(713)에 제공할 수 있다.The CA receiver 711 may receive the CA signal and provide the CA signal to the CA buffer 712 . The CA buffer 712 may sample the CA signal based on the first and third clock signals CK1 and CK3. The embodiment is not limited thereto, and the CA buffer 712 has a phase difference

The CA signal may be sampled based on the second clock signal CK2 and the fourth clock signal CK4. The CA buffer 712 may provide sampled CA data to the command/address decoder 713 .

The command/address decoder 713 may decode a command CMD or an address ADDR from CA data. For example, the command decoder 123 may decode a read command, a write command, a mode register write command (MRW), a mode register read command (MRR), a row address, a column address, and the like. The command/address decoder 713 may provide the decoded result to the decoder 714 or the mode register circuit 720.

Decoder 714 can decode row addresses and column addresses. The decoder 714 may select or activate at least one word line corresponding to the row address. The decoder 714 may select or activate at least one bit line corresponding to the column address.

The mode register circuit 720 may be configured to store various information required for the operation of the memory device 200'. For example, the mode register circuit 720 may include a plurality of mode registers. Each of the plurality of mode registers may be configured to store predetermined information. For example, the first mode register may be configured to store information about an impedance value of at least one of the first to fourth memory termination resistors ODT_M1 to ODT_M4.

For example, the second mode register may be configured to store information about duty cycles of the first to fourth clock signals CK1 to CK4. For example, the third mode register may be configured to store skew compensation information of the first to fourth clock signals CK1 to CK4.

The terminating resistor control circuit 730 changes the impedance values of the first to fourth memory terminating resistors ODT_M1 to ODT_M4 based on information stored in the mode register circuit 720 (eg, information stored in the first mode register). can Specifically, the terminating resistor control circuit 730 may change the impedance values of the second and fourth memory terminating resistors ODT_M2 and ODT_M4 to high impedance in response to the mode register write command MRW indicating the 2-phase clock mode, Impedance values of the first and third memory termination resistors ODT_M1 and ODT_M3 may be changed to predetermined values. The terminating resistor control circuit 730 may change the impedance values of the first to fourth memory terminating resistors ODT_M1 to ODT_M4 to predetermined values in response to the mode register write command MRW indicating the 4-phase clock mode.

The clock receiver circuit 741 may receive the first to fourth clock signals CK1 to CK4 through the first to fourth memory pads M1 to M4. A separate receiver may be provided for each of the first to fourth clock signals CK1 to CK4. The clock buffer 742 may sample the first to fourth clock signals CK1 to CK4 based on a separate clock signal (not shown).

The clock adjuster 743 adjusts the first to fourth clock signals CK1 to CK4 based on information stored in the mode register circuit 720 (for example, information stored in the second or third mode register) to control the first to fourth clock signals CK1 to CK4. 4 internal clock signals (ICK1 to ICK4) can be generated. The clock adjuster 743 may be described in detail later with reference to FIG. 8 .

The memory bank 761 may include a plurality of memory cells respectively connected to word lines and bit lines. Each of the plurality of memory cells may be configured to store data under the control of the write driver 762 or output stored data under the control of the sense amplifier 763 .

The RDQS transmitter 744 may provide the first to fourth internal clock signals ICK1 to ICK4 to the memory controller 100 through the seventh memory pad M7 .

The DQ receiver 751 may receive the DQ signal from the memory controller 100 through the fifth memory pad M5. The DQ transmitter 753 may transmit a DQ signal to the memory controller 100 through the fifth memory pad M5.

The DQ reception buffer 752 may sample the DQ signal in response to the first to fourth internal clock signals ICK1 to ICK4. In some embodiments, the clock regulator 743 may be omitted, and the DQ receive buffer 752 receives the DQ signal in response to the first to fourth clock signals CK1 to CK4 received from the clock buffer 742. You can also sample. The DQ receive buffer 752 may provide sampled data to the write driver 762 .

The DQ transmit buffer 754 may sample data received from the sense amplifier 763 in response to first to fourth internal clock signals ICK1 to ICK4 . In some embodiments, clock coordinator 743 may be omitted, and DQ transmit buffer 752 samples data in response to first to fourth clock signals CK1 to CK4 received from clock buffer 742. You may. The DQ transmit buffer 754 may provide the sampled data to the DQ transmitter 753.

8 is a block diagram illustrating a clock regulator 743 according to an exemplary embodiment of the present disclosure.

Referring to FIG. 8 , the clock adjuster 743 may include a duty cycle adjuster 810 and a skew adjuster 820 . The clock adjuster 743 may receive first to fourth clock signals CK1 to CK4 and generate first to fourth internal clock signals ICK1 to ICK4.

The duty cycle adjuster 810 may adjust the duty cycles of the first to fourth clock signals CK1 to CK4. For example, the duty cycle adjuster 810 may adjust the duty cycles of the first to fourth clock signals CK1 to CK4 to 50%.

인 제1 내지 4 내부 클럭 신호들(ICK1 내지 ICK4)을 생성할 수 있다.The skew adjuster 820 adjusts the skew between the first to fourth clock signals CK1 to CK4 of which the duty cycle is adjusted, so that the phase difference is

The first to fourth internal clock signals ICK1 to ICK4 may be generated.

9A and 9B are timing diagrams illustrating clock adjustment according to exemplary embodiments of the present disclosure. Specifically, FIG. 9A is a timing diagram illustrating duty cycle adjustment, and FIG. 9B is a timing diagram illustrating skew adjustment. 9A and 9B may be described later with reference to FIGS. 7 and 8 .

Referring to FIG. 9A , the duty cycle adjuster 810 may generate the first adjusted clock signal DCK1 by adjusting the duty ratio of the first clock signal CK1. The duty ratio of the first clock signal CK1 may be 30%, and the duty ratio of the first adjusted clock signal DCK1 may be 50%. The duty ratio may refer to a ratio of time during which a logic high level is maintained within one cycle. The duty ratio between the first clock signal CK1 and the first adjusted clock signal DCK1 is not limited thereto. Although only the first clock signal CK1 is shown, the duty cycle adjuster 810 adjusts the duty ratio of the second to fourth clock signals CK2 to CK4 to adjust the second to fourth adjusted clock signals DCK2 to DCK4. can also create

와 상이할 수 있다. 스큐 조정기(820)는 제1 내지 4 조정된 클럭 신호들(DCK1 내지 DCK4)의 타이밍 스큐를 보상함으로써 제1 내지 4 내부 클럭 신호(ICK1 내지 ICK4)를 생성할 수 있다. 예를 들어, 스큐 조정기(820)는 제1 조정된 클럭 신호(DCK1)로부터 제1 스큐(SK1)를 식별하고, 제1 스큐(SK1)를 보상함으로써 제1 내부 클럭 신호(ICK1)를 생성할 수 있다. 제1 내지 4 스큐(SK1 내지 SK4)가 보상됨으로써 제1 내지 4 내부 클럭 신호들(ICK1 내지 ICK4) 간의 위상 차이는

일 수 있다.Referring to FIG. 9B , the phase difference between the first to fourth clock signals DCK1 to DCK4 adjusted by the first to fourth timing skews SK1 to SK4 is

may differ from The skew adjuster 820 may generate the first to fourth internal clock signals ICK1 to ICK4 by compensating for the timing skew of the first to fourth adjusted clock signals DCK1 to DCK4 . For example, the skew adjuster 820 may generate a first internal clock signal ICK1 by identifying a first skew SK1 from the first adjusted clock signal DCK1 and compensating for the first skew SK1. can As the first to fourth skews SK1 to SK4 are compensated, the phase difference between the first to fourth internal clock signals ICK1 to ICK4 is

can be

10 is a timing diagram illustrating a process of changing a terminating resistor according to an exemplary embodiment of the present disclosure. FIG. 10 may be described later with reference to FIG. 1 or FIG. 7 .

Referring to FIG. 10 , at a first time point t41 , the terminating resistor ODT may have an old setting value. The termination resistors ODT may correspond to the first to fourth controller termination resistors ODT_C1 to ODT_C4 of FIG. 1 or to the first to fourth memory termination resistors ODT_M1 to M4. At the first time point t41 , the memory system 10 may operate in the 2-phase clock mode. Accordingly, in some embodiments, the first and third controller terminating resistors ODT_C1 and ODT_C3 may have predetermined impedance values so that the first and third clock signals CK1 and CK3 are in a steady state. In some embodiments, the first and third memory termination resistors ODT_M1 and ODT_M3 may have predetermined impedance values so that the first and third clock signals CK1 and CK3 are in a steady state. Also, in some embodiments, the second and fourth controller termination resistors ODT_C2 and ODT_C4 may have a high impedance value so that the second and fourth clock signals CK2 and CK4 are in a high impedance (Hi-Z) state. . In some embodiments, the second and fourth memory termination resistors ODT_M2 and ODT_M4 may have high impedance values so that the second and fourth clock signals CK2 and CK4 are in a high impedance (Hi-Z) state.

The memory controller 100 may provide CA signals indicating the first MRW command MRW1 and the second MRW command MRW2 to the memory device 200 . The MRW command is a mode register write command, and may be a command for changing a setting value of a mode register included in the memory device 200 . For example, the MRW command may be a command for changing a setting value of a mode register storing information on an impedance value of at least one of the first to fourth memory termination resistors ODT_M1 to ODT_M4. In some embodiments, the MRW command may be a command for changing a setting value of a mode register that stores the duty cycles of the first to fourth clock signals CK1 to CK4 . In some embodiments, the MRW command may be a command for changing a set value of a mode register storing skew compensation information of the first to fourth clock signals CK1 to CK4.

At the first time point t41, the CA buffer 211 may sample the first MRW command MRW1 based on the first and third clock signals CK1 and CK3, and at the second time point t42, the CA buffer 211 may sample the first MRW command MRW1. And the second MRW command MRW2 may be sampled based on the three clock signals CK1 and CK3.

The setting value of the terminating resistor ODT may be updated from the third time point t43 to the fourth time point t44. For example, the terminating resistor control circuit 730 of the memory device 200' of FIG. 7 may change the impedance values of the first to fourth memory terminating resistors ODT_M1 to ODT_M4. At the fourth time point t44 , the termination resistor ODT may have a new setting value. The fourth time point t44 may be a time point when the terminating resistor update time tODTUP from the second time point t42 elapses. States of the second and fourth clock signals CK2 and CK4 may transition from a high impedance state to a normal state from the third time point t43 to the fourth time point t44 . At the fourth time point t44, the second and fourth clock signals CK2 and CK4 may toggle between a high level and a low level. Accordingly, at the fourth time point t44, the memory system 10 may operate in the 4-phase clock mode.

Although it has been described that the memory system 10 is in the 2-phase clock mode at the first time point t41 and the memory system 10 is in the 4-phase clock mode at the fourth time point t44, the embodiment is not limited thereto. . In some embodiments, the memory system 10 may be in the 4-phase clock mode at the first time point t41, and the memory system 10 may be in the 2-phase clock mode at the fourth time point t44. That is, the second and fourth clock signals CK2 and CK4 may be in a normal state at the first time point t41, and the second and fourth clock signals CK2 and CK4 may be in a high impedance state at the fourth time point t44. .

In some embodiments, after the fourth time point t44, the clock adjuster 743 performs a clock adjustment operation for the first to fourth clock signals CK1 to CK4 described above with reference to FIGS. 9A and 9B. can

11 is a timing diagram according to a write command according to an exemplary embodiment of the present disclosure. 11 may be described later with reference to FIG. 1 or FIG. 7 .

Referring to FIG. 11 , at a first time point t52 , the CA buffer 712 may sequentially sample the first write command WR1 and the second write command WR2 . At the first time point t52 , the termination resistors ODT (eg, the first to fourth memory termination resistors ODT_M1 to ODT_M4 ) may have a preset value. The existing setting value is described as a high impedance value, but the embodiment is not limited thereto.

From the second time point t52 to the third time point t53, the setting value of the terminating resistor ODT may be updated. For example, the terminating resistor control circuit 730 of the memory device 200' of FIG. 7 may change the impedance values of the first to fourth memory terminating resistors ODT_M1 to ODT_M4. From the third point in time t53, the terminating resistor ODT may have a new setting value. The third time point t53 may be a time point when the write clock delay time tCKL_WR has elapsed from the first time point t51 . States of the second and fourth clock signals CK2 and CK4 may transition from a high impedance state to a normal state from the second time point t52 to the third time point t53. From the third point in time t53, the second and fourth clock signals CK2 and CK4 may be toggled between a high level and a low level. Accordingly, at the third point in time t53, the memory system 10 may operate in the 4-phase clock mode.

In some embodiments, after the third time point t53, the clock adjuster 743 performs a clock adjustment operation for the first to fourth clock signals CK1 to CK4 described above with reference to FIGS. 9A and 9B. can

As above, exemplary embodiments have been disclosed in the drawings and specifications. Although the embodiments have been described using specific terms in this specification, they are only used for the purpose of explaining the technical idea of the present disclosure, and are not used to limit the scope of the present disclosure described in the claims. . Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical scope of protection of the present disclosure should be determined by the technical spirit of the appended claims.

Claims (20)

a memory bank including a plurality of memory cells; and
a memory interface circuit for storing data in the plurality of memory cells based on a command/address signal and a data signal;
The memory interface circuit,
a first buffer circuit for sampling the command/address signal in response to activation timings of first and third clock signals having opposite phases among first to fourth clock signals received through first to fourth pads; and
and a second buffer circuit sampling the data signal in response to activation timings of the first to fourth clock signals. According to claim 1,
The first to fourth clock signals have the same frequency,
The phase difference between the first clock signal and the second clock signal is

ego,
The phase difference between the first clock signal and the third clock signal is

ego,
The phase difference between the first clock signal and the fourth clock signal is

In-memory device. According to claim 1,
The second and fourth clock signals,
A memory device that changes to a high-impedance state or a normal state depending on the phase mode. According to claim 3,
The memory interface circuit,
Further comprising first to fourth termination resistors connected to the first to fourth pads,
The second and fourth terminating resistors connected to the second and fourth pads,
A memory device that is disabled or enabled depending on the phase clock mode. According to claim 4,
The memory interface circuit,
A memory device that enables the disabled second and fourth terminating resistors for a first reference time in response to a write command. According to claim 4,
When the second and fourth termination resistors are disabled, the second and fourth clock signals are in the high impedance state;
When the second and fourth termination resistors are enabled, the second and fourth clock signals are in the normal state. According to claim 4,
The memory interface circuit,
a first mode register storing information on impedance values of the first to fourth terminating resistors; and
and a terminating resistor control circuit configured to change impedance values of the first to fourth terminating resistors based on the information stored in the first mode register. According to claim 1,
The memory interface circuit,
a second mode register for storing information on duty cycles of the first to fourth clock signals; and
and a clock adjuster configured to adjust duty cycles of the first to fourth clock signals based on the information stored in the second mode register. According to claim 8,
The memory interface circuit,
Further comprising a third mode register for storing information on the timing skew of the first to fourth clock signals,
The clock regulator,
A memory device compensating for timing skew of the first to fourth clock signals based on information stored in the third mode register. According to claim 9,
The second buffer circuit,
a data reception buffer sampling data received through a fifth pad in response to activation timings of the first to fourth clock signals; and
and a data transmission buffer sampling data read from the memory bank in response to activation timings of the first to fourth clock signals. a memory controller generating first to fourth clock signals having the same frequency and outputting the first to fourth clock signals, a data signal, and a command/address signal; and
A memory device configured to sample the command/address signal based on the first and third clock signals having opposite phases among the first to fourth clock signals, and to sample the data signal based on the first to fourth clock signals. A memory system comprising a. According to claim 11,
The phase difference between the first clock signal and the second clock signal is

ego,
The phase difference between the first clock signal and the third clock signal is

ego,
The phase difference between the first clock signal and the fourth clock signal is

In-memory system. According to claim 12,
The memory controller,
a first flip-flop that receives the fourth clock signal at an input terminal and outputs the first clock signal and the third clock signal having an opposite phase to the first clock signal in response to a reference clock signal; and
And a second flip-flop that receives the first clock signal at an input terminal and outputs the second clock signal and the fourth clock signal having an opposite phase to the second clock signal in response to the reference clock signal. memory system. According to claim 11,
The memory controller,
A memory system operating in one of a 4-phase clock mode or a 2-phase clock mode based on whether the data signal is to be transmitted to the memory device. According to claim 14,
The memory device,
first to fourth controller pads to which the first to fourth clock signals are transmitted; and
Further comprising first to fourth controller termination resistors connected to the first to fourth controller pads,
The memory controller,
In the 4-phase clock mode, all of the first to fourth controller termination resistors are enabled, and in the 2-phase clock mode, the second and fourth controller termination resistors are disabled. According to claim 11,
The memory device,
a duty cycle adjuster adjusting duty cycles of the first to fourth clock signals; and
and a skew adjuster compensating for a timing skew of the first through fourth clock signals. receiving first to fourth clock signals, a data signal, and a command/address signal having the same frequency;
sampling the data signal based on the first to fourth clock signals;
sampling the command/address signal based on the first and third clock signals having opposite phases among the first to fourth clock signals; and
A method of operating a memory device, comprising writing a sampled data signal to a memory cell identified by the sampled command/address signal. According to claim 17,
The phase difference between the first clock signal and the second clock signal is

ego,
The phase difference between the first clock signal and the third clock signal is

ego,
The phase difference between the first clock signal and the fourth clock signal is

A method of operating an in-memory device. According to claim 17,
receiving a command; and
and adjusting impedance values of first to fourth terminating resistors connected to first to fourth memory pads to which the first to fourth clock signals are transmitted in response to the command. According to claim 19,
The step of adjusting the impedance values of the first to fourth terminating resistors,
maintaining the first and third terminating resistors in an enabled state; and
and changing the second and fourth terminating resistors from a disabled state to an enabled state within a reference time from when the command is received.

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