KR20230011214A - Storage device and operating method thereof - Google Patents

Abstract

In accordance with an embodiment of the present invention, a storage device includes: a memory device; and a memory controller receiving a read command from an external host, and controlling the memory device in accordance with the read command. The read command, includes: a basic header segment commonly included in commands transmitted and received between the external host and the memory controller, and including information indicating that the read command is a command requesting data stored in the memory device; a transaction specification field including information indicating that the read command is a read command for at least two logical addresses; and an additional header segment including information about the at least two logical addresses. Therefore, the present invention is capable of reading a plurality of logical addresses.

Description

Storage device and its operating method {STORAGE DEVICE AND OPERATING METHOD THEREOF}

The present invention relates to an electronic device, and more particularly, to a storage device and an operating method thereof.

The storage device is a device that stores data under the control of a host device such as a computer or smart phone. The storage device may include a memory device that stores data and a memory controller that controls the memory device. Memory devices may be classified into volatile memory devices and non-volatile memory devices.

A volatile memory device may be a memory device that stores data only while power is supplied and the stored data disappears when power is cut off. Volatile memory devices may include static random access memory (SRAM), dynamic random access memory (DRAM), and the like.

A non-volatile memory device is a memory device in which data is not destroyed even when power is cut off, and includes Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable and Programmable ROM (EEPROM), and Flash. Flash memory, etc.

An embodiment of the present invention provides a storage device capable of performing a read operation on a plurality of logical addresses and an operation method thereof.

A storage device according to an embodiment of the present invention includes a memory device; and a memory controller that receives a read command from an external host and controls the memory device according to the read command, wherein the read command is commonly included in commands transmitted and received between the external host and the memory controller. , a basic header segment including information indicating that the read command is a command requesting data stored in the memory device; a transaction specific field including information indicating that the read command is a read command for at least two or more logical addresses; and an additional header segment including information about the at least two or more logical addresses.

An operating method according to an embodiment of the present invention is an operating method of a storage device including a memory device and a memory controller controlling the memory device, which is commonly included in commands transmitted and received between an external host and the memory controller, A basic header segment including information indicating that the read command is a read command requesting data stored in the memory device, a transaction specific field including information indicating that the read command is a read command for at least two or more logical addresses, and the at least two or more logical addresses receiving, by the memory controller, a read command including an additional header segment including information about the memory from an external host; and performing a read operation based on information about the at least two or more logical addresses.

A memory controller according to an embodiment of the present invention is a memory controller that controls a memory device, and includes a map data storage unit that stores mapping information between a logical address and a physical address of data stored in the memory device; a read request processor receiving a read request from an external host and acquiring a physical address corresponding to one or more logical addresses included in the read request from the map data storage unit; and a read operation controller configured to provide a read command for a physical address corresponding to the at least one logical address to the memory device, wherein the read request is common to requests transmitted and received between the external host and the memory controller. and a basic header segment including information indicating that the read request is a request for data stored in the memory device, and a transaction specific field including information indicating that the read request is a read request for at least two or more logical addresses. and an additional header segment including information about the at least two or more logical addresses.

The present technology provides a storage device capable of performing read operations on a plurality of logical addresses and an operation method thereof.

1 is a diagram for explaining a storage device according to an exemplary embodiment of the present invention.
FIG. 2 is a diagram for explaining the memory device of FIG. 1 .
FIG. 3 is a diagram for explaining the structure of one memory block among the memory blocks of FIG. 2 .
4 is a diagram for explaining a data communication unit between a host and a memory controller.
5 is a diagram for explaining the structure of a basic header segment of a protocol unit included in a command.
6 is a diagram illustrating an embodiment of a command protocol unit (Command PIU) included in a command.
7 is a diagram for explaining the structure of a lead (6) command descriptor block.
8 is a diagram for explaining the structure of a lead (10) command descriptor block.
9 is a diagram for explaining the structure of a lead 16 command descriptor block.
10 is a diagram illustrating an additional header segment according to an embodiment of the present invention.
11 is a diagram for describing a memory controller according to an exemplary embodiment of the present invention.
12 is a flowchart illustrating a method of operating a storage device according to an exemplary embodiment.
13 is a flowchart illustrating a multi-read operation of a storage device according to an embodiment of the present invention.
14 is a flowchart illustrating a normal read operation of a storage device according to an embodiment of the present invention.
15 is a diagram explaining a data providing sequence of a storage device according to an embodiment of the present invention.
16 is a diagram illustrating another embodiment of the memory controller of FIG. 1 .
17 is a block diagram showing a memory card system to which a storage device according to an embodiment of the present invention is applied.
18 is a block diagram illustrating a solid state drive (SSD) system to which a storage device according to an embodiment of the present invention is applied.
19 is a block diagram illustrating a user system to which a storage device according to an embodiment of the present invention is applied.

Specific structural or functional descriptions of the embodiments according to the concept of the present invention disclosed in the present specification or application are only exemplified for the purpose of explaining the embodiment according to the concept of the present invention, and the implementation according to the concept of the present invention Examples may be embodied in many forms and should not be construed as limited to the embodiments described in this specification or application.

1 is a diagram for explaining a storage device according to an exemplary embodiment of the present invention.

Referring to FIG. 1 , a storage device 50 may include a memory device 100 and a memory controller 200 . The storage device 50 stores data under the control of the host 400, such as a mobile phone, smart phone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system. It may be a device that Alternatively, the storage device 50 may be a device that stores data under the control of the host 400 that stores high-capacity data in one place, such as a server or data center.

The storage device 50 may be manufactured as one of various types of storage devices according to a host interface, which is a communication method with the host 400 . For example, the storage device 50 may include a multimedia card in the form of SSD, MMC, eMMC, RS-MMC, and micro-MMC, secure digital in the form of SD, mini-SD, and micro-SD. card, universal serial bus (USB) storage device, universal flash storage (UFS) device, personal computer memory card international association (PCMCIA) card-type storage device, PCI (peripheral component interconnection) card-type storage device, PCI-E ( It may be configured with any one of various types of storage devices such as a PCI express card type storage device, a CF (compact flash) card, a smart media card, a memory stick, and the like.

The storage device 50 may be manufactured in any one of various types of packages. For example, the storage device 50 may include package on package (POP), system in package (SIP), system on chip (SOC), multi-chip package (MCP), chip on board (COB), wafer- level fabricated package), wafer-level stack package (WSP), and the like.

The memory device 100 may store data. The memory device 100 operates in response to control of the memory controller 200 . The memory device 100 may include a memory cell array (not shown) including a plurality of memory cells that store data.

The memory cells are single-level cells (SLC) each storing one data bit, multi-level cells (MLC) storing two data bits, and triple-level cells storing three data bits. (Triple Level Cell; TLC) or Quad Level Cell (QLC) capable of storing four data bits.

A memory cell array (not shown) may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. Each memory block may include a plurality of pages. In an embodiment, a page may be a unit for storing data in the memory device 100 or reading data stored in the memory device 100 . A memory block may be a unit for erasing data.

In an embodiment, the memory device 100 may include DDR Double Data Rate Synchronous Dynamic Random Access Memory (SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), and RDRAM. (Rambus Dynamic Random Access Memory), NAND flash memory, Vertical NAND, NOR flash memory, resistive random access memory (RRAM), phase change memory (phase-change memory: PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin transfer torque random access memory (STT-RAM), etc. This can be. In this specification, for convenience of explanation, it is assumed that the memory device 100 is a NAND flash memory.

The memory device 100 is configured to receive a command and an address from the memory controller 200 and access a region selected by the address in the memory cell array. The memory device 100 may perform an operation indicated by a command with respect to an area selected by an address. For example, the memory device 100 may perform a write operation (program operation), a read operation, and an erase operation. During a program operation, the memory device 100 will program data into an area selected by an address. During a read operation, the memory device 100 will read data from an area selected by an address. During the erase operation, the memory device 100 will erase data stored in the area selected by the address.

The memory controller 200 may control overall operations of the storage device 50 .

When power is applied to the storage device 50 , the memory controller 200 may execute firmware (FW). When the memory device 100 is a flash memory device, the memory controller 200 may execute firmware such as a Flash Translation Layer (FTL) for controlling communication between the host 400 and the memory device 100 . there is.

In an embodiment, the memory controller 200 receives data and a logical block address (LBA) from the host 400, and the logical block address is used to indicate memory cells in which data included in the memory device 100 will be stored. It can be converted to a physical block address (PBA) representing an address.

The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, or an erase operation according to a request of the host 400 . During a program operation, the memory controller 200 may provide a program command, a physical block address, and data to the memory device 100 . During a read operation, the memory controller 200 may provide a read command and a physical block address to the memory device 100 . During an erase operation, the memory controller 200 may provide an erase command and a physical block address to the memory device 100 .

At this time, information transmitted and received between the host 400 and the memory controller 200 may be referred to as a request or a command in the present specification.

Also, in this specification, information provided to the memory device 100 by the memory controller 200 may be referred to as a command.

In an embodiment, the memory controller 200 may generate commands, addresses, and data on its own and transmit them to the memory device 100 regardless of a request from the host 400 . For example, the memory controller 200 uses commands for performing program operations, read operations, and erase operations involved in performing wear leveling, read reclaim, garbage collection, and the like. , addresses and data may be provided to the memory device 100 .

In an embodiment, the memory controller 200 may control at least two or more memory devices 100 . In this case, the memory controller 200 may control the memory devices 100 according to an interleaving method to improve operating performance. The interleaving method may be a method of controlling operations of at least two or more memory devices 100 to overlap.

The host 400 is USB (Universal Serial Bus), SATA (Serial AT Attachment), SAS (Serial Attached SCSI), HSIC (High Speed Interchip), SCSI (Small Computer System Interface), PCI (Peripheral Component Interconnection), PCIe ( PCI express), NVMe (NonVolatile Memory express), UFS (Universal Flash Storage), SD (Secure Digital), MMC (MultiMedia Card), eMMC (embedded MMC), DIMM (Dual In-line Memory Module), RDIMM (Registered DIMM ), LRDIMM (Load Reduced DIMM), etc., may communicate with the storage device 50 using at least one of various communication methods.

FIG. 2 is a diagram for explaining the memory device of FIG. 1 .

Referring to FIG. 2 , the memory device 100 may include a memory cell array 110 , a voltage generator 120 , an address decoder 130 , an input/output circuit 140 and a control logic 150 .

The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKi. The plurality of memory blocks BLK1 to BLKi are connected to the address decoder 130 through row lines RL. The plurality of memory blocks BLK1 to BLKi may be connected to the input/output circuit 140 through column lines CL. In an embodiment, the row lines RL may include word lines, source select lines, and drain select lines. In an embodiment, the column lines CL may include bit lines.

Each of the plurality of memory blocks BLK1 to BLKi includes a plurality of memory cells. In an embodiment, the plurality of memory cells may be nonvolatile memory cells. Among the plurality of memory cells, memory cells connected to the same word line may be defined as one physical page. That is, the memory cell array 110 may include a plurality of physical pages. The memory cells of the memory device 100 include a single level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, and three data bits. It may be configured as a triple level cell (TLC) that stores . or a quad level cell (QLC) that can store four data bits.

In an embodiment, the voltage generator 120, the address decoder 130, and the input/output circuit 140 may be collectively referred to as a peripheral circuit. The peripheral circuit may drive the memory cell array 110 under the control of the control logic 150 . A peripheral circuit may drive the memory cell array 110 to perform a program operation, a read operation, and an erase operation.

The voltage generator 120 is configured to generate a plurality of operating voltages using an external power supply voltage supplied to the memory device 100 . The voltage generator 120 operates in response to control of the control logic 150 .

As an example embodiment, the voltage generator 120 may generate an internal power voltage by regulating an external power voltage. The internal power supply voltage generated by the voltage generator 120 is used as an operating voltage of the memory device 100 .

As an embodiment, the voltage generator 120 may generate a plurality of operating voltages using an external power supply voltage or an internal power supply voltage. The voltage generator 120 may be configured to generate various voltages required by the memory device 100 . For example, the voltage generator 120 may generate a plurality of erase voltages, a plurality of program voltages, a plurality of pass voltages, a plurality of select read voltages, and a plurality of non-select read voltages.

The voltage generator 120 includes a plurality of pumping capacitors receiving an internal power supply voltage in order to generate a plurality of operating voltages having various voltage levels, and generates a plurality of pumping capacitors in response to the control of the control logic 150. It will selectively activate to generate a plurality of operating voltages.

The generated operating voltages may be supplied to the memory cell array 110 by the address decoder 130 .

The address decoder 130 is connected to the memory cell array 110 through row lines RL. The address decoder 130 is configured to operate in response to control of the control logic 150 . The address decoder 130 may receive the address ADDR from the control logic 150 . The address decoder 130 may decode a block address among the received addresses ADDR. The address decoder 130 selects at least one memory block among the memory blocks BLK1 to BLKi according to the decoded block address. The address decoder 130 may decode a row address among the received addresses ADDR. The address decoder 130 may select at least one word line among word lines of the selected memory block according to the decoded row address. In an embodiment, the address decoder 130 may decode a column address among the received addresses ADDR. The address decoder 130 may connect the input/output circuit 140 and the memory cell array 110 according to the decoded column address.

Illustratively, the address decoder 130 may include components such as a row decoder, a column decoder, and an address buffer.

The input/output circuit 140 may include a plurality of page buffers. A plurality of page buffers may be connected to the memory cell array 110 through bit lines. During a program operation, data may be stored in memory cells selected according to data stored in a plurality of page buffers.

During a read operation, data stored in selected memory cells may be sensed through bit lines, and the sensed data may be stored in page buffers.

The control logic 150 may control the address decoder 130 , the voltage generator 120 and the input/output circuit 140 . The control logic 150 may operate in response to a command CMD transmitted from an external device. The control logic 150 may control peripheral circuits by generating control signals in response to the command CMD and the address ADDR.

FIG. 3 is a diagram for explaining the structure of one memory block among the memory blocks of FIG. 2 .

The memory block BLKi is a diagram showing one memory block BLKi among the memory blocks BLK1 to BLKi of FIG. 2 .

Referring to FIG. 2 , a plurality of word lines arranged in parallel with each other may be connected between the first select line and the second select line. Here, the first select line may be the source select line SSL, and the second select line may be the drain select line DSL. More specifically, the memory block BLKi may include a plurality of strings (ST) connected between the bit lines BL1 to BLn and the source line SL. The bit lines BL1 to BLn may be respectively connected to the strings ST, and the source line SL may be connected to the strings ST in common. Since the strings ST may be configured identically to each other, the string ST connected to the first bit line BL1 will be described in detail as an example.

The string ST may include a source select transistor SST, a plurality of memory cells MC1 to MC16, and a drain select transistor DST connected in series between the source line SL and the first bit line BL1. can One string ST may include at least one source select transistor SST and at least one drain select transistor DST, and memory cells MC1 to MC16 may also include more memory cells than shown in the figure.

A source of the source select transistor SST may be connected to the source line SL, and a drain of the drain select transistor DST may be connected to the first bit line BL1. The memory cells MC1 to MC16 may be connected in series between the source select transistor SST and the drain select transistor DST. Gates of the source select transistors SST included in different strings ST may be connected to the source select line SSL, and gates of the drain select transistors DST may be connected to the drain select line DSL, Gates of the memory cells MC1 to MC16 may be connected to a plurality of word lines WL1 to WL16. A group of memory cells connected to the same word line among memory cells included in different strings ST may be referred to as a physical page (PG). Accordingly, as many physical pages PG as the number of word lines WL1 to WL16 may be included in the memory block BLKi.

One memory cell can store 1 bit of data. This is commonly referred to as a single level cell (SLC). In this case, one physical page (PG) can store one logical page (LPG) data. One logical page (LPG) data may include as many data bits as the number of cells included in one physical page (PG).

One memory cell can store more than two bits of data. In this case, one physical page (PG) can store two or more logical page (LPG) data.

4 is a diagram for explaining a data communication unit between a host and a memory controller.

Referring to FIG. 4 , the host 400 and the memory controller 200 may communicate using data packets called Protocol Information Units (PIUs).

The protocol unit (PIU) includes a command protocol unit (Command PIU), a response protocol unit (Response PIU), a data out protocol unit (Data Out PIU), and data according to an operation to be performed by the host 400 or the memory controller 200. It may include an in-protocol unit (Data In PIU) and a ready-to-transfer protocol unit (Ready To Transfer PIU).

The command protocol unit (Command PIU) may be a protocol unit transmitted when the host 400 transmits a command to the storage device 50 .

The response protocol unit (Response PIU) may be a protocol unit transmitted when the storage device 50 provides a response to a command provided by the host 400 .

The data out protocol unit (Data Out PIU) may be a protocol unit transmitted when the host 400 provides data to the storage device 50 .

The data in protocol unit (Data In PIU) may be a protocol unit transmitted when the storage device 50 provides data to the host 400 .

The ready to transfer protocol unit (Ready To Transfer PIU) may be a protocol unit transmitted when the storage device 50 informs that it is ready to receive a data out protocol unit (Data Out PIU) from the host 400 . The Ready To Transfer Protocol Unit (PIU) may be transmitted when the storage device 50 has sufficient buffer space to store data provided by the host 400 .

The size of the smallest unit of protocol unit (PIU) may be 32 bytes, and the maximum size of the protocol unit may be 65600 bytes. The format of the protocol unit (PIU) may have different sizes depending on its type.

The protocol unit (PIU) may include a basic header segment 61 , a transaction specific field 62 , an additional header segment 63 and a data segment 64 .

The basic header segment 61 may have a size of 12 bytes. The basic header segment 61 may be commonly included in all protocol units (PIUs).

The transaction specific field 62 may be included at byte addresses 12 through byte addresses 31 of the protocol unit (PIU). The transaction specific field 62 may include a dedicated transaction code according to the type of protocol unit (PIU).

The additional header segment 63 may be defined when the total additional header length (Total EHS Length) field of the basic header segment 61 has a value other than 0. The additional header segment 63 may start at byte address 32 of the protocol unit (PIU). The additional header segment 63 may be an area capable of additionally storing data when sufficient information is not included in the basic header segment 61 .

The data segment 64 may be included in a data out protocol unit (Data Out PIU) or a data in protocol unit (Data In PIU), and may not be included in other protocol units (PIUs).

In an embodiment, the additional header segment 63 and the data segment 64 may not be included in all protocol units (PIUs), but may be included only in a specific protocol unit (PIU).

5 is a diagram for explaining the structure of a basic header segment of a protocol unit included in a command.

Referring to FIG. 5, the basic header segment 61 includes a transaction type, a flag, a logical unit number (LUN), a task tag, an initiator ID, and a command set type. (Command Set Type), query function/task management function (Query Function, Task Manag. Function), response (Response), status (Status), total additional header segment length (Total EHS Length), device information (Device Information), and It may include a data segment length (Data Segment Length).

The transaction type (Transaction Type) may have a unique value according to the type of protocol unit (PIU). Examples of transaction types according to types of protocol units (PIUs) are shown in Table 1 below.

When a host presents to a storage device transaction type When the storage device presents it to the host transaction type command protocol unit 00 0001b response protocol unit 10 0001b data out protocol unit 00 0010b data in protocol unit 10 0010b X X Delivery readiness protocol unit 11 0001b

Flags may be fields having different values according to transaction types. The logical unit number (LUN) may be a field indicating the number of a logical unit to perform a corresponding operation among a plurality of logical units included in an operation target.

A task tag may be a field having different values according to a transaction type.

An initiator ID may be a field identifying who an initiator requesting an operation is. Accordingly, it may have different values when the host creates the protocol unit and when the storage device creates the protocol unit.

A command set type may be a field included in a command protocol unit and a response protocol unit. The command set type may be a field indicating which interface supports the command, such as whether the command is a SCSI command, a UFS command, or a command defined by a manufacturer.

The query function/task management function (Query Function, Task Manag. Function) may be a field input to a protocol unit such as a query request, query response, or task management request.

The response may be a field indicating whether the requested operation has succeeded or failed.

Status may be a field indicating a SCSI state.

The total additional header segment length (Total EHS Length) may be a field indicating the size of the additional header segment in units of 32 bits. The total additional header segment length (Total EHS Length) may be used when the protocol unit (PIU) includes additional header segments. The length of the additional header segment may be in units of 4 bytes. The value of the total additional header segment length (Total EHS Length) may be a value obtained by dividing the total number of bytes of additional header segments by 4. The maximum size of the additional header segment may be 1024 bytes. If the additional header segment is not used, the total additional header segment length (Total EHS Length) may be zero.

Device information may include information used only when a specific function is performed.

The data segment length may be a field indicating the length of a data segment of a protocol unit. When the protocol unit does not include a data segment, the data segment length may be zero.

6 is a diagram illustrating an embodiment of a command protocol unit (Command PIU) included in a command.

Referring to FIGS. 5 and 6 , a command (or command PIU) may include a basic header segment, a transaction specific field, and an additional header segment.

In the case of the basic header segment, it may be commonly included in commands transmitted and received between the host and the memory controller. In addition, in the case of a basic header segment included in a command, information indicating that it is a command may be included. For example, in the case of a basic header segment included in a read command, information representing the read command may be included. That is, in the case of FIG. 6, since it corresponds to the command protocol unit included in the command, the transaction type may be 00 0001b. In addition, according to an embodiment of the present invention, since the command protocol unit (Command PIU) of FIG. 6 includes an additional header segment, the total additional header segment length (total additional header segment length corresponding to byte address 8) among fields included in the basic header segment EHS Length) may have a value other than zero (non-zero). For example, the value of the total additional header segment length (Total EHS Length) may be a value obtained by dividing the total number of bytes of logical block address information of an area to be read by 4 during a multi-read operation.

In the case of a transaction specific field, a plurality of Command Descriptor Blocks (CDBs) may be included. Such a CDB may include information about various commands and addresses according to its type. These CDBs are USB (Universal Serial Bus), SATA (Serial AT Attachment), SAS (Serial Attached SCSI), HSIC (High Speed Interchip), SCSI (Small Computer System Interface), PCI (Peripheral Component Interconnection), PCIe (PCI express) ), NVMe (NonVolatile Memory express), UFS (Universal Flash Storage), SD (Secure Digital), MMC (MultiMedia Card), eMMC (embedded MMC), DIMM (Dual In-line Memory Module), RDIMM (Registered DIMM), It may be a CDB based on various communication methods such as LRDIMM (Load Reduced DIMM). In one embodiment, when the command of FIG. 6 is a lead command, the transaction specific field of FIG. 6 may include a lead CDB.

The additional header segment included in the command of FIG. 6 may include information about two or more logical addresses provided by the host 400 .

In the case of a normal read operation, i.e., a normal read operation, the host 400 provides the memory controller 200 with information about a start logical block address and a transfer length corresponding to the start logical block address, so that sequential data from the start logical block address according to the transfer length are stored. A read operation is performed on the area up to the logical block address. On the other hand, when a read operation is performed on at least two or more logical addresses, that is, in the case of a multi-read operation, a plurality of logical addresses that are not consecutive to each other are simultaneously read. Accordingly, during a multi-read operation, information on at least two or more logical addresses may include a plurality of starting logical block addresses and information on transmission lengths respectively corresponding to the plurality of starting logical block addresses. The memory controller 200 can simultaneously read a plurality of logical addresses that are not consecutive to each other by receiving such information from the host 400 .

In one embodiment, one piece of logical address information including information about a start logical block address and a transmission length corresponding thereto may be 8 bytes in size. Accordingly, in the case of a multi-read operation, information on at least two or more logical addresses may be sequentially set by 8 bytes in an additional header segment, but the size or setting method of logical address information is not limited thereto.

7 to 9 are diagrams illustrating exemplary embodiments of a read command descriptor block (CDB). 7 to 9 may be a lead (6) command CDB, a lead (10) command CDB, and a lead (16) command CDB, respectively.

Referring to FIGS. 6 to 9 , a lead CDB may be included in a transaction specific field of a read command. Illustratively, the lead CDB may include the 0th to 9th bytes (0 to 9). The columns of the CDB indicate each bit of each byte of the CDB. For example, each byte may include 0th to 7th bits (0 to 7). The 0th to 7th bits (0 to 7) of the 0th byte (0) of the CDB indicate an operation code. For example, the operation code of the read command may be 08h (lead (6) command, FIG. 7), 28h (lead (10) command, FIG. 8), or 88h (lead (16) command, FIG. 9).

Hereinafter, Fig. 8, which is a read CDB related to the read (10) command, will be described as a representative. In the case of a read (10) command, the 0th bit (0) of the first byte (1) of the CDB may be obsolete. The first bit (1) of the first byte (1) may indicate FUA_NV. The second bit 2 of the first byte 1 may be a reserved block. The third bit (3) of the first byte (1) may indicate Force Unit Access (FUA). FUA may indicate whether the data cache is used. The fourth bit (4) of the first byte (1) indicates DPO (Disable Page Out). DPO can indicate how to set the retention priority. The fifth to seventh bits (5 to 7) of the first byte (1) are RDPROTECT and may have a value of '000b'. The second to fifth bytes 2 to 5 of the read 10 command CDB may indicate a logical address (LOGICAL ADDRESS, LA). The logical address LA may include a most significant bit (MSB) to a least significant bit (LSB).

Lead 10 The 0th to 4th bits (0 to 4) of the sixth byte (6) of the command CDB indicate a group number (GROUP NUMBER). The group number (GROUP NUMBER) may indicate a context identifier (Context ID) associated with a read request. The fifth to seventh bits 5 to 7 of the sixth byte 6 may be reserved.

The seventh and eighth bytes (7, 8) of the lead (10) command CDB indicate the TRANSFER LENGTH. The transmission length (TRANSFER LENGTH) may indicate the length of data to be read through a read request.

The ninth byte (9) of the lead (10) command CDB may contain CONTROL. For example, the control may be '00h'.

The read CDB may include information indicating that the read command is a read command for at least two or more logical addresses. For example, a read mode message indicating whether the read command is a multi-read command requesting a read of at least two or more logical addresses or a normal read command requesting a read of one logical address may be included. . In one embodiment, the lead mode message may express each lead mode as a predetermined value of 0 or 1. According to the read mode message, the memory controller may perform a normal read operation or a multi-read operation.

In one embodiment, the read CDB may include information indicating whether the read command is a read command for at least two or more logical addresses (a read mode message) in a preliminary block in the lead CDB. For example, in the case of the read 10 command, a read mode message may be included in the spare block located at the second bit 2 of the first byte 1 as shown in FIG. 8, but is not limited thereto, and the read CDB It can be included in various preliminary blocks within

When a read operation (multi-read operation) for at least two or more logical addresses is performed according to the read mode message, the multi-read operation may be performed using logical block address information stored in the additional header segment. When a read operation (normal read operation) for one logical address is performed according to the read mode message, the normal read operation may be performed using logical block address information stored in the read CDB. The read CDB may include information about a start logical block address of an area to be read and a transfer length corresponding to the start logical block address during a normal read operation. However, the embodiment is not limited only to the logical block address information related to the normal read operation being included in the read CDB, and may be stored in an additional header segment or in other fields of the read command.

The contents described in FIG. 8 may be modified and applied to other types of lead CDBs as shown in FIGS. 7 and 9 according to the corresponding format.

10 is a diagram illustrating an embodiment of an additional header segment including information on at least two or more logical addresses.

Referring to FIG. 10 , the additional header segment may include a plurality of start logical block addresses (LBAs) and information about transmission lengths respectively corresponding to the plurality of start logical block addresses. For example, as shown in FIG. 10, LBA #1 - TRANSFER LENGTH #1, LBA #2 - TRANSFER LENGTH #2, LBA #3 - TRANSFER LENGTH #3, LBA #4 - TRANSFER LENGTH #4 in the additional header segment. In this case, the memory controller operates from PBA #1, which is the physical block address (PBA) corresponding to LBA #1, to TRANSFER LENGTH #1, and from PBA #2 to TRANSFER LENGTH corresponding to LBA #2. Area corresponding to the length corresponding to #2, area corresponding to the length corresponding to TRANSFER LENGTH #3 from PBA #3 corresponding to LBA #3, and length corresponding to PBA #4 to TRANSFER LENGTH #4 corresponding to LBA #4 It is possible to simultaneously read the data of as many areas as possible.

11 is a diagram for describing a memory controller according to an exemplary embodiment of the present invention.

Referring to FIG. 11 , the memory controller 200 may include a read request processing unit 210 , a map data storage unit 220 , and a read operation control unit 230 .

The memory controller 200 may receive a read request requesting to read data stored in the memory device from the host 400 .

At this time, the read request may include a basic header segment, a transaction specific field, and an additional header segment.

The basic header segment may be a part commonly included in requests transmitted and received between an external host and the memory controller, and may include a total additional header segment length (Total EHS Length) indicating the length of additional header segments. In an embodiment, since the read request includes additional header segments, the total additional header segment length may have a value other than zero (non-zero).

The transaction specific field may include a lead command descriptor block (CDB). The read CDB may include information indicating whether the read request is a read request for at least two or more logical addresses. For example, a read mode message indicating whether the read request is a multi-read request for requesting a read for at least two or more logical addresses or a normal read request for requesting a read for one logical address may be included. . In one embodiment, the lead mode message may express each lead mode as a predetermined value of 0 or 1. According to the read mode message, the memory controller may perform a normal read operation or a multi-read operation. In one embodiment, the lead CDB may include information indicating whether the read request is a read request for at least two or more logical addresses (a read mode message) in a preliminary block in the lead CDB.

Additional header segments may include logical block addresses for multi-read operation. The logical block address for the multi-read operation may include a plurality of starting logical block addresses and information about transmission lengths respectively corresponding to the plurality of starting logical block addresses.

The read request processing unit 210 may receive a read request from an external host and obtain a physical address corresponding to one or more logical addresses included in the read request from the map data storage unit 220 . Also, the read request processing unit 210 may check whether the read request is for at least two or more logical addresses. In an embodiment, the lead request processing unit 210 may check the read mode message included in the lead request. A read mode message indicating whether the read request is a read request for at least two or more logical addresses may be included in a transaction specific field, and more specifically, a lead mode message included in the transaction specific field may be included in a preliminary block in the lead CDB. can be included

The map data storage unit 220 may include a logical-to-physical address mapping table constituting a mapping relationship between logical addresses and physical addresses. As a result of checking the read mode message of the read request processing unit 210, if the read request is a read request for at least two or more logical addresses (multi-read mode), the map data storage unit 220 includes an additional header segment included in the read request. Map data corresponding to two or more logical addresses may be provided to the read request processor 210 . As a result of checking the read mode message of the read request processing unit 210, if the read request is a read request for one logical address (normal read mode), the map data storage unit 220 includes it in the lead CDB in the transaction specific field of the read request. Map data corresponding to one logical address may be provided to the read request processing unit 210 . However, the logical block address information for the normal read operation is not limited to being included in the read CDB, and may be included in various fields in the read request including an additional header segment.

The read operation control unit 230 may control the memory device to perform a read operation according to instructions from the read request processing unit 210 . The read request processing unit 210 may provide the map data received from the map data storage unit 220 to the read operation controller 230 . The read operation control unit 230 may control the memory device to perform a read operation on a corresponding address based on map data received from the read request processing unit 210 . More specifically, the read operation controller 230 may provide a read command for a physical address corresponding to one or more logical addresses included in the read request to the memory device.

12 is a flowchart illustrating a method of operating a storage device according to an exemplary embodiment.

Referring to FIG. 12 , in step S1201, the storage device may receive a read command requesting to read data stored in the memory device from an external host. More specifically, a memory controller in the storage device may receive a read command.

In this case, the read command may include a basic header segment, a transaction specific field, and an additional header segment.

The basic header segment may be a part commonly included in commands transmitted and received between an external host and the memory controller, and may include a total additional header segment length (Total EHS Length) indicating the length of additional header segments. In an embodiment, since the read command includes additional header segments, the total additional header segment length may have a value other than zero (non-zero).

The transaction specific field may include a lead command descriptor block (CDB). Information indicating whether the read command is a read command for at least two or more logical addresses may be included in the read CDB. For example, a read mode message indicating whether the read command is a multi-read command requesting a read of at least two or more logical addresses or a normal read command requesting a read of one logical address may be included. . In one embodiment, the lead mode message may express each lead mode as a predetermined value of 0 or 1. According to the read mode message, the memory controller may perform a normal read operation or a multi-read operation. In one embodiment, the read CDB may include information indicating whether the read command is a read command for at least two or more logical addresses (a read mode message) in a preliminary block in the lead CDB.

Additional header segments may include logical block addresses for multi-read operation. The logical block address for the multi-read operation may include a plurality of starting logical block addresses and information about transmission lengths respectively corresponding to the plurality of starting logical block addresses.

In step S1203, the storage device may check the read mode message stored in the lead CDB.

In step S1205, when the read mode message indicates the multi-read mode, that is, the read command is a read command for at least two or more logical addresses, a multi-read operation that is a read operation for at least two or more logical addresses in step S1207 is performed. can

In step S1205, if the read mode message indicates that it is not a multi-read mode, that is, if the read command is not a read command for at least two or more logical addresses, if it indicates normal read mode, one logic in step S1209 A normal read operation, which is a read operation for an address, may be performed.

That is, the multi-read operation may be performed according to the read mode message stored in the lead CDB, or the normal read operation may be performed instead of the multi-read operation.

13 is a flowchart illustrating a multi-read operation of a storage device according to an embodiment of the present invention.

Referring to FIGS. 12 and 13 , the storage device may perform a multi-read operation according to the read mode message stored in the read CDB in step S1301. In this case, the far read operation in step S1303 may be performed using information about at least two or more logical addresses included in the additional header segment in the read command. The information on the at least two or more logical addresses included in the additional header segment may include at least two or more starting logical block addresses for a multi-read operation and information on transmission lengths respectively corresponding to the at least two or more starting logical block addresses. .

14 is a flowchart illustrating a normal read operation of a storage device according to an embodiment of the present invention.

12 and 14 , the storage device may perform a normal read operation according to the read mode message stored in the read CDB in step S1401. In this case, the normal read operation in step S1403 may be performed using the transaction specific field, more specifically, information about one logical address included in the read CDB. Information about the logical address included in the read CDB may include information about one starting logical block address for a normal read operation and a transmission length corresponding thereto.

However, the logical block address information for the normal read operation is not limited to being included in the read CDB, and may be included in various fields of the read command including an additional header segment.

15 is a diagram explaining a data providing sequence of a storage device according to an embodiment of the present invention.

Referring to FIGS. 1, 4, and 15 , the memory controller in the storage device receiving a read command requesting to read data stored in the memory device from the host performs a read operation and provides the acquired data to the host. there is.

When a read operation for at least two or more logical addresses, that is, a far read operation is performed, data of a plurality of areas having non-consecutive logical addresses may be simultaneously read and obtained. For example, as shown in FIG. 14, DATA #1 in the area corresponding to LBA #1 - TRANSFER LENGTH #1 stored in the additional header segment of the read command, and DATA # in the area corresponding to LBA #2 - TRANSFER LENGTH #2 2, LBA #3 - DATA #3 of the area corresponding to TRANSFER LENGTH #3 and DATA #4 of the area corresponding to LBA #4 - TRANSFER LENGTH #4 can be read simultaneously.

At this time, data obtained by the multi-read operation may be provided to the host according to the order of logical block address information included in the additional header segment. For example, as shown in FIG. 12, the physical block address information in the additional header segment of the read command is 1) LBA #1 - TRANSFER LENGTH #1, 2) LBA #2 - TRANSFER LENGTH #2, 3) LBA #3 - TRANSFER LENGTH #3, 4) LBA #4 - If TRANSFER LENGTH #4 is listed in the order, the data is also 1) DATA #1, 2) DATA #2, 3) DATA #3, 4) DATA #4. can be provided to However, it is not limited to a specific order, and may be provided in an order opposite to the above, and in addition, data of a plurality of areas may be provided to the host in various preset orders.

16 is a diagram illustrating another embodiment of the memory controller of FIG. 1 .

Referring to FIG. 16 , a memory controller 1600 may include a processor 1610, a RAM 1620, an error correction circuit 1630, a host interface 1640, a ROM 1650, and a flash interface 1660. there is.

The processor 1610 may control overall operations of the memory controller 1600 . The RAM 1620 may be used as a buffer memory, cache memory, operation memory, or the like of the memory controller 1600 .

The ROM 1650 may store various information required for the operation of the memory controller 1600 in the form of firmware.

The memory controller 1600 may communicate with an external device (eg, the host 400 or an application processor) through the host interface 1640 .

The memory controller 1600 may communicate with the memory device 100 through the flash interface 1660 . The memory controller 1600 may transmit a command CMD, an address ADDR, a control signal CTRL, etc. to the memory device 100 through a flash interface 1660 and may receive data DATA. . For example, the flash interface 1660 may include a NAND interface.

17 is a block diagram showing a memory card system to which a storage device according to an embodiment of the present invention is applied.

Referring to FIG. 17 , a memory card system 2000 includes a memory controller 2100 , a memory device 2200 , and a connector 2300 .

The memory controller 2100 is connected to the memory device 2200 . The memory controller 2100 is configured to access the memory device 2200 . For example, the memory controller 2100 may be configured to control read, program, erase, and background operations of the memory device 2200 . The memory controller 2100 is configured to provide an interface between the memory device 2200 and a host. The memory controller 2100 is configured to drive firmware for controlling the memory device 2200 . The memory controller 2100 may be implemented identically to the memory controller 200 described with reference to FIG. 1 .

Illustratively, the memory controller 2100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error correction unit. can

The memory controller 2100 may communicate with an external device through the connector 2300 . The memory controller 2100 may communicate with an external device (eg, a host) according to a specific communication standard. For example, the memory controller 2100 may include universal serial bus (USB), multimedia card (MMC), embedded MMC (eMMC), peripheral component interconnection (PCI), PCI-express (PCI-E), and advanced technology attachment (ATA). ), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, It is configured to communicate with an external device through at least one of various communication standards such as NVMe. Illustratively, the connector 2300 may be defined by at least one of the above-described various communication standards.

For example, the memory device 2200 may include electrically erasable and programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and STT-MRAM. (Spin Transfer Torque Magnetic RAM) and the like.

The memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and the memory device 2200 are integrated into a single semiconductor device such as a personal computer memory card international association (PCMCIA), a compact flash card (CF), or a smart media card (SM, SMC). ), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro, eMMC), SD cards (SD, miniSD, microSD, SDHC), and universal flash memory (UFS).

18 is a block diagram illustrating a solid state drive (SSD) system to which a storage device according to an embodiment of the present invention is applied.

Referring to FIG. 18 , an SSD system 3000 includes a host 3100 and an SSD 3200 . The SSD 3200 exchanges signals with the host 3100 through the signal connector 3001 and receives power through the power connector 3002 . The SSD 3200 includes an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

According to an embodiment of the present invention, the SSD controller 3210 may perform the function of the memory controller 200 described with reference to FIG. 1 .

The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal received from the host 3100 . For example, the signals may be signals based on an interface between the host 3100 and the SSD 3200 . For example, signals include universal serial bus (USB), multimedia card (MMC), embedded MMC (eMMC), peripheral component interconnection (PCI), PCI-express (PCI-E), advanced technology attachment (ATA), serial- Interfaces such as ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, NVMe, etc. It may be a signal defined by at least one of

The auxiliary power supply 3230 is connected to the host 3100 through a power connector 3002 . The auxiliary power supply 3230 can receive power from the host 3100 and charge it. The auxiliary power supply 3230 may provide power to the SSD 3200 when power supply from the host 3100 is not smooth. For example, the auxiliary power supply 3230 may be located inside the SSD 3200 or outside the SSD 3200 . For example, the auxiliary power supply 3230 is located on the main board and may provide auxiliary power to the SSD 3200.

The buffer memory 3240 operates as a buffer memory of the SSD 3200. For example, the buffer memory 3240 temporarily stores data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or metadata (metadata) of the flash memories 3221 to 322n. For example, a mapping table) may be temporarily stored. The buffer memory 3240 may include volatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM.

19 is a block diagram illustrating a user system to which a storage device according to an embodiment of the present invention is applied.

Referring to FIG. 19 , a user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

The application processor 4100 may drive components included in the user system 4000, an operating system (OS), or a user program. Illustratively, the application processor 4100 may include controllers, interfaces, graphic engines, and the like that control components included in the user system 4000 . The application processor 4100 may be provided as a System-on-Chip (SoC).

The memory module 4200 may operate as a main memory, working memory, buffer memory, or cache memory of the user system 4000 . The memory module 4200 includes volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDARM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile random access memory such as PRAM, ReRAM, MRAM, FRAM, and the like. can do. For example, the application processor 4100 and the memory module 4200 may be packaged based on a package on package (POP) and provided as a single semiconductor package.

The network module 4300 may communicate with external devices. Illustratively, the network module 4300 may include code division multiple access (CDMA), global system for mobile communication (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), and long term evolution (LTE). ), wireless communication such as Wimax, WLAN, UWB, Bluetooth, Wi-Fi, etc. may be supported. For example, the network module 4300 may be included in the application processor 4100 .

The storage module 4400 may store data. For example, the storage module 4400 may store data received from the application processor 4100 . Alternatively, the storage module 4400 may transmit data stored in the storage module 4400 to the application processor 4100 . For example, the storage module 4400 is a non-volatile semiconductor memory device such as a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a NAND flash, a NOR flash, a 3D NAND flash, and the like. can be implemented For example, the storage module 4400 may be provided as a removable storage medium such as a memory card or an external drive of the user system 4000 .

For example, the storage module 4400 may include a plurality of nonvolatile memory devices, and the plurality of nonvolatile memory devices may operate in the same way as the memory device 100 described with reference to FIG. 1 . The storage module 4400 may operate in the same way as the storage device 50 described with reference to FIG. 1 .

The user interface 4500 may include interfaces for inputting data or commands to the application processor 4100 or outputting data to an external device. For example, the user interface 4500 may include user input interfaces such as a keyboard, keypad, button, touch panel, touch screen, touch pad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, piezoelectric element, and the like. there is. The user interface 4500 may include user output interfaces such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a monitor.

50: storage device
100: memory device
200: memory controller
400: host

Claims (20)

memory device; and
A memory controller receiving a read command from an external host and controlling the memory device according to the read command;
The lead command is
a basic header segment commonly included in commands transmitted and received between the external host and the memory controller and including information indicating that the read command is a command requesting data stored in the memory device;
a transaction specific field including information indicating that the read command is a read command for at least two or more logical addresses; and
and an additional header segment including information about the at least two logical addresses.
The method of claim 1, wherein the information about the at least two or more logical addresses comprises:
A storage device comprising at least two or more starting logical block addresses and information about transfer lengths respectively corresponding to the at least two or more starting logical block addresses.
According to claim 1,
The at least two logical addresses are not consecutive to each other.
The method of claim 1, wherein the transaction specific field,
A storage device including a Read Command Descriptor Block (CDB).
The method of claim 4, wherein the lead CDB,
and information indicating that the read command is a read command for at least two or more logical addresses.
The method of claim 5, wherein the information indicating that the read command is a read command for at least two or more logical addresses comprises:
A storage device included in a reserved block in the lead CDB.
The method of claim 6, wherein the lead CDB,
A storage device that further includes an Opcode (Operation Code) field, a FUA (Force Unit Access) field, and a Group Number (GROUP NUMBER) field.
The method of claim 1, wherein the basic header segment,
and a Total Additional Header Segment Length field indicating the length of the additional header segments.
According to claim 8,
The storage device of claim 1, wherein the Total Additional Header Segment Length field includes a non-zero value.
A method of operating a storage device including a memory device and a memory controller controlling the memory device, the method comprising:
A basic header segment commonly included in commands transmitted and received between an external host and the memory controller and including information indicating that the read command is a read command requesting data stored in the memory device; receiving, by the memory controller, a read command including a transaction specific field including information representing a read command and an additional header segment including information on the at least two logical addresses from an external host; and
performing a read operation based on information about the at least two or more logical addresses;
Operation method including.
11. The method of claim 10, wherein the information about the at least two or more logical addresses comprises:
An operation method comprising at least two or more starting logical block addresses and information about transmission lengths respectively corresponding to the at least two or more starting logical block addresses.
11. The method of claim 10, wherein the basic header segment,
and a Total Additional Header Segment Length field indicating the length of the additional header segments.
According to claim 12,
The total additional header segment length field includes a non-zero value.
According to claim 10,
The method of operation, wherein the at least two or more logical addresses are not consecutive to each other.
The method of claim 10, wherein the transaction specific field,
An operating method comprising a Read Command Descriptor Block (CDB).
The method of claim 15, wherein the lead CDB,
and information indicating that the read command is a read command for at least two or more logical addresses.
17. The method of claim 16, wherein the information indicating that the read command is a read command for at least two or more logical addresses comprises:
An operating method included in a reserved block in the lead CDB.
According to claim 10,
and providing data read from the memory device to the external host as a read operation is performed on the at least two or more logical addresses.
The method of claim 18, wherein the read data,
Provided to the external host according to the order of logical block address information included in the additional header segment.
A memory controller for controlling a memory device,
a map data storage unit to store mapping information between logical addresses and physical addresses of data stored in the memory device;
a read request processor receiving a read request from an external host and acquiring a physical address corresponding to one or more logical addresses included in the read request from the map data storage unit; and
A read operation control unit providing a read command for a physical address corresponding to the at least one logical address to the memory device;
The lead request,
a basic header segment commonly included in requests transmitted and received between the external host and the memory controller and including information indicating that the read request is a request for data stored in the memory device;
a transaction specific field including information indicating that the read request is a read request for at least two or more logical addresses; and
and an additional header segment including information about the at least two logical addresses.

Images