KR20230010540A - Electronic device for performing smart refresh operation - Google Patents

Abstract

Provided is an electronic device, which includes: a target address generation circuit which generates a counting signal by counting the number of inputs for each logic level combination of addresses by performing an internal read operation and an internal write operation during an active operation, stores the counting signal as the stored counting signal when the counting signal is counted more than the stored counting signal stored therein, and stores the address corresponding to the counting signal as a target address; and a refresh control circuit which controls a smart refresh operation for the target address.

Description

Electronic device for performing smart refresh operation {ELECTRONIC DEVICE FOR PERFORMING SMART REFRESH OPERATION}

The present invention relates to an electronic device for performing a smart refresh operation by counting the number of inputs for each logic level combination of all addresses.

A semiconductor device includes a plurality of memory cells for storing data. Each memory cell is composed of a cell capacitor and a cell transistor. A semiconductor device stores data through an operation of charging or discharging electric charge in a cell capacitor, and the amount of electric charge stored in the cell capacitor should ideally always be constant. However, the amount of charge stored in the cell capacitor changes due to the voltage difference with the peripheral circuit. Such a change in the amount of charge of the cell capacitor means that the data stored in the cell capacitor is changed, which means that the stored data is lost. The semiconductor device performs a refresh operation to prevent data loss.

On the other hand, as process technology develops, the degree of integration of semiconductor devices gradually increases, so that intervals between memory cells are reduced and intervals between word lines connected to each memory cell are reduced. When the distance between word lines is narrowed, an interference effect occurs between adjacent word lines, making it difficult to maintain data stored in a memory cell connected to a corresponding word line. That is, the probability that data may be lost increases.

The present invention further includes a memory area for storing input count information of logic level combinations of all addresses, and refreshes word lines adjacent to the most activated word line according to a result of counting logic level combinations of all addresses. It relates to an electronic device that performs a refresh operation.

To this end, the present invention generates a counting signal by counting the number of inputs for each logic level combination of addresses by performing an internal read operation and an internal write operation during an active operation, and when the counting signal counts more than the stored counting signal stored therein An electronic device including a target address generation circuit for storing the counting signal as the storage counting signal and storing the address corresponding to the counting signal as a target address, and a refresh control circuit for controlling a smart refresh operation for the target address. provides

In addition, the present invention generates a counting signal by counting the number of inputs for each logic level combination of addresses by performing an internal read operation and an internal write operation during an active operation, and stores the counting signal as a counting signal when the counting signal is up-counted. A target address generation circuit that stores the address corresponding to the counting signal as a target address, initializes the stored counting signal during a first smart refresh operation, and outputs the target address during a second smart refresh operation; and Provided is an electronic device including a refresh control circuit for controlling a smart refresh operation for the target address during the second smart refresh operation.

In addition, the present invention includes an internal read and internal write operation step of generating a counting signal by counting the number of inputs for each logic level combination of addresses during an active operation, generating a flag signal by comparing the counting signal and a storage counting signal, and generating the flag signal. A target address generation step of generating a target address for performing a smart refresh operation from the address based on a signal, and a word line adjacent to a word line corresponding to the target address among word lines included in a memory area when a refresh command is input. It provides a smart refresh method including a smart refresh performing step of performing a smart refresh operation for refreshing the data.

According to the present invention, a memory area for storing input count information of logic level combinations of all addresses is additionally provided, and word lines adjacent to the most activated word line are refreshed according to a result of counting logic level combinations of all addresses. A smart refresh operation can be performed.

In addition, according to the present invention, interference between word lines can be prevented by storing the result of counting all address combinations and refreshing word lines adjacent to the most activated word line using the result.

1 is a block diagram showing the configuration of an electronic device according to an embodiment of the present invention.
2 is a diagram illustrating locations of components included in an electronic device according to an embodiment of the present invention.
3 is a block diagram showing the configuration of an active control circuit included in the electronic device shown in FIG. 1;
FIG. 4 is a block diagram showing the configuration of a target address generation circuit included in the electronic device shown in FIG. 1;
FIG. 5 is a block diagram showing the configuration of a comparison circuit included in the target address generating circuit shown in FIG. 4;
FIG. 6 is a block diagram showing the configuration of a flag signal generating circuit included in the comparator circuit shown in FIG. 5;
FIG. 7 is a block diagram showing the configuration of a smart refresh control circuit included in the target address generating circuit shown in FIG. 4 .
FIG. 8 is a block diagram showing the configuration of a refresh control circuit included in the electronic device shown in FIG. 1 .
FIG. 9 is a diagram for explaining operations of a first memory area and a second memory area included in the electronic device shown in FIG. 1 .
10 is a flowchart for explaining a smart refresh operation of an electronic device according to an embodiment of the present invention.
11 is a timing diagram for explaining a smart refresh operation of an electronic device according to an embodiment of the present invention.
12 is a block diagram showing the configuration of an electronic device according to another embodiment of the present invention.
13 is a block diagram showing the configuration of an electronic device according to another embodiment of the present invention.
FIG. 14 is a block diagram showing the configuration of a target address generation circuit included in the electronic device shown in FIG. 13. Referring to FIG.
FIG. 15 is a block diagram showing the configuration of a smart refresh control circuit included in the target address generating circuit shown in FIG. 14 .
FIG. 16 is a block diagram showing the configuration of a refresh control circuit included in the electronic device shown in FIG. 13 .
17 is a flowchart for explaining a smart refresh operation of an electronic device according to another embodiment of the present invention.
18 is a timing diagram for explaining a smart refresh operation of an electronic device according to another embodiment of the present invention.
19 is a diagram illustrating a configuration according to an embodiment of an electronic system to which the electronic devices shown in FIGS. 1 to 18 are applied.

The term "preset" means that the value of a parameter is predetermined when using that parameter in a process or algorithm. The value of the parameter may be set when a process or algorithm starts or may be set during a period during which a process or algorithm is performed, depending on embodiments.

Terms such as "first" and "second" used to distinguish various components are not limited by the components. For example, a first element may be termed a second element, and conversely, a second element may be termed a first element.

It should be understood that when one component is said to be "connected" or "connected" to another component, it may be directly connected or connected through another component in the middle. On the other hand, descriptions of "directly connected" and "directly connected" should be understood as directly connecting one component to another component without intervening another component.

"Logic high level" and "logic low level" are used to describe logic levels of signals. A signal having a "logic high level" is distinguished from a signal having a "logic low level". For example, when a signal having a first voltage corresponds to a “logic high level”, a signal having a second voltage may correspond to a “logic low level”. According to an embodiment, the “logic high level” may be set to a higher voltage than the “logic low level”. Meanwhile, the logic levels of the signals may be set to other logic levels or opposite logic levels according to embodiments. For example, a signal having a logic high level may be set to have a logic low level according to embodiments, and a signal having a logic low level may be set to have a logic high level according to embodiments.

Hereinafter, the present invention will be described in more detail through examples. These examples are only for exemplifying the present invention, and the protection scope of the present invention is not limited by these examples.

As shown in FIG. 1, an electronic device 1 according to an embodiment of the present invention includes an active control circuit 11, a target address generation circuit 12, an internal address generation circuit 13, and a refresh control circuit 14. ), the first memory area 21 and the second memory area 22 may be included.

The active control circuit 11 may receive an active command (ACT) and a refresh command (REF) from an external device (eg, a controller). The active control circuit 11 may generate an internal read signal IRD, an internal comparison signal ICMP, and an internal write signal IWT based on the active command ACT and the refresh command REF. The active control circuit 11 may generate an internal read signal IRD, an internal comparison signal ICMP, and an internal write signal IWT sequentially generated based on the active command ACT. The active control circuit 11 may generate an internal write signal IWT based on the refresh command REF.

The target address generation circuit 12 may receive an internal read signal IRD, an internal comparison signal ICMP, and an internal write signal IWT from the active control circuit 11 . The target address generation circuit 12 may receive first through Nth addresses ADD<1:N> from an external device (eg, a controller). The target address generation circuit 12 may receive the smart refresh signal SR from the refresh control circuit 14 . The target address generation circuit 12 includes first to sixth read counting signals (RCA<1:6>), which are input count information of the logic level combination of the first to Nth addresses (ADD<1:N>) during an internal read operation. ) may be up-counted to generate the first to sixth counting signals (TWC<1:6> in FIG. 3). The target address generation circuit 12 up-counts the first to sixth read counting signals RCA<1:6> input from the first memory area 21 when the internal read signal IRD is input, to a sixth counting signal (TWC<1:6> in FIG. 3). The target address generation circuit 12 counts the first to sixth counting signals (TWC<1:6> in FIG. 3) more than the first to sixth storage counting signals (SWC<1:6> in FIG. 6). At this time, the first to sixth counting signals (TWC<1:6> in FIG. 3) may be stored as the first to sixth storage counting signals (SWC<1:6> in FIG. 6). The target address generating circuit 12 receives the smart refresh signal SR and receives the first to Nth addresses ADD<1:N corresponding to the first to sixth counting signals (TWC<1:6> in FIG. 3). >) may be stored as first to Nth target addresses (TAD<1:N>). The target address generation circuit 12 generates first to sixth light counting signals (WCA<1:6>) generated from first to sixth counting signals (TWC<1:6> in FIG. 3) during internal light operation. It can be output to the first memory area 21 . The target address generating circuit 12 receives the internal light signal IWT and generates first to sixth light counting signals (WCA<1:6> in FIG. 3) from first to sixth counting signals (TWC<1:6> in FIG. 3). :6>) may be output to the first memory area 21 . The target address generation circuit 12 converts the most counted first to sixth counting signals (TWC<1:6> in FIG. 3) into first to sixth storage counting signals (SWC<1:6> in FIG. 6). can be saved as The target address generation circuit 12 may initialize the first to sixth storage counting signals (SWC<1:6> in FIG. 6) in the smart refresh operation.

The internal address generating circuit 13 may receive first through Nth addresses ADD<1:N> from an external device (eg, a controller). The internal address generating circuit 13 may generate first to Nth internal addresses IADD<1:N> from the first to Nth addresses ADD<1:N>. The internal address generation circuit 13 may output the first to Nth addresses ADD<1:N> as the first to Nth internal addresses IADD<1:N>. The internal address generation circuit 13 is implemented to output the first to Nth addresses ADD<1:N> as the first to Nth internal addresses IADD<1:N>, but the first to Nth addresses It may be implemented to decode (ADD<1:N>) to generate first to Nth internal addresses (IADD<1:N>). The number of bits of the first to Nth addresses ADD<1:N> and the first to Nth internal addresses IADD<1:N> may be set in various ways according to embodiments.

The refresh control circuit 14 may receive a refresh command REF from an external device (eg, a controller). The refresh control circuit 14 may generate a smart refresh signal SR and an internal refresh signal IR based on the refresh command REF. The refresh control circuit 14 may generate a smart refresh signal SR that is enabled when the refresh command REF is repeatedly input the number of times to perform a smart refresh operation. The refresh control circuit 14 may generate an internal refresh signal IR that is enabled when the refresh command REF is repeatedly input the number of times for performing the self-refresh operation.

The first memory area 21 may include first to sixteenth row hammering word lines (RWL1 to RWL16 in FIGS. 2 and 9 ). The first memory area 21 may include a plurality of row hammering cells (RCs in FIGS. 2 and 9 ) connected to first to sixteenth row hammering word lines (RWL1 to RWL16 in FIGS. 2 and 9 ). The first memory area 21 selects among the first to sixteenth row hammering word lines (RWL1 to RWL16 in FIGS. 2 and 9) by the first to Nth internal addresses (IADD<1:N>) during an internal read operation. The first to sixth write counting signals (WCA<1:6>) stored in the row hammering cells (RC in FIGS. 2 and 9) connected to the row hammering word line to be 6>). The first memory area 21 selects among the first to sixteenth row hammering word lines (RWL1 to RWL16 in FIGS. 2 and 9) by the first to Nth internal addresses (IADD<1:N>) during an internal write operation. The first to sixth write counting signals WCA<1:6> may be stored in the row hammering cells (RCs of FIGS. 2 and 9 ) connected to the row hammering word lines. The first memory area 21 receives the initialization signal INIT input during the power-up period for starting the operation of the electronic device 1 and during the boot-up operation, and stores the first to sixth light counting signals WCA<1 :6>) can be initialized. All bits of the initialized first to sixth light counting signals WCA<1:6> may be generated at a logic low level. The first memory area 21 is implemented to include first to sixteenth row hammering word lines (RWL1 to RWL16 in FIGS. 2 and 9 ), but may be implemented to include various numbers of row hammering word lines according to embodiments. there is. The first memory area 21 includes first to Nth addresses (ADD<1: The first to sixth write counting signals (WCA<1:6>), which are input count information for each logic level combination of N>), are connected to the first to sixteenth row hammering word lines (RWL1 to RWL16 in FIGS. 2 and 9) It can be stored in a row hammering cell (RC in FIG. 13).

The second memory area 22 may include first to sixteenth word lines (WL1 to WL16 in FIGS. 2 and 9 ). The second memory area 22 may include a plurality of memory cells (MC in FIGS. 2 and 9 ) connected to the first to sixteenth word lines (WL1 to WL16 in FIGS. 2 and 9 ). The second memory area 22 receives the read signal RD during a read operation and uses the first to Nth internal addresses IADD<1:N> to the first to sixteenth word lines (WL1 of FIGS. 2 and 9). The data DATA stored in the memory cell (MC of FIGS. 2 and 9) connected to the selected word line among ~WL16) can be output. The second memory area 22 receives the write signal WT during a write operation and uses the first to Nth internal addresses IADD<1:N> to the first to sixteenth word lines (WL1 of FIGS. 2 and 9). Data DATA may be stored in a memory cell (MC of FIGS. 2 and 9 ) connected to a word line selected from among ~WL16 ). During the self-refresh operation, the second memory area 22 may receive the internal refresh signal IR and perform a refresh operation on the first to sixteenth word lines (WL1 to WL16 in FIGS. 2 and 9 ). During the smart refresh operation, the second memory area 22 may refresh word lines adjacent to the word lines selected by the first to Nth target addresses TADD<1:N>. The read signal RD and the write signal WT may be internally generated by a command input from an external device (eg, a controller) during read and write operations in a general active operation. The second memory area 22 is implemented to include first to sixteenth word lines (WL1 to WL16 in FIGS. 2 and 9 ), but may be implemented to include various numbers of word lines according to embodiments.

The first to sixteenth row hammering word lines (RWL1 to RWL16 in FIGS. 2 and 9) included in the first memory area 21 and the first to sixteenth word lines included in the second memory area 22 (FIG. 2) and WL1 to WL16 of 9), word lines of the same order may be simultaneously activated by the first to N th internal addresses (IADD<1:N>). For example, when the first row hammering word line (RWL1 in FIGS. 2 and 9) included in the first memory area 21 is activated by the first to Nth internal addresses IADD<1:N>, The first word line (WL1 in FIGS. 2 and 9 ) included in the second memory area 22 may be activated. The first to sixteenth row hammering word lines (RWL1 to RWL16 in FIGS. 2 and 9) included in the first memory area 21 and the first to sixteenth word lines included in the second memory area 22 (FIG. 2) and WL1 to WL16 of 9) are implemented with different word lines, but this is only one embodiment and may be implemented with the same word line depending on the embodiment.

Referring to FIG. 2, positions of components of the electronic device 1 according to an embodiment of the present invention will be described as follows.

A row area for controlling the first memory area 21 and the second memory area 22 may be located on the left side of the first memory area 21 and the second memory area 22 . A column area for controlling the first memory area 21 and the second memory area 22 may be positioned below the first memory area 21 and the second memory area 22 . A cross area (CRESS AREA) may be located at a position where the lower side of the row area and the left side of the column area (COLUMN AREA) intersect. Depending on the embodiment, the row area may be implemented to be located on the right side of the first memory area 21 and the second memory area 22, and the column area COLUMN AREA may be located in the first memory area 21. and the upper side of the second memory area 22 may be implemented.

Meanwhile, the active control circuit 11, the target address generation circuit 12, the internal address generation circuit 13, and the refresh control circuit 14 include a first memory area 21 and a second memory area 22. It may be located in the row area (10, ROW AREA) for controlling the memory area 20, or may be located in the row area (10, ROW AREA) and the cross area (CRESS AREA) together. The row area (ROW AREA), column area (COLUMN AREA) and cross area (CROSS AREA) shown in FIG. 2 activate a plurality of word lines included in the second memory area 22 to input and output data (DATA). It can be implemented to include control circuits for

3 is a block diagram of an active control circuit 11 according to one embodiment. As shown in FIG. 3 , the active control circuit 11 may include a ring oscillator 111 , an ROD counter 122 and an internal signal generating circuit 113 .

The ring oscillator 111 may generate a toggled periodic signal OSC based on the active command ACT and the refresh command REF. The ring oscillator 111 may generate a periodic signal OSC that is periodically toggled when the active command ACT is input. The ring oscillator 111 may generate a periodic signal OSC that is periodically toggled when the refresh command REF is input.

The ROD counter 122 may generate first to K th vibration counting signals OCNT<1:K> counted based on the periodic signal OSC. The ROD counter 122 may generate first to K th vibration counting signals OCNT<1:K> that are counted whenever a pulse of the periodic signal OSC is input. The number of bits 'K' of the first to Kth vibration counting signals OCNT<1:K> may be set to various numbers according to embodiments.

The internal signal generating circuit 113 includes an internal read signal (IRD) and an internal comparison signal (ICMP) sequentially enabled based on the refresh signal REF and the first to K th vibration counting signals OCNT<1:K>. and an internal light signal IWT. The internal signal generating circuit 113 may generate an internal lead signal IRD when the first to K th vibration counting signals OCNT<1:K> are counted with a first logic level combination. The internal signal generating circuit 113 may generate an internal comparison signal ICMP when the first to K th vibration counting signals OCNT<1:K> are counted with the second logic level combination. The internal signal generating circuit 113 may generate the internal light signal IWT when the first to K th vibration counting signals OCNT<1:K> are counted as a third logic level combination. The internal signal generating circuit 113 generates the internal light signal IWT when the refresh command REF is input and the first to K th vibration counting signals OCNT<1:K> are counted as a third logic level combination. can create When the first to Kth vibration counting signals OCNT<1:K> are counted in the second logic level combination, the first to Kth vibration counting signals OCNT<1:K> are counted in the first logic level combination. It means a case that is counted more than the case that is counted. When the first to Kth vibration counting signals OCNT<1:K> are counted in a third logic level combination, the first to Kth vibration counting signals OCNT<1:K> are counted in a second logic level combination. It means a case that is counted more than the case that is counted.

4 is a block diagram of a target address generation circuit 12 according to one embodiment. As shown in FIG. 4, the target address generation circuit 12 may include an input circuit 121, an adder 122, an output circuit 123, a comparison circuit 124, and a smart refresh control circuit 125. there is.

The input circuit 121 transmits first to sixth read counting signals RCA<1:6> received from the first memory area 21 when the internal read signal IRD is input. A lead counting signal (TRC<1:6>) can be generated. When the internal lead signal IRD is input, the input circuit 121 buffers the first to sixth lead counting signals RCA<1:6> to transfer the first to sixth transfer lead counting signals TRC<1:6 >) can be created. Although the first to sixth lead counting signals (RCA<1:6>) and the first to sixth transfer lead counting signals (TRC<1:6>) are implemented with 6 bits, this is only one example, depending on the embodiment. It can be implemented with various bit numbers.

The adder 122 may up-count the first to sixth transfer lead counting signals TRC<1:6>. The adder 122 may generate first to sixth counting signals TWC<1:6> by up-counting the first to sixth transfer lead counting signals TRC<1:6>. Although the first to sixth counting signals TWC<1:6> are implemented with 6 bits, this is only an example and may be implemented with various numbers of bits according to embodiments.

The output circuit 123 may generate first to sixth light counting signals WCA<1:6> from the first to sixth counting signals TWC<1:6> during internal light operation. The output circuit 123 generates first to sixth light counting signals WCA<1:6> from the first to sixth counting signals TWC<1:6> when the internal light signal IWT is input. can do. The output circuit 123 may output the first to sixth light counting signals WCA<1:6> to the first memory area 21 when the internal write signal IWT is input. The output circuit 123 may initialize all bits of the first to sixth light counting signals WCA<1:6> to a logic low level after the smart refresh operation is performed. The output circuit 123 may initialize all bits of the first to sixth light counting signals WCA<1:6> to a logic low level when the reset signal RST is input after the smart refresh operation is performed. . When the internal light signal IWT is input after the smart refresh operation is performed, the output circuit 123 has first to sixth light counting signals WCA< 1:6>) can be output to the first memory area 21 . Although the first to sixth light counting signals WCA<1:6> are implemented with 6 bits, this is only an example and may be implemented with various numbers of bits according to embodiments.

When the internal comparison signal ICMP is input, the comparison circuit 124 includes the first to sixth counting signals TWC<1:6> and the first to sixth stored counting signals (SWC<1 in FIG. 6). :6>) can be compared to generate the flag signal UPF. When the internal comparison signal ICMP is input, the comparison circuit 124 has first to sixth counting signals TWC<1:6> stored therein (SWC<1 in FIG. 6). :6>), an enabled flag signal UPF can be generated. When the internal comparison signal ICMP is input, the comparison circuit 124 has first to sixth counting signals TWC<1:6> stored therein (SWC<1 in FIG. 6). :6>) When counting is less than or equal to, a disabled flag signal UPF may be generated. When the internal comparison signal ICMP is input, the comparison circuit 124 has first to sixth counting signals TWC<1:6> stored therein (SWC<1 in FIG. 6). :6>), the first to sixth counting signals (TWC<1:6>) may be stored as the first to sixth storage counting signals (SWC<1:6> in FIG. 6). The comparison circuit 124 initializes all bits of the first to sixth storage counting signals (SWC<1:6> in FIG. 6) to a logic low level when the reset signal RST is input after the smart refresh operation is performed. can do.

When the flag signal UPF is input, the smart refresh control circuit 125 may store the first to Nth addresses ADD<1:N> as the first to Nth target addresses TADD<1:N>. there is. The smart refresh control circuit 125 may output the stored first to Nth target addresses TADD<1:N> to the second memory area 22 when the smart refresh signal SR is input. The smart refresh control circuit 125 may generate a reset signal RST that is enabled when the first to Nth target addresses TADD<1:N> are output.

5 is a block diagram of a comparator circuit 124 according to one embodiment. As shown in FIG. 5 , the comparison circuit 124 may include a counting signal storage circuit 124_1 and a flag signal generation circuit 124_2.

When the flag signal UPF is input, the counting signal storage circuit 124_1 converts the first to sixth counting signals TWC<1:6> into first to sixth storage counting signals SWC<1:6>. can be saved The counting signal storage circuit 124_1 may output the stored first to sixth counting signals TWC<1:6> as first to sixth stored counting signals SWC<1:6>. The counting signal storage circuit 124_1 may initialize the first to sixth storage counting signals SWC<1:6> when the reset signal RST is input. The counting signal storage circuit 124_1 may initialize all bits of the first to sixth storage counting signals SWC<1:6> to a logic low level when the reset signal RST is input.

The flag signal generation circuit 124_2 generates a flag signal UPF by comparing the first to sixth counting signals TWC<1:6> with the first to sixth storage counting signals SWC<1:6>. can do. The flag signal generating circuit 124_2 is a flag signal that is enabled when the first to sixth counting signals TWC<1:6> are counted more than the first to sixth storage counting signals SWC<1:6>. (UPF) can be created.

6 is a block diagram of a flag signal generating circuit 124_2 according to an embodiment. As shown in FIG. 6 , the flag signal generating circuit 124_2 may include a first comparator 210 , a second comparator 220 , a third comparator 230 and a logic circuit 240 .

The first comparator 210 compares the fifth and sixth counting signals TWC<5:6> with the fifth and sixth storage counting signals SWC<5:6>, and compares the first detection signal DET<1 >) and the second detection signal DET<2>. The first comparator 210 is enabled when the fifth and sixth counting signals TWC<5:6> and the fifth and sixth storage counting signals SWC<5:6> are the same logic level combination. 1 detection signal (DET<1>) can be generated. The first comparator 210 is enabled when the fifth and sixth counting signals TWC<5:6> and the fifth and sixth storage counting signals SWC<5:6> are different logic level combinations. 2 detection signals (DET<2>) can be generated. The first comparator 210 is implemented to compare the 2-bit fifth and sixth counting signals TWC<5:6> with the fifth and sixth storage counting signals SWC<5:6>, but this is one is only an example of, and may be implemented to compare various numbers of bits according to embodiments.

The second comparator 220 compares the third and fourth counting signals TWC<3:4> and the third and fourth storage counting signals SWC<3:4> to obtain a third detection signal DET<3 >) and a fourth detection signal DET<4>. The second comparator 220 is enabled when the third and fourth counting signals TWC<3:4> and the third and fourth storage counting signals SWC<3:4> are the same logic level combination. 3 detection signals (DET<3>) can be generated. The second comparator 220 is enabled when the third and fourth counting signals TWC<3:4> and the third and fourth storage counting signals SWC<3:4> are different logic level combinations. 4 detection signals (DET<4>) can be generated. The second comparator 220 is implemented to compare the 2-bit third and fourth counting signals (TWC<3:4>) and the third and fourth storage counting signals (SWC<3:4>), but this is one is only an example of, and may be implemented to compare various numbers of bits according to embodiments.

The third comparator 230 compares the first and second counting signals TWC<1:2> and the first and second storage counting signals SWC<1:2> to obtain a fifth detection signal DET<5 >) and a sixth detection signal DET<6>. The third comparator 230 is enabled when the first and second counting signals TWC<1:2> and the first and second storage counting signals SWC<1:2> are the same logic level combination. 5 detection signals (DET<5>) can be generated. The third comparator 230 is enabled when the first and second counting signals TWC<1:2> and the first and second storage counting signals SWC<1:2> are different logic level combinations. 6 detection signals (DET<6>) can be generated. The third comparator 230 is implemented to compare the 2-bit first and second counting signals TWC<1:2> and the first and second storage counting signals SWC<1:2>, but this is one is only an example of, and may be implemented to compare various numbers of bits according to embodiments.

The logic circuit 240 receives the first detection signal DET<1>, the second detection signal DET<2>, the third detection signal DET<3>, the fourth detection signal DET<4>, and The flag signal UPF may be generated based on the sixth detection signal DET<6>. The logic circuit 240 receives the first detection signal DET<1>, the second detection signal DET<2>, the third detection signal DET<3>, the fourth detection signal DET<4>, and The flag signal UPF may be generated according to the logic level of the sixth detection signal DET<6>. The logic circuit 240 is disabled when both the first detection signal DET<1> and the third detection signal DET<3> are enabled and the sixth detection signal DET<6> is disabled. A flag signal UPF may be generated. The logic circuit 240 has a flag enabled when any one of the second detection signal DET<2>, the fourth detection signal DET<4>, and the sixth detection signal DET<6> is enabled. A signal UPF can be generated.

7 is a block diagram of a smart refresh control circuit 125 according to an embodiment. As shown in FIG. 7 , the smart refresh control circuit 125 may include an address storage circuit 125_1 and a reset control circuit 125_2.

The address storage circuit 125_1 stores the first to Nth target addresses TAD<1:N> from the first to Nth addresses ADD<1:N> based on the flag signal UPF and the smart refresh signal SR. ) can be created. The address storage circuit 125_1 converts the first to Nth addresses ADD<1:N> into the first to Nth target addresses TAD<1:N> when the flag signal UPF is input at a logic high level. can be saved as The address storage circuit 125_1 may output the stored first to Nth target addresses TAD<1:N> when the smart refresh signal SR is input at a logic high level.

The reset control circuit 125_2 may generate a reset signal RST based on the smart refresh signal SR. The reset control circuit 125_2 may generate a reset signal RST that is enabled when the smart refresh operation is completed after the smart refresh signal SR is input. The reset control circuit 125_2 may generate an enabled reset signal RST by delaying the smart refresh signal SR after the smart refresh operation is completed.

8 is a block diagram of a refresh control circuit 14 according to an embodiment. As shown in FIG. 8 , the refresh control circuit 14 may include a refresh counter 141 and a refresh signal generation circuit 142 .

The refresh counter 141 may generate first through Jth refresh counting signals RCNT<1:J> based on the refresh command REF. The refresh counter 141 may generate first through Jth refresh counting signals RCNT<1:J> that are up-counted whenever the refresh command REF is input. The number of bits 'J' of the first to Jth refresh counting signals RCNT<1:J> may be set to various numbers according to embodiments.

The refresh signal generating circuit 142 may generate the smart refresh signal SR and the internal refresh signal IR based on the first through Jth refresh counting signals RCNT<1:J>. The refresh signal generating circuit 142 may generate the smart refresh signal SR when the first to Jth refresh counting signals RCNT<1:J> are counted as the fourth logic level combination. The refresh signal generating circuit 142 generates a smart refresh signal SR including pulses sequentially generated when the first to Jth refresh counting signals RCNT<1:J> are counted as the fourth logic level combination. can do. The fourth logic level combination of the first to Jth refresh counting signals RCNT<1:J> may be set to the number of times the refresh command REF is input to perform the smart refresh operation. The refresh signal generating circuit 142 may generate an internal refresh signal IR when the first to Jth refresh counting signals RCNT<1:J> are counted as a fifth logic level combination. A fifth logic level combination of the first to Jth refresh counting signals RCNT<1:J> may be set to the number of times the refresh command REF is input to perform the self-refresh operation.

The operation of the first memory area 21 and the second memory area 22 for performing the smart refresh operation will be described with reference to FIG. 9, but the first to Nth internal addresses IADD<1:N> are A case of a combination for selecting two word lines WL2 will be described as follows.

In the first memory area 21, the second row hammering word line RWL2 is formed by the first to Nth internal addresses IADD<1:N> for selecting the second word line WL2 during an internal read operation. can be activated. The first memory area 21 transmits the first to sixth write counting signals WCA<1:6> stored in the row hammering cells RC connected to the second row hammering word line RWL2 through first to sixth leads. It can be output as a counting signal (RCA<1:6>).

The second memory area 22 includes the first word line WL1: N−1 and the third word line WL1: N−1 by the first to N th target addresses TAD<1:N> for selecting the second word line WL2. The word line (WL3: N+1) is activated so that a smart refresh operation can be performed.

In the first memory area 21, the second row hammering word line RWL2 is formed by the first to Nth internal addresses IADD<1:N> for selecting the second word line WL2 during an internal write operation. can be activated. The first memory area 21 may store first to sixth write counting signals WCA<1:6> stored in the row hammering cells RC connected to the second row hammering word line RWL2. At this time, since the first to sixth light counting signals WCA<1:6> are after performing the smart refresh operation, all bits can be initialized to a logic low level.

That is, the first memory area 21 stores input count information of logic level combinations of all first to Nth addresses ADD<1:N>, and stores all first to Nth addresses ADD<1:N>. The first to sixth lead counting signals RCA<1:6> obtained by counting logic level combinations of >) may be provided to the target address generation circuit 12 . The second memory area 22 includes first to sixteenth word lines WL1 to WL16, which are information on word lines most activated by the first to Nth addresses ADD<1:N>. A smart refresh operation can be performed by N target addresses (TAD<1:N>).

A smart refresh operation of the electronic device 1 according to an embodiment of the present invention will be described with reference to FIG. 10 .

The smart refresh operation may include an initialization operation step S1, an active detection step S2, a target address generation step S3, and a smart refresh execution step S4.

The initialization operation step S1 may be set to a power-up period and a boot-up operation for starting the operation of the electronic device 1 . In the initialization operation step S1 , the first memory area 21 receives the initialization signal INIT to initialize the first to sixth light counting signals WCA<1:6> stored therein. The first to sixth write counting signals WCA<1:6> stored therein are stored in the first to sixteenth row hammering word lines RWL1 to RWL16, respectively. :6>), and all bits of the first to sixth write counting signals WCA<1:6> may be initialized to a logic low level.

The active sensing step (S2) may include an active operation step (S21), an internal read, counting and internal write operation step (S22), and a comparison operation step (S23).

The active operation step (S21) is set to a step of receiving an active command (ACT), a refresh command (REF), and the first to Nth addresses (ADD<1:N>) from an external device (eg, a controller). can

The internal read, counting and internal write operation step S22 may be set to generate an internal read signal IRD, an internal comparison signal ICMP, and an internal write signal IWT based on the active command ACT. In the internal read, counting, and internal write operation step S22, the active control circuit 11 generates an internal read signal IRD, an internal comparison signal ICMP, and an internal write signal IWT based on the active command ACT. can When the internal read signal IRD is generated in the internal read, counting and internal write operation step S22, the target address generation circuit 12 receives the first to sixth read counting signals (input from the first memory area 21). RCA<1:6>) may be up-counted to generate first to sixth counting signals TWC<1:6>. In the internal read, counting, and internal write operation step S22, the active control circuit 11 may generate the internal comparison signal ICMP and the internal write signal IWT after generating the internal read signal IRD. When the internal write signal IWT is generated in the internal read, counting, and internal write operation step S22, the target address generating circuit 12 generates first through sixth counting signals TWC<1:6>. A sixth light counting signal WCA<1:6> may be generated, and the first to sixth light counting signals WCA<1:6> may be output to the first memory area 21 . In the internal read, counting, and internal write operation step S22, the first memory area 21 may store the first to sixth light counting signals WCA<1:6>.

The comparison operation step S23 may be set to an operation of comparing the first to sixth counting signals TWC<1:6> with the first to sixth storage counting signals SWC<1:6>. In the comparison operation step (S23), when the internal comparison signal (ICMP) is input to the target address generation circuit 12, the first to sixth counting signals (TWC<1:6>) and the first to sixth storage counting signals ( SWC<1:6>) can be compared. In the comparison operation step (S23), the target address generating circuit 12 counts the first to sixth counting signals TWC<1:6> more than the first to sixth storage counting signals SWC<1:6>. If yes, an enabled flag signal UPF may be generated. In the comparison operation step (S23), the target address generation circuit 12 has the first to sixth counting signals (TWC<1:6>) less than the first to sixth storage counting signals (SWC<1:6>) or In the case of identical counting (NO), a disabled flag signal UPF may be generated.

The target address generation step (S3) may include a counting signal update operation step (S31), a target address update operation step (S32), and a target address maintenance operation step (S33).

In the counting signal update operation step (S31), the first to sixth counting signals (TWC<1:6>) in the comparison operation step (S23) are larger than the first to sixth storage counting signals (SWC<1:6>). If counting (YES) may be performed. In the counting signal updating operation step (S31), the target address generating circuit 12 converts the first to sixth counting signals TWC<1:6> according to the enabled flag signal UPF into the first to sixth storage counting It can be stored as a signal (SWC<1:6>).

In the target address update operation step (S32), the first to sixth counting signals (TWC<1:6>) in the comparison operation step (S23) are larger than the first to sixth storage counting signals (SWC<1:6>). If counting (YES) may be performed. In the target address updating operation step S32, the target address generating circuit 12 converts the first to Nth addresses ADD<1:N> into the first to Nth target addresses ( TAD<1:N>).

In the target address maintaining operation step (S33), the first to sixth counting signals (TWC<1:6>) in the comparison operation step (S23) are smaller than the first to sixth storage counting signals (SWC<1:6>). or if they are counted equally (NO), it can be performed. In the target address maintaining operation step S33, the target address generating circuit 12 converts the first to Nth addresses ADD<1:N> into the first to Nth target addresses ( TAD<1:N>). That is, the first to Nth target addresses (TAD<1:N>) retain the most activated word line information. When the target address maintaining operation step (S33) ends, the active operation step (S21) can be re-entered.

The smart refresh execution step (S4) may be set to a step of performing a smart refresh operation by the refresh command (REF). In the smart refresh execution step (S4), the target address generation circuit 12 stores the first to Nth target addresses TAD<1:N> stored when the smart refresh signal SR is input into the second memory area 22. can be output as In the smart refresh execution step S4, the second memory area 22 includes word lines N+1 and N+1 adjacent to word lines selected by the first to Nth target addresses TAD<1:N>. ) to activate the smart refresh operation. In the smart refresh operation S4 , the row hammering cells RC included in the first memory area 61 may be initialized. When the smart refresh step (S4) ends, the active operation step (S21) can be re-entered.

Referring to FIG. 11, a smart refresh operation of another electronic device 1 according to an embodiment of the present invention will be described as follows.

At time T1, an active command (ACT) is input from an external device (eg, a controller).

At time T2, the active control circuit 11 generates the internal lead signal IRD based on the active command ACT. The target address generation circuit 12 receives the internal read signal IRD and up-counts the first to sixth read counting signals RCA<1:6> input from the first memory area 21 to generate the first through sixth read counting signals RCA<1:6>. A sixth counting signal (TWC<1:6>) is generated.

At time T3, the active control circuit 11 generates the internal comparison signal ICMP based on the active command ACT. When the internal comparison signal ICMP is input, the target address generating circuit 12 generates first to sixth counting signals TWC<1:6> and first to sixth storage counting signals SWC<1:6>. is compared to generate a flag signal UPF. The target address generation circuit 12 stores the first to Nth addresses ADD<1:N> as the first to Nth target addresses TAD<1:N> when the flag signal UPF is enabled. do. When the flag signal UPF is enabled, the target address generation circuit 12 converts the first to sixth counting signals TWC<1:6> into the first to sixth storage counting signals SWC<1:6>. Save as The first to sixth storage counting signals SWC<1:6> are generated from the first to sixth counting signals TWC<1:6> that are counted the most. The target address generating circuit 12 stores the first to Nth addresses ADD<1:N> as the first to Nth target addresses TAD<1:N> when the flag signal UPF is disabled. I never do that. The target address generation circuit 12 converts the first to sixth counting signals TWC<1:6> into the first to sixth storage counting signals SWC<1:6> when the flag signal UPF is disabled. do not save as

At time T4, the active control circuit 11 generates an internal write signal IWT based on the active command ACT. The target address generation circuit 12 receives the internal write signal IWT and receives the first to sixth light counting signals WCA<1:6> generated from the first to sixth counting signals TWC<1:6>. ) is output to the first memory area 21. The first memory area 21 includes row hammer rings connected to row hammer ring word lines activated by the first to N th internal addresses IADD<1:N> among the first to sixteen row hammer ring word lines RWL1 to RWL16. The first to sixth light counting signals WCA<1:6> are stored in the cell RC.

At the time T5, a refresh command (REF) is input from an external device (eg, a controller). At this time, the refresh command (REF) means a case where it is repeatedly input to perform a smart refresh operation.

At time T6, the refresh control circuit 14 generates a first pulse of the smart refresh signal SR based on the refresh command REF. The target address generation circuit 12 outputs the first to Nth target addresses TAD<1:N> to the second memory area 22 by the first pulse of the smart refresh signal SR. The second memory area 22 includes word lines N+1 adjacent to word lines selected by the first to Nth target addresses TAD<1:N> among the first to sixteenth word lines WL1 to WL16. ) is activated to perform the smart refresh operation (SMART REFRESH). Meanwhile, the second memory area 22 is adjacent to the word line N of the word line selected by the first to Nth target addresses TAD<1:N> among the first to sixteenth word lines WL1 to WL16. +2) is activated to perform the smart refresh operation (SMART REFRESH).

At time T7, the refresh control circuit 14 generates a second pulse of the smart refresh signal SR based on the refresh command REF. The target address generation circuit 12 outputs the first to Nth target addresses TAD<1:N> to the second memory area 22 by the second pulse of the smart refresh signal SR. The second memory area 22 is an adjacent word line (N-1) of a word line selected by the first to Nth target addresses (TAD<1:N>) among the first to sixteenth word lines (WL1 to WL16). ) is activated to perform the smart refresh operation (SMART REFRESH). Meanwhile, the second memory area 22 is adjacent to the word line N of the word line selected by the first to Nth target addresses TAD<1:N> among the first to sixteenth word lines WL1 to WL16. -2) is activated to perform the smart refresh operation (SMART REFRESH).

At time T8, the refresh control circuit 14 generates a third pulse of the smart refresh signal SR based on the refresh command REF.

The reset control circuit 125_2 generates an enabled reset signal RST when a smart refresh operation is completed after the smart refresh signal SR is input.

The counting signal storage circuit 124_1 initializes all bits of the first to sixth storage counting signals SWC<1:6> to a logic low level when the reset signal RST is input. That is, the first to sixth storage counting signals (SWC<1:6>) are initialized (STORAGE COUNTING SIGNAL INITIAL).

The active control circuit 11 generates an internal write signal IWT based on the refresh command REF. The target address generation circuit 12 receives the internal write signal IWT and transmits the first to sixth write counting signals WCA<1:6>, in which all bits are initialized to a logic low level, to the first memory area 21. output as The first memory area 21 includes row hammer rings connected to row hammer ring word lines activated by the first to N th internal addresses IADD<1:N> among the first to sixteen row hammer ring word lines RWL1 to RWL16. The initialized first to sixth light counting signals WCA<1:6> are stored in the cell RC. That is, the row hammering cells RC of the first memory area 21 are initialized (RC INITIAL).

The electronic device 1 according to an embodiment of the present invention as described above further includes a memory area storing information on the number of inputs of logic level combinations of all addresses, and according to a result of counting all address combinations, the most active A smart refresh operation may be performed to refresh word lines adjacent to the selected word line. In addition, the electronic device 1 may prevent interference between word lines by storing a result of counting all address combinations and refreshing word lines adjacent to the most activated word line using the result.

As shown in FIG. 12, the electronic device 2 according to another embodiment of the present invention includes an active control circuit 31, a target address generation circuit 32, an internal address generation circuit 33, and a counting signal input/output circuit. (34), a refresh control circuit 35, a column control circuit 36, a first memory area 41 and a second memory area 42.

The active control circuit 31 may receive an active command ACT and a refresh command REF from an external device (eg, a controller). The active control circuit 31 may generate an internal read signal IRD, an internal comparison signal ICMP, and an internal write signal IWT based on the active command ACT and the refresh command REF. The active control circuit 31 may generate an internal read signal IRD, an internal comparison signal ICMP, and an internal write signal IWT sequentially generated based on the active command ACT. The active control circuit 31 may generate an internal write signal IWT based on the refresh command REF. Since the active control circuit 31 is implemented with the same circuit as the active control circuit 11 shown in FIG. 1 and performs the same operation, a detailed description thereof will be omitted.

The target address generation circuit 32 may receive an internal read signal IRD, an internal comparison signal ICMP, and an internal write signal IWT from the active control circuit 31 . The target address generating circuit 32 may receive first to Nth addresses ADD<1:N> from an external device (eg, a controller). The target address generating circuit 32 may receive the smart refresh signal SR from the refresh control circuit 35 . The target address generation circuit 32 includes first to sixth read counting signals (RCA<1:6>), which are input count information of the logic level combination of the first to Nth addresses (ADD<1:N>) during an internal read operation. ) may be up-counted to generate the first to sixth counting signals (TWC<1:6> in FIG. 3). The target address generating circuit 32 up-counts the first to sixth lead counting signals RCA<1:6> input from the counting signal input/output circuit 34 when the internal lead signal IRD is input, to a sixth counting signal (TWC<1:6> in FIG. 3). The target address generation circuit 32 counts the first to sixth counting signals (TWC<1:6> in FIG. 3) more than the first to sixth storage counting signals (SWC<1:6> in FIG. 6). At this time, the first to sixth counting signals (TWC<1:6> in FIG. 3) may be stored as the first to sixth storage counting signals (SWC<1:6> in FIG. 6). The target address generating circuit 32 receives the smart refresh signal SR and receives the first to Nth addresses ADD<1:N corresponding to the first to sixth counting signals (TWC<1:6> in FIG. 3). >) may be stored as first to Nth target addresses (TAD<1:N>). The target address generation circuit 32 receives the internal write signal IWT and receives the first to sixth light counting signals WCA<1:6> generated from the first to sixth counting signals (TWC<1:6> in FIG. :6>) can be output to the counting signal input/output circuit 34. The target address generating circuit 32 converts the most counted first to sixth counting signals (TWC<1:6> in FIG. 3) into first to sixth storage counting signals (SWC<1:6> in FIG. 6). can be saved as The target address generation circuit 32 may initialize the first to sixth storage counting signals (SWC<1:6> in FIG. 6) in a smart refresh operation. Since the target address generating circuit 32 is implemented with the same circuit as the target address generating circuit 12 shown in FIG. 1 and performs the same operation, a detailed description thereof will be omitted.

The internal address generating circuit 33 may receive first to Nth addresses ADD<1:N> from an external device (eg, a controller). The internal address generation circuit 33 may generate the first to Nth internal addresses IADD<1:N> from the first to Nth addresses ADD<1:N>. The internal address generation circuit 33 may output the first to Nth addresses ADD<1:N> as the first to Nth internal addresses IADD<1:N>. The internal address generation circuit 33 is implemented to output the first to Nth addresses ADD<1:N> as the first to Nth internal addresses IADD<1:N>, but the first to Nth addresses It may be implemented to decode (ADD<1:N>) to generate first to Nth internal addresses (IADD<1:N>). The number of bits of the first to Nth addresses ADD<1:N> and the first to Nth internal addresses IADD<1:N> may be set in various ways according to embodiments.

The counting signal input/output circuit 34 may be located between the target address generation circuit 32 and the first memory area 41 . The counting signal input/output circuit 34 may be connected to the first memory area 41 through a row hammering input/output line (RIO). The counting signal input/output circuit 34 may include an input/output sense amplifier 341 and a write driver 342 . The input/output sense amplifier 341 converts the first to sixth read counting signals RCA<1:6> output from the first memory area 41 to the row hammering input/output line RIO during an internal read operation into a target address generating circuit. (32) can be output. The write driver 342 may output the first to sixth write counting signals WCA<1:6> output from the target address generating circuit 32 to the row hammering input/output line RIO during an internal write operation. The row hammering input/output line (RIO) may be configured to include a plurality of row hammering input/output lines.

The refresh control circuit 35 may receive a refresh command REF from an external device (eg, a controller). The refresh control circuit 35 may generate a smart refresh signal SR and an internal refresh signal IR based on the refresh command REF. The refresh control circuit 35 may generate a smart refresh signal SR that is enabled when the refresh command REF is repeatedly input the number of times to perform the smart refresh operation. The refresh control circuit 35 may generate an internal refresh signal IR that is enabled when the refresh command REF is repeatedly input the number of times for performing the self-refresh operation. Since the refresh control circuit 35 is implemented with the same circuit as the refresh control circuit 14 shown in FIG. 1 and performs the same operation, a detailed description thereof will be omitted.

The column control circuit 36 may be connected to the second memory area 42 through a local input/output line (LIO). The column control circuit 36 may output data DATA output from the second memory area 42 to the local input/output line LIO during a read operation to an external device (eg, a controller). The column control circuit 36 may output data DATA input from an external device (eg, a controller) to the local input/output line LIO during a write operation. The column control circuit 36 may be implemented as a circuit that performs an operation of inputting/outputting data in a general memory device. The local input/output line (LIO) may be set to include a plurality of local input/output lines.

The first memory area 41 may include first to sixteenth row hammering word lines (RWL1 to RWL16 in FIGS. 2 and 9 ). The first memory area 41 may include a plurality of row hammering cells (RCs in FIGS. 2 and 9 ) connected to the first to sixteenth row hammering word lines (RWL1 to RWL16 in FIGS. 2 and 9 ). The first memory area 41 selects among the first to sixteenth row hammering word lines (RWL1 to RWL16 in FIGS. 2 and 9) by the first to Nth internal addresses (IADD<1:N>) during an internal read operation. The first to sixth lead counting signals RCA<1:6> stored in the row hammering cells (RCs in FIGS. 2 and 9 ) connected to the row hammering word lines may be output to the row hammering input/output lines (RIO). The first memory area 41 selects among the first to sixteenth row hammering word lines (RWL1 to RWL16 in FIGS. 2 and 9) by the first to Nth internal addresses (IADD<1:N>) during an internal write operation. The first to sixth light counting signals WCA<1:6> carried on the row hammering input/output line RIO may be stored in the row hammering cell (RC in FIGS. 2 and 9 ) connected to the row hammering word line. The first memory area 41 receives the initialization signal INIT input during the power-up period for starting the operation of the electronic device 2 and the boot-up operation, and stores the first to sixth light counting signals WCA<1 :6>) can be initialized. All bits of the initialized first to sixth light counting signals WCA<1:6> may be generated at a logic low level. The first memory area 41 is implemented to include the first to 16th row hammering word lines (RWL1 to RWL16 in FIGS. 2 and 9 ), but may be implemented to include various numbers of row hammering word lines according to embodiments. there is. The first memory area 41 includes first to Nth addresses (ADD<1: The first to sixth write counting signals (WCA<1:6>), which are input count information for each logic level combination of N>), are connected to the first to sixteenth row hammering word lines (RWL1 to RWL16 in FIGS. 2 and 9) It can be stored in a row hammering cell (RC in FIGS. 2 and 9). Since the first memory area 41 is implemented identically to the first memory area 21 shown in FIGS. 2 and 9 and performs the same operation, a detailed description thereof will be omitted.

The second memory area 42 may include first to sixteenth word lines (WL1 to WL16 in FIGS. 2 and 9 ). The second memory area 42 may include a plurality of memory cells (MC in FIGS. 2 and 9 ) connected to the first to sixteenth word lines (WL1 to WL16 in FIGS. 2 and 9 ). The second memory area 42 receives the read signal RD during a read operation and uses the first to Nth internal addresses IADD<1:N> to the first to sixteenth word lines (WL1 of FIGS. 2 and 9). ~ WL16) can output data (DATA) stored in the memory cell (MC of FIGS. 2 and 9) connected to the selected word line to the local input/output line (LIO). The second memory area 42 receives the write signal WT during a write operation and uses the first to Nth internal addresses IADD<1:N> to the first to sixteenth word lines (WL1 of FIGS. 2 and 9). ~ WL16) can store data (DATA) loaded on the local input/output line (LIO) in a memory cell (MC in FIG. 13) connected to a selected word line. During the self-refresh operation, the second memory area 42 may receive the internal refresh signal IR and perform a refresh operation on the first to sixteenth word lines (WL1 to WL16 in FIGS. 2 and 9 ). During the smart refresh operation, the second memory area 42 may refresh word lines adjacent to the word lines selected by the first to Nth target addresses TADD<1:N>. The read signal RD and the write signal WT may be internally generated by a command input from an external device (eg, a controller) during a general read and write operation. The second memory area 42 is implemented to include first to sixteenth word lines (WL1 to WL16 in FIGS. 2 and 9 ), but may be implemented to include various numbers of word lines according to embodiments. Since the second memory area 42 is implemented identically to the second memory area 22 shown in FIGS. 2 and 9 and performs the same operation, a detailed description thereof will be omitted.

The first to sixteenth row hammering word lines (RWL1 to RWL16 in FIGS. 2 and 9 ) included in the first memory area 41 and the first to sixteenth word lines included in the second memory area 42 (FIG. 2 and WL1 to WL16 of 9), word lines of the same order may be simultaneously activated by the first to N th internal addresses (IADD<1:N>). For example, when the first row hammering word line (RWL1 in FIGS. 2 and 9) included in the first memory area 41 is activated by the first to Nth internal addresses IADD<1:N>, The first word line (WL1 in FIGS. 2 and 9 ) included in the second memory area 42 may be activated. The first to sixteenth row hammering word lines (RWL1 to RWL16 in FIGS. 2 and 9 ) included in the first memory area 41 and the first to sixteenth word lines included in the second memory area 42 (FIG. 2 and WL1 to WL16 of 9) are implemented with different word lines, but this is only one embodiment and may be implemented with the same word line depending on the embodiment.

Meanwhile, the active control circuit 31, the target address generation circuit 32, the internal address generation circuit 33, the counting signal input/output circuit 34, the refresh control circuit 35, and the column control circuit 36 are the first memory It is located in the column area 30 (COLUMN AREA of FIG. 2) for controlling the memory area 40 including the area 41 and the second memory area 42, or the column area 30 (COLUMN AREA of FIG. 2) and may be located together in the cross area (CROSS AREA in FIG. 2).

The electronic device 2 according to an embodiment of the present invention as described above further includes a memory area storing information on the number of inputs of logic level combinations of all addresses, and according to a result of counting all address combinations, the most active A smart refresh operation may be performed to refresh word lines adjacent to the selected word line. In addition, the electronic device 2 may prevent interference between word lines by storing the result of counting all address combinations and refreshing word lines adjacent to the most activated word line using the result.

As shown in FIG. 13, the electronic device 3 according to another embodiment of the present invention includes an active control circuit 51, a target address generation circuit 52, an internal address generation circuit 53, a refresh control circuit ( 54), the first memory area 61 and the second memory area 62 may be included.

The active control circuit 51 may receive an active command (ACT) and a refresh command (REF) from an external device (eg, a controller). The active control circuit 51 may generate an internal read signal IRD, an internal comparison signal ICMP, and an internal write signal IWT based on the active command ACT and the refresh command REF. The active control circuit 51 may generate an internal read signal IRD, an internal comparison signal ICMP, and an internal write signal IWT sequentially generated based on the active command ACT. The active control circuit 51 may generate the internal write signal IWT based on the refresh command REF. Since the active control circuit 51 is implemented with the same circuit as the active control circuit 11 shown in FIG. 1 and performs the same operation, a detailed description thereof will be omitted.

The target address generating circuit 52 may receive an internal read signal IRD, an internal comparison signal ICMP, and an internal write signal IWT from the active control circuit 51 . The target address generating circuit 52 may receive first to Nth addresses ADD<1:N> from an external device (eg, a controller). The target address generating circuit 52 may receive the first smart refresh signal SR1 and the second smart refresh signal SR2 from the refresh control circuit 35 . The target address generation circuit 52 includes first to sixth read counting signals (RCA<1:6>), which are input count information of the logic level combination of the first to Nth addresses (ADD<1:N>) during an internal read operation. ) may be up-counted to generate the first to sixth counting signals (TWC<1:6> in FIG. 14). The target address generation circuit 52 up-counts the first to sixth read counting signals RCA<1:6> input from the first memory area 61 when the internal read signal IRD is input, to sixth counting signals (TWC<1:6> in FIG. 14). The target address generation circuit 52 counts the first to sixth counting signals (TWC<1:6> in FIG. 14) more than the first to sixth storage counting signals (SWC<1:6> in FIG. 5). At this time, the first to sixth counting signals (TWC<1:6> in FIG. 14) may be stored as the first to sixth storage counting signals (SWC<1:6> in FIG. 5). The target address generation circuit 52 receives the first smart refresh signal SR1 and the second smart refresh signal SR2 and receives the first to sixth counting signals (TWC<1:6> in FIG. 14) corresponding to the first to sixth counting signals. The first to Nth addresses ADD<1:N> may be stored as the first to Nth target addresses TAD<1:N>. The target address generation circuit 52 generates first to sixth light counting signals (WCA<1:6>) generated from first to sixth counting signals (TWC<1:6> in FIG. 14) during internal light operation. It can be output to the first memory area 21 . The target address generation circuit 52 receives the internal write signal IWT and generates first to sixth light counting signals WCA<1:6> generated from the first to sixth counting signals (TWC<1:6> in FIG. :6>) may be output to the first memory area 61 . The target address generation circuit 52 converts the most counted first to sixth counting signals (TWC<1:6> in FIG. 14) into first to sixth storage counting signals (SWC<1:6> in FIG. 6). can be saved as The target address generating circuit 52 converts the most counted first to sixth counting signals (TWC<1:6> in FIG. 14) into first to sixth storage counting signals (SWC<1:6> in FIG. 5). can be saved as The target address generation circuit 52 may initialize the first to sixth storage counting signals (SWC<1:6> in FIG. 5) in a smart refresh operation.

The internal address generation circuit 53 may receive first through Nth addresses ADD<1:N> from an external device (eg, a controller). The internal address generating circuit 53 may generate the first to Nth internal addresses IADD<1:N> from the first to Nth addresses ADD<1:N>. The internal address generating circuit 53 may output the first to Nth addresses ADD<1:N> as the first to Nth internal addresses IADD<1:N>. The internal address generating circuit 53 is implemented to output the first to Nth addresses ADD<1:N> as the first to Nth internal addresses IADD<1:N>, but the first to Nth addresses It may be implemented to decode (ADD<1:N>) to generate first to Nth internal addresses (IADD<1:N>). The number of bits of the first to Nth addresses ADD<1:N> and the first to Nth internal addresses IADD<1:N> may be set in various ways according to embodiments.

The refresh control circuit 54 may receive a refresh command REF from an external device (eg, a controller). The refresh control circuit 54 may generate a first smart refresh signal SR1, a second smart refresh signal SR2, and an internal refresh signal IR based on the refresh command REF. The refresh control circuit 54 generates a first smart refresh signal SR1 and a second smart refresh signal SR2 that are sequentially enabled when the refresh command REF is repeatedly input the number of times to perform the smart refresh operation. can do. The refresh control circuit 54 may generate an internal refresh signal IR that is enabled when the refresh command REF is repeatedly input the number of times for performing the self-refresh operation.

The first memory area 61 may include first to sixteenth row hammering word lines (RWL1 to RWL16 in FIGS. 2 and 9 ). The first memory area 61 may include a plurality of row hammering cells (RCs in FIGS. 2 and 9 ) connected to the first to sixteenth row hammering word lines (RWL1 to RWL16 in FIGS. 2 and 9 ). The first memory area 61 selects among the first to sixteenth row hammering word lines (RWL1 to RWL16 in FIGS. 2 and 9) by the first to Nth internal addresses (IADD<1:N>) during an internal read operation. The first to sixth write counting signals (WCA<1:6>) stored in the row hammering cells (RC in FIGS. 2 and 9) connected to the row hammering word line to be 6>). The first memory area 61 selects among the first to 16th row hammering word lines (RWL1 to RWL16 in FIGS. 2 and 9) by the first to Nth internal addresses (IADD<1:N>) during an internal write operation. The first to sixth write counting signals WCA<1:6> may be stored in the row hammering cells (RCs of FIGS. 2 and 9 ) connected to the row hammering word lines. The first memory area 61 receives the initialization signal INIT input during the power-up period for starting the operation of the electronic device 3 and the boot-up operation, and stores the first to sixth light counting signals WCA<1 :6>) can be initialized. All bits of the initialized first to sixth light counting signals WCA<1:6> may be generated at a logic low level. The first memory area 61 is implemented to include the first to sixteenth row hammering word lines (RWL1 to RWL16 in FIGS. 2 and 9 ), but may be implemented to include various numbers of row hammering word lines according to embodiments. there is. The first memory area 61 includes first to Nth addresses (ADD<1: The first to sixth write counting signals (WCA<1:6>), which are input count information for each logic level combination of N>), are connected to the first to sixteenth row hammering word lines (RWL1 to RWL16 in FIGS. 2 and 9) It can be stored in a row hammering cell (RC in FIGS. 2 and 9). Since the first memory area 61 is implemented identically to the first memory area 21 shown in FIGS. 2 and 9 and performs the same operation, a detailed description thereof will be omitted.

The second memory area 62 may include first to sixteenth word lines (WL1 to WL16 in FIGS. 2 and 9 ). The second memory area 62 may include a plurality of memory cells (MC in FIGS. 2 and 9 ) connected to the first to sixteenth word lines (WL1 to WL16 in FIGS. 2 and 9 ). The second memory area 62 receives the read signal RD during a read operation and uses the first to Nth internal addresses IADD<1:N> to the first to sixteenth word lines (WL1 of FIGS. 2 and 9). The data DATA stored in the memory cell (MC of FIGS. 2 and 9) connected to the selected word line among ~WL16) can be output. The second memory area 62 receives the write signal WT during a write operation and uses the first to Nth internal addresses IADD<1:N> to the first to sixteenth word lines (WL1 of FIGS. 2 and 9). Data DATA may be stored in a memory cell (MC of FIGS. 2 and 9 ) connected to a word line selected from among ~WL16 ). During the self-refresh operation, the second memory area 62 may receive the internal refresh signal IR and perform a refresh operation on the first to sixteenth word lines (WL1 to WL16 in FIGS. 2 and 9 ). During the smart refresh operation, the second memory area 62 may refresh word lines adjacent to the word lines selected by the first to Nth target addresses TADD<1:N>. The read signal RD and the write signal WT may be internally generated by a command input from an external device (eg, a controller) during a general read and write operation. The second memory area 62 is implemented to include first to sixteenth word lines (WL1 to WL16 in FIGS. 2 and 9 ), but may be implemented to include various numbers of word lines according to embodiments. Since the second memory area 62 is implemented identically to the second memory area 22 shown in FIGS. 2 and 9 and performs the same operation, a detailed description thereof will be omitted.

The first to sixteenth row hammering word lines (RWL1 to RWL16 in FIGS. 2 and 9) included in the first memory area 61 and the first to sixteenth word lines included in the second memory area 62 (FIG. 2) and WL1 to WL16 of 9), word lines of the same order may be simultaneously activated by the first to N th internal addresses (IADD<1:N>). For example, when the first row hammering word line (RWL1 in FIGS. 2 and 9) included in the first memory area 61 is activated by the first to Nth internal addresses IADD<1:N>, The first word line (WL1 in FIGS. 2 and 9 ) included in the second memory area 62 may be activated. The first to sixteenth row hammering word lines (RWL1 to RWL16 in FIGS. 2 and 9) included in the first memory area 61 and the first to sixteenth word lines included in the second memory area 62 (FIG. 2) and WL1 to WL16 of 9) are implemented with different word lines, but this is only one embodiment and may be implemented with the same word line depending on the embodiment.

Meanwhile, the active control circuit 51, the target address generation circuit 52, the internal address generation circuit 53, and the refresh control circuit 54 include a first memory area 61 and a second memory area 62. It can be located in the row area (50, ROW AREA in FIG. 2) for controlling the memory area 60, or in the low area (50, ROW AREA in FIG. 2) and the cross area (CROSS AREA in FIG. 2) together. there is. In addition, the active control circuit 51, the target address generation circuit 52, the internal address generation circuit 53, and the refresh control circuit 54 are a column area for controlling the memory area 60 (COLUMN AREA in FIG. 2). , or can be implemented to be located in a column area (COLUMN AREA in FIG. 2) and a cross area (CROSS AREA in FIG. 2).

14 is a block diagram of a target address generation circuit 52 according to one embodiment. As shown in FIG. 14, the target address generation circuit 52 may include an input circuit 521, an adder 522, an output circuit 523, a comparison circuit 524, and a smart refresh control circuit 525. there is.

The input circuit 521 transmits first to sixth read counting signals RCA<1:6> received from the first memory area 61 when the internal read signal IRD is input. A lead counting signal (TRC<1:6>) can be generated. When the internal lead signal IRD is input, the input circuit 521 buffers the first to sixth lead counting signals RCA<1:6> to transmit the first to sixth transfer lead counting signals TRC<1:6 >) can be created.

The adder 522 may up-count the first to sixth transfer lead counting signals TRC<1:6>. The adder 522 may generate first to sixth counting signals TWC<1:6> by up-counting the first to sixth transfer lead counting signals TRC<1:6>.

The output circuit 523 may generate first to sixth light counting signals WCA<1:6> from the first to sixth counting signals TWC<1:6> during internal light operation. The output circuit 523 generates first to sixth light counting signals WCA<1:6> from the first to sixth counting signals TWC<1:6> when the internal light signal IWT is input. can do. The output circuit 523 may output the first to sixth light counting signals WCA<1:6> to the first memory area 21 when the internal write signal IWT is input. The output circuit 523 may initialize all bits of the first to sixth light counting signals WCA<1:6> to a logic low level after the smart refresh operation is performed. The output circuit 523 may initialize all bits of the first to sixth light counting signals WCA<1:6> to a logic low level when the reset signal RST is input after the smart refresh operation is performed. . The output circuit 523 outputs the first to sixth light counting signals WCA<1:6> with all bits initialized to a logic low level when the internal light signal IWT is input after the smart refresh operation is performed. 1 can be output to the memory area 21.

When the internal comparison signal ICMP is input, the comparison circuit 524 includes the first to sixth counting signals TWC<1:6> and the first to sixth stored counting signals (SWC<1 in FIG. 5). :6>) can be compared to generate the flag signal UPF. When the internal comparison signal ICMP is input, the comparison circuit 524 has first to sixth counting signals TWC<1:6> stored therein (SWC<1 in FIG. 5). :6>), an enabled flag signal UPF can be generated. When the internal comparison signal ICMP is input, the comparison circuit 524 has first to sixth counting signals TWC<1:6> stored therein (SWC<1 in FIG. 5). :6>) When counting is less than or equal to, a disabled flag signal UPF may be generated. When the internal comparison signal ICMP is input, the comparison circuit 524 has first to sixth counting signals TWC<1:6> stored therein (SWC<1 in FIG. 5). :6>), the first to sixth counting signals (TWC<1:6>) may be stored as the first to sixth storage counting signals (SWC<1:6> in FIG. 5). The comparison circuit 524 may initialize all bits of the first to sixth storage counting signals (SWC<1:6> in FIG. 5) to a logic low level when the reset signal RST is input in the smart refresh operation. .

The smart refresh control circuit 525 may store the first to Nth addresses ADD<1:N> when the flag signal UPF is input. When the first smart refresh signal SR1 is input, the smart refresh control circuit 525 stores the first to Nth target addresses TAD<1:N> from the stored first to Nth addresses ADD<1:N>. ) can be created. The smart refresh control circuit 525 may output the first to Nth target addresses TAD<1:N> to the second memory area 62 when the second smart refresh signal SR2 is input. The smart refresh control circuit 525 may generate an enabled reset signal RST after the first smart refresh signal SR1 is input.

15 is a block diagram of a smart refresh control circuit 525 according to an embodiment. As shown in FIG. 15 , the smart refresh control circuit 525 may include a first address storage circuit 525_1, a reset control circuit 525_2, and a second address storage circuit 525_3.

The first address storage circuit 525_1 stores the first to Nth storage addresses SAD< from the first to Nth addresses ADD<1:N> based on the flag signal UPF and the first smart refresh signal SR1. 1:N>). The first address storage circuit 525_1 stores the first to Nth addresses ADD<1:N> when the flag signal UPF is input at a logic high level to the first to Nth storage addresses SAD<1:N. >) to save. The first address storage circuit 525_1 may output the stored first through Nth storage addresses SAD<1:N> when the first smart refresh signal SR1 is input at a logic high level.

The reset control circuit 525_2 may generate a reset signal RST based on the first smart refresh signal SR1. The reset control circuit 525_2 may generate a reset signal RST that is enabled when the first smart refresh signal SR1 is input.

The second address storage circuit 525_3 may store first through Nth storage addresses SAD<1:N>. When the second smart refresh signal SR2 is input at a logic high level, the second address storage circuit 525_3 stores the first to Nth storage addresses SAD<1:N> as first to Nth target addresses ( TAD<1:N>) can be output.

16 is a block diagram of a refresh control circuit 54 according to an embodiment. As shown in FIG. 16 , the refresh control circuit 54 may include a refresh counter 541 and a refresh signal generation circuit 542 .

The refresh counter 541 may generate first through Jth refresh counting signals RCNT<1:J> based on the refresh command REF. The refresh counter 541 may generate first through J-th refresh counting signals RCNT<1:J> that are up-counted whenever the refresh command REF is input.

The refresh signal generating circuit 542 generates a first smart refresh signal SR1, a second smart refresh signal SR2, and an internal refresh signal IR based on the first to Jth refresh counting signals RCNT<1:J>. can create The refresh signal generating circuit 142 generates a first smart refresh signal SR1 and a second smart refresh signal SR1 that are sequentially enabled when the first to Jth refresh counting signals RCNT<1:J> are counted as the fourth logic level combination. A smart refresh signal SR2 may be generated. The fourth logic level combination of the first to Jth refresh counting signals RCNT<1:J> may be set to the number of times the refresh command REF is input to perform the smart refresh operation. The refresh signal generating circuit 542 may generate an internal refresh signal IR when the first through Jth refresh counting signals RCNT<1:J> are counted as a fifth logic level combination. A fifth logic level combination of the first to Jth refresh counting signals RCNT<1:J> may be set to the number of times the refresh command REF is input to perform the self-refresh operation.

A smart refresh operation of the electronic device 3 according to an embodiment of the present invention will be described with reference to FIG. 17 .

The smart refresh operation may include an initialization operation step (S10), an active detection step (S20), a target address generation step (S30), and a smart refresh operation step (S40).

The initialization operation step (S10) may be set to a power-up period and a boot-up operation for starting the operation of the electronic device 3. In the initialization operation step S10 , the first memory area 61 receives the initialization signal INIT to initialize the first to sixth light counting signals WCA<1:6> stored therein. The first to sixth write counting signals WCA<1:6> stored therein are stored in the first to sixteenth row hammering word lines RWL1 to RWL16, respectively. :6>), and all bits of the first to sixth write counting signals WCA<1:6> may be initialized to a logic low level.

The active sensing step (S20) may include an active operation step (S210), an internal read, counting and internal write operation step (S220), and a comparison operation step (S230).

The active operation step (S210) is set to a step of receiving an active command (ACT), a refresh command (REF), and the first to Nth addresses (ADD<1:N>) from an external device (eg, a controller). can

The internal read, counting, and internal write operation step S220 may be set to generate an internal read signal IRD, an internal comparison signal ICMP, and an internal write signal IWT based on the active command ACT. In the internal read, counting, and internal write operation step (S220), the active control circuit 51 generates an internal read signal IRD, an internal comparison signal ICMP, and an internal write signal IWT based on the active command ACT. can When the internal read signal IRD is generated in the internal read, counting and internal write operation step S220, the target address generation circuit 52 receives the first to sixth read counting signals (input from the first memory area 61). RCA<1:6>) may be up-counted to generate first to sixth counting signals TWC<1:6>. In the internal read, counting, and internal write operation step S220, the active control circuit 51 may generate an internal comparison signal ICMP and an internal write signal IWT after generating the internal read signal IRD. When the internal write signal IWT is generated in the internal read, counting, and internal write operation step S220, the target address generating circuit 52 performs the first to sixth counting signals TWC<1:6> from the first to sixth counting signals TWC<1:6>. A sixth light counting signal WCA<1:6> may be generated, and the first to sixth light counting signals WCA<1:6> may be output to the first memory area 61 . In the internal read, counting, and internal write operation step S220, the first memory area 61 may store the first to sixth light counting signals WCA<1:6>.

The comparison operation step S230 may be set to an operation of comparing the first to sixth counting signals TWC<1:6> with the first to sixth storage counting signals SWC<1:6>. In the comparison operation step (S230), when the internal comparison signal ICMP is input, the target address generation circuit 52 receives the first to sixth counting signals TWC<1:6> and the first to sixth storage counting signals ( SWC<1:6>) can be compared. In the comparison operation step (S230), the target address generating circuit 52 counts the first to sixth counting signals TWC<1:6> more than the first to sixth storage counting signals SWC<1:6>. If yes, an enabled flag signal UPF may be generated. In the comparison operation step (S230), the target address generation circuit 52 has the first to sixth counting signals (TWC<1:6>) less than the first to sixth storage counting signals (SWC<1:6>) or In the case of identical counting (NO), a disabled flag signal UPF may be generated.

The target address generation step (S30) may include a counting signal update operation step (S310), a target address update operation step (S320), and a target address maintenance operation step (S330).

In the counting signal update operation step (S310), the first to sixth counting signals (TWC<1:6>) in the comparison operation step (S230) are larger than the first to sixth storage counting signals (SWC<1:6>). If counting (YES) may be performed. In the counting signal update operation step (S310), the target address generating circuit 52 stores the first to sixth counting signals TWC<1:6> according to the enabled flag signal UPF, and counts the first to sixth counting signals. It can be stored as a signal (SWC<1:6>).

In the target address update operation step (S320), the first to sixth counting signals (TWC<1:6>) in the comparison operation step (S230) are larger than the first to sixth storage counting signals (SWC<1:6>). If counting (YES) may be performed. In the target address updating operation step (S320), the target address generating circuit 12 converts the first to Nth addresses ADD<1:N> into the first to Nth target addresses ( TAD<1:N>).

In the target address maintaining operation step (S330), the first to sixth counting signals (TWC<1:6>) in the comparison operation step (S230) are smaller than the first to sixth storage counting signals (SWC<1:6>). or if they are counted equally (NO), it can be performed. In the target address maintaining operation step (S330), the target address generation circuit 52 converts the first to Nth addresses ADD<1:N> into the first to Nth target addresses ( TAD<1:N>). That is, the first to Nth target addresses (TAD<1:N>) retain the most activated word line information. When the target address maintaining step (S330) ends, the active operation step (S210) may be re-entered.

The smart refresh operation step (S4) may include a storage counting signal reset operation step (S410) and a smart refresh execution step (S420).

The storage counting signal reset operation step (S410) may be set to a step of initializing the first to sixth storage counting signals (SWC<1:6> in FIG. 6). The storage counting signal resetting operation ( S410 ) may be set as a step of initializing the row hammering cells RC included in the first memory area 61 . In the storage counting signal reset operation step S410, the refresh control circuit 54 generates the first smart refresh signal SR1 according to the refresh command REF. In the storage counting signal reset operation step (S410), the target address generating circuit 54 uses the reset signal RST generated by the first smart refresh signal SR1 to generate the first to sixth storage counting signals (SWC of FIG. 5). <1:6>) can be initialized to a logic low level. In the storage counting signal reset operation step S410, the row hammering cells RC included in the first memory area 61 may be initialized.

The smart refresh execution step (S420) may be set to a step of performing a smart refresh operation by the refresh command REF. In the smart refresh execution step (S420), the target address generating circuit 52 stores the first to Nth target addresses TAD<1:N> stored when the second smart refresh signal SR2 is input into the second memory area ( 62) can be output. In the smart refresh execution step (S420), the second memory area 62 includes word lines (N+1, N+1) adjacent to the word lines selected by the first to Nth target addresses (TAD<1:N>). ) to activate the smart refresh operation. When the smart refresh step (S420) ends, the active operation step (S210) may be re-entered.

Referring to FIG. 18, a smart refresh operation of another electronic device 3 according to an embodiment of the present invention will be described as follows.

At the time T11, an active command (ACT) is input from an external device (eg, a controller).

At time T12, the active control circuit 51 generates the internal lead signal IRD based on the active command ACT. The target address generating circuit 52 receives the internal read signal IRD and up-counts the first to sixth read counting signals RCA<1:6> input from the first memory area 61 to generate first to sixth read counting signals RCA<1:6>. A sixth counting signal (TWC<1:6>) is generated.

At time T13, the active control circuit 51 generates the internal comparison signal ICMP based on the active command ACT. The target address generation circuit 52 generates a flag signal UPF by comparing the first to sixth counting signals TWC<1:6> with the first to sixth storage counting signals SWC<1:6>. do. The target address generation circuit 52 stores the first to Nth addresses ADD<1:N> as the first to Nth storage addresses SAD<1:N> when the flag signal UPF is enabled. do. When the flag signal UPF is enabled, the target address generation circuit 52 converts the first to sixth counting signals TWC<1:6> into the first to sixth storage counting signals SWC<1:6>. Save as The first to sixth storage counting signals SWC<1:6> are generated from the first to sixth counting signals TWC<1:6> that are counted the most. The target address generating circuit 52 stores the first to Nth addresses ADD<1:N> as the first to Nth storage addresses SAD<1:N> when the flag signal UPF is disabled. I never do that. The target address generation circuit 52 converts the first to sixth counting signals TWC<1:6> into the first to sixth storage counting signals SWC<1:6> when the flag signal UPF is disabled. do not save as

At time T14, the active control circuit 51 generates the internal write signal IWT based on the active command ACT. The target address generating circuit 52 receives the internal write signal IWT and receives the first to sixth light counting signals WCA<1:6> generated from the first to sixth counting signals TWC<1:6>. ) is output to the first memory area 61. The first memory area 61 includes a row hammer ring connected to row hammer ring word lines activated by the first to N th internal addresses IADD<1:N> among the first to sixteen row hammer ring word lines RWL1 to RWL16. The first to sixth light counting signals WCA<1:6> are stored in the cell RC.

At the time T15, a refresh command (REF) is input from an external device (eg, a controller).

At time T16, the refresh control circuit 54 generates a first smart refresh signal SR1 based on the refresh command REF. The target address generation circuit 52 converts the first to Nth storage addresses SAD<1:N> to the first to Nth target addresses TAD<1:N> in response to the first smart refresh signal SR1. Save. The target address generation circuit 52 generates a reset signal RST when the first smart refresh signal SR1 is input. The refresh control circuit 54 outputs the first to Nth storage addresses SAD<1:N> and then outputs the first to sixth storage counting signals SWC<1:6> by the reset signal RST. ) to a logic low level. That is, the first to sixth storage counting signals (SWC<1:6>) are initialized (STORAGE COUNTING SIGNAL INITIAL).

The active control circuit 51 generates an internal write signal IWT based on the refresh command REF. The target address generation circuit 52 receives the internal write signal IWT and outputs the first to sixth write counting signals WCA<1:6>, in which all bits are initialized to a logic low level, to the first memory area 61. output as The first memory area 61 includes a row hammer ring connected to row hammer ring word lines activated by the first to N th internal addresses IADD<1:N> among the first to sixteen row hammer ring word lines RWL1 to RWL16. The initialized first to sixth light counting signals WCA<1:6> are stored in the cell RC. That is, the row hammering cells RC of the first memory area 61 are initialized (RC INITIAL).

At the time of T17, a refresh command (REF) is input from an external device (eg, a controller).

At time T18, the refresh control circuit 54 generates a first pulse of the second smart refresh signal SR2 based on the refresh command REF. The target address generation circuit 52 outputs the first to Nth target addresses TAD<1:N> to the second memory area 62 by the first pulse of the first smart refresh signal SR2. The second memory area 62 includes word lines (N+1) adjacent to word lines selected by the first to Nth target addresses TAD<1:N> among the first to sixteenth word lines WL1 to WL16. ) is activated to perform the smart refresh operation (SMART REFRESH). Meanwhile, the second memory area 62 is adjacent to the word line N of the word line selected by the first to Nth target addresses TAD<1:N> among the first to sixteenth word lines WL1 to WL16. +2) is activated to perform the smart refresh operation (SMART REFRESH).

At time T19, the refresh control circuit 54 generates a second pulse of the second smart refresh signal SR2 based on the refresh command REF. The target address generating circuit 52 outputs the first to Nth target addresses TAD<1:N> to the second memory area 62 by the second pulse of the second smart refresh signal SR2. The second memory area 62 is an adjacent word line (N−1) of a word line selected by the first to Nth target addresses (TAD<1:N>) among the first to sixteenth word lines (WL1 to WL16). ) is activated to perform the smart refresh operation (SMART REFRESH). Meanwhile, the second memory area 62 is adjacent to the word line N of the word line selected by the first to Nth target addresses TAD<1:N> among the first to sixteenth word lines WL1 to WL16. -2) is activated to perform the smart refresh operation (SMART REFRESH).

The electronic device 3 according to an embodiment of the present invention as described above further includes a memory area storing information on the number of inputs of logic level combinations of all addresses, and according to a result of counting all address combinations, the most active A smart refresh operation may be performed to refresh word lines adjacent to the selected word line. In addition, the electronic device 3 may prevent interference between word lines by storing a result of counting all address combinations and refreshing word lines adjacent to the most activated word line using the result.

19 is a block diagram showing a configuration according to an embodiment of an electronic system 1000 according to an embodiment of the present invention. As shown in FIG. 19 , the electronic system 1000 may include a host 1100 and a semiconductor system 1200 .

The host 1100 and the semiconductor system 1200 may mutually transmit signals using an interface protocol. Interface protocols used between the host 1100 and the semiconductor system 1200 include MMC (Multi-Media Card), ESDI (Enhanced Small Disk Interface), IDE (Integrated Drive Electronics), PCI-E (Peripheral Component Interconnect-Express) , ATA (Advanced Technology Attachment), SATA (Serial ATA), PATA (Parallel ATA), SAS (serial attached SCSI), and USB (Universal Serial Bus).

The semiconductor system 1200 may include a controller 1300 and electronic devices 1400 (K:1). The controller 1300 may control the electronic devices 1400 (K: 1) so that the electronic devices 1400 (K: 1) perform a smart refresh operation. Each of the electronic devices 1400 (K:1) further includes a memory area for storing input count information of logic level combinations of all addresses, and according to a result of counting all address combinations, the most activated word line. It is possible to perform a smart refresh operation for refreshing adjacent word lines of . Each of the electronic devices 1400 (K:1) stores the result of counting all address combinations, and uses this to refresh word lines adjacent to the most activated word line, thereby preventing interference between word lines. there is.

Each of the electronic devices 1400 (K: 1) may be implemented as an electronic device 1 shown in FIG. 1 , an electronic device 2 shown in FIG. 12 , and an electronic device 3 shown in FIG. 13 . . According to embodiments, the electronic device 1400 (K:1) may include dynamic random access memory (DRAM), phase change random access memory (PRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), and FRAM. (Ferroelectric Random Access Memory).

Example 1
1. Electronics 10. Low Area
11. Active control circuit 12. Target address generation circuit
13. Internal address generation circuit 14. Refresh control circuit
20. Memory area 21. First memory area
22. Second memory area 111. Ring oscillator
112. ROD counter 113. Internal signal generating circuit
121. Input circuit 122. Adder
123. Output circuit 124. Comparator circuit
124_1. Counting signal storage circuit 124_2. flag signal generation circuit
125. Smart refresh control circuit 125_1. address storage circuit
125_2. Reset control circuit 141. Refresh counter
142. Refresh signal generation circuit 210. First comparator
220. Second comparator 230. Third comparator
240. Logic Circuits
Second embodiment
2. Electronics 30. Column area
31. Active control circuit 32. Target address generation circuit
33. Internal address generation circuit 34. Refresh control circuit
40. Memory area 41. First memory area
42. Second memory area
Third embodiment
3. Electronics 50. Low area
51. Active control circuit 52. Target address generation circuit
53. Internal address generation circuit 54. Refresh control circuit
60. Memory area 61. First memory area
62. Second memory area 521. Input circuit
522. Adder 523. Output circuit
524. Comparison circuit 525. Smart refresh control circuit
525_1. First address storage circuit 525_2. reset control circuit
525_3. Second address storage circuit 541. Refresh counter
542. Refresh signal generation circuit

Claims (27)

During active operation, an internal read operation and an internal write operation are performed to count the number of inputs for each logic level combination of addresses to generate a counting signal, and when the counting signal counts more than the stored counting signal stored therein, the counting signal is a target address generation circuit for storing a storage counting signal and storing the address corresponding to the counting signal as a target address; and
An electronic device comprising a refresh control circuit for controlling a smart refresh operation for the target address.
The electronic device of claim 1 , wherein the target address generation circuit stores the counting signal, which is counted the most among logic level combinations of the addresses, as the storage counting signal.
The electronic device of claim 1, wherein the target address generation circuit initializes a row hammering cell storing the counting signal counted identically to the storage counting signal after the smart refresh operation is performed.
The electronic device of claim 1, wherein the smart refresh operation refreshes word lines disposed adjacent to a word line selected by the target address among a plurality of word lines included in a memory area.
The method of claim 1, wherein the target address generation circuit
an input circuit for generating a transfer lead counting signal from a lead counting signal received from the memory area when an internal lead signal is input;
an adder generating the counting signal by up-counting the transfer lead counting signal;
an output circuit generating a write counting signal from the counting signal when an internal write signal is input, and outputting the write counting signal to the memory area;
Comparing the counting signal and the storage counting signal to generate a flag signal, restoring the counting signal as the storage counting signal when the flag signal is generated, and initializing the storage counting signal when a reset signal is input comparison circuit; and
A smart refresh control circuit for storing the address when the flag signal is input, outputting the stored address as the target address when the smart refresh signal is input, and generating a reset signal by delaying the smart refresh signal electronics.
6. The method of claim 5, wherein the comparison circuit
a counting signal storage circuit that stores the counting signal as the storage counting signal when the flag signal is input and initializes the storage counting signal when the reset signal is input; and
and a flag signal generation circuit for generating the flag signal when the counting signal is up-counted from the stored counting signal.
The method of claim 5, wherein the smart refresh control circuit
an address storage circuit for storing the address when the flag signal is input and outputting the stored address as the target address when the smart refresh signal is input; and
and a reset control circuit configured to generate the reset signal by delaying the smart refresh signal after the smart refresh operation is completed.
6. The method of claim 5, wherein the memory area
a plurality of row hammering word lines and a plurality of row hammering cells connected to the plurality of row hammering word lines, and connected to a row hammering word line selected by an internal address among the plurality of row hammering word lines during the internal read operation; outputting the read counting signal stored in the row hammering cell, and storing the write counting signal in the row hammering cell connected to a row hammering word line selected by the internal address among the plurality of row hammering word lines during the internal write operation; a first memory area to; and
It includes a plurality of word lines and a plurality of memory cells connected to the plurality of word lines, refreshes word lines adjacent to a word line selected by the target address during the smart refresh operation, and refreshes the plurality of word lines during a read operation. First data stored in a memory cell connected to a word line selected by the internal address is output, and during a write operation, second data is stored in a memory cell connected to a word line selected by the internal address among the plurality of word lines. An electronic device including a second memory area for storing.
According to claim 8,
an active control circuit which receives an active command and a refresh command and generates the internal read signal for controlling the internal read operation, the internal write signal and the internal comparison signal for controlling the internal write operation; and
An electronic device further comprising an internal address generation circuit for generating an internal address from the address.
10. The method of claim 9, wherein the active control circuit, the internal address generation circuit, the target address generation circuit, and the refresh control circuit are located in a row area for controlling the memory area or are located together in the row area and a cross area. electronics.
According to claim 8,
an active control circuit which receives an active command and a refresh command and generates the internal read signal for controlling the internal read operation, the internal write signal and the internal comparison signal for controlling the internal write operation;
an internal address generation circuit for generating an internal address from the address;
It is connected to the first memory area through a row hammering input/output line, receives and outputs a read counting signal through the row hammering input/output line during the internal read operation, and receives a write counting signal during the internal write operation to generate the row hammering an input/output control circuit outputting through an input/output line; and
It is connected to the second memory area through a local I/O line, receives and outputs the first data through the local I/O line during a read operation, and receives and outputs the second data through the local I/O line during a write operation. Electronic device further comprising a column control circuit that does.
12. The method of claim 11 , wherein the active control circuit, the internal address generation circuit, the target address generation circuit, the refresh control circuit, the input/output control circuit, and the column control circuit are located in a column area for controlling the memory area, or An electronic device co-located in the column area and the cross area.
During an active operation, an internal read operation and an internal write operation are performed to count the number of inputs for each logic level combination of addresses to generate a counting signal, and when the counting signal is up-counted, the counting signal is stored as a storage counting signal. a target address generation circuit that stores the address corresponding to the counting signal as a target address, initializes the stored counting signal during a first smart refresh operation, and outputs the target address during a second smart refresh operation; and
An electronic device comprising a refresh control circuit for controlling a smart refresh operation for the target address during the second smart refresh operation.
The electronic device of claim 13, wherein the first smart refresh operation and the second smart refresh operation are sequentially performed by a refresh command.
14. The electronic device of claim 13, wherein the target address generation circuit stores the counting signal, which is counted the most among logic level combinations of the addresses, as the storage counting signal.
14. The electronic device of claim 13, wherein the second smart refresh operation refreshes word lines disposed adjacent to a word line selected by the target address among a plurality of word lines included in a memory area.
14. The method of claim 13, wherein the target address generating circuit
an input circuit for generating a transfer lead counting signal from a lead counting signal received from the memory area when an internal lead signal is input;
an adder generating the counting signal by up-counting the transfer lead counting signal;
an output circuit generating a write counting signal from the counting signal when an internal write signal is input, and outputting the write counting signal to the memory area;
Comparing the counting signal and the storage counting signal to generate a flag signal, restoring the counting signal as the storage counting signal when the flag signal is generated, and initializing the storage counting signal when a reset signal is input comparison circuit; and
When the flag signal is input, the address is stored as a storage address, when the first smart refresh signal is input, the reset signal is generated, and when the second smart refresh signal is input, the storage address is output as the target address. An electronic device including a smart refresh control circuit that does.
18. The method of claim 17, wherein the comparison circuit
a counting signal storage circuit that stores the counting signal as the storage counting signal when the flag signal is input and initializes the storage counting signal when the reset signal is input; and
and a flag signal generation circuit for generating the flag signal when the counting signal is up-counted from the stored counting signal.
18. The method of claim 17, wherein the smart refresh control circuit
a first address storage circuit for storing the address when the flag signal is input and outputting the stored address as the storage address when the first smart refresh signal is input;
a reset control circuit generating the reset signal that is enabled when the first smart refresh signal is input; and
and a second address storage circuit outputting the storage address as the target address when the second smart refresh signal is input.
18. The method of claim 17, wherein the memory area
a plurality of row hammering word lines and row hammering cells connected to the plurality of row hammering word lines, and connected to a row hammering word line selected by an internal address among the plurality of row hammering word lines during the internal read operation; a first method for outputting the read counting signal stored in a cell and storing the write counting signal in the row hammering cell connected to a row hammering word line selected by an internal address among the plurality of row hammering word lines during the internal write operation; memory area; and
It includes a plurality of word lines and a plurality of memory cells connected to the plurality of word lines, refreshes word lines adjacent to a word line selected by the target address when the second smart refresh signal is input, and during a read operation Outputs first data stored in a memory cell connected to a word line selected by the internal address among the plurality of word lines, and outputs first data stored in a memory cell connected to a word line selected by the internal address among the plurality of word lines during a write operation. An electronic device comprising a second memory area for storing second data in.
21. The method of claim 20,
an active control circuit which receives an active command and a refresh command and generates the internal read signal for controlling the internal read operation, the internal write signal and the internal comparison signal for controlling the internal write operation; and
An electronic device further comprising an internal address generation circuit for generating an internal address from the address.
22. The method of claim 21, wherein the active control circuit
a ring oscillator generating a periodic signal that toggles when one of the active command and the refresh command is input;
an ROD counter generating a vibration counting signal that is counted whenever a pulse of the periodic signal is input; and
generate an internal lead signal when the vibration counting signal counts to a first logic level combination, generate an internal light signal when the vibration counting signal counts to a second logic level combination, and generate an internal light signal when the vibration counting signal counts to a third logic level combination; An electronic device comprising an internal signal generation circuit for generating an internal comparison signal when counting up to level combinations.
14. The method of claim 13, wherein the refresh control circuit
a refresh counter generating a refresh counting signal that is counted according to the number of times a refresh command is input; and
When the refresh counting signal counts up to a fourth logic level combination, a first smart refresh for controlling the first smart refresh operation is generated, and when the refresh counting signal counts up to a fifth logic level combination, the second smart refresh is generated. An electronic device comprising a refresh signal generating circuit generating a second smart refresh for controlling a refresh operation.
an internal read and write operation step of generating a counting signal by counting the number of inputs for each logic level combination of addresses during an active operation;
a target address generation step of generating a flag signal by comparing the counting signal with the storage counting signal and generating a target address for performing a smart refresh operation from the address based on the flag signal; and
and a smart refresh performing step of performing a smart refresh operation of refreshing word lines adjacent to a word line corresponding to the target address among word lines included in a memory area when a refresh command is input.
25. The smart refresh method of claim 24, wherein the storage counting signal is initialized in the smart refresh operation.
25. The method of claim 24, wherein the step of generating the target address
a counting signal update operation step of storing the counting signal as the storage counting signal when the counting signal is counted more than the storage counting signal and the flag signal is enabled;
a target address update operation step of storing the address as the target address when the flag signal is enabled; and
and a target address maintaining operation step of maintaining the target address when the flag signal is disabled.
25. The method of claim 24, wherein the performing smart refresh
a storage counting signal reset operation step of initializing the storage counting signal during a first smart refresh operation; and
and a second smart refresh performing step of outputting the target address to the memory area and performing the smart refresh operation of refreshing word lines adjacent to a word line corresponding to the target address during a second smart refresh operation. Way.

Images