KR20230007205A - To improve the yield of wafer processes - Google Patents

To improve the yield of wafer processes Download PDF

Info

Publication number
KR20230007205A
KR20230007205A KR1020210088166A KR20210088166A KR20230007205A KR 20230007205 A KR20230007205 A KR 20230007205A KR 1020210088166 A KR1020210088166 A KR 1020210088166A KR 20210088166 A KR20210088166 A KR 20210088166A KR 20230007205 A KR20230007205 A KR 20230007205A
Authority
KR
South Korea
Prior art keywords
wafer
yield
stage
improving
particles
Prior art date
Application number
KR1020210088166A
Other languages
Korean (ko)
Inventor
최대영
Original Assignee
최대영
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 최대영 filed Critical 최대영
Priority to KR1020210088166A priority Critical patent/KR20230007205A/en
Publication of KR20230007205A publication Critical patent/KR20230007205A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/458—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
    • C23C16/4582—Rigid and flat substrates, e.g. plates or discs
    • C23C16/4583—Rigid and flat substrates, e.g. plates or discs the substrate being supported substantially horizontally
    • C23C16/4584—Rigid and flat substrates, e.g. plates or discs the substrate being supported substantially horizontally the substrate being rotated

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

The present invention relates to a method for improving the yield of a wafer process, and more specifically, to a method for improving the yield of a semiconductor process, which is configured to fundamentally reduce a decrease in the yield caused by particles which fall on a wafer when the wafer is being loaded and unloaded during a semiconductor process. The method for improving the yield of a wafer process of the present invention comprises: a step of placing a wafer on a stage in a chamber and fixing the stage with a chuck; a step of rotating the fixed stage with respect to process equipment; a step in which a process is conducted in a state in which the wafer is rotated; and a step in which the wafer is returned to its original state when the process is completed. Accordingly, the method for improving the yield of a wafer process, of the present invention, is conducted in a way that the stage rotates after the wafer enters the process equipment and is placed on the stage so that particles falling from the chamber fall on a rear surface of the wafer so that the particles do not affect the yield. Therefore, the yield is improved.

Description

웨이퍼 공정의 수율 개선 방법{To improve the yield of wafer processes}Yield improvement method of wafer process {To improve the yield of wafer processes}

본 발명은 웨이퍼 공정의 수율 개선 방법에 관한 것으로, 보다 자세하게는 웨이퍼 공정중 웨이퍼의 로딩 및 언로딩시 웨이퍼 상에 떨어지는 파티클에 의한 수율의 감소를 근본적으로 개선하기 위한 웨이퍼 공정의 수율 개선 방법에 관한 것이다.도 1은 종래의 웨이퍼 스테이지를 나타내는 개략도이다. 도 1에서와 같이, 일반적으로 반도체 소자를 제조하기 위한 대부분의 공정 장비는 웨이퍼 스테이지(40)로의 로딩, 정렬, 챔버(10) 내의 공정 및 웨이퍼 언로딩의 순으로 공정이 진행된다.상기 공정을 위해 웨이퍼(30)가 장비 내로 로딩 및 언로딩시, 또한 웨이퍼 공정 중에 챔버(10) 내에서 많은 파티클(20)이떨어지며, 상기 발생한 파티클(20) 등은 챔버(10) 내의 증착 및 패턴, 식각, 확산 과정을 통해 제거되지 않고, 웨이퍼(30)내에 그대로 존재하며, 상기 웨이퍼(30) 상의 파티클에 의해 웨이퍼의 수율에는 치명적인 영향을 주게 된다.상기 공정과정 중에서 발생하는 파티클(20)의 억제를 위해 종래에는 장비의 세정공정을 통하여 해결하였지만, 장비의 세정시 소요되는 시간에 의해, 실제 장비가 공정에 기여하는 시간은 줄어들게 되는 문제점이 있었다.The present invention relates to a method for improving the yield of a wafer process, and more particularly, to a method for improving the yield of a wafer process for fundamentally improving the yield reduction due to particles falling on the wafer during loading and unloading of the wafer during the wafer process. 1 is a schematic diagram showing a conventional wafer stage. As shown in FIG. 1 , most process equipment for manufacturing semiconductor devices generally proceeds in the order of loading to the wafer stage 40, alignment, processing in the chamber 10, and wafer unloading. When the wafer 30 is loaded and unloaded into the equipment, and during the wafer process, a large number of particles 20 fall from the chamber 10, and the generated particles 20 are deposited, patterned, and etched in the chamber 10 , is not removed through the diffusion process, and remains in the wafer 30, and has a fatal effect on the yield of the wafer due to the particles on the wafer 30. The suppression of the particles 20 generated during the process Conventionally, this has been solved through a cleaning process of equipment, but due to the time required for cleaning the equipment, the time that the actual equipment contributes to the process is reduced.

따라서, 본 발명은 상기와 같은 종래 기술의 제반 단점과 문제점을 해결하기 위한 것으로, 웨이퍼로 떨어지는 파티클을막기 위해 스테이지를 회전하여 챔버로부터 떨어지는 파티클을 방지하기 위한 웨이퍼 공정의 수율 개선 방법을 제공함에본 발명의 목적이 있다.Therefore, the present invention is to solve various disadvantages and problems of the prior art as described above, and to provide a method for improving the yield of a wafer process for preventing particles falling from a chamber by rotating a stage to prevent particles falling onto a wafer. The invention has a purpose.

따라서, 본 발명은 상기와 같은 종래 기술의 제반 단점과 문제점을 해결하기 위한 것으로, 웨이퍼로 떨어지는 파티클을막기 위해 스테이지를 회전하여 챔버로부터 떨어지는 파티클을 방지하기 위한 웨이퍼 공정의 수율 개선 방법을 제공함에본 발명의 목적이 있다.Therefore, the present invention is to solve various disadvantages and problems of the prior art as described above, and to provide a method for improving the yield of a wafer process for preventing particles falling from a chamber by rotating a stage to prevent particles falling onto a wafer. The invention has a purpose.

본 발명은 이상에서 살펴본 바와 같이 바람직한 실시예를 들어 도시하고 설명하였으나, 상기한 실시예에 한정되지 아니하며 본 발명의 정신을 벗어나지 않는 범위 내에서 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해 다양한 변경과 수정이 가능할 것이다.Although the present invention has been shown and described with preferred embodiments as described above, it is not limited to the above embodiments, and to those skilled in the art within the scope of not departing from the spirit of the present invention Various changes and modifications will be possible.

따라서, 본 발명의 웨이퍼 공정의 수율 개선 방법은 웨이퍼가 공정 장비에 들어가서 스테이지에 올려진 후 스테이지를 회전하여 챔버로부터 떨어지는 파티클이 웨이퍼의 뒷면에 떨어지므로 수율에 영향을 주지 않아 수율이 개선되는 효과가 있다.Therefore, the yield improvement method of the wafer process of the present invention has an effect of improving the yield because the wafer enters the process equipment and is placed on the stage, and then the stage is rotated so that particles falling from the chamber fall on the back side of the wafer without affecting the yield. there is.

도 1은 종래의 웨이퍼 스테이지를 나타내는 개략도이다.1 is a schematic diagram showing a conventional wafer stage.

본 발명은 웨이퍼 공정의 수율 개선 방법에 관한 것으로, 보다 자세하게는 반도체 공정중 웨이퍼의 로딩 및 언로딩시 웨이퍼 상에 떨어지는 파티클에 의한 수율의 감소를 근본적으로 개선하기 위한 웨이퍼 공정의 수율 개선 방법에 관한 것이다.도 1은 종래의 웨이퍼 스테이지를 나타내는 개략도이다. 도 1에서와 같이, 일반적으로 반도체 소자를 제조하기 위한 대부분의 공정 장비는 웨이퍼 스테이지(40)로의 로딩, 정렬, 챔버(10) 내의 공정 및 웨이퍼 언로딩의 순으로 공정이 진행된다.상기 공정을 위해 웨이퍼(30)가 장비 내로 로딩 및 언로딩시, 또한 웨이퍼 공정 중에 챔버(10) 내에서 많은 파티클(20)이떨어지며, 상기 발생한 파티클(20) 등은 챔버(10) 내의 증착 및 패턴, 식각, 확산 과정을 통해 제거되지 않고, 웨이퍼(30)내에 그대로 존재하며, 상기 웨이퍼(30) 상의 파티클에 의해 웨이퍼의 수율에는 치명적인 영향을 주게 된다.상기 공정과정 중에서 발생하는 파티클(20)의 억제를 위해 종래에는 장비의 세정공정을 통하여 해결하였지만, 장비의 세정시 소요되는 시간에 의해, 실제 장비가 공정에 기여하는 시간은 줄어들게 되는 문제점이 있었다.The present invention relates to a method for improving the yield of a wafer process, and more particularly, to a method for improving the yield of a wafer process for fundamentally improving yield reduction due to particles falling on a wafer during loading and unloading of a wafer during a semiconductor process. 1 is a schematic diagram showing a conventional wafer stage. As shown in FIG. 1 , most process equipment for manufacturing semiconductor devices generally proceeds in the order of loading to the wafer stage 40, alignment, processing in the chamber 10, and wafer unloading. When the wafer 30 is loaded and unloaded into the equipment, and during the wafer process, a large number of particles 20 fall from the chamber 10, and the generated particles 20 are deposited, patterned, and etched in the chamber 10 , is not removed through the diffusion process, and remains in the wafer 30, and has a fatal effect on the yield of the wafer due to the particles on the wafer 30. The suppression of the particles 20 generated during the process Conventionally, this has been solved through a cleaning process of equipment, but due to the time required for cleaning the equipment, the time that the actual equipment contributes to the process is reduced.

수율, 공정, 파티클Yield, Process, Particles

Claims (1)

웨이퍼 공정의 수율 개선 방법에 있어서,
웨이퍼를 챔버 내 스테이지에 올려 놓고 척으로 고정하는 단계;
상기 고정된 스테이지를 공정 장비에 대하여 회전하는 단계;
상기 웨이퍼가 회전된 상태에서 공정이 진행되는 단계; 및
상기 공정 진행이 완료되면 웨이퍼가 원상태로 되돌아오는 단계
를 포함하여 이루어짐을 특징으로 하는 웨이퍼 공정의 수율 개선 방법.In the yield improvement method of the wafer process,
Placing the wafer on a stage in the chamber and fixing it with a chuck;
rotating the fixed stage relative to process equipment;
performing a process while the wafer is rotated; and
Returning the wafer to its original state when the process is completed
Yield improvement method of the wafer process, characterized in that comprising a.
KR1020210088166A 2021-07-05 2021-07-05 To improve the yield of wafer processes KR20230007205A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020210088166A KR20230007205A (en) 2021-07-05 2021-07-05 To improve the yield of wafer processes

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020210088166A KR20230007205A (en) 2021-07-05 2021-07-05 To improve the yield of wafer processes

Publications (1)

Publication Number Publication Date
KR20230007205A true KR20230007205A (en) 2023-01-12

Family

ID=84923719

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020210088166A KR20230007205A (en) 2021-07-05 2021-07-05 To improve the yield of wafer processes

Country Status (1)

Country Link
KR (1) KR20230007205A (en)

Similar Documents

Publication Publication Date Title
KR20230007205A (en) To improve the yield of wafer processes
US20090246955A1 (en) Wafer processing method and wafer processing apparatus
KR100549270B1 (en) Method of improving yield in semiconductor process
JP2005286102A (en) Vacuum processing equipment and vacuum processing method
CN109894962B (en) Silicon wafer edge polishing process
JP2731752B2 (en) Processing method of resist film
KR101037467B1 (en) Apparatus for manufacturing semiconductor device and method using the same
US20060137711A1 (en) Single-wafer cleaning procedure
KR101934883B1 (en) semiconductor fabricating method and apparatus
JP2005051101A (en) Method of cleaning substrate
KR100599101B1 (en) Method of restraining particle in semiconductor process
JP6683277B1 (en) Method for measuring thickness of semiconductor wafer and double-sided polishing apparatus for semiconductor wafer
US11878329B2 (en) Method for cleaning silicon wafer
TW201719797A (en) Substrate housing method and substrate processing device
KR20090044551A (en) Apparatus for manufacturing semiconductor device and method using the same
TWI227752B (en) Method for decreasing number of particles during etching process and the etching process
KR20090044578A (en) Apparatus for manufacturing semiconductor device and method using the same
KR100641518B1 (en) Develop method of semiconductor patterning process
KR20090044571A (en) Apparatus for manufacturing semiconductor device and method using the same
KR101684572B1 (en) A method for recycling photomask
KR100577606B1 (en) Method for back up in semiconductor apparatus
KR20070045517A (en) Method for aging of semiconductor fabricating apparatus
KR20030042494A (en) Method for cleaning of semiconductor process chamber
KR20060067316A (en) Semiconductor photolithography method comprising in-line particle removing step for back side of wafer and semiconductor photolithography equipment comprising in-line particle removing unit for back side of wafer
JPS61177727A (en) Development method for positive type photo resist