KR20230006740A - Display apparatus - Google Patents

Abstract

The present invention is for a display apparatus to reduce the stress on a conductive layer and an insulating layer to prevent the boundary between the conductive layer and the insulating layer from opening up and causing the insulating layer to lift, comprising: a substrate; a first electrode disposed on the substrate; a semiconductor layer interposed between the substrate and the first electrode and including a semiconductor region overlapping the first electrode; an insulating layer disposed on the first electrode; and a second electrode disposed on the insulating layer, and including a first portion at least partially overlapping with the first electrode and a second portion adjacent to the first part in a first direction, wherein a first length of the first portion along a second direction intersecting the first direction is greater than a second length of the second portion along the second direction.

Description

Display apparatus {Display apparatus}

The present invention relates to a display device.

The display device is a device that visually displays data. The display device may be used as a display for a small product such as a mobile phone or the like or a display for a large product such as a television.

The display device includes a plurality of pixels that receive electrical signals and emit light in order to display an image externally. Each pixel includes a display element, for example, an organic light-emitting diode (OLED) as a display element in the case of an organic light emitting display device. In general, an organic light emitting diode display operates by forming a thin film transistor and an organic light emitting diode on a substrate, and the organic light emitting diode itself emits light.

Recently, as the uses of display devices have diversified, various attempts have been made to improve the quality of display devices.

An object of the present invention is to provide a display device for preventing a phenomenon in which a boundary between a conductive layer and an insulating layer is widened and the insulating layer is lifted by reducing stress applied to the conductive layer and the insulating layer.

The technical problems to be achieved by the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description of the present invention. .

According to one aspect of the invention, the substrate; a first electrode disposed on the substrate; a semiconductor layer interposed between the substrate and the first electrode and including a semiconductor region overlapping the first electrode; an insulating layer disposed on the first electrode; and a second electrode disposed on the insulating layer and including a first portion overlapping at least partially with the first electrode, and a second portion adjacent to the first portion in a first direction, A first length of the first portion along a second direction crossing the first direction is greater than a second length of the second portion along the second direction.

According to an example, the semiconductor layer may further include a first region and a second region that extends in the second direction and are spaced apart from each other with the semiconductor region interposed therebetween, and the first portion of the second electrode and the second region are spaced apart from each other. The first regions at least partially overlap each other, the second portion of the second electrode and the second region at least partially overlap each other, and a first overlapping area of the first portion of the second electrode and the first region. may be greater than a second overlapping area of the second portion of the second electrode and the second region.

According to one example, the first part of the second electrode has a first edge and a third edge spaced apart from each other in the second direction, and the second part of the second electrode is spaced apart from each other in the second direction has a second edge and a fourth edge, and an imaginary first line extending in the longitudinal direction of the first edge and an imaginary second line extending in the longitudinal direction of the second edge are spaced apart from each other along the second direction An imaginary third line extending in the longitudinal direction of the third edge and a virtual fourth line extending in the longitudinal direction of the fourth edge may coincide with each other.

According to an example, the separation distance between the imaginary first line and the imaginary second line may be equal to a difference between the first length and the second length.

According to one example, the first part of the second electrode has a first edge and a third edge spaced apart from each other in the second direction, and the second part of the second electrode is spaced apart from each other in the second direction has a second edge and a fourth edge, and an imaginary first line extending in the longitudinal direction of the first edge and an imaginary second line extending in the longitudinal direction of the second edge are spaced apart from each other along the second direction An imaginary third line extending in the longitudinal direction of the third edge and an imaginary fourth line extending in the longitudinal direction of the fourth edge may be spaced apart from each other along the second direction.

According to an example, the sum of the first separation distance between the imaginary first line and the imaginary second line and the second separation distance between the imaginary third line and the imaginary fourth line is equal to the first length It may be the same as the difference between the second lengths.

According to an example, the display device further includes a third electrode disposed on the same layer as the first electrode and spaced apart from the first electrode along the first direction, wherein the second electrode is the third electrode. and a third portion at least partially overlapping and spaced apart from the first portion with the second portion interposed therebetween, wherein a third length of the third portion along the second direction is the first portion of the first portion. It can be equal to 1 length.

According to an example, the display device may include a display element; a driving transistor controlling a current flowing to the display element according to a gate-source voltage and including the semiconductor region and the first electrode; a scan transistor that transmits a data voltage to the driving transistor in response to a scan signal; and a storage capacitor connected to the gate of the driving transistor and including the first electrode and the second electrode.

According to another aspect of the present invention, a substrate; a first electrode disposed on the substrate; an insulating layer disposed on the first electrode; and a second electrode disposed on the insulating layer and having first to third openings each exposing a portion of the insulating layer, the first opening overlapping the first electrode, and the second opening overlapping the first electrode. and the third opening is spaced apart from each other with the first opening therebetween.

According to an example, a longitudinal direction of the second electrode may be a first direction, and the second opening and the third opening may be spaced apart from each other along a second direction crossing the first direction.

According to an example, the second electrode has a first edge and a second edge spaced apart from each other in the first direction and the second direction in a longitudinal direction, and the first edge and the second edge along the second direction An opening, the first opening, the third opening, and the second edge are located in that order, and a first separation distance between the first edge and the second opening, a first separation distance between the second opening and the first opening The sum of two separation distances, the third separation distance between the first opening and the third opening, and the fourth separation distance between the third opening and the second edge of the second electrode along the second direction may be less than the length.

According to an example, the display device may include a semiconductor region interposed between the substrate and the first electrode and overlapping the first electrode, and a second semiconductor region extending in the second direction and spaced apart from each other with the semiconductor region interposed therebetween. The semiconductor layer may further include a first region and a second region, wherein a first overlapping area of the second electrode and the first region may be equal to a second overlapping area of the second electrode and the second region. .

According to an example, the display device further includes a third electrode disposed on the same layer as the first electrode and spaced apart from the first electrode along the first direction, and each of the second electrodes includes the insulating layer. further comprising fourth to sixth openings exposing a portion of the , the fourth opening overlapping the third electrode, and the fifth opening and the sixth opening interposing the fourth opening in the second direction. may be spaced apart from each other along

According to an example, a longitudinal direction of the second electrode may be in a first direction, and the second opening and the third opening may be spaced apart from each other along the first direction.

According to an example, the second electrode has a first edge and a second edge spaced apart from each other in a second direction crossing the first direction, and a first separation distance between the first edge and the first opening; The sum of the second separation distance between the first opening and the second edge and the first length of the first opening along the second direction is a third separation distance between the first edge and the second opening; It may be equal to the sum of a fourth separation distance between the second opening and the second edge and a second length of the second opening along the second direction.

According to an example, the second electrode has a first edge and a second edge spaced apart from each other in a second direction crossing the first direction, and a first separation distance between the first edge and the first opening; The sum of the second separation distance between the first opening and the second edge is the third separation distance between the first edge and the second opening and the fourth separation distance between the second opening and the second edge. can be greater than the sum.

According to an example, the display device further includes a third electrode disposed on the same layer as the first electrode and spaced apart from the first electrode along the first direction, and the second electrode is formed of the insulating layer. It may further include a fourth opening exposing a portion thereof and overlapping the third electrode, and the second opening or the third opening may be positioned between the first opening and the fourth opening.

According to one example, a planar shape of each of the first to third openings may be a quadrangle.

According to an example, a planar shape of each of the second opening and the third opening may be circular.

According to an example, the display device may include a display element; a driving transistor configured to control a current flowing to the display element according to a gate-source voltage and including the first electrode; a scan transistor that transmits a data voltage to the driving transistor in response to a scan signal; and a storage capacitor connected to the gate of the driving transistor and including the first electrode and the second electrode.

Other aspects, features, and advantages other than those described above will become clear from the detailed description, claims, and drawings for carrying out the invention below.

These general and specific aspects may be practiced using a system, method, computer program, or any combination of systems, methods, or computer programs.

According to one embodiment of the present invention made as described above, a display device for preventing a phenomenon in which a boundary between a conductive layer and an insulating layer is widened and the insulating layer is lifted can be implemented by reducing the stress applied to the conductive layer and the insulating layer. . Of course, the scope of the present invention is not limited by these effects.

1 is a plan view schematically illustrating a display device according to an exemplary embodiment of the present invention.
2 is an equivalent circuit diagram schematically illustrating a pixel according to an exemplary embodiment of the present invention.
3 is an equivalent circuit diagram schematically illustrating a pixel according to an exemplary embodiment of the present invention.
4 is an enlarged plan view schematically illustrating a portion of a display device according to an exemplary embodiment.
5 is an exemplary cross-sectional view of a portion of FIG. 4 taken along lines II' and II-II'.
6 is an enlarged plan view schematically illustrating a portion of a display device according to an exemplary embodiment.
7 is an enlarged plan view schematically illustrating a portion of a display device according to an exemplary embodiment.
8 is an exemplary cross-sectional view of a portion of FIG. 7 taken along line III-III'.
9 is an enlarged plan view schematically illustrating a portion of a display device according to an exemplary embodiment.
10 is an enlarged plan view schematically illustrating a portion of a display device according to an exemplary embodiment.

Since the present invention can apply various transformations and have various embodiments, specific embodiments will be illustrated in the drawings and described in detail in the detailed description. Effects and features of the present invention, and methods for achieving them will become clear with reference to the embodiments described later in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various forms.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, and when describing with reference to the drawings, the same or corresponding components are assigned the same reference numerals, and overlapping descriptions thereof will be omitted. .

In the following embodiments, terms such as first and second are used for the purpose of distinguishing one component from another component without limiting meaning.

In the following examples, expressions in the singular number include plural expressions unless the context clearly dictates otherwise.

In the following embodiments, terms such as include or have mean that features or elements described in the specification exist, and do not preclude the possibility that one or more other features or elements may be added. .

In the following embodiments, when a part such as a film, region, component, etc. is on or on another part, not only is it directly above the other part, but another film, region, component, etc. is interposed therebetween. Including cases where

In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, since the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of description, the present invention is not necessarily limited to the illustrated bar.

When an embodiment is otherwise implementable, a specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously, or may be performed in an order reverse to the order described.

In this specification, "A and/or B" represents the case of A, B, or A and B. And, "at least one of A and B" represents the case of A, B, or A and B.

In the following embodiments, when films, regions, components, etc. are connected, when films, regions, and components are directly connected, or/and other films, regions, and components are interposed between the films, regions, and components. It also includes cases where they are interposed and indirectly connected. For example, when a film, region, component, etc. is electrically connected in this specification, when a film, region, component, etc. is directly electrically connected, and/or another film, region, component, etc. is interposed therebetween. This indicates an indirect electrical connection.

The x-axis, y-axis, and z-axis are not limited to the three axes of the Cartesian coordinate system, and may be interpreted in a broad sense including them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but may refer to different directions that are not orthogonal to each other.

1 is a plan view schematically illustrating a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1 , the display device 1 includes a display area DA that implements an image and a peripheral area PA disposed around the display area DA. The display device 1 may provide an image to the outside using light emitted from the display area DA.

The substrate 100 may be made of various materials such as glass, metal or plastic. According to one embodiment, the substrate 100 may include a flexible material. Here, the flexible material may be a material that can be easily bent, bent, folded or rolled. The flexible substrate 100 may be made of ultra-thin glass, metal or plastic.

Pixels PXs having various display elements such as organic light emitting diodes (OLEDs) may be disposed in the display area DA of the substrate 100 . The pixel PX is composed of a plurality, and the plurality of pixels PX may be arranged in various forms such as a stripe arrangement, a pentile arrangement, and a mosaic arrangement to implement an image.

A planar shape of the display area DA may be a rectangle as shown in FIG. 1 . In another embodiment, the planar shape of the display area DA may be a polygonal shape such as a triangle, pentagon, or hexagon, or a circular shape, an elliptical shape, or an atypical shape.

The peripheral area PA of the substrate 100 is an area disposed around the display area DA, and may be an area in which an image is not displayed. In the peripheral area PA, various wires for transmitting electric signals to be applied to the display area DA, pads to which a printed circuit board or a driver IC chip are attached may be positioned.

2 is an equivalent circuit diagram schematically illustrating a pixel according to an exemplary embodiment of the present invention.

Referring to FIG. 2 , the pixel PX may include a pixel circuit PC connected to the scan line SL and the data line DL, and a display element DE connected to the pixel circuit PC. The display element DE may be an organic light emitting diode (OLED). A cathode of the display element DE may be a common electrode to which the second driving voltage ELVSS is applied.

The pixel circuit PC may include a first transistor T1 , a second transistor T2 , and a storage capacitor Cst.

The first transistor T1 is a driving transistor whose drain current is determined according to the gate-source voltage, and the second transistor T2 is a switching transistor turned on/off according to the gate-source voltage, substantially the gate voltage. can The first transistor T1 and the second transistor T2 may be formed as thin film transistors.

The first transistor T1 may be referred to as a driving transistor, and the second transistor T2 may be referred to as a scan transistor.

The storage capacitor Cst is connected between the driving voltage line PL and the gate of the driving transistor T1. The storage capacitor Cst may have a second electrode CE2 connected to the driving voltage line PL, and a first electrode CE1 connected to the gate of the driving transistor T1. The storage capacitor Cst may store a voltage corresponding to a difference between the voltage received from the scan transistor T2 and the first driving voltage ELVDD supplied to the driving voltage line PL.

The driving transistor T1 may control the magnitude of the current Id flowing from the driving voltage line PL to the display element DE according to the gate-source voltage. The display element DE may emit light having a predetermined luminance by the driving current Id. The driving transistor T1 may have a gate connected to the first electrode CE1 of the storage capacitor Cst, a source connected to the driving voltage line PL, and a drain connected to the display element DE.

The scan transistor T2 may transmit the data voltage Dm to the gate of the driving transistor T1 in response to the scan signal Sn. The scan transistor T2 may have a gate connected to the scan line SL, a source connected to the data line DL, and a drain connected to the gate of the driving transistor T1.

In FIG. 2, the case where the pixel circuit PC includes two transistors and one storage capacitor has been described, but the present invention is not limited thereto. For example, the pixel circuit PC may include three or more transistors and/or two or more storage capacitors. As an example, the pixel circuit PC may include 7 transistors and 1 storage capacitor as shown in FIG. 3 to be described later.

3 is an equivalent circuit diagram schematically illustrating a pixel according to an exemplary embodiment of the present invention.

Referring to FIG. 3 , one pixel PX may include a pixel circuit PC and a display element DE electrically connected to the pixel circuit PC. The display element DE may be an organic light emitting diode (OLED).

For example, as shown in FIG. 3 , the pixel circuit PC includes first to seventh transistors T1 to T7 and a storage capacitor Cst. The first to seventh transistors T1 to T7 and the storage capacitor Cst transmit the first to third scan signals Sn, Sn−1, and Sn+1, respectively, to the first to third scan lines SL, SL-1, SL+1), data line DL for transmitting data voltage Dm, emission control line EL for transmitting emission control signal En, driving for transmitting first driving voltage ELVDD The voltage line PL, the initialization voltage line VL delivering the initialization voltage Vint, and the common electrode to which the second driving voltage ELVSS are applied are connected.

The first transistor T1 is a driving transistor whose drain current is determined according to the gate-source voltage, and the second to seventh transistors T2 to T7 are turned on/off according to the gate-source voltage, substantially the gate voltage. It may be a switching transistor that is turned off. The first to seventh transistors T1 to T7 may be formed as thin film transistors.

The first transistor T1 is referred to as a driving transistor, the second transistor T2 is referred to as a scan transistor, the third transistor T3 is referred to as a compensation transistor, and the fourth transistor T4 is referred to as a gate initialization transistor. , the fifth transistor T5 may be referred to as a first light emission control transistor, the sixth transistor T6 may be referred to as a second light emission control transistor, and the seventh transistor T7 may be referred to as an anode initialization transistor. .

The storage capacitor Cst is connected between the driving voltage line PL and the gate of the driving transistor T1. The storage capacitor Cst may have a second electrode CE2 connected to the driving voltage line PL, and a first electrode CE1 connected to the gate of the driving transistor T1.

The driving transistor T1 may control the magnitude of the driving current Id flowing from the driving voltage line PL to the display element DE according to the gate-source voltage. The driving transistor T1 includes a gate connected to the first electrode CE1 of the storage capacitor Cst, a source connected to the driving voltage line PL through the first light emission control transistor T5, and a second light emission control transistor T6. ) may have a drain connected to the display element DE.

The driving transistor T1 may output the driving current Id to the display element DE according to the gate-source voltage. The size of the driving current Id is determined based on the difference between the gate-source voltage and the threshold voltage of the driving transistor T1. The display element DE may receive the driving current Id from the driving transistor T1 and may emit light with brightness according to the magnitude of the driving current Id.

The scan transistor T2 transfers the data voltage Dm to the source of the driving transistor T1 in response to the first scan signal Sn. The scan transistor T2 may have a gate connected to the first scan line SL, a source connected to the data line DL, and a drain connected to the source of the driving transistor T1.

The compensation transistor T3 is connected in series between the drain and gate of the driving transistor T1 and connects the drain and gate of the driving transistor T1 to each other in response to the first scan signal Sn. The compensation transistor T3 may have a gate connected to the first scan line SL, a source connected to the drain of the driving transistor T1, and a drain connected to the gate of the driving transistor T1. In FIG. 3 , the compensating transistor T3 is illustrated as being composed of one transistor, but as another embodiment, the compensating transistor T3 may include two transistors connected in series with each other.

The gate initialization transistor T4 applies the initialization voltage Vint to the gate of the driving transistor T1 in response to the second scan signal Sn−1. The gate initialization transistor T4 may have a gate connected to the second scan line SL- 1 , a source connected to the gate of the driving transistor T1 , and a drain connected to the initialization voltage line VL. In FIG. 3 , the gate initialization transistor T4 is illustrated as being composed of one transistor, but as another embodiment, the gate initialization transistor T4 may include two transistors connected in series with each other.

The anode initialization transistor T7 applies the initialization voltage Vint to the anode of the display element DE in response to the third scan signal Sn+1. The anode initialization transistor T7 may have a gate connected to the third scan line SL+1, a source connected to the anode of the display element DE, and a drain connected to the initialization voltage line VL.

The first light emission control transistor T5 may connect the driving voltage line PL and the source of the driving transistor T1 to each other in response to the light emission control signal En. The first emission control transistor T5 may have a gate connected to the emission control line EL, a source connected to the driving voltage line PL, and a drain connected to the source of the driving transistor T1.

The second light emission control transistor T6 may connect the drain of the driving transistor T1 and the anode of the display element DE in response to the light emission control signal En. The second emission control transistor T6 may have a gate connected to the emission control line EL, a source connected to the drain of the driving transistor T1, and a drain connected to the anode of the display element DE.

The second scan signal Sn−1 may be substantially synchronized with the first scan signal Sn of the previous row. The third scan signal Sn+1 may be substantially synchronized with the first scan signal Sn. According to another example, the third scan signal Sn+1 may be substantially synchronized with the first scan signal Sn of the next row.

In this embodiment, the first to seventh transistors T1 to T7 may include a semiconductor layer including silicon. For example, the first to seventh transistors T1 to T7 may include a semiconductor layer including low temperature poly-silicon (LTPS). Polysilicon materials have high electron mobility (more than 100 cm 2 /Vs), low energy consumption and excellent reliability.

As another example, the semiconductor layers of the first to seventh transistors T1 to T7 may include indium (In), gallium (Ga), stanium (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), and cadmium. (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and oxides of at least one material selected from the group containing zinc (Zn). can include For example, the semiconductor layer may be an ITZO (InSnZnO) semiconductor layer, an IGZO (InGaZnO) semiconductor layer, or the like.

As another example, some semiconductor layers of the first to seventh transistors T1 to T7 may be formed of low-temperature polysilicon (LTPS), and some other semiconductor layers may be formed of an oxide semiconductor (IGZO, etc.).

Hereinafter, a specific operation process of one pixel PX of the display device according to an exemplary embodiment will be described in detail. As shown in FIG. 3 , it is assumed that the first to seventh transistors T1 to T7 are p-type MOSFETs.

First, when a high-level light emission control signal En is received, the first light emission control transistor T5 and the second light emission control transistor T6 are turned off, and the driving transistor T1 outputs the driving current Id. stops, and the display element DE stops emitting light.

Thereafter, during the gate initialization period in which the low-level second scan signal Sn−1 is received, the gate initialization transistor T4 is turned on, and the initialization voltage Vint is applied to the gate of the driving transistor T1, that is, the storage applied to the first electrode CE1 of the capacitor Cst. The difference (ELVDD - Vint) between the first driving voltage ELVDD and the initialization voltage Vint is stored in the storage capacitor Cst.

Thereafter, during a data writing period in which the low-level first scan signal Sn is received, the scan transistor T2 and the compensation transistor T3 are turned on, and the data voltage Dm is applied to the source of the driving transistor T1. Received. The driving transistor T1 is diode-connected and forward biased by the compensation transistor T3. The gate voltage of the driving transistor T1 rises from the initialization voltage Vint. When the gate voltage of the driving transistor T1 becomes equal to the data compensation voltage (Dm - |Vth|) reduced by the threshold voltage (Vth) of the driving transistor T1 from the data voltage Dm, the driving transistor T1 As this is turned off, the increase of the gate voltage of the driving transistor T1 stops. Accordingly, the difference (ELVDD - Dm + |Vth|) between the first driving voltage ELVDD and the data compensation voltage Dm - |Vth| is stored in the storage capacitor Cst.

Also, during the anode initialization period in which the low-level third scan signal Sn+1 is received, the anode initialization transistor T7 is turned on, and the initialization voltage Vint is applied to the anode of the display element DE. By applying the initialization voltage Vint to the anode of the display element DE to make the display element DE completely non-emit, the pixel PX receives the data voltage Dm corresponding to the black gradation in the next frame, but displays A phenomenon in which the element DE emits minute light may be removed.

The first scan signal Sn and the third scan signal Sn+1 may be substantially synchronized, and in this case, the data write period and the anode initialization period may be the same period.

Then, when the low-level light emission control signal En is received, the first light emission control transistor T5 and the second light emission control transistor T6 are turned on, and the driving transistor T1 is stored in the storage capacitor Cst. corresponding to the voltage (ELVDD - Dm) obtained by subtracting the threshold voltage (|Vth|) of the driving transistor T1 from the source-gate voltage (ELVDD - Dm + |Vth|) of the driving transistor T1. The driving current Id is output, and the display element DE can emit light with a luminance corresponding to the magnitude of the driving current Id.

4 is an enlarged plan view schematically illustrating a portion of a display device according to an exemplary embodiment. Specifically, FIG. 4 illustrates a first pixel area PXA1 and a second pixel area PXA2 in which pixels adjacent to each other in a first direction (eg, ±x direction) are disposed among a plurality of pixels. FIG. 4 illustratively illustrates some members of pixels respectively disposed in the first pixel area PXA1 and the second pixel area PXA2 .

Referring to FIG. 4 , the display device 1 (refer to FIG. 1 ) may include a first pixel area PXA1 and a second pixel area PXA2 adjacent to each other in a first direction (eg, ±x direction). can

A first semiconductor layer Act1 and a first electrode E1 are sequentially disposed in the first pixel area PXA1, and a second semiconductor layer Act2 and a third electrode E3 are sequentially disposed in the second pixel area PXA2. These can be arranged sequentially. A second electrode E2 may be disposed on the first electrode E1 and the third electrode E3.

The first semiconductor layer Act1 and the second semiconductor layer Act2 may include amorphous silicon, polysilicon, or oxide. The first semiconductor layer Act1 and the second semiconductor layer Act2 may be composed of a single layer or multiple layers.

The first semiconductor layer Act1 may include a semiconductor region SA, a first conductive region CA1 , a second conductive region CA2 , a first region AR1 , and a second region AR2 . The semiconductor region SA may overlap the first electrode E1. The first conductive region CA1 and the second conductive region CA2 may be disposed on both sides of the semiconductor region SA and may be doped regions by adding dopants. The first region AR1 and the second region AR2 may be spaced apart from each other with the semiconductor region SA interposed therebetween, and each may extend in a second direction (eg, ±y direction). The first region AR1 and the second region AR2 may be doped regions by adding impurities. Although the first semiconductor layer Act1 has been described as a standard, the second semiconductor layer Act2 may also be applied in the same manner.

The first electrode E1 may be disposed on the first semiconductor layer Act1, and the third electrode E3 may be disposed on the second semiconductor layer Act2. The first electrode E1 and the third electrode E3 may be disposed on the same layer. The first electrode E1 and the third electrode E3 include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and the like, and may be formed of a single layer or multiple layers. For example, the first electrode E1 and the third electrode E3 may be a single layer of Mo.

Meanwhile, a transistor may be implemented through the first semiconductor layer Act1 and the first electrode E1. For example, the driving transistor T1 of FIG. 2 and/or driving of FIG. 3 is performed through the semiconductor area SA, the first conductive area CA1 , the second conductive area CA2 , and the first electrode E1. Transistor T1 can be implemented. In other words, the driving transistor T1 may include a semiconductor area SA, a first conductive area CA1 , a second conductive area CA2 , and a first electrode E1 . The first conductive region CA1 corresponds to the source or drain of the driving transistor T1, the second conductive region CA2 corresponds to the source or drain of the driving transistor T1, and the first electrode E1 is driven. It may correspond to the gate of the transistor T1. Although the description has been made based on the first semiconductor layer Act1 and the first electrode E1, the second semiconductor layer Act2 and the third electrode E3 may also be applied in the same manner.

Referring back to FIG. 4 , the second electrode E2 may be disposed on the first electrode E1 and the third electrode E3. The second electrode E2 may extend substantially along the first direction (eg, the ±x direction) and at least partially overlap the first pixel area PXA1 and the second pixel area PXA2 . The second electrode E2 includes molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed of a single layer or multiple layers. For example, the second electrode E2 may be a single layer of Mo.

The second electrode E2 includes a first portion E2a that at least partially overlaps the first electrode E1, a third portion E2c that at least partially overlaps the third electrode E3, and a first portion E2a. and a second portion E2b positioned between the third portion E2c. The second portion E2b may be adjacent to the first portion E2a and the third portion E2c in a first direction (eg, ±x direction).

In an embodiment, the first length ℓ1 of the first portion E2a along the second direction (eg, ±y direction) is a second length ℓ1 along the second direction (eg, ±y direction). It may be greater than the second length ℓ2 of the portion E2b. The third length ℓ3 of the third portion E2c along the second direction (eg, ±y direction) is the first length ℓ3 of the first portion E2a along the second direction (eg, ±y direction). 1 may be substantially equal to the length ℓ1.

In one embodiment, the first portion E2a has a first edge ed1 and a third edge ed3 spaced apart from each other in a second direction (eg, ±y direction), and the second portion E2b ) may have a second edge ed2 and a fourth edge ed4 spaced apart from each other in a second direction (eg, ±y direction). The imaginary first line vℓ1 extending in the longitudinal direction of the first edge ed1 and the imaginary second line vℓ2 extending in the longitudinal direction of the second edge ed2 may be spaced apart from each other. The imaginary third line vℓ3 extending in the longitudinal direction of the third edge ed3 and the imaginary fourth line vℓ4 extending in the longitudinal direction of the fourth edge ed4 may coincide with each other. The separation distance d between the imaginary first line vℓ1 and the imaginary second line vℓ2 is the first length ℓ1 of the first part E2a and the second length of the second part E2b ( It may be substantially equal to the difference of ℓ2). Although the first part E2a and the second part E2b have been described, the third part E2c may be equally applied.

In an embodiment, the first region AR1 of the first semiconductor layer Act1 at least partially overlaps the first portion E2a of the second electrode E2, and the second region AR1 of the first semiconductor layer Act1 overlaps with the first portion E2a of the second electrode E2. Area AR2 may at least partially overlap the second portion E2b of the second electrode E2. A first overlapping area OAR1 of the first region AR1 and the first portion E2a may be greater than a second overlapping area OAR2 of the second region AR2 and the second portion E2b. Although the first semiconductor layer Act1 has been described as a standard, the second semiconductor layer Act2 may also be applied in the same manner.

As a comparative example, the first length ℓ1 of the first portion E2a and the second length ℓ2 of the second portion E2b may be the same. An interlayer insulating layer 117 shown in FIG. 5 to be described later may be disposed on the second electrode E2. When the second length ℓ2 of the second portion E2b is equal to the first length ℓ1 of the first portion E2a, the area of the second electrode E2 contacting the interlayer insulating layer 117 increases. Accordingly, a boundary between the interlayer insulating layer 117 and the second electrode E2 may widen during the subsequent heat treatment process. As the boundary between the interlayer insulating layer 117 and the second electrode E2 widens, the upper surface of the interlayer insulating layer 117 is curved, and the conductive layer disposed on the interlayer insulating layer 117 is bent by the bending. The thickness and/or width may be reduced or broken.

However, when the second length ℓ2 of the second portion E2b is smaller than the first length ℓ1 of the first portion E2a, as in one embodiment of the present invention, contact with the interlayer insulating layer 117 An area of the second electrode E2 may be reduced. When the area of the second electrode E2 contacting the interlayer insulating layer 117 is reduced, stress applied to the interlayer insulating layer 117 and the second electrode E2 may be reduced during a subsequent heat treatment process. Since the stress applied to the interlayer insulating layer 117 and the second electrode E2 is reduced, the boundary between the interlayer insulating layer 117 and the second electrode E2 can be prevented from widening and the interlayer insulating layer 117 It is possible to prevent defects of the conductive layer (for example, the connection electrode CM, see FIG. 5 ) disposed on the .

In one embodiment, the first portion E2a of the second electrode E2 has a first opening OP1 overlapping the first electrode E1, and the third portion E2c of the second electrode E2. ) may have a second opening OP2 overlapping the third electrode E3. The first opening OP1 and the second opening OP2 may expose portions of the insulating layer interposed between the first and third electrodes E1 and E3 and the second electrode E2. The first opening OP1 and the second opening OP2 may serve as a passage through which the gate of the driving transistor T1 is connected to another transistor or a conductive layer.

Although FIG. 4 illustrates that each of the first and second openings OP1 and OP2 have a rectangular planar shape, in another embodiment, each of the first and second openings OP1 and OP2 have a planar shape. It may be a polygonal shape such as a triangle, pentagon, or hexagon, or a circular shape, an elliptical shape, or an atypical shape.

Meanwhile, a capacitor may be implemented through the first electrode E1 and the second electrode E2. For example, the storage capacitor Cst of FIG. 2 and/or the storage capacitor Cst of FIG. 3 may be implemented through the first portion E2a of the first electrode E1 and the second electrode E2. In other words, the storage capacitor Cst may include the first part E2a of the first electrode E1 and the second electrode E2. The first electrode E1 may correspond to the first electrode CE1 of FIG. 2 and/or the first electrode CE1 of FIG. 3 connected to the gate of the driving transistor T1. The second electrode E2 may correspond to the second electrode CE2 of FIG. 2 and/or the second electrode CE2 of FIG. 3 connected to the driving voltage line PL (see FIGS. 2 and 3 ). Although the first electrode E1 and the second electrode E2 have been described as standards, the third electrode E3 may also be applied in the same manner.

5 is an exemplary cross-sectional view of a portion of FIG. 4 taken along lines II' and II-II'. FIG. 5 additionally shows display elements DE and connection electrodes CM omitted in FIG. 4 .

Hereinafter, components included in the display device will be described in more detail according to the laminated structure with reference to FIG. 5 . The description will be made based on the first portion E2a of the first semiconductor layer Act1, the first electrode E1, and the second electrode E2 disposed in the first pixel area PXA1 (see FIG. 4). The same may be applied to the second semiconductor layer Act2, the third electrode E3, the second portion E2b of the second electrode E2, and the third portion E2c of the second electrode E2.

The substrate 100 may include glass or polymer resin. Polymer resins include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, It may include polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate 100 including the polymer resin may have flexible, rollable or bendable characteristics. The substrate 100 may have a multi-layered structure including a layer containing the aforementioned polymer resin and an inorganic layer (not shown).

The buffer layer 111 may reduce or block penetration of foreign matter, moisture, or air from the lower portion of the substrate 100 and may provide a flat surface on the substrate 100 . The buffer layer 111 may include an inorganic material such as oxide or nitride, an organic material, or an organic/inorganic composite, and may have a single-layer or multi-layer structure of inorganic and organic materials.

A barrier layer (not shown) may be further included between the substrate 100 and the buffer layer 111 . The barrier layer may play a role of preventing or minimizing penetration of impurities from the substrate 100 or the like into the first semiconductor layer Act1. The barrier layer may include an inorganic material such as an oxide or nitride, an organic material, or an organic/inorganic composite, and may have a single layer or multilayer structure of inorganic and organic materials.

A first semiconductor layer Act1 may be disposed on the buffer layer 111 . The first semiconductor layer Act1 may include amorphous silicon or polysilicon. In another embodiment, the first semiconductor layer Act1 may include indium (In), gallium (Ga), stanium (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), or germanium. It may include oxides of at least one material selected from the group consisting of (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). .

The first semiconductor layer Act1 may include a semiconductor area SA, and first and second conductive areas CA1 and CA2 disposed on both sides of the semiconductor area SA. The first conductive region CA1 and the second conductive region CA2 may be doped regions by adding impurities. The first semiconductor layer Act1 may be composed of a single layer or multiple layers.

A first gate insulating layer 113 and a second gate insulating layer 115 may be stacked and disposed on the substrate 100 to cover the first semiconductor layer Act1 . The first gate insulating layer 113 and the second gate insulating layer 115 may be formed of silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), or titanium oxide. (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), hafnium oxide (HfO ₂ ), or zinc oxide (ZnO ₂ ).

A first electrode E1 may be disposed on the first gate insulating layer 113 . The first electrode E1 may be disposed to at least partially overlap the first semiconductor layer Act1. A partial region of the first semiconductor layer Act1 overlapping the first electrode E1 may be referred to as a semiconductor region SA. The first electrode E1 includes molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed of a single layer or multiple layers. For example, the first electrode E1 may be a single layer of Mo.

In an exemplary embodiment, the driving transistor T1 may include a semiconductor area SA, a first conductive area CA1 , a second conductive area CA2 , and a first electrode E1 .

A first portion E2a of the second electrode E2 may be disposed on the second gate insulating layer 115 . The first portion E2a of the second electrode E2 may have a first opening OP1 exposing a portion of the second gate insulating layer 115 . The first portion E2a of the second electrode E2 includes molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed of a single layer or multiple layers. For example, the first portion E2a of the second electrode E2 may be a single layer of Mo.

In one embodiment, the storage capacitor Cst is provided as a first part E2a of the first electrode E1 and the second electrode E2, and overlaps with the driving transistor T1 as shown in FIG. 5 . It can be. For example, the gate of the driving transistor T1 may function as an electrode of the storage capacitor Cst. Alternatively, the storage capacitor Cst does not overlap with the driving transistor T1 and may exist separately.

The first portion E2a of the second electrode E2 overlaps the first electrode E1 with the second gate insulating layer 115 therebetween, and forms capacitance. In this case, the second gate insulating layer 115 may function as a dielectric layer of the storage capacitor Cst.

An interlayer insulating layer 117 may be provided on the second gate insulating layer 115 to cover the first portion E2a of the second electrode E2. The interlayer insulating layer 117 is made of silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), hafnium oxide (HfO ₂ ), or zinc oxide (ZnO ₂ ).

A connection electrode CM may be disposed on the interlayer insulating layer 117 . The connection electrode CM may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and the like, and may be formed as a multilayer or single layer including the above material. there is. For example, the connection electrode CM may have a multilayer structure of Ti/Al/Ti.

The connection electrode CM is connected to the first electrode E1 through the first contact hole CNT1 formed in the second gate insulating layer 115 and the second contact hole CNT2 formed in the interlayer insulating layer 117. It can be. Although not shown in FIG. 5 , the connection electrode CM may be connected to a semiconductor layer or another electrode. The first electrode E1 may be connected to a semiconductor layer or another electrode through the connection electrode CM. The first opening OP1 of the first portion E2a of the second electrode E2 may serve as a passage through which the first electrode E1 is connected to a semiconductor layer or another electrode.

Although one connection electrode CM is shown in FIG. 5 , a plurality of connection electrodes CM may be provided. Each of the plurality of connection electrodes CM may be connected to a semiconductor layer or an electrode layer through a contact hole formed in the first gate insulating layer 113, the second gate insulating layer 115, or the interlayer insulating layer 117. .

The connection electrode CM may be covered with an inorganic protective layer (not shown). The inorganic protective layer may be a single layer or a multi-layered layer of silicon nitride (SiN _x ) and silicon oxide (SiO _x ). The inorganic protective layer may be introduced to cover and protect some wires disposed on the interlayer insulating layer 117 .

A planarization layer 119 may be disposed to cover the connection electrode CM. The planarization layer 119 may be formed of a single layer or multiple layers of a film made of an organic material, and provides a flat upper surface. The planarization layer 119 is a general-purpose polymer such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), polymethylmethacrylate (PMMA), or polystyrene (PS), a polymer derivative having a phenolic group, and an acrylic polymer. , imide-based polymers, aryl ether-based polymers, amide-based polymers, fluorine-based polymers, p-xylene-based polymers, vinyl alcohol-based polymers, and blends thereof.

A display element DE may be disposed on the planarization layer 119 . The display element DE may be an organic light emitting diode (OLED). The display element DE may include a pixel electrode 210 , an intermediate layer 220 including an organic emission layer, and a counter electrode 230 .

Although not shown in FIG. 5 , the display element DE may be connected to the transistor through a contact hole formed in the planarization layer 119 . As a result, the display element DE may be electrically connected to the pixel circuit (PC, see FIGS. 2 and 3 ) including the transistor.

The pixel electrode 210 may be a (semi-)transmissive electrode or a reflective electrode. In some embodiments, the pixel electrode 210 includes a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and compounds thereof, and a transparent or translucent electrode layer formed on the reflective layer. can do. The transparent or translucent electrode layer is indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In ₂ O ₃ ; indium oxide), indium gallium It may include at least one selected from the group consisting of indium gallium oxide (IGO) and aluminum zinc oxide (AZO). In some embodiments, the pixel electrode 210 may be made of ITO/Ag/ITO.

In the display area of the substrate 100 , a pixel defining layer 121 may be disposed on the planarization layer 119 . The pixel defining layer 121 may cover an edge of the pixel electrode 210 and may have an opening exposing a central portion of the pixel electrode 210 . A light emitting area of the display element DE may be defined by the opening.

The pixel-defining layer 121 increases the distance between the edge of the pixel electrode 210 and the counter electrode 230 above the pixel electrode 210, thereby preventing an arc from occurring at the edge of the pixel electrode 210. can play a role

The pixel defining layer 121 is formed of one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin, and may be formed by a method such as spin coating.

The intermediate layer 220 is disposed within the opening formed by the pixel defining layer 121 and may include an organic emission layer. The organic emission layer may include an organic material including a fluorescent or phosphorescent material that emits red, green, blue, or white light. The organic light emitting layer may be a low molecular weight organic material or a high molecular weight organic material, and below and above the organic light emitting layer, a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), Alternatively, a functional layer such as an electron injection layer (EIL) may be selectively further disposed.

The counter electrode 230 may be a light-transmitting electrode or a reflective electrode. In some embodiments, the counter electrode 230 may be a transparent or translucent electrode, and may be formed of a metal thin film having a low work function including Li, Ca, LiF/Ca, LiF/Al, Al, Ag, Mg, and compounds thereof. can be formed In addition, a transparent conductive oxide (TCO) layer such as ITO, IZO, ZnO, or In ₂ O ₃ may be further disposed on the metal thin film. The counter electrode 230 may be disposed over the display area and may be disposed over the intermediate layer 220 and the pixel defining layer 121 . The counter electrode 230 may be integrally formed in the plurality of display elements DE to correspond to the plurality of pixel electrodes 210 .

Since these display elements DE can be easily damaged by moisture or oxygen from the outside, an encapsulation layer (not shown) may cover these display elements DE to protect them. The encapsulation layer covers the display area and may extend to at least a portion of the peripheral area. The encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer.

6 is an enlarged plan view schematically illustrating a portion of a display device according to an exemplary embodiment. FIG. 6 is a modified embodiment of FIG. 4 and has a difference in the structure of the second electrode E2. Hereinafter, overlapping contents will be replaced with the description of FIG. 4 and the differences will be mainly described.

Referring to FIG. 6 , the first portion E2a of the second electrode E2 has a first edge ed1 and a third edge ed3 spaced apart from each other in a second direction (eg, ±y direction). In addition, the second portion E2b of the second electrode E2 may have a second edge ed2 and a fourth edge ed4 spaced apart from each other in a second direction (eg, ±y direction). The imaginary first line vℓ1 extending in the longitudinal direction of the first edge ed1 and the imaginary second line vℓ2 extending in the longitudinal direction of the second edge ed2 may be spaced apart from each other. The imaginary third line vℓ3 extending in the longitudinal direction of the third edge ed3 and the imaginary fourth line vℓ4 extending in the longitudinal direction of the fourth edge ed4 may be spaced apart from each other.

A first separation distance d1 between the first imaginary line vℓ1 and the second imaginary line vℓ2 and a second separation distance between the third imaginary line vℓ3 and the imaginary fourth line vℓ4 The sum of (d2) may be substantially equal to the difference between the first length ℓ1 of the first portion E2a and the second length ℓ2 of the second portion E2b. In other words, the first separation distance d1 between the imaginary first line vℓ1 and the imaginary second line vℓ2, the third imaginary line vℓ3 and the imaginary fourth line vℓ4 The sum of the two separation distances d2 and the second length ℓ2 of the second portion E2b may be substantially equal to the first length ℓ1 of the first portion E2a.

Although the first part E2a and the second part E2b have been described, the third part E2c may be equally applied. For example, a first separation distance d1 between the imaginary first line vℓ1 and the imaginary second line vℓ2 and the imaginary third line vℓ3 and the imaginary fourth line vℓ4 The sum of the second separation distances d2 may be substantially equal to the difference between the third length ℓ3 of the third portion E2c and the second length ℓ2 of the second portion E2b. In other words, the first separation distance d1 between the imaginary first line vℓ1 and the imaginary second line vℓ2, the third imaginary line vℓ3 and the imaginary fourth line vℓ4 The sum of the two separation distances d2 and the second length ℓ2 of the second portion E2b may be substantially equal to the third length ℓ3 of the third portion E2c.

When the second length ℓ2 of the second portion E2b is smaller than the first length ℓ1 of the first portion E2a, as in one embodiment of the present invention, the interlayer insulating layer 117 (see FIG. 5) and An area of the contacting second electrode E2 may be reduced. When the area of the second electrode E2 contacting the interlayer insulating layer 117 is reduced, stress applied to the interlayer insulating layer 117 and the second electrode E2 may be reduced during a subsequent heat treatment process. Since the stress applied to the interlayer insulating layer 117 and the second electrode E2 is reduced, the boundary between the interlayer insulating layer 117 and the second electrode E2 can be prevented from widening and the interlayer insulating layer 117 It is possible to prevent defects of the conductive layer (for example, the connection electrode CM, see FIG. 5 ) disposed on the .

FIG. 7 is an enlarged plan view schematically illustrating a portion of a display device according to an exemplary embodiment, and FIG. 8 is an exemplary cross-sectional view of a portion of FIG. 7 taken along line III-III′. In FIGS. 7 and 8, the same reference numerals as those in FIGS. 4 and 5 denote the same members, and duplicate descriptions thereof are omitted.

First, referring to FIG. 7 , the display device 1 (refer to FIG. 1 ) includes a first pixel area PXA1 and a second pixel area PXA2 adjacent to each other in a first direction (eg, ±x direction). can include A first semiconductor layer Act1 and a first electrode E1 are sequentially disposed in the first pixel area PXA1, and a second semiconductor layer Act2 and a third electrode E3 are sequentially disposed in the second pixel area PXA2. These can be arranged sequentially. A second electrode E2' may be disposed on the first electrode E1 and the third electrode E3.

The second electrode E2 ′ extends in a first direction (eg, a ±x direction) and may overlap at least a portion of the first pixel area PXA1 and the second pixel area PXA2 . The second electrode E2' includes molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed of a single layer or multiple layers. For example, the second electrode E2' may be a single layer of Mo.

In one embodiment, as shown in FIGS. 7 and 8 , the second electrode E2' includes a first opening OP1 exposing a part of the second gate insulating layer 115, which is an insulating layer, and a third opening. (OP3), and a fourth opening (OP4). The first opening OP1 may overlap the first electrode E1 and serve as a passage through which the first electrode E1 is connected to the connection electrode CM or the like. The third opening OP3 and the fourth opening OP4 may be spaced apart from each other along the second direction (eg, ±y direction) with the first opening OP1 interposed therebetween.

Although the first pixel area PXA1 has been described as a reference, the same may be applied to the second pixel area PXA2. For example, the second electrode E2 ′ may have a second opening OP2 , a fifth opening OP5 , and a sixth opening OP6 exposing portions of the second gate insulating layer 115 . . The second opening OP2 may overlap the third electrode E3 and serve as a passage through which the third electrode E3 is connected to the connection electrode CM or the like. The fifth opening OP5 and the sixth opening OP6 may be spaced apart from each other along the second direction (eg, ±y direction) with the second opening OP2 interposed therebetween.

In one embodiment, the second electrode E2' may have a first edge ed1' and a second edge ed2' spaced apart from each other in a second direction (eg, ±y direction). The first edge ed1', the third opening OP3, the first opening OP1, the fourth opening OP4, and the second edge ed2' are in the second direction (eg, ±y direction) It can be located in order according to . A first separation distance d1' between the first edge ed1' and the third opening OP3, a second separation distance d2' between the third opening OP3 and the first opening OP1, The sum of the third separation distance d3' between the first opening OP1 and the fourth opening OP4 and the fourth separation distance d4' between the fourth opening OP4 and the second edge ed2' may be smaller than the length ℓ1' of the second electrode E2' along the second direction (eg, ±y direction). In other words, the sum of the first separation distance d1', the second separation distance d2', the third separation distance d3', and the fourth separation distance d4' is equal to the first edge ed1' It may be smaller than the distance between the second edges ed2'.

A first separation distance d1', a second separation distance d2', a third separation distance d3', a fourth separation distance d4', along a second direction (eg, ±y direction) The length ℓ2′ of the third opening OP3, the length ℓ3′ of the first opening OP1 along the second direction (eg, ±y direction), and the second direction (eg, ±y direction) The sum of the lengths ℓ4' of the fourth opening OP4 along the y direction) may be substantially equal to the length ℓ1' of the second electrode. In other words, the first separation distance d1', the second separation distance d2', the third separation distance d3', the fourth separation distance d4', and the length of the third opening OP3 (ℓ2'). ), the sum of the length ℓ3′ of the first opening OP1, and the length ℓ4′ of the fourth opening OP4 is the separation distance between the first edge ed1′ and the second edge ed2′ may be substantially the same as Although the first opening OP1 , the third opening OP3 , and the fourth opening OP4 have been described, the second opening OP2 , the fifth opening OP5 , and the sixth opening OP6 are the same. can be applied

In an embodiment, the first region AR1 and the second region AR2 of the first semiconductor layer Act1 may at least partially overlap the second electrode E2'. The first overlapping area OAR1' of the first region AR1 and the second electrode E2' is substantially the same as the second overlapping area OAR2' of the second region AR2 and the second electrode E2'. can be the same Although the description has been made based on the first semiconductor layer Act1, the second semiconductor layer Act2 may also be applied in the same manner.

When a plurality of openings are formed in the second electrode E2' as in one embodiment of the present invention, the area of the second electrode E2' contacting the interlayer insulating layer 117 (see FIG. 8) may be reduced. there is. When the area of the second electrode E2' in contact with the interlayer insulating layer 117 is reduced, stress on the interlayer insulating layer 117 and the second electrode E2' may be reduced during the subsequent heat treatment process. there is. Since the stress applied to the interlayer insulating layer 117 and the second electrode E2' is reduced, the boundary between the interlayer insulating layer 117 and the second electrode E2' can be prevented from widening, and the interlayer insulating layer 117 ), it is possible to prevent defects of the conductive layer (for example, the connection electrode CM, see FIG. 8) disposed on the surface.

On the other hand, in FIG. 7, the planar shape of each of the third opening OP3, fourth opening OP4, fifth opening OP5, and sixth opening OP6 is shown as a rectangle, but as another embodiment, Planar shapes of each of the third opening OP3, fourth opening OP4, fifth opening OP5, and sixth opening OP6 are polygonal shapes such as triangles, pentagons, and hexagons, circular shapes, elliptical shapes, and irregular shapes. shape, etc. In addition, although FIG. 7 shows that one third opening OP3, fourth opening OP4, fifth opening OP5, and sixth opening OP6 are formed one by one, as another embodiment, The number of the three openings OP3 , the fourth opening OP4 , the fifth opening OP5 , and the sixth opening OP6 may be plural.

Hereinafter, one form of the third opening OP3 , the fourth opening OP4 , the fifth opening OP5 , and the sixth opening OP6 will be described with reference to FIG. 9 .

9 is an enlarged plan view schematically illustrating a portion of a display device according to an exemplary embodiment. FIG. 9 is a modified embodiment of FIG. 7 and has a difference in the structure of the second electrode E2''. Hereinafter, overlapping contents will be replaced with the description of FIG. 7 and the differences will be mainly described.

Referring to FIG. 9 , a planar shape of each of the third opening OP3 ′, the fourth opening OP4 ′, the fifth opening OP5 ′, and the sixth opening OP6 ′ may be circular.

There may be a plurality of third openings OP3', fourth openings OP4', fifth openings OP5', and sixth openings OP6'. For example, as shown in FIG. 9 , there may be two third openings OP3 ′, fourth openings OP4 ′, fifth openings OP5 ′, and sixth openings OP6 ′. The plurality of third openings OP3 ′ and the plurality of fourth openings OP4 ′ may be spaced apart from each other with the first opening OP1 interposed therebetween. The plurality of fifth openings OP5' and the plurality of sixth openings OP6' may be spaced apart from each other with the second opening OP2 therebetween.

10 is an enlarged plan view schematically illustrating a portion of a display device according to an exemplary embodiment. FIG. 10 is a modified embodiment of FIG. 7 and has a difference in the structure of the second electrode E2'''. Hereinafter, overlapping contents will be replaced with the description of FIG. 7 and the differences will be mainly described.

Referring to FIG. 10 , a second electrode E2''' may be disposed on the first electrode E1 and the third electrode E3. The second electrode E2''' extends in a first direction (eg, a ±x direction) and may overlap at least a portion of the first pixel area PXA1 and the second pixel area PXA2. The second electrode E2''' includes molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed of a single layer or multiple layers. For example, the second electrode E2''' may be a single layer of Mo.

In one embodiment, the second electrode E2''' includes a first opening OP1 and a second opening OP2 exposing a part of the second gate insulating layer 115 (see FIG. 8), which is an insulating layer; A seventh opening OP7 and an eighth opening OP8 may be provided. The first opening OP1 may overlap the first electrode E1 and serve as a passage through which the first electrode E1 is connected to the connection electrode CM (refer to FIG. 8 ). The second opening OP2 may overlap the third electrode E3 and serve as a passage through which the third electrode E3 is connected to the connection electrode CM or the like. The seventh opening OP7 and the eighth opening OP8 may be spaced apart from each other along the first direction (eg, ±x direction) with the first opening OP1 interposed therebetween. The seventh opening OP7 may be positioned between the first opening OP1 and the second opening OP2.

In one embodiment, the second electrode E2''' includes a first edge ed1'' and a second edge ed2'' spaced apart from each other in a second direction (eg, ±y direction). can have A first separation distance d1'' between the first edge ed1'' and the first opening OP1, and a second separation distance d2 between the first opening OP1 and the second edge ed2'' ' '), and the sum of the length ℓ2'' of the first opening OP1 along the second direction (eg, ±y direction) is the second direction (eg, ±y direction). It may be substantially the same as the length (ℓ1″) of the second electrode (E2″). In other words, the sum of the first separation distance d1'', the second separation distance d2'', and the length ℓ2'' of the first opening OP1 is the first edge ed1'' and the second It may be substantially equal to the distance between the two edges ed2''.

A third separation distance d3'' between the first edge ed1'' and the seventh opening OP7, and a fourth separation distance d4 between the seventh opening OP7 and the second edge ed2'' '') and the length ℓ3'' of the seventh opening OP7 along the second direction (eg, ±y direction) is the first along the second direction (eg, ±y direction). It may be substantially the same as the length (ℓ1″) of the second electrode (E2″). In other words, the sum of the third separation distance d3'', the fourth separation distance d4'', and the length ℓ3'' of the seventh opening OP7 is equal to the first edge ed1'' and the second It may be substantially equal to the distance between the two edges ed2''. That is, the sum of the first separation distance d1'', the second separation distance d2'', and the length ℓ2'' of the first opening OP1 is the third separation distance d3'', It may be substantially equal to the sum of the 4 separation distances d4'' and the length ℓ3'' of the seventh opening OP7.

A first separation distance d1 ″ between the first edge ed1″ and the first opening OP1 and a second separation distance d2 between the first opening OP1 and the second edge ed2″ The sum of '' is the third separation distance d3'' between the first edge ed1'' and the seventh opening OP7 and the distance between the seventh opening OP7 and the second edge ed2''. It may be greater than the sum of the fourth separation distances d4''. Although the description has been made based on the first opening OP1 , the second opening OP2 may be equally applied.

When a plurality of openings are formed in the second electrode E2''' as in one embodiment of the present invention, the area of the second electrode E2''' in contact with the interlayer insulating layer 117 (see FIG. 8) this may decrease When the area of the second electrode E2''' in contact with the interlayer insulating layer 117 is reduced, stress on the interlayer insulating layer 117 and the second electrode E2''' during the subsequent heat treatment process may decrease. Since the stress applied to the interlayer insulating layer 117 and the second electrode E2''' is reduced, it is possible to prevent the boundary between the interlayer insulating layer 117 and the second electrode E2''' from widening, and A defect in a conductive layer (eg, a connection electrode CM, see FIG. 8 ) disposed on the insulating layer 117 may be prevented.

Meanwhile, in FIG. 10 , the planar shapes of each of the seventh opening OP7 and the eighth opening OP8 are shown as being rectangular, but in another embodiment, each of the seventh opening OP7 and the eighth opening OP8 has a rectangular shape. The planar shape may be a polygonal shape such as a triangle, pentagon, or hexagon, or a circular shape, an elliptical shape, or an atypical shape. In addition, although FIG. 10 illustrates that one seventh opening OP7 and one eighth opening OP8 are formed, as another embodiment, the seventh opening OP7 and the eighth opening OP8 may be plural. can

So far, only the display device has been mainly described, but the present invention is not limited thereto. For example, a manufacturing method of a display device for manufacturing such a display device will also fall within the scope of the present invention.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

1: display device
100: substrate
PX: pixels
E1, E2, E3: first to third electrodes
Act1, Act2: first and second semiconductor layers
OP1, OP2, OP3: first to third openings

Claims (20)

Board;
a first electrode disposed on the substrate;
a semiconductor layer interposed between the substrate and the first electrode and including a semiconductor region overlapping the first electrode;
an insulating layer disposed on the first electrode; and
A second electrode disposed on the insulating layer and including a first portion overlapping the first electrode at least partially, and a second portion adjacent to the first portion in a first direction,
A first length of the first portion along a second direction crossing the first direction is greater than a second length of the second portion along the second direction. According to claim 1,
The semiconductor layer further includes a first region and a second region extending in the second direction and spaced apart from each other with the semiconductor region interposed therebetween;
The first portion and the first region of the second electrode at least partially overlap each other;
the second portion of the second electrode and the second region at least partially overlap each other;
A first overlapping area of the first portion of the second electrode and the first region is greater than a second overlapping area of the second portion of the second electrode and the second region. According to claim 1,
The first part of the second electrode has a first edge and a third edge spaced apart from each other in the second direction,
The second part of the second electrode has a second edge and a fourth edge spaced apart from each other in the second direction,
An imaginary first line extending in the longitudinal direction of the first edge and an imaginary second line extending in the longitudinal direction of the second edge are spaced apart from each other along the second direction,
An imaginary third line extending in the longitudinal direction of the third edge and an imaginary fourth line extending in the longitudinal direction of the fourth edge coincide with each other. According to claim 3,
A distance between the first imaginary line and the second imaginary line is equal to a difference between the first length and the second length. According to claim 1,
The first part of the second electrode has a first edge and a third edge spaced apart from each other in the second direction,
The second part of the second electrode has a second edge and a fourth edge spaced apart from each other in the second direction,
An imaginary first line extending in the longitudinal direction of the first edge and an imaginary second line extending in the longitudinal direction of the second edge are spaced apart from each other along the second direction,
A third imaginary line extending in the longitudinal direction of the third edge and an imaginary fourth line extending in the longitudinal direction of the fourth edge are spaced apart from each other along the second direction. According to claim 5,
The sum of the first separation distance between the imaginary first line and the imaginary second line and the second separation distance between the imaginary third line and the imaginary fourth line is equal to the first length and the second length Same indicator as car. According to claim 1,
A third electrode disposed on the same layer as the first electrode and spaced apart from the first electrode along the first direction;
The second electrode further includes a third portion overlapping the third electrode at least partially and spaced apart from the first portion with the second portion interposed therebetween;
A third length of the third portion along the second direction is equal to the first length of the first portion. According to claim 1,
display element;
a driving transistor controlling a current flowing to the display element according to a gate-source voltage and including the semiconductor region and the first electrode;
a scan transistor that transmits a data voltage to the driving transistor in response to a scan signal; and
and a storage capacitor connected to the gate of the driving transistor and including the first electrode and the second electrode. Board;
a first electrode disposed on the substrate;
an insulating layer disposed on the first electrode; and
a second electrode disposed on the insulating layer and having first to third openings each exposing a portion of the insulating layer;
The first opening overlaps the first electrode;
The second opening and the third opening are spaced apart from each other with the first opening therebetween. According to claim 9,
The longitudinal direction of the second electrode is a first direction,
The second opening and the third opening are spaced apart from each other along a second direction crossing the first direction. According to claim 10,
The second electrode has a first edge and a second edge spaced apart from each other in a longitudinal direction in the first direction and in the second direction,
Located in the order of the first edge, the second opening, the first opening, the third opening, and the second edge along the second direction,
a first separation distance between the first edge and the second opening, a second separation distance between the second opening and the first opening, a third separation distance between the first opening and the third opening, and the The display device of claim 1 , wherein a sum of a fourth separation distance between a third opening and the second edge is smaller than a length of the second electrode along the second direction. According to claim 10,
A semiconductor region interposed between the substrate and the first electrode and overlapping the first electrode, and a first region and a second region extending in the second direction and spaced apart from each other with the semiconductor region interposed therebetween. Further comprising a semiconductor layer,
A first overlapping area of the second electrode and the first region is equal to a second overlapping area of the second electrode and the second region. According to claim 10,
A third electrode disposed on the same layer as the first electrode and spaced apart from the first electrode along the first direction;
The second electrode further has fourth to sixth openings each exposing a portion of the insulating layer;
The fourth opening overlaps the third electrode,
The fifth opening and the sixth opening are spaced apart from each other along the second direction with the fourth opening interposed therebetween. According to claim 9,
The longitudinal direction of the second electrode is a first direction,
The second opening and the third opening are spaced apart from each other along the first direction. According to claim 14,
The second electrode has a first edge and a second edge spaced apart from each other in a second direction crossing the first direction,
The sum of the first separation distance between the first edge and the first opening, the second separation distance between the first opening and the second edge, and the first length of the first opening along the second direction is a sum of a third separation distance between the first edge and the second opening, a fourth separation distance between the second opening and the second edge, and a second length of the second opening along the second direction; same display device. According to claim 14,
The second electrode has a first edge and a second edge spaced apart from each other in a second direction crossing the first direction,
The sum of the first separation distance between the first edge and the first opening and the second separation distance between the first opening and the second edge is a third separation distance between the first edge and the second opening and a display device greater than a sum of a fourth separation distance between the second opening and the second edge. According to claim 14,
A third electrode disposed on the same layer as the first electrode and spaced apart from the first electrode along the first direction;
the second electrode further has a fourth opening exposing a portion of the insulating layer and overlapping the third electrode;
The second opening or the third opening is positioned between the first opening and the fourth opening. According to claim 9,
A planar shape of each of the first to third openings is a rectangle. According to claim 9,
A planar shape of each of the second opening and the third opening is circular. According to claim 9,
display element;
a driving transistor configured to control a current flowing to the display element according to a gate-source voltage and including the first electrode;
a scan transistor that transmits a data voltage to the driving transistor in response to a scan signal; and
and a storage capacitor connected to the gate of the driving transistor and including the first electrode and the second electrode.

Images