KR20230006720A - Light emitting display device - Google Patents

Abstract

The present invention relates to a light-emitting display device which comprises: a substrate including a light sensor region located in a display region; a first semiconductor layer located on the substrate on the display region of the substrate; a first gate insulation film located on the first semiconductor layer; a first gate conductive layer located on the first gate insulation film; a second gate insulation film located on the first gate conductive layer; a second gate conductive layer located on the second gate insulation film; a first interlayer insulation film located on the second gate conductive layer; an oxide semiconductor layer located on the first interlayer insulation film; a third gate insulation film located on the oxide semiconductor layer; a third gate conductive layer located on the third gate insulation film; and a second interlayer insulation film located on the third gate conductive layer. The light sensor region has the first gate insulation film, the second gate insulation film, the first interlayer insulation film, the third gate insulation film, an additional organic film pattern, and the second interlayer insulation film which are successively stacked on the substrate. The additional organic film pattern overlaps with the light sensor region on a plane, and is located only on the light sensor region and a part near the region. Therefore, display quality can be improved.

Description

Light emitting display device {LIGHT EMITTING DISPLAY DEVICE}

The present disclosure relates to a light emitting display device, and more particularly, to a light emitting display device that reduces reflectance of external light without using a polarizing plate.

A display device is a device that displays a screen, and includes a liquid crystal display (LCD), an organic light emitting diode (OLED), and the like. Such display devices are used in various electronic devices such as mobile phones, navigation devices, digital cameras, electronic books, portable game consoles, and various terminals.

A display device such as an organic light emitting display device may have a bendable or foldable structure by using a flexible substrate.

In addition, in small electronic devices such as mobile phones, optical elements such as cameras and optical sensors are formed in the bezel area around the display area, but as the size of the display screen is increased, the size of the area around the display area gradually decreases However, a technology that can position an optical sensor on the back of the display area is being developed.

The embodiments are intended to improve display quality by reducing the reflectance of external light or reducing color spreading (color separation) caused by reflected light. In addition, the embodiments are intended to improve light transmittance of an optical sensor area located in a display panel.

A light emitting display device according to an exemplary embodiment includes a substrate including a photosensor area positioned in a display area; a first semiconductor layer positioned on the substrate in the display area of the substrate; a first gate insulating layer positioned on the first semiconductor layer; a first gate conductive layer positioned on the first gate insulating layer; a second gate insulating layer positioned on the first gate conductive layer; a second gate conductive layer positioned on the second gate insulating layer; a first interlayer insulating film positioned on the second gate conductive layer; an oxide semiconductor layer positioned on the first interlayer insulating film; a third gate insulating layer positioned on the oxide semiconductor layer; a third gate conductive layer positioned on the third gate insulating layer; and a second interlayer insulating film positioned on the third gate conductive layer, wherein the photosensor region includes the first gate insulating film, the second gate insulating film, the first interlayer insulating film, the third gate insulating film, An additional organic layer pattern and the second interlayer insulating layer are sequentially stacked, and the additional organic layer pattern overlaps the photosensor region in a plan view and is located only in the photosensor region and a portion adjacent thereto.

The additional organic layer pattern may be an organic insulating layer.

A plurality of additional organic layer patterns are formed, and each of the additional organic layers has an island-like structure and may be separated from each other.

The additional organic layer pattern may have a pentagonal shape.

The display area may further include a metal layer between the substrate and the first semiconductor layer and a buffer layer positioned on the metal layer, and in the photosensor area, the buffer layer may be positioned between the substrate and the first gate insulating layer. .

The display area may include a first data conductive layer positioned on the second interlayer insulating layer; a first organic layer on the first data conductive layer; a second data conductive layer positioned on the first organic layer; a second organic layer and a third organic layer positioned on the second data conductive layer and sequentially formed; and an anode positioned on the third organic layer, wherein the first organic layer, the second organic layer, and the third organic layer may be sequentially stacked on the second interlayer insulating layer in the photosensor region. .

The display area may include a black pixel defining layer having an anode exposure opening exposing the anode; a light emitting layer within the opening for exposing the anode and positioned over the anode; a functional layer and a cathode sequentially positioned on the black pixel-defining layer and the anode; an encapsulation layer covering the cathode; a light blocking member positioned on the encapsulation layer and having an opening for a color filter; and a color filter filling the opening for the color filter of the light blocking member, wherein the functional layer, the cathode, and the encapsulation layer may be sequentially stacked on the third organic layer in the photosensor area.

the color filter includes a first color filter, a second color filter, and a third color filter, the first color filter includes a color filter opening, and is divided into an overlapping portion connecting a main portion and an adjacent main portion; The second color filter and the third color filter may be positioned at the color filter opening of the first color filter, respectively.

The black pixel defining layer, the light blocking member, and the color filter may each have the additional opening overlapping the photosensor region in a plan view.

The display area may include a sensing electrode disposed between the encapsulation layer and the light blocking member, overlapping the light blocking member in a plane view, and covered by the light blocking member; and a sensing insulating layer positioned between the encapsulation layer and the light blocking member and positioned above and below the sensing electrode, wherein the sensing insulating layer may be further stacked on the encapsulation layer in the optical sensor region.

The first data conductive layer may include a first extension, the second data conductive layer may include a second extension, and each of the first extension and the second extension may overlap the anode on a plane.

The display area further includes a spacer disposed between the black pixel defining layer and the cathode, the spacer having a first portion and a height lower than the first portion, and integrally formed with the first portion. It may include a structure having a step difference including the second part.

According to an exemplary embodiment, the light emitting display device has a photosensor area positioned in the display area, and the photosensor area includes a buffer layer, a first gate insulating layer, a second gate insulating layer, a first interlayer insulating layer, a third gate insulating layer, and an additional layer on a substrate. An organic layer pattern, a second interlayer insulating layer, a first organic layer, and a second organic layer are sequentially stacked, and the additional organic layer pattern overlaps the photosensor region in a plan view, and the photosensor region and a portion adjacent thereto. located only in

The additional organic layer pattern may be an organic insulating layer.

A plurality of additional organic layer patterns are formed, and each of the additional organic layers has an island-like structure and may be separated from each other.

The additional organic layer pattern may have a pentagonal shape.

In the photosensor region, a third organic layer, a functional layer, a cathode, an encapsulation layer, and a sensing insulating layer may be sequentially stacked on the second organic layer.

The display area may include a metal layer positioned on the substrate; the buffer layer positioned on the metal layer; a first semiconductor layer positioned on the buffer layer; the first gate insulating layer positioned on the first semiconductor layer; a first gate conductive layer positioned on the first gate insulating layer; the second gate insulating layer positioned on the first gate conductive layer; a second gate conductive layer positioned on the second gate insulating layer; the first interlayer insulating film positioned on the second gate conductive layer; an oxide semiconductor layer positioned on the first interlayer insulating film; the third gate insulating layer positioned on the oxide semiconductor layer; a third gate conductive layer positioned on the third gate insulating layer; the second interlayer insulating film positioned on the third gate conductive layer; a first data conductive layer positioned on the second interlayer insulating layer; the first organic layer positioned on the first data conductive layer; a second data conductive layer positioned on the first organic layer; the second organic layer and the third organic layer positioned on the second data conductive layer and sequentially formed; an anode positioned on the third organic layer; a black pixel defining layer having an opening for exposing the anode to expose the anode; a light emitting layer within the opening for exposing the anode and positioned over the anode; the functional layer and the cathode sequentially positioned on the black pixel-defining layer and the anode; an encapsulation layer covering the cathode; a light blocking member positioned on the encapsulation layer and having an opening for a color filter; a color filter filling an opening for the color filter of the light blocking member; a sensing electrode positioned between the encapsulation layer and the light blocking member, overlapping the light blocking member in a plane view, and covered by the light blocking member; and a sensing insulating layer positioned between the encapsulation layer and the light blocking member and positioned above and below the sensing electrode.

the color filter includes a first color filter, a second color filter, and a third color filter, the first color filter includes a color filter opening, and is divided into an overlapping portion connecting a main portion and an adjacent main portion; The second color filter and the third color filter may be positioned at the color filter opening of the first color filter, respectively.

The black pixel defining layer, the light blocking member, and the color filter may each have the additional opening overlapping the photosensor region in a plan view.

According to embodiments, a reflection rate of external light may be reduced by using a black pixel defining layer for separating the light emitting layers from each other instead of the polarizing plate. On the other hand, by forming the optical sensor area adjacent to the anode flat, the anode is made flatter so that the light reflected from the anode does not spread asymmetrically, reducing color spreading (color separation) caused by reflected light to improve display quality. can In addition, according to embodiments, the light reflected from the anode is prevented from spreading asymmetrically by forming the light sensor area located on the display panel flat so that the anode adjacent to the light sensor area is also formed flat.

1 is a schematic perspective view illustrating a use state of a display device according to an exemplary embodiment.
2 is an exploded perspective view of a display device according to an exemplary embodiment.
3 is a block diagram of a display device according to an exemplary embodiment.
4 is a perspective view schematically illustrating a light emitting display device according to another exemplary embodiment.
5 is a plan view illustrating an enlarged portion of a light emitting display device according to an exemplary embodiment.
6 is a circuit diagram of one pixel included in a light emitting display device according to an exemplary embodiment.
7 to 20 are diagrams specifically illustrating the structure of each layer according to the manufacturing order of the lower panel layer in the light emitting display device according to an exemplary embodiment.
21 is a cross-sectional view of an additional organic layer pattern and its surroundings in a light emitting display device according to an exemplary embodiment.
22 is a cross-sectional view of a light emitting display device according to an exemplary embodiment.
23 is a top plan view of a portion of an upper panel layer of a light emitting display device according to an exemplary embodiment.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. This invention may be embodied in many different forms and is not limited to the embodiments set forth herein.

In order to clearly describe the present invention, parts irrelevant to the description are omitted, and the same reference numerals are assigned to the same or similar components throughout the specification.

In addition, since the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, the present invention is not necessarily limited to the shown bar. In the drawings, the thickness is shown enlarged to clearly express the various layers and regions. And in the drawings, for convenience of explanation, the thicknesses of some layers and regions are exaggerated.

In addition, when a part such as a layer, film, region, plate, etc. is said to be "on" or "on" another part, this includes not only the case where it is "directly on" the other part, but also the case where another part is in the middle. . Conversely, when a part is said to be "directly on" another part, it means that there is no other part in between. In addition, being "above" or "on" a reference part means being located above or below the reference part, and does not necessarily mean being located "above" or "on" in the opposite direction of gravity. .

In addition, throughout the specification, when a certain component is said to "include", it means that it may further include other components without excluding other components unless otherwise stated.

In addition, throughout the specification, when it is referred to as "planar image", it means when the target part is viewed from above, and when it is referred to as "cross-sectional image", it means when a cross section of the target part cut vertically is viewed from the side.

Hereinafter, a schematic structure of the light emitting display device will be described through FIGS. 1 to 3 .

FIG. 1 is a schematic perspective view illustrating a use state of a display device according to an exemplary embodiment, FIG. 2 is an exploded perspective view of the display device according to an exemplary embodiment, and FIG. 3 is a block diagram of the display device according to an exemplary embodiment.

The light emitting display device 1000 according to an exemplary embodiment is a device that displays moving images or still images, and can be used with a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, or an electronic notebook. Display of various products such as televisions, laptops, monitors, billboards, internet of things (IOT) as well as portable electronic devices such as e-books, PMP (portable multimedia player), navigation, and UMPC (Ultra Mobile PC) Can be used as a screen. In addition, the light emitting display device 1000 according to an embodiment is a wearable device such as a smart watch, a watch phone, a glasses-type display, and a head mounted display (HMD). can be used for In addition, the light emitting display device 1000 according to an exemplary embodiment includes a dashboard of a vehicle, a center information display (CID) disposed on a center fascia or dashboard of a vehicle, and a room mirror display replacing a side mirror of a vehicle. (room mirror display), entertainment for the back seat of a car, can be used as a display placed on the back of the front seat. 1 illustrates that the light emitting display device 1000 is used as a smart phone for convenience of description.

1, 2, and 3 , the light emitting display device 1000 displays an image in a third direction DR3 on a display surface parallel to the first and second directions DR1 and DR2 respectively. can do. The display surface on which the image is displayed may correspond to the front surface of the light emitting display device 1000 and may correspond to the front surface of the cover window WU. The image may include a still image as well as a dynamic image.

In this embodiment, the front (or upper surface) and rear surface (or lower surface) of each member are defined based on the direction in which the image is displayed. The front surface and the rear surface oppose each other in the third direction DR3, and a normal direction of each of the front surface and the rear surface may be parallel to the third direction DR3. The separation distance between the front and rear surfaces in the third direction DR3 may correspond to the thickness of the light emitting display panel DP in the third direction DR3.

The light emitting display device 1000 according to an exemplary embodiment may detect a user's input (refer to a hand in FIG. 1 ) applied from the outside. The user's input may include various types of external inputs, such as a part of the user's body, light, heat, or pressure. In one embodiment, the user's input is shown as the user's hand being applied in the foreground. However, the present invention is not limited thereto. User input may be provided in various forms, and the light emitting display device 1000 may detect a user input applied to the side or rear surface of the light emitting display device 1000 according to the structure of the light emitting display device 1000. may be

Meanwhile, the display area DA may be largely divided into a first display area DA1 and a second display area DA2 (hereinafter also referred to as a component area). In an embodiment, the second display area DA2 is a light It may include a transmission area LTA, and may additionally include pixels displaying an image. The second display area DA2 may be an area that at least partially overlaps the optical element ES such as a camera or an optical sensor. Although the second display area DA2 is illustrated in FIG. 1 as having a circular shape at the upper right corner of the light emitting display device 1000, the present invention is not limited thereto. The second display area DA2 may be provided in various numbers and shapes according to the number and shape of the optical elements ES.

The light emitting display device 1000 may receive an external signal required for the optical element ES through the second display area DA2 or may provide a signal output from the optical element ES to the outside. In an exemplary embodiment, since the second display area DA2 overlaps the light transmission area LTA, the area of the blocking area BA for forming the light transmission area LTA may be reduced. Here, the blocking area BA is an area having relatively low light transmittance compared to the transmission area TA, and may include a bezel area.

The light emitting display device 1000 may include a cover window WU, a housing HM, a light emitting display panel DP, and an optical element ES. In an exemplary embodiment, the cover window WU and the housing HM may be combined to form the exterior of the light emitting display device 1000 .

The cover window WU may include an insulating panel. For example, the cover window WU may be made of glass, plastic, or a combination thereof.

The front surface of the cover window WU may define the front surface of the light emitting display device 1000 . The transmission area TA may be an optically transparent area. For example, the transmission area TA may have a visible light transmittance of about 90% or more.

The blocking area BA may define the shape of the transmission area TA. The blocking area BA may be adjacent to the transmission area TA and may surround the transmission area TA. The blocking area BA may have relatively low light transmittance compared to the transmission area TA. The blocking area BA may include an opaque material that blocks light. The blocking area BA may have a predetermined color. The blocking area BA may be defined by a bezel layer provided separately from the transparent substrate defining the transmission area TA, or may be defined by an ink layer inserted into or colored in the transparent substrate.

The light emitting display panel DP may include a display panel DP for displaying an image, a touch sensor TS for detecting an external input, and a driving unit 50 . The light emitting display panel DP may include a front surface including a display area DA and a non-display area PA. The display area DA may be an area where pixels operate according to electrical signals to emit light.

In an embodiment, the display area DA is an area including pixels to display an image, and at the same time, the touch sensor TS is positioned on the upper side of the pixel in the third direction DR3 to sense an external input. there is.

The transmission area TA of the cover window WU may at least partially overlap the display area DA of the light emitting display panel DP. For example, the transmission area TA may overlap the entire surface of the display area DA or may overlap at least a portion of the display area DA. Accordingly, the user may view the image through the transmission area TA or provide an external input based on the image. However, the present invention is not limited thereto. For example, within the display area DA, an area where an image is displayed and an area where an external input is sensed may be separated from each other.

The non-display area PA of the light emitting display panel DP may at least partially overlap the blocking area BA of the cover window WU. The non-display area PA may be an area covered by the blocking area BA. The non-display area PA is adjacent to the display area DA and may surround the display area DA. An image is not displayed in the non-display area PA, and a driving circuit or a driving wire for driving the display area DA may be disposed. The non-display area PA may include a first peripheral area PA1 located outside the display area DA and a second peripheral area PA2 including the driving unit 50, connection wires, and a bending area. . In the exemplary embodiment of FIG. 2 , the first peripheral area PA1 is located on the third side of the display area DA, and the second peripheral area PA2 is located on the other side of the display area DA.

In an exemplary embodiment, the light emitting display panel DP may be assembled in a flat state with the display area DA and the non-display area PA facing the cover window WU. However, the present invention is not limited thereto. A part of the non-display area PA of the light emitting display panel DP may be bent. In this case, a part of the non-display area PA faces the rear surface of the light emitting display device 1000, so that the blocking area BA visible on the front surface of the light emitting display device 1000 can be reduced. In FIG. 2 , the second peripheral area After the area PA2 is bent and placed on the rear surface of the display area DA, assembly may be performed.

The display area DA may include a first display area DA1 and a second display area DA2. The second display area DA2 may have a relatively higher light transmittance than the first display area DA1 including the light transmission area LTA. Also, the second display area DA2 may have a relatively smaller area than the first display area DA1. The second display area DA2 may be defined as an area overlapping an area of the light emitting display panel DP where the optical element ES is disposed inside the housing HM. In one embodiment, the second display area DA2 is shown in a circular shape, but the present invention is not limited thereto. can have

The first display area DA1 may be adjacent to the second display area DA2. In one embodiment, the first display area DA1 may surround the entire second display area DA2. However, the present invention is not limited thereto. The first display area DA1 may partially surround the second display area DA2.

Referring to FIG. 3 , the light emitting display panel DP may include a display area DA including display pixels and a touch sensor TS. The light emitting display panel DP may be visually recognized by a user from the outside through the transmission area TA, including pixels that generate an image. In addition, the touch sensor TS may be positioned above the pixel and may detect an external input applied from the outside. The touch sensor TS may detect an external input provided to the cover window WU.

Again, referring to FIG. 2 , the second peripheral area PA2 may include a bending portion. The display area DA and the first peripheral area PA1 may have a flat state substantially parallel to a plane defined by the first and second directions DR1 and DR2 , and the second peripheral area PA1 may be flat. One side of (PA2) may be extended from a flat state to have a flat state again after passing through a bending portion. As a result, at least a portion of the second peripheral area PA2 may be bent and assembled to be positioned on the rear side of the display area DA. When assembled, at least a portion of the second peripheral area PA2 overlaps the display area DA on a plane, so the blocking area BA of the light emitting display device 1000 may be reduced. However, the present invention is not limited thereto. For example, the second peripheral area PA2 may not be bent.

The driving unit 50 may be mounted on the second peripheral area PA2 and may be mounted on the bending unit or located on one of both sides of the bending unit. The driving unit 50 may be provided in the form of a chip.

The driver 50 may be electrically connected to the display area DA to transmit an electrical signal to the display area DA. For example, the driver 50 may provide data signals to the pixels PX disposed in the display area DA. Alternatively, the driving unit 50 may include a touch driving circuit and may be electrically connected to the touch sensor TS disposed in the display area DA. Meanwhile, the driver 50 may include various circuits in addition to the above-described circuits or may be designed to provide various electrical signals to the display area DA.

Meanwhile, in the light emitting display device 1000, a pad part may be positioned at an end of the second peripheral area PA2, and a flexible printed circuit board (FPCB) including a driving chip is electrically connected by the pad part. can be connected to Here, the driving chip positioned on the flexible printed circuit board may include various driving circuits for driving the light emitting display device 1000 or connectors for supplying power. According to embodiments, a rigid printed circuit board (PCB) may be used instead of a flexible printed circuit board.

The optical element ES may be disposed under the light emitting display panel DP. The optical element ES may receive an external input transmitted through the second display area DA2 or output a signal through the second display area DA2. In an embodiment, the second display area DA2 having a relatively high transmittance is provided inside the display area DA, so that the optical element ES may be disposed to overlap the display area DA, and thus, The area (or size) of the blocking area BA may be reduced.

Referring to FIG. 3 , the light emitting display device 1000 may include a light emitting display panel DP, a power supply module PM, a first electronic module EM1, and a second electronic module EM2. The light emitting display panel DP, the power supply module PM, the first electronic module EM1 and the second electronic module EM2 may be electrically connected to each other. FIG. 3 illustratively illustrates a display pixel and a touch sensor TS positioned in the display area DA among components of the light emitting display panel DP.

The power supply module PM may supply power required for overall operation of the light emitting display device 1000 . The power supply module (PM) may include a conventional battery module.

The first electronic module EM1 and the second electronic module EM2 may include various functional modules for operating the light emitting display device 1000 . The first electronic module EM1 may be directly mounted on a motherboard electrically connected to the display panel DP or may be mounted on a separate board and electrically connected to the motherboard through a connector (not shown).

The first electronic module EM1 may include a control module CM, a wireless communication module TM, an image input module IIM, an audio input module AIM, a memory MM, and an external interface IF. there is. Some of the modules may not be mounted on the motherboard and may be electrically connected to the motherboard through a flexible printed circuit board connected thereto.

The control module CM may control overall operations of the light emitting display device 1000 . The control module (CM) may be a microprocessor. For example, the control module CM activates or deactivates the display panel DP. The control module CM may control other modules such as the image input module IIM or the audio input module AIM based on the touch signal received from the display panel DP.

The wireless communication module (TM) can transmit/receive radio signals with other terminals using a Bluetooth or Wi-Fi line. The wireless communication module (TM) can transmit/receive voice signals using a general communication line. The wireless communication module TM includes a transmitter TM1 for modulating and transmitting a signal to be transmitted, and a receiver TM2 for demodulating a received signal.

The image input module (IIM) may process the image signal and convert it into image data that can be displayed on the light emitting display panel (DP). The audio input module (AIM) may receive an external sound signal through a microphone in a recording mode, a voice recognition mode, or the like, and convert it into electrical voice data.

The external interface (IF) may serve as an interface connected to an external charger, a wired/wireless data port, a card socket (eg, a memory card, a SIM/UIM card), and the like.

The second electronic module EM2 may include an audio output module (AOM), a light emitting module (LM), a light receiving module (LRM), and a camera module (CMM), at least some of which are optical elements (ES). 1 and 2 may be located on the rear surface of the display area DA. The optical element ES may include a light emitting module LM, a light receiving module LRM, and a camera module CMM. In addition, the second electronic module EM2 is directly mounted on the motherboard, mounted on a separate board and electrically connected to the light emitting display panel DP through a connector (not shown), or the first electronic module EM1. can be electrically connected to

The audio output module AOM may convert audio data received from the wireless communication module TM or audio data stored in the memory MM and output the converted audio data to the outside.

The light emitting module LM may generate and output light. The light emitting module LM may output infrared rays. For example, the light emitting module LM may include an LED element. For example, the light receiving module (LRM) may detect infrared rays. The light receiving module LRM may be activated when infrared rays of a predetermined level or higher are detected. The light receiving module LRM may include a CMOS sensor. After the infrared light generated by the light emitting module LM is output, it is reflected by an external subject (eg, a user's finger or face), and the reflected infrared light may be incident to the light receiving module LRM. The camera module (CMM) may capture an external image.

In one embodiment, the optical element ES may additionally include a light detection sensor or a heat detection sensor. The optical element ES may detect an external subject received through the front surface or provide a sound signal such as voice to the outside through the front surface. Also, the optical element ES may include a plurality of elements, and is not limited to one embodiment.

Again, referring to FIG. 2 , the housing HM may be coupled to the cover window WU. The cover window WU may be disposed on the front surface of the housing HM. The housing HM may be coupled to the cover window WU to provide a predetermined accommodation space. The light emitting display panel DP and the optical element ES may be accommodated in a predetermined accommodating space provided between the housing HM and the cover window WU.

The housing HM may include a material with relatively high rigidity. For example, the housing HM may include a plurality of frames and/or plates made of glass, plastic, or metal, or a combination thereof. The housing HM can stably protect components of the light emitting display device 1000 accommodated in the inner space from external impact.

Hereinafter, the structure of the light emitting display device 1000 according to another exemplary embodiment will be described through FIG. 4 .

4 is a perspective view schematically illustrating a light emitting display device according to another exemplary embodiment.

4 illustrates a foldable light emitting display having a structure in which the light emitting display 1000 is folded through a folding line FAX.

In the foldable light emitting display device, the second display area DA2 (hereinafter referred to as a component area) may be positioned at one edge as shown in FIG. 4 .

An optical element such as a camera or an optical sensor is positioned on the rear surface of the second display area DA2 of FIG. 4 , and a light transmission area LTA is positioned in the second display area DA2 . The structure of the light transmission area LTA may have a structure to be described later.

Referring to FIG. 4 , in an embodiment, the light emitting display device 1000 may be a foldable light emitting display device. The light emitting display device 1000 may be folded outward or inward with respect to the folding axis FAX. When folded outward with respect to the folding axis FAX, the display surface of the light emitting display device 1000 is positioned on the outer side in the third direction DR3 so that images can be displayed in both directions. When folded inward with respect to the folding axis FAX, the display surface may not be visually recognized from the outside.

The light emitting display device 1000 may include a housing, a light emitting display panel, and a cover window.

In one embodiment, the light emitting display panel may include a display area DA and a non-display area PA. The display area DA is an area where an image is displayed and may also be an area where an external input is sensed. The display area DA may be an area where a plurality of pixels, which will be described later, are disposed.

The display area DA may include a first display area DA1 and a second display area DA2. Also, the first display area DA1 may be divided into a 1-1st display area DA1-1, a 1-2nd display area DA1-2, and a folding area FA. The 1-1st display area DA1-1 and the 1-2nd display area DA1-2 may be located on the left and right sides of the folding axis FAX, respectively, based on (or centered on), and the first The folding area FA may be positioned between the -1 display area DA1 - 1 and the 1 - 2nd display area DA1 - 2 . At this time, when folded outward based on the folding axis FAX, the 1-1 display area DA1-1 and the 1-2 display area DA1-2 are located on both sides in the third direction DR3. and can display images in both directions. Also, when folded inward with respect to the folding axis FAX, the 1-1st display area DA1-1 and the 1-2nd display area DA1-2 may not be visually recognized from the outside.

Depending on the embodiment, the light emitting display panel DP may have the photosensor area OPS adjacent to the second display area DA2 of the first display area DA1.

5 is a plan view illustrating an enlarged portion of a light emitting display device according to an exemplary embodiment.

5 illustrates a portion of a light emitting display panel (DP) of a light emitting display device according to an exemplary embodiment, and is illustrated using a display panel for a mobile phone.

The display area DA is positioned on the front of the light emitting display panel DP, and the display area DA is largely divided into a first display area DA1 (hereinafter referred to as a main display area) and a second display area DA2. . Additionally, in the embodiment of FIG. 5 , the photosensor area OPS is located in the first display area DA1 adjacent to the second display area DA2. In the embodiment of FIG. 5 , the photosensor area OPS is located on the left side of the second display area DA2. The location and number of optical sensor regions OPS may vary according to embodiments.

The first display area DA1 includes a plurality of light emitting diodes and a plurality of pixel circuit units generating and transmitting light emitting current to each of the plurality of light emitting diodes. Here, one light emitting diode and one pixel circuit part are referred to as a pixel PX. In the first display area DA1, one pixel circuit unit and one light emitting diode are formed one-to-one. The first display area DA1 is hereinafter also referred to as a 'normal display area'. Although the structure of the light emitting display panel DP below the cutting line is not shown in FIG. 5 , the first display area DA1 may be located below the cutting line.

The optical sensor region OPS is composed of only a transparent layer so that light can pass therethrough, and no conductive layer or semiconductor layer is located, and the black pixel defining layer 380, the light blocking member 220, and the color filter 230 An opening (hereinafter referred to as an additional opening) may be formed at a position corresponding to the optical sensor area OPS to have a structure that does not block light.

The light emitting display panel DP according to the exemplary embodiment can be largely divided into a lower panel layer and an upper panel layer. The lower panel layer is a portion where light emitting diodes constituting pixels and pixel circuits are located, and may even include an encapsulation layer (see 400 in FIG. 22 ) covering it. That is, the lower panel layer includes an anode, a black pixel defining layer (see 380 in FIG. 22), a light emitting layer (see EML in FIG. 22), and a spacer (see 110 in FIG. 385), a functional layer (see FL in FIG. 22), a cathode (see Cathode in FIG. 22), and an insulating film between the substrate and the anode, a semiconductor layer, and a conductive layer. On the other hand, the upper panel layer is a portion located above the encapsulation layer, and a sensing insulating layer capable of detecting a touch (see 501, 510, and 511 in FIG. 22) and a plurality of sensing electrodes (see 540 and 541 in FIG. 22) and may include a light blocking member (see 220 of FIG. 22 ), a color filter (see 230 of FIG. 22 ), and a planarization layer (see 550 of FIG. 22 ).

Meanwhile, the structure of the upper panel layer in the photosensor area OPS of the first display area DA1 will be reviewed in FIG. 22 , and the structure of the lower panel layer will be reviewed in FIGS. 11 to 22 .

Meanwhile, the second display area DA2 is a display area located in front of the optical element, and has a structure in which a plurality of pixels are formed and a light transmission area LTA is additionally formed between adjacent pixels. The second display area DA2 may be formed to have one unit structure by combining a plurality of pixels, and a light transmission area LTA may be positioned between adjacent unit structures.

The light transmission area LTA is composed of only a transparent layer to allow light to pass through, no conductive layer or semiconductor layer is located, and the black pixel defining layer 380, the light blocking member 220, and the color filter 230 An opening (hereinafter referred to as a light transmitting area opening) may be formed at a position corresponding to the light transmitting area LTA to have a structure that does not block light. The transparent material includes an inorganic insulating layer or an organic insulating layer, and may additionally include a functional layer FL. A structure in which an inorganic insulating layer or an organic insulating layer is stacked on the light transmitting region LTA may vary, and a cross-sectional structure of the light transmitting region according to an exemplary embodiment may be described as follows.

On the substrate, a buffer layer as an inorganic insulating layer (see 111 in FIG. 22 ), a first organic film as an organic insulating layer (see 181 in FIG. 22 ), a functional layer included in a light emitting diode (see FL in FIG. 22 ), and an encapsulation layer ( Reference 400 of FIG. 22) may be located. More specifically, a functional layer, a first inorganic encapsulation layer (see 401 in FIG. 22 ), an organic encapsulation layer (see 402 in FIG. 22 ) and a second inorganic encapsulation layer (see 403 in FIG. 22 ) are sequentially formed on the first organic film. can be formed as Depending on embodiments, a functional layer may be omitted between the first organic layer and the encapsulation layer. On the encapsulation layer, a component area (DA2; also referred to as a second display area) is formed except for the sensing electrode (see 540 in FIG. 22 ), the light blocking member (see 220 in FIG. 22 ), and the color filter (see 230 in FIG. 22 ). It may be the same as the layer stacked on the pixel of . That is, a sensing insulating layer (refer to 501, 510, and 511 of FIG. 22) and a planarization layer (see 550 of FIG. 22) may be positioned on the encapsulation layer in the light transmission area LTA.

Although not shown in FIG. 5 , a peripheral area may be further positioned outside the display area DA. In addition, although FIG. 5 shows a display panel for a mobile phone, the present embodiment can be applied to any display panel in which an optical element can be positioned on the rear surface of the display panel, or a flexible display device. In the case of a foldable display among flexible display devices, the positions of the second display area DA2 and the photosensor area OPS may be formed at positions different from those of FIG. 5 .

Hereinafter, the structure of a pixel located in the lower panel layer of the light emitting display panel DP will be examined in detail through FIGS. 6 to 22 . The following pixel structure may be a pixel structure of the first display area DA1 and/or the second display area DA2 including the photosensor area OPS.

First, a circuit structure of a pixel will be described through FIG. 6 .

6 is a circuit diagram of one pixel included in a light emitting display device according to an exemplary embodiment.

The circuit structure shown in FIG. 6 is a circuit structure of a pixel circuit part and a light emitting diode formed in the first display area DA1 and the second display area DA2 .

One pixel according to an exemplary embodiment includes a plurality of transistors T1, T2, T3, T4, T5, and T6 connected to various wires 127, 128, 151, 152, 153, 155, 171, 172, and 741. , T7), a holding capacitor (Cst), a boost capacitor (C _boost ), and a light emitting diode (LED). Here, transistors and capacitors other than the light emitting diode (LED) constitute a pixel circuit unit. Depending on embodiments, the boost capacitor (C _boost ) may be omitted.

A plurality of wires 127 , 128 , 151 , 152 , 153 , 155 , 171 , 172 , and 741 are connected to one pixel PX. The plurality of wires include a first initialization voltage line 127, a second initialization voltage line 128, a first scan line 151, a second scan line 152, an initialization control line 153, an emission control line 155, A data line 171, a driving voltage line 172, and a common voltage line 741 are included. Although the first scan line 151 connected to the seventh transistor T7 is also connected to the second transistor T2, the seventh transistor T7 differs from the second transistor T2 in some embodiments. It may be connected with a bypass control line.

The first scan line 151 is connected to a scan driver (not shown) to transfer the first scan signal GW to the second transistor T2 and the seventh transistor T7. A voltage of opposite polarity to that applied to the first scan line 151 may be applied to the second scan line 152 at the same timing as the signal of the first scan line 151 . For example, when a voltage of negative polarity is applied to the first scan line 151, a voltage of positive polarity may be applied to the second scan line 152. The second scan line 152 transfers the second scan signal GC to the third transistor T3. The initialization control line 153 transfers the initialization control signal GI to the fourth transistor T4. The emission control line 155 transmits the emission control signal EM to the fifth transistor T5 and the sixth transistor T6.

The data line 171 is a wire that transmits the data voltage DATA generated by the data driver (not shown), and accordingly, the size of the light emitting current transmitted to the light emitting diode (LED) is changed so that the light emitting diode (LED) emits light. Luminance also changes. The driving voltage line 172 applies the driving voltage ELVDD. The first initialization voltage line 127 transfers the first initialization voltage Vinit, and the second initialization voltage line 128 transfers the second initialization voltage AVinit. The common voltage line 741 applies the common voltage ELVSS to the cathode of the light emitting diode LED. In this embodiment, voltages applied to the driving voltage line 172, the first and second initialization voltage lines 127 and 128, and the common voltage line 741 may be constant voltages.

The driving transistor T1 (also referred to as a first transistor) is a p-type transistor and has a silicon semiconductor as a semiconductor layer. This transistor adjusts the amount of light emitting current output to the anode of the light emitting diode LED according to the level of the voltage of the gate electrode of the driving transistor T1 (that is, the voltage stored in the storage capacitor Cst). Since the brightness of the light emitting diode (LED) is adjusted according to the magnitude of the light emitting current output to the anode electrode of the light emitting diode (LED), the light emitting luminance of the light emitting diode (LED) can be adjusted according to the data voltage (DATA) applied to the pixel. . To this end, the first electrode of the driving transistor T1 is disposed to receive the driving voltage ELVDD and is connected to the driving voltage line 172 via the fifth transistor T5. In addition, the first electrode of the driving transistor T1 is also connected to the second electrode of the second transistor T2 to receive the data voltage DATA. Meanwhile, the second electrode of the driving transistor T1 outputs light emitting current to the light emitting diode LED and is connected to the anode of the light emitting diode LED via the sixth transistor T6 (hereinafter referred to as an output control transistor). . In addition, the second electrode of the driving transistor T1 is also connected to the third transistor T3 to transfer the data voltage DATA applied to the first electrode to the third transistor T3. Meanwhile, the gate electrode of the driving transistor T1 is connected to one electrode (hereinafter referred to as a 'second storage electrode') of the storage capacitor Cst. Accordingly, the voltage of the gate electrode of the driving transistor T1 is changed according to the voltage stored in the storage capacitor Cst, and the emission current output from the driving transistor T1 is changed accordingly. The storage capacitor Cst serves to keep the voltage of the gate electrode of the driving transistor T1 constant for one frame. Meanwhile, the gate electrode of the driving transistor T1 is also connected to the third transistor T3 so that the data voltage DATA applied to the first electrode of the driving transistor T1 passes through the third transistor T3 to the driving transistor T1. ) can be passed to the gate electrode of Meanwhile, the gate electrode of the driving transistor T1 may also be connected to the fourth transistor T4 to be initialized by receiving the first initialization voltage Vinit.

The second transistor T2 is a p-type transistor and has a silicon semiconductor as a semiconductor layer. The second transistor T2 is a transistor that receives the data voltage DATA into the pixel. The gate electrode of the second transistor T2 is connected to the first scan line 151 and one electrode (hereinafter referred to as a 'lower boost electrode') of the boost capacitor C _boost . A first electrode of the second transistor T2 is connected to the data line 171 . The second electrode of the second transistor T2 is connected to the first electrode of the driving transistor T1. When the second transistor T2 is turned on by the negative voltage of the first scan signal GW transmitted through the first scan line 151, the data voltage DATA transmitted through the data line 171 The data voltage DATA is finally transferred to the gate electrode of the driving transistor T1 and stored in the storage capacitor Cst.

The third transistor T3 is an n-type transistor and has an oxide semiconductor as a semiconductor layer. The third transistor T3 electrically connects the second electrode of the driving transistor T1 and the gate electrode of the driving transistor T1. As a result, the data voltage DATA is compensated by the threshold voltage of the driving transistor T1 and then stored in the second storage electrode of the storage capacitor Cst. The gate electrode of the third transistor T3 is connected to the second scan line 152, and the first electrode of the third transistor T3 is connected to the second electrode of the driving transistor T1. The second electrode of the third transistor T3 is the second storage electrode of the storage capacitor Cst, the gate electrode of the driving transistor T1, and the other electrode of the boost capacitor C _boost (hereinafter referred to as 'upper boost electrode'). is connected with The third transistor T3 is turned on by the voltage of the positive polarity among the second scan signals GC transmitted through the second scan line 152, and the gate electrode of the driving transistor T1 and the driving transistor T1 are turned on. The second electrode is connected, and the voltage applied to the gate electrode of the driving transistor T1 is transferred to the second storage electrode of the storage capacitor Cst and stored in the storage capacitor Cst. At this time, the voltage stored in the storage capacitor Cst is the voltage of the gate electrode of the driving transistor T1 when the driving transistor T1 is turned off, so that the threshold voltage Vth of the driving transistor T1 is stored in a compensated state.

The fourth transistor T4 is an n-type transistor and has an oxide semiconductor as a semiconductor layer. The fourth transistor T4 serves to initialize the gate electrode of the driving transistor T1 and the second storage electrode of the storage capacitor Cst. The gate electrode of the fourth transistor T4 is connected to the initialization control line 153, and the first electrode of the fourth transistor T4 is connected to the first initialization voltage line 127. The second electrode of the fourth transistor T4 includes the second electrode of the third transistor T3, the second storage electrode of the storage capacitor Cst, the gate electrode of the driving transistor T1, and the boost capacitor C _boost . It is connected to the upper boost electrode. The fourth transistor T4 is turned on by a voltage of positive polarity among the initialization control signals GI transmitted through the initialization control line 153. At this time, the first initialization voltage Vinit is applied to the voltage of the driving transistor T1. It is initialized by transmitting to the gate electrode, the second storage electrode of the storage capacitor Cst, and the upper boost electrode of the boost capacitor C _boost .

The fifth transistor T5 and the sixth transistor T6 are p-type transistors, and have a silicon semiconductor as a semiconductor layer.

The fifth transistor T5 serves to transfer the driving voltage ELVDD to the driving transistor T1. The gate electrode of the fifth transistor T5 is connected to the emission control line 155, the first electrode of the fifth transistor T5 is connected to the driving voltage line 172, and the first electrode of the fifth transistor T5 is connected to the driving voltage line 172. The second electrode is connected to the first electrode of the driving transistor T1.

The sixth transistor T6 serves to transfer the light emitting current output from the driving transistor T1 to the light emitting diode LED. The gate electrode of the sixth transistor T6 is connected to the emission control line 155, the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T1, and the sixth transistor ( The second electrode of T6) is connected to the anode of the light emitting diode (LED).

The seventh transistor T7 is a p-type or n-type transistor, and has a silicon semiconductor or an oxide semiconductor as a semiconductor layer. The seventh transistor T7 serves to initialize the anode of the light emitting diode (LED). The gate electrode of the seventh transistor T7 is connected to the first scan line 151, the first electrode of the seventh transistor T7 is connected to the anode of the light emitting diode (LED), and the seventh transistor T7 The second electrode of ) is connected to the second initialization voltage line 128 . When the seventh transistor T7 is turned on by the negative voltage of the first scan line 151, the second initialization voltage AVinit is applied to the anode of the light emitting diode (LED) to initialize it. Meanwhile, the gate electrode of the seventh transistor T7 may be connected to a separate bypass control line to be controlled by a separate wire from the first scan line 151 . Also, depending on embodiments, the second initialization voltage line 128 to which the second initialization voltage AVinit is applied may be the same as the first initialization voltage line 127 to which the first initialization voltage Vinit is applied.

It has been described that one pixel PX includes seven transistors T1 to T7 and two capacitors (a storage capacitor Cst and a boost capacitor C _boost ), but is not limited thereto. A boost capacitor (C _boost ) may be excluded. Also, although the third transistor and the fourth transistor are formed of n-type transistors, only one of them may be formed of n-type transistors or other transistors may be formed of n-type transistors.

In the above, the circuit structure of the pixel formed in the display area DA has been reviewed through FIG. 6 .

Hereinafter, a detailed planar structure of pixels formed in the display area DA and a stacked structure of the photosensor area OPS will be reviewed through FIGS. 7 to 22 .

First, through FIGS. 7 to 20, a planar structure of each layer according to the manufacturing sequence will be looked at. The pixel structure shown here may be a pixel structure of the first display area DA1 and/or the second display area DA2 including the photosensor area OPS.

7 to 20 are diagrams specifically illustrating the structure of each layer according to the manufacturing order of the lower panel layer in the light emitting display device according to an exemplary embodiment.

Referring to FIG. 7 , a metal layer BML is positioned on the substrate 110 .

The substrate 110 may include a rigid material, such as glass, that does not bend, or may include a flexible material that can bend, such as plastic or polyimide. In the case of a flexible substrate, as shown in FIG. 22 , a double-layered structure of polyimide and a barrier layer formed of an inorganic insulating material thereon may be formed.

The metal layer BML includes a plurality of expansion parts BML1 and a connection part BML2 connecting the plurality of expansion parts BML1 to each other. The expansion part BML1 of the metal layer BML may be formed at a position overlapping the channel 1132 of the driving transistor T1 in a planar view among the subsequent first semiconductor layers. The metal layer (BML) is also referred to as a lower shielding layer, and may include a metal or metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), and titanium (Ti), and may additionally include amorphous silicon, , may be composed of a single layer or multiple layers.

Referring to FIG. 22 , a buffer layer 111 covering the substrate 110 and the metal layer BML is positioned. The buffer layer 111 serves to block impurity elements from penetrating into the first semiconductor layer 130, and may be an inorganic insulating layer including silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiONx).

On the buffer layer 111, as shown in FIG. 8, a first semiconductor layer 130 formed of a silicon semiconductor (eg, polycrystalline semiconductor) is positioned. The first semiconductor layer 130 includes the channel 1132 of the driving transistor T1, the first region 1131, and the second region 1133. In addition, the first semiconductor layer 130 includes channels of not only the driving transistor T1 but also the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, Both sides of each channel have regions having conductive layer characteristics by plasma treatment or doping to serve as the first electrode and the second electrode.

The channel 1132 of the driving transistor T1 may be formed in a curved shape on a plane. However, the shape of the channel 1132 of the driving transistor T1 is not limited thereto and may be variously changed. For example, the channel 1132 of the driving transistor T1 may be bent in a different shape or formed in a rod shape. The first region 1131 and the second region 1133 of the driving transistor T1 may be positioned on both sides of the channel 1132 of the driving transistor T1 . The first region 1131 and the second region 1133 positioned on the first semiconductor layer serve as first and second electrodes of the driving transistor T1.

In the portion 1134 extending downward from the first region 1131 of the driving transistor T1 in the first semiconductor layer 130, the channel, the first region, and the second region of the second transistor T2 are positioned. . A channel, a first region, and a second region of the fifth transistor T5 are positioned in a portion 1135 extending upward from the first region 1131 of the driving transistor T1. The channel, first region, and second region of the sixth transistor T6 are positioned in the portion 1136 extending upward from the second region 1133 of the driving transistor T1. A channel, a first region, and a second region of the seventh transistor T7 are positioned in a portion 1137 of the first semiconductor layer 130 that is bent and further extended from the portion 1136 .

Referring to FIG. 22 , a first gate insulating layer 141 is positioned on the first semiconductor layer 130 including the channel 1132 of the driving transistor T1, the first region 1131, and the second region 1133. can do. The first gate insulating layer 141 may be an inorganic insulating layer including silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiONx).

Referring to FIG. 9 , a first gate conductive layer including the gate electrode 1151 of the driving transistor T1 may be positioned on the first gate insulating layer 141 . The first gate conductive layer includes not only the driving transistor T1 , but also gate electrodes of the second transistor T2 , the fifth transistor T5 , the sixth transistor T6 , and the seventh transistor T7 . The gate electrode 1151 of the driving transistor T1 may overlap the channel 1132 of the driving transistor T1. The channel 1132 of the driving transistor T1 is covered by the gate electrode 1151 of the driving transistor T1.

The first gate conductive layer may further include a first scan line 151 and an emission control line 155 . The first scan line 151 and the emission control line 155 may extend substantially in a horizontal direction (hereinafter referred to as a first direction). The first scan line 151 may be connected to the gate electrode of the second transistor T2. The first scan line 151 may be integrally formed with the gate electrode of the second transistor T2. The first scan line 151 is also connected to the gate electrode of the seventh transistor T7 of the next pixel.

Meanwhile, the light emitting control line 155 may be connected to the gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6, and the light emitting control line 155 and the fifth transistor T5 and the sixth transistor The gate electrode of (T6) may be formed integrally.

The first gate conductive layer may include a metal or metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti), and may be composed of a single layer or multiple layers.

After the first gate conductive layer including the gate electrode 1151 of the driving transistor T1 is formed, a plasma treatment or doping process may be performed to make the exposed region of the first semiconductor layer conductive. That is, the first semiconductor layer covered by the first gate conductive layer is not conductive, and a portion of the first semiconductor layer not covered by the first gate conductive layer may have the same characteristics as the conductive layer. As a result, the transistor including the conductive portion has p-type transistor characteristics, and thus the driving transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 ) may be a p-type or n-type transistor.

Referring to FIG. 22 , a second gate insulating layer 142 may be positioned on the first gate conductive layer including the gate electrode 1151 of the driving transistor T1 and the first gate insulating layer 141 . The second gate insulating layer 142 may be an inorganic insulating layer including silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiONx).

Referring to FIG. 10 , the first storage electrode 1153 of the storage capacitor Cst, the lower shielding layer 3155 of the third transistor T3 and the lower portion of the fourth transistor T4 are formed on the second gate insulating layer 142 . A second gate conductive layer including the shielding layer 4155 may be positioned. The lower shielding layers 3155 and 4155 are positioned below the channels of the third and fourth transistors T3 and T4, respectively, to serve as shielding from light or electromagnetic interference provided to the channels from the lower side. can

The first storage electrode 1153 overlaps the gate electrode 1151 of the driving transistor T1 to form a storage capacitor Cst. An opening 1152 is formed in the first storage electrode 1153 of the storage capacitor Cst. The opening 1152 of the first storage electrode 1153 of the storage capacitor Cst may overlap the gate electrode 1151 of the driving transistor T1. The first storage electrode 1153 extends in a horizontal direction (first direction) and is connected to an adjacent first storage electrode 1153 .

The lower shielding layer 3155 of the third transistor T3 may overlap the channel 3137 and the gate electrode 3151 of the third transistor T3. The lower shielding layer 4155 of the fourth transistor T4 may overlap the channel 4137 and the gate electrode 4151 of the fourth transistor T4.

The second gate conductive layer may further include a lower second scan line 152a, a lower initialization control line 153a, and a first initialization voltage line 127. The lower second scan line 152a, the lower initialization control line 153a, and the first initialization voltage line 127 may extend substantially in a horizontal direction (first direction). The lower second scan line 152a may be connected to the lower shielding layer 3155 of the third transistor T3. The lower second scan line 152a may be integrally formed with the lower shielding layer 3155 of the third transistor T3. The lower initialization control line 153a may be connected to the lower shielding layer 4155 of the fourth transistor T4. The lower initialization control line 153a may be integrally formed with the lower shielding layer 4155 of the fourth transistor T4.

The second gate conductive layer GAT2 may include a metal or metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti), and may be composed of a single layer or multiple layers. .

Referring to FIG. 22 , the first storage electrode 1153 of the storage capacitor Cst, the lower shielding layer 3155 of the third transistor T3 and the lower shielding layer 4155 of the fourth transistor T4 are included. A first interlayer insulating layer 161 may be positioned on the second gate conductive layer. The first interlayer insulating film 161 may include an inorganic insulating film including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiONx), or the like, and depending on embodiments, an inorganic insulating material may be formed thickly. .

Referring to FIG. 11 , a channel 3137 of the third transistor T3, a first region 3136 and a second region 3138, and a channel 4137 of the fourth transistor T4 are formed on the first interlayer insulating film 161. ), an oxide semiconductor layer including the first region 4136 and the second region 4138 may be located. In addition, the oxide semiconductor layer may include an upper boost electrode 3138t of the capacitor C _boost .

Channel 3137, first region 3136 and second region 3138 of third transistor T3, channel 4137, first region 4136 and second region 4138 of fourth transistor T4 ) may be integrally connected to each other. The first region 3136 and the second region 3138 of the third transistor T3 are positioned on both sides of the channel 3137 of the third transistor T3, and the channel 4137 of the fourth transistor T4 A first region 4136 and a second region 4138 of the fourth transistor T4 are positioned on both sides. The second region 3138 of the third transistor T3 is connected to the second region 4138 of the fourth transistor T4. The channel 3137 of the third transistor T3 overlaps the lower shielding layer 3155, and the channel 4137 of the fourth transistor T4 overlaps the lower shielding layer 4155.

An upper boost electrode 3138t of the capacitor C _boost is positioned between the second region 3138 of the third transistor T3 and the second region 4138 of the fourth transistor T4. The upper boost electrode 3138t of the boost capacitor C _boost overlaps the lower _boost electrode 151a of the boost capacitor C _boost to form the boost capacitor C boost .

Referring to FIG. 22 , the channel 3137, the first region 3136 and the second region 3138 of the third transistor T3, the channel 4137 of the fourth transistor T4, and the first region 4136 A third gate insulating layer 143 may be positioned on the oxide semiconductor layer including the second region 4138 and the upper boost electrode 3138t of the boost capacitor C _boost .

The third gate insulating layer 143 may be positioned on the entire surface of the oxide semiconductor layer and the first interlayer insulating layer 161 . Accordingly, the third gate insulating film 143 is formed on the channel 3137, the first region 3136 and the second region 3138 of the third transistor T3, the channel 4137 of the fourth transistor T4, the first The region 4136 and the second region 4138 may cover top and side surfaces of the upper boost electrode 3138t of the boost capacitor C _boost . However, the present embodiment is not limited thereto, and the third gate insulating layer 143 may not be located on the entire surface of the oxide semiconductor layer and the first interlayer insulating layer 161 . For example, the third gate insulating layer 143 may overlap the channel 3137 of the third transistor T3 and may not overlap the first region 3136 and the second region 3138. Also, the third gate insulating layer 143 may overlap the channel 4137 of the fourth transistor T4 and may not overlap the first region 4136 and the second region 4138 .

The third gate insulating layer 143 may include an inorganic insulating layer including silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiONx).

Referring to FIG. 12 , a third gate conductive layer including a gate electrode 3151 of the third transistor T3 and a gate electrode 4151 of the fourth transistor T4 may be positioned on the third gate insulating layer 143. can

The gate electrode 3151 of the third transistor T3 may overlap the channel 3137 of the third transistor T3. The gate electrode 3151 of the third transistor T3 may overlap the lower shielding layer 3155 of the third transistor T3.

The gate electrode 4151 of the fourth transistor T4 may overlap the channel 4137 of the fourth transistor T4. The gate electrode 4151 of the fourth transistor T4 may overlap the lower shielding layer 4155 of the fourth transistor T4.

The third gate conductive layer may further include an upper second scan line 152b and an upper initialization control line 153b.

The upper second scan line 152b and the upper initialization control line 153b may extend substantially in a horizontal direction (first direction). The upper second scan line 152b forms the second scan line 152 together with the lower second scan line 152a. The upper second scan line 152b may be connected to the gate electrode 3151 of the third transistor T3. The upper second scan line 152b may be integrally formed with the gate electrode 3151 of the third transistor T3. The upper initialization control line 153b forms the initialization control line 153 together with the lower initialization control line 153a. The upper initialization control line 153b may be connected to the gate electrode 4151 of the fourth transistor T4. The upper initialization control line 153b may be integrally formed with the gate electrode 4151 of the fourth transistor T4.

In addition, the third gate conductive layer may further include a lower second initialization voltage line 128a. The lower second initialization voltage line 128a may extend substantially in a horizontal direction (first direction), and the second initialization voltage AVinit is applied.

The third gate conductive layer GAT3 may include a metal or metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti), and may be composed of a single layer or multiple layers. .

After forming the third gate conductive layer including the gate electrode 3151 of the third transistor T3 and the gate electrode 4151 of the fourth transistor T4 through a plasma treatment or doping process, the third gate conductive layer A portion of the oxide semiconductor layer covered by is formed as a channel, and a portion of the oxide semiconductor layer not covered by the third gate conductive layer becomes a conductor. The channel 3137 of the third transistor T3 may be positioned below the gate electrode 3151 to overlap with the gate electrode 3151 . The first region 3136 and the second region 3138 of the third transistor T3 may not overlap the gate electrode 3151 . The channel 4137 of the fourth transistor T4 may be positioned below the gate electrode 4151 to overlap with the gate electrode 4151 . The first region 4136 and the second region 4138 of the fourth transistor T4 may not overlap the gate electrode 4151 . The upper boost electrode 3138t may not overlap the third gate conductive layer. A transistor including an oxide semiconductor layer may have characteristics of an n-type transistor.

Referring to FIGS. 13 and 21 , an additional organic film pattern (VIA Pattern) is formed on the third gate insulating layer 143 and overlaps the photosensor region OPS in plan view.

The additional organic layer pattern (VIA Pattern) is positioned between the third gate conductive layer and, in the embodiment of FIG. 13 , between the upper second scan line 152b and the upper initialization control line 153b in the second direction DR2 ) may have a structure extending to. In addition, the additional organic film pattern (VIA Pattern) may be in contact with the third gate conductive layer (upper second scan line 152b and upper initialization control line 153b) or spaced apart from it at a slight interval, and may be slightly flat. may overlap.

The additional organic layer pattern (VIA Pattern) may be located only in the photosensor area OPS and a portion adjacent to the photosensor area OPS. In addition, a plurality of additional organic film patterns (VIA Patterns) may be formed, and each may have an island structure and be separated from each other.

The additional organic film pattern (VIA Pattern) may be an organic insulating film and may include one or more materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin.

A planar shape of the additional organic layer pattern (VIA Pattern) may have the same planar shape as that of the photosensor area (OPS), and may have a pentagonal shape with reference to FIG. 13 . In addition, the additional organic layer pattern VIA pattern may overlap the entire photosensor area OPS on a plane and may be formed wider than the photosensor area OPS.

As shown in FIG. 21 , the additional organic layer pattern VIA Pattern is an organic layer pattern additionally formed to form the photosensor region OPS flat. The additional organic film pattern VIA pattern may be formed to have a flat optical sensor region OPS so that some light at the boundary is not refracted to other directions and transmittance is improved when light is transmitted therethrough.

Also, referring to FIGS. 20 and 21 , an additional organic film pattern (VIA Pattern) is located adjacent to the anode. Therefore, the photosensor region OPS is formed flat by the additional organic layer pattern VIA pattern, so that one end of the anode adjacent thereon can also be formed flat. When the anode is formed flat, light reflected from the anode does not spread asymmetrically, and as a result, color spreading (color separation) caused by the reflected light is reduced and display quality is improved.

Referring to FIG. 22 , on the third gate conductive layer including the gate electrode 3151 of the third transistor T3 and the gate electrode 4151 of the fourth transistor T4 and the additional organic film pattern (VIA Pattern), A second interlayer insulating layer 162 may be positioned. The second interlayer insulating layer 162 may have a single-layer or multi-layer structure. The second interlayer insulating layer 162 may include an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), and silicon nitride oxide (SiOxNy), and may include an organic material according to embodiments.

Referring to FIG. 14 , two types of openings OP1 and OP2 may be formed in the second interlayer insulating film 162 . The two types of openings OP1 and OP2 may be formed using different masks.

The opening OP1 is an opening in at least one of the second interlayer insulating film 162 , the third gate insulating film 143 , the first interlayer insulating film 161 , the second gate insulating film 142 , and the first gate insulating film 141 . By forming, it is possible to expose the first semiconductor layer 130, the first gate conductive layer, or the second gate conductive layer. Also, those located around the photosensor region OP among the openings OP1 may also be formed in the additional organic layer pattern VIA Pattern.

The opening OP2 forms an opening in the second interlayer insulating layer 162 and/or the third gate insulating layer 143 and may expose the oxide semiconductor layer or the third gate conductive layer.

One of the openings OP1 overlaps at least a portion of the gate electrode 1151 of the driving transistor T1, and is also formed on the third gate insulating layer 143, the first interlayer insulating layer 161, and the second gate insulating layer 142. It can be. In this case, one of the openings OP1 may overlap the opening 1152 of the first storage electrode 1153 and may be positioned inside the opening 1152 of the first storage electrode 1153 .

One of the openings OP2 may at least partially overlap the boost capacitor C _boost and may be further formed on the third gate insulating layer 143 .

Another one of the openings OP1 overlaps at least a portion of the second region 1133 of the driving transistor T1, and the third opening 3165 includes the third gate insulating layer 143 and the first interlayer insulating layer 161. , may be formed on the second gate insulating layer 142 and the first gate insulating layer 141 .

Another one of the openings OP2 overlaps at least a portion of the first region 3136 of the third transistor T3 and may be formed on the third gate insulating layer 143 .

Referring to FIGS. 15 and 16 , a first data conductive layer including a first connection electrode 1175 and a second connection electrode 3175 may be positioned on the second interlayer insulating layer 162 . FIG. 15 is a plan view of FIG. 16 with only the first data conductive layer, the additional organic film pattern (VIA Pattern), and openings OP1 and OP2 subtracted since it may be difficult to easily recognize the first data conductive layer. FIG. is a plan view showing all layers below the first data conductive layer.

The first connection electrode 1175 may overlap the gate electrode 1151 of the driving transistor T1. The first connection electrode 1175 may be connected to the gate electrode 1151 of the driving transistor T1 through the opening OP1 and the opening 1152 of the first storage electrode 1153 . The first connection electrode 1175 may overlap the boost capacitor C _boost . The first connection electrode 1175 may be connected to the upper boost electrode 3138t of the boost capacitor C _boost through the opening OP2 . Accordingly, the gate electrode 1151 of the driving transistor T1 and the upper boost electrode 3138t of the boost capacitor C _boost may be connected by the first connection electrode 1175 . At this time, the gate electrode 1151 of the driving transistor T1 is connected to the second region 3138 of the third transistor T3 and the second region 4138 of the fourth transistor T4 by the first connection electrode 1175. may also be connected.

The second connection electrode 3175 may overlap the second region 1133 of the driving transistor T1. The second connection electrode 3175 may be connected to the second region 1133 of the driving transistor T1 through the opening OP1. The second connection electrode 3175 may overlap the first region 3136 of the third transistor T3. The second connection electrode 3175 may be connected to the first region 3136 of the third transistor T3 through the opening OP2 . Accordingly, the second region 1133 of the driving transistor T1 and the first region 3136 of the third transistor T3 may be connected by the second connection electrode 3175 .

The first data conductive layer may further include a second initialization voltage line 128b. The second initialization voltage line 128 includes a wiring part 128b-1 extending in the vertical direction (second direction) and a first protruding part in the horizontal direction (first direction) from the wiring part 128b-1. It has an extension part 128b-2, and includes a second extension part 128b-3 bent in the vertical direction (second direction) from the first extension part 128b-2. Where the first extension 128b-2 and the second extension 128b-3 meet, it is electrically connected to the second initialization voltage line 128a positioned on the third gate conductive layer through the opening OP2. As a result, the second initialization voltage AVinit is transmitted in the horizontal direction (first direction) through the second initialization voltage line 128a positioned in the third gate conductive layer, and the first data conductive layer is transferred to the second initialization voltage line 128b. ) through which it is transmitted in the vertical direction (second direction).

An end of the second extension 128b - 3 is electrically connected to a portion 1137 of the first semiconductor layer 130 through the opening OP1 .

The first data conductive layer may further include connection parts 127CM and 171CM, an anode connection member ACM1, and an extension part FL-SD1.

The connection portion 127CM is connected to the first initialization voltage line 127 of the second gate conductive layer through the opening OP1, and to a portion 4136 of the second semiconductor layer (oxide semiconductor layer) through the opening OP2. The first initialization voltage Vinit connected to and flowing through the first initialization voltage line 127 is transmitted to the fourth transistor T4 of the oxide semiconductor layer.

The connection portion 171CM is electrically connected to a portion 1137 of the first semiconductor layer 130, that is, the second transistor T2, through the opening OP1, and the opening overlaps the connection portion 171CM on a plane. (OP1) is also formed on the additional organic film pattern (VIA Pattern).

The anode connecting member ACM1 is electrically connected to a portion 1136 of the first semiconductor layer 130, that is, the sixth transistor T6, through the opening OP1.

The expansion part FL-SD1 is formed wide to flatten the anode located on the upper part. In addition, the extension FL-SD1 is connected to a portion 1135 of the first semiconductor layer 130, that is, the fifth transistor T5, through the opening OP1, and is connected to the first retainer through the opening OP1. It is also electrically connected to the electrode 1153.

The first data conductive layer SD1 may include a metal or metal alloy such as aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), or the like, and may be composed of a single layer or multiple layers. there is.

Referring to FIG. 22 , a first organic layer 181 may be positioned on the first data conductive layer including the first connection electrode 1175 and the second connection electrode 3175 . The first organic layer 181 may be an organic insulating layer including an organic material, and the organic material includes at least one material selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin. can do.

Referring to FIGS. 17 , 18 , and 22 , the lower organic layer opening OP3 is positioned in the first organic layer 181 . A second data conductive layer including a data line 171 , a driving voltage line 172 , and an anode connection member ACM2 may be positioned on the first organic layer 181 . A second organic layer 182 and a third organic layer 183 are positioned on the second data conductive layer, and an opening OP4 for anode connection is formed in the second organic layer 182 and the third organic layer 183. is formed The anode connection member ACM2 is electrically connected to the anode through the anode connection opening OP4. FIG. 20 is a plan view of FIG. 21 with only the second data conductive layer, additional organic film pattern (VIA Pattern), and openings OP3 and OP4 subtracted since it may be difficult to easily recognize the second data conductive layer. FIG. is a plan view showing the second data conductive layer and all layers around it.

20 and 21 , the lower organic film opening OP3 overlaps the connecting portion 171CM, the anode connecting member ACM1, and the expansion portion FL-SD1 positioned on the first data conductive layer to expose them, respectively. let it

The second data conductive layer may include a data line 171 , a driving voltage line 172 , and an anode connection member ACM2 .

The data line 171 and the driving voltage line 172 may extend substantially in a vertical direction (second direction). The data line 171 is connected to the connection part 171CM of the first data conductive layer through the lower organic film opening OP3 and is connected to the second transistor T2 through this. In this embodiment, at least one of the openings (opening OP1) formed to electrically connect the second transistor T2 to the data line 171 may also be formed in the additional organic layer pattern VIA Pattern. The driving voltage line 172 is electrically connected to the fifth transistor T5 and the first storage electrode 1153 through the lower organic film opening OP3 and the extension FL-SD1 of the first data conductive layer. . The anode connecting member ACM2 is electrically connected to the anode connecting member ACM1 of the first data conductive layer through the opening OP3 and is electrically connected to the sixth transistor T6.

Referring to FIG. 17 , the driving voltage line 172 further includes an extension portion FL-SD2 and a protruding wiring portion 172-e, and has a structure not formed in a portion where the anode connecting member ACM2 is formed. have

The expansion part FL-SD2 is formed wide to flatten the anode located on the upper part.

Meanwhile, two protruding wiring parts 172-e of the driving voltage line 172 are also formed on both sides of the two data lines 171 to form an anode positioned thereon flat, resulting in a total of four wiring structures ( 171 and 172-e) have a structure to be located under the anode.

Structure of the lower portion of the anode as described above (first data conductive layer expansion part (FL-SD1) and wiring part 128b-1, and second data conductive layer expansion part (FL-SD2), data line 171 ), and the wiring portion 172-e) and the organic layers 181, 182, and 183, the anode has a planarization characteristic. In addition, in this embodiment, the photosensor region OPS is formed flat by using the additional organic film pattern VIA pattern so that the end of the adjacent anode is also formed flat without bending.

In this embodiment, the extension part FL-SD1 and the extension part FL-SD2 are electrically connected to the driving voltage line 172 to transmit the driving voltage ELVDD.

The second data conductive layer SD2 may include a metal or metal alloy such as aluminum (Al), copper (Cu), molybdenum (Mo), or titanium (Ti), and may be composed of a single layer or multiple layers. .

Referring to FIG. 22 , a second organic layer 182 and a third organic layer 183 are positioned on the second data conductive layer. The second organic layer 182 and the third organic layer 183 may be organic insulating layers, and may include at least one material selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin. can Depending on embodiments, the third organic layer 183 may be omitted.

An anode connection opening OP4 is formed in the second organic layer 182 and the third organic layer 183 , through which the anode and the anode connecting member ACM2 are electrically connected.

Referring to FIG. 19 , an anode is formed on the third organic layer 183 . The anode may further include an extension portion Anode-e to receive current from the pixel circuit through the anode connection opening OP4.

19 and 22 , a black pixel defining layer 380 is positioned on the anode, and an opening OP of the black pixel defining layer 380 overlaps the anode. The extension portion Anode-e of the anode is not exposed by the opening OP of the black pixel defining layer 380 and has a structure overlapping the black pixel defining layer 380 on a plane. As a result, the opening OP4 for anode connection also has a structure overlapping the black pixel defining layer 380 on a plane.

A planar structure in which the above structure is entirely stacked is shown in FIG. 20 .

Referring to FIG. 20 , an additional organic film pattern (VIA Pattern) is formed in an area overlapping the photosensor area (OPS) in plan view. The photosensor region OPS is formed flat by the additional organic film pattern (VIA Pattern), which will be described in detail with reference to FIG. 21 .

The optical sensor region OPS flattened by the additional organic film pattern (VIA Pattern) has a feature of forming a flat end of an anode located around it without being bent. As a result, light reflected from the anode can be prevented from being asymmetrically reflected.

Since the opening OP4 for anode connection does not overlap the opening OP of the black pixel defining layer 380 and the opening OPBM of the light blocking member 220 in plan view, the black pixel defining layer 380 and the light blocking member are formed in plan view. It can be seen that the structure overlaps with (220).

In addition, some of the lower organic layer openings OP3 (first lower organic layer openings) overlap at least partially in plan with the opening OPBM of the light blocking member 220, and the remaining lower organic layer openings OP3, that is, the second The lower organic layer opening overlaps the light blocking member 220 on a plane. Meanwhile, all of the lower organic layer openings OP3 overlap the black pixel defining layer 380 in plan view.

In addition, in the present embodiment, at least one of the anodes is formed by the extension part FL-SD1 of the first data conductive layer and the extension part FL-SD2 of the second data conductive layer located below the anode. A portion of the black pixel defining layer 380 exposed through the opening OP may be formed flat.

External light is not asymmetrically reflected and color spreading (color separation) does not occur due to the above-described positional relationship between the anode and the opening OP4 for connecting the anode below the anode.

Hereinafter, the cross-sectional structure of the photosensor region OPS planarized by the additional organic film pattern (VIA Pattern) will be described first through FIG. 21 .

21 is a cross-sectional view of an additional organic layer pattern and its surroundings in a light emitting display device according to an exemplary embodiment.

In the cross-sectional structure of FIG. 21, the structure is as follows, focusing on the additional organic film pattern (VIA Pattern).

An additional organic film pattern (VIA Pattern) is formed on the third gate insulating film 143 and between the third gate conductive layer (in the embodiment of FIG. 13, the upper second scan line 152b and the upper initialization control line 153b). is formed A portion where the additional organic layer pattern (VIA Pattern) is formed may correspond to the photosensor area OPS.

In FIG. 21 , the additional organic film pattern (VIA Pattern) is shown as being in contact with the third gate conductive layer (GAT3), but depending on the embodiment, it is separated from the third gate conductive layer (GAT3) at a slight interval or partially removed from the third gate conductive layer (GAT3). It may overlap with the 3 gate conductive layer (GAT3).

Since the second interlayer insulating layer 162 positioned above the additional organic layer pattern (VIA Pattern) is formed of an inorganic insulating layer, it has a lower level difference. However, referring to FIG. 21 , the second interlayer insulating layer 162 is planarized by the additional organic layer pattern (VIA Pattern) and is formed in a structure having no step in the photosensor region OPS. As a result, the steps of the optical sensor region OPS are eliminated as a whole, and the end of the anode adjacent to the optical sensor region OPS is also formed flat without inclination.

Before the additional organic film pattern (VIA Pattern) is formed, the step of the second interlayer insulating film 162 formed in the photosensor area OPS was 0.53 μm, and the step of the third organic film 183 was 40 nm. A gap has occurred.

However, the level difference is reduced by forming an additional organic film pattern (VIA Pattern), and the level of the level difference of the second interlayer insulating film 162 and the insulating film positioned thereon is adjusted by adjusting the thickness of the additional organic film pattern (VIA Pattern). can In the case of forming by optimizing the additional organic film pattern (VIA Pattern), steps formed in the second interlayer insulating film 162, the first organic film 181, the second organic film 182, and the third organic film 183 may not form. In this case, when the thickness of the additional organic film pattern (VIA Pattern) has a value greater than 0 and less than or equal to 1.06 μm, the step difference may be improved compared to the conventional step difference. In the case of forming an additional organic film pattern (VIA Pattern) with a thickness of 0.4 μm or more and 0.6 μm or less, an upper insulating film (two-layer insulating film 162, a first organic film 181, a second organic film 182, and The level difference of the third organic layer 183 may be almost eliminated, and the level difference may not be formed in the third organic layer 183 positioned at the top.

In the above, the planar structure and cross-sectional structure of the optical sensor area (OPS) were examined. Hereinafter, the entire cross-sectional structure of the light emitting display device will be described with reference to FIG. 22 .

22 is a cross-sectional view of a light emitting display device according to an exemplary embodiment.

22 shows up to the upper panel layer, and the photosensor area OPS is also shown up to the upper panel layer.

First, a detailed stacked structure of pixels in the display area DA will be described through FIG. 22 . Here, the display area DA may have a stacked structure of pixels positioned in the main display area D1 (also referred to as a first display area) and the component area D2 (also referred to as a second display area). In addition, in the embodiment of FIG. 22 , the pixel circuit unit means a configuration located below the second organic layer 182 and the third organic layer 183, and the light emitting diode is above the third organic layer 183. It may refer to some of components located under the encapsulation layer 400 . In addition, up to the encapsulation layer 400 is referred to as a lower panel layer, and a layer formed on the encapsulation layer 400 is referred to as an upper panel layer.

A brief look at the stacked structure of the display area DA of FIG. 22 is as follows.

A metal layer BML is positioned on the substrate 110 , and the metal layer BML may be positioned in a region overlapping a channel of the first semiconductor layer ACT1 . A buffer layer 111 covering the metal layer BML is positioned, and a first semiconductor layer ACT1 is positioned on the buffer layer 111 . The first semiconductor layer ACT1 includes a channel region and a first region and a second region positioned on both sides of the channel region.

The first gate insulating layer 141 may cover the first semiconductor layer ACT1 or may be positioned to overlap only the channel region of the first semiconductor layer ACT1. A first gate conductive layer GAT1 is positioned on the first gate insulating layer 141 , and the first gate conductive layer GAT1 includes a gate electrode of a transistor LTPS TFT including a silicon semiconductor. A region of the first semiconductor layer ACT1 overlapping the gate electrode on a plane may be a channel region. Also, the gate electrode may serve as one electrode of the storage capacitor.

The first gate conductive layer GAT1 is covered with the second gate insulating layer 142 , and the second gate conductive layer GAT2 is positioned on the second gate insulating layer 142 . The second gate conductive layer GAT2 may include a first storage electrode overlapping the gate electrode and constituting a storage capacitor, and a lower shielding layer for an oxide semiconductor transistor positioned below the oxide semiconductor layer ACT2.

The second gate conductive layer GAT2 is covered by the first interlayer insulating film 161 , and an oxide semiconductor layer ACT2 is positioned on the first interlayer insulating film 161 , and the oxide semiconductor layer ACT2 covers the channel region and the channel region. It includes a first region and a second region located on both sides of the channel region.

The oxide semiconductor layer ACT2 is covered by the third gate insulating layer 143 , and the third gate conductive layer GAT3 is positioned on the third gate insulating layer 143 . The third gate conductive layer GAT3 may include a connecting member connected to the gate electrode of the oxide semiconductor transistor and the lower shielding layer for the oxide semiconductor transistor.

The third gate conductive layer GAT3 and the additional organic film pattern VIA Pattern are covered by the second interlayer insulating film 162, and the first data conductive layer SD1 is positioned on the second interlayer insulating film 162. . The first data conductive layer SD1 may serve as a connection member to provide voltage or current to the first semiconductor layer ACT1 and the oxide semiconductor layer ACT2 or transfer the voltage or current to other devices.

The first data conductive layer SD1 is covered by the first organic layer 181, and the second data conductive layer SD2 is positioned on the first organic layer 181. The second data conductive layer SD2 may be connected to the first data conductive layer SD1 through an opening. The second data conductive layer SD2 is covered by the second organic layer 182 and the third organic layer 183 .

An anode may be positioned on the third organic layer 183 and connected to the second data conductive layer SD2 through openings located in the second organic layer 182 and the third organic layer 183. has a structure that

On the anode, a black pixel defining layer 380 having an opening overlapping at least a portion of the anode (hereinafter referred to as an opening for exposing the anode) and covering another portion of the anode is positioned. The black pixel defining layer 380 may further include a light blocking material in addition to an organic insulating material.

A spacer 385 is formed on the black pixel defining layer 380 . The spacer 385 may be formed in a structure having a step difference. The spacer 385 includes a first part 385-1 having a high height and located in a narrow area and a second part 385 having a low height and located in a wide area. -2) may be included.

The light emitting layer EML is positioned within the opening of the black pixel defining layer 380 and above the anode. A functional layer FL is positioned on the spacer 385 and the exposed black pixel defining layer 380 , and the functional layer FL may be formed on the entire surface of the light emitting display panel DP. The functional layer FL may include an electron injection layer, an electron transport layer, a hole transport layer, and a hole injection layer, and the functional layer FL may be positioned above and below the light emitting layer EML. That is, a hole injection layer, a hole transport layer, a light emitting layer (EML), an electron transport layer, an electron injection layer, and a cathode are sequentially positioned on the anode so that the hole injection layer and the hole in the functional layer (FL) are sequentially formed. The transport layer may be positioned below the light emitting layer EML, and the electron transport layer and electron injection layer may be positioned above the light emitting layer EML.

The cathode may be formed of a light-transmitting electrode or a reflective electrode. The cathode may be integrally formed over the entire surface of the light emitting display panel DP except for the light transmission area.

An encapsulation layer 400 is positioned on the cathode. The encapsulation layer 400 includes at least one inorganic layer and at least one organic layer, and may have a triple layer structure including a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer. The encapsulation layer 400 may be for protecting the light emitting layer EML formed of an organic material from moisture or oxygen that may be introduced from the outside. Depending on the embodiment, the encapsulation layer 400 may include a structure in which an inorganic layer and an organic layer are sequentially stacked.

On the encapsulation layer 400, sensing insulating layers 501, 510, and 511 and two sensing electrodes 540 and 541 are positioned for touch sensing. A lower sensing insulating layer 501 is positioned on the encapsulation layer 400, a lower sensing electrode 541 is positioned thereon, an intermediate sensing insulating layer 510 is positioned thereon, and an upper sensing electrode 540 is positioned thereon. , the upper sensing insulating layer 511 is positioned thereon.

A light blocking member 220 and a color filter 230 are positioned on the upper sensing insulating layer 511 .

The light blocking member 220 may be positioned to overlap the sensing electrodes 540 and 541 on a plane, and may be positioned not to overlap the anode on a plane. This is to prevent the anode and the light emitting layer (EML) capable of displaying an image from being covered by the light blocking member 220 and the sensing electrodes 540 and 541 .

A color filter 230 is positioned on the sensing insulating layers 501 , 510 , and 511 and the light blocking member 220 . The color filter 230 includes a red color filter that transmits red light, a green color filter that transmits green light, and a blue color filter that transmits blue light. Each color filter 230 may be positioned to overlap the anode of the light emitting diode on a plane. Since the light emitted from the light emitting layer EML can be emitted while being changed to a corresponding color while passing through a color filter, all lights emitted from the light emitting layer EML may have the same color. However, in the light emitting layer EML, light of different colors may be emitted, and a displayed color may be enhanced by allowing light to pass through a color filter of the same color.

The light blocking member 220 may be positioned between each color filter 230 . According to embodiments, the color filter 230 may be replaced with a color conversion layer or may further include a color conversion layer. The color conversion layer may include quantum dots.

A planarization layer 550 covering the color filter 230 is positioned on the color filter 230 . The planarization layer 550 may be a transparent organic insulating layer. According to exemplary embodiments, a low refraction layer and an additional planarization layer may be further positioned on the planarization layer 550 to improve front visibility and light emission efficiency of the display panel. Light may be emitted while being refracted to the front surface by the low refractive layer and the additional planarization layer having high refractive properties. In this case, the low refractive layer and the additional planarization layer may be positioned directly on the color filter 230 while the planarization layer 550 is omitted, depending on the embodiment.

In this embodiment, the polarizer is not included on the planarization layer 550 . That is, the polarizing plate may play a role of preventing display quality from deteriorating while a user recognizes external light as it is incident and reflected from an anode or the like. However, in this embodiment, the side surface of the anode is covered with the black pixel-defining film 380 to reduce the degree of reflection from the anode, and the light blocking member 220 is also formed to reduce the degree of incident light to the reflection. It already includes a structure that prevents deterioration of display quality due to Therefore, it is not necessary to separately form the polarizing plate on the front surface of the light emitting display panel DP.

Meanwhile, in FIG. 22, a cross-sectional structure of the optical sensor area OPS is also shown, and unlike FIG. 21, a stacked structure of an upper display panel and an anode or more of the optical sensor area OPS is also shown in FIG. 22.

The optical sensor region OPS is composed of only a transparent layer so that light can pass therethrough, and no conductive layer or semiconductor layer is located, and the black pixel defining layer 380, the light blocking member 220, and the color filter 230 An opening (hereinafter referred to as an additional opening; see FIG. 23 ) may be formed at a position corresponding to the optical sensor area OPS to have a structure that does not block light. Also, unlike the display area DA, the photosensor area OPS may further include an additional organic layer pattern VIA pattern. The photosensor region OPS is formed flat by the additional organic film pattern (VIA Pattern), and the insulating film (second interlayer insulating film 162, first organic film 181) positioned on the additional organic film pattern (VIA Pattern). ), the steps of the second organic layer 182 and the third organic layer 183 may be removed. As a result, the anode positioned on the third organic layer 183 is also formed flat.

Specifically, based on FIG. 22 , a stacked structure of the photosensor area OPS according to an exemplary embodiment is as follows.

A buffer layer 111 as an inorganic insulating film is positioned on the substrate 110 , and a first gate insulating film 141 and a second gate insulating film 142 as inorganic insulating films are sequentially positioned thereon. In addition, on the second gate insulating layer 142 , a first interlayer insulating layer 161 , which is an inorganic insulating layer, and a third gate insulating layer 143 are sequentially stacked.

An additional organic layer pattern (VIA Pattern) may be positioned on the third gate insulating layer 143 , and the additional organic layer pattern (VIA Pattern) may be positioned only in and around the photosensor area OPS. A second interlayer insulating layer 162 , a first organic layer 181 , a second organic layer 182 , and a third organic layer 183 are sequentially stacked on the additional organic layer pattern VIA Pattern. A functional layer FL may be positioned on the third organic layer 183 , and a cathode may be positioned thereon.

An encapsulation layer 400 is positioned on the cathode, and sensing insulating layers 501, 510, and 511 are sequentially positioned thereon. The encapsulation layer 400 may have a triple layer structure including a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer. In addition, all of the sensing insulating layers 501, 510, and 511 may be inorganic insulating layers. A planarization layer 550 may be positioned on the sensing insulating layers 501 , 510 , and 511 .

In the photosensor region OPS as described above, the metal layer BML, the first semiconductor layer ACT1, the first gate conductive layer GAT1, the second gate conductive layer GAT2, the oxide semiconductor layer ACT2, the third The gate conductive layer GAT3, the first data conductive layer SD1, the second data conductive layer SD2, and the anode are not located. Also, the light emitting layer EML and the sensing electrodes 540 and 541 are not formed.

Hereinafter, a planar structure including an upper panel layer of the photosensor area OPS according to an exemplary embodiment will be reviewed through FIG. 23 .

23 is a top plan view of a portion of an upper panel layer of a light emitting display device according to an exemplary embodiment.

In FIG. 23 , to clearly show the relationship between the upper panel layer and the lower panel layer, the opening OP of the black pixel defining layer 380 and the first portion 385-1 of the spacer 385 located in the lower panel layer ) is also shown additionally.

The light blocking member 220 includes an opening OPBM, and the opening OPBM may be wider while overlapping the opening OP of the black pixel defining layer 380 in plan view. In addition, in FIG. 8 , to clearly show the relationship between the upper panel layer and the lower panel layer, the opening OP of the black pixel defining layer 380 and the first part 385 of the spacer 385 located in the lower panel layer -1) is also shown additionally.

Color filters 230R, 230G, and 230B are positioned on the light blocking member 220 . One color of the color filters 230R, 230G, and 230B may have an opening and be entirely disposed, and the other two colors may fill the opening. Referring to FIG. 8 , an embodiment in which a red color filter 230R has openings OPCrg and OPCrb and is entirely disposed, and green and blue color filters 230G and 230B fill the openings OPCrg and OPCrb, respectively. In FIG. 23, color filters of each color are shown with different hatching lines so as to be easily distinguished.

The red color filter 230R overlaps the light blocking member 220, and among the openings OPBM of the light blocking member 220, the red color filter 230R is filled in the opening OPBM for the red pixel, so that the opening for the red pixel is filled in the planar view. (OPBM) and the red color filter 230R have an overlapping structure. That is, in the embodiment of FIG. 23 , the red color filter 230R further includes an overlapping portion 230R-1 overlapping the light blocking member 220 in addition to the main portion located in the opening OPBM of the light blocking member 220. . Meanwhile, in the red color filter 230R, openings OPCrg and OPCrb are positioned at positions corresponding to the green pixel opening OPBM and the blue pixel opening OPBM, respectively. The openings OPCrg and OPCrb of the red color filter 230R are wider than the opening OPBM of the light blocking member 220 .

The green color filter 230G is formed only at a position overlapping the green pixel opening OPBM of the light blocking member 220 and the green pixel opening OPCrg of the red color filter 230R. The green color filter 230G overlaps the green pixel opening OPBM and the green pixel opening OPCrg on a plane and may be wider.

The blue color filter 230B is formed only at a position overlapping the blue pixel opening OPBM of the light blocking member 220 and the blue pixel opening OPCrb of the red color filter 230R. The blue color filter 230B may overlap the blue pixel opening OPBM and the blue pixel opening OPCrb in plan view and may be wider.

Referring to FIG. 23 , the position of the first portion 385-1 of the spacer 385 is also shown, and overlaps with the overlapping portion 230R-1 of the light blocking member 220 and the red color filter 230R on a plane. It can be formed in a location where However, in the first portion 385 - 1 of the spacer 385 , the black pixel defining layer 380 is formed on the third direction DR3 , but the light blocking member 220 or the red color filter 230R is overlapped. It is located lower than the portion 230R-1 in the third direction DR3.

Additionally, an additional opening OP-1 is formed in the black pixel defining layer 380 corresponding to the photosensor region OPS, an additional opening OPBM-1 is formed in the light blocking member 220, and a red color filter ( 230R) is also formed with an additional opening (OPC-1). The additional opening OPC- 1 formed in the red color filter 230R is formed to extend from the green pixel opening OPCrg and the blue pixel opening OPCrb. That is, in the red color filter 230R, the green pixel opening OPCrg, the blue pixel opening OPCrb, and the additional opening OPC-1 are formed as one opening. However, depending on embodiments, each opening of the red color filter 230R may be separately formed.

Due to the additional opening (OPBM-1) of the light blocking member 220 and the additional opening (OPC-1) of the red color filter 230R, there is no light blocking structure in the light sensor area (OPS) of the upper panel layer. . In addition, as shown in FIG. 22, the lower panel layer is formed so that neither the conductive layer nor the semiconductor layer is located in the photosensor region OPS. As a result, even when an optical sensor (including an infrared ray sensor, etc.) is placed on the rear surface of the light emitting display panel DP, the front surface of the light emitting display panel DP can be sensed with light.

The position of the first portion 385-1 of the spacer 385 is also shown, and is formed at a position overlapping the light blocking member 220 and the overlapping portion 230R-1 of the red color filter 230R in plan view, It may not overlap with the optical sensor area OPS. However, in the first portion 385 - 1 of the spacer 385 , the black pixel defining layer 380 is formed on the third direction DR3 , but the light blocking member 220 or the red color filter 230R is overlapped. It is located lower than the portion 230R-1 in the third direction DR3.

Additionally, additional openings are formed in the black pixel defining layer 380, the light blocking member 220, and the color filter 230 in the photosensor region OPS so that the black pixel defining layer 380, the light blocking member 220, and the color filter 230 are formed. Filter 230 is not formed.

As described above, by the additional organic film pattern (VIA Pattern) located in the photosensor area (OPS), the insulating film (second interlayer insulating film 162, first organic film 181) positioned on top of the additional organic film pattern (VIA Pattern) ), the second organic layer 182, and the third organic layer 183 are removed, and an anode positioned on the third organic layer 183 is also formed flat. As a result, light is not reflected asymmetrically at the anode.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the present invention defined in the following claims are also included in the scope of the present invention. that fall within the scope of the right.

DP: display panel OPS: optical sensor area
DA: Display area VIA Pattern: Additional organic film pattern
110: substrate 111: buffer layer
141, 142, 143: gate insulating film 161, 162: interlayer insulating film
180, 181, 182, 183: organic film 400: encapsulation layer
401, 403: inorganic encapsulation layer 402: organic encapsulation layer
501, 510, 511: sensing insulating layer 550: planarization layer
127, 128, 151, 152, 153, 155, 171, 172, 741: Wiring
385, 385-1, 385-2: spacer BML: metal layer
EL: light emitting layer FL: functional layer
OP4: opening for anode connection OP3: lower organic film opening
380: black pixel defining film OP: opening of black pixel defining film
220: light blocking member OPBM: opening of light blocking member
230R, 230G, 230B: Color filter 230R-m: Main part
230R-1: overlap OPC: opening of color filter
540, 541: sensing electrode OPBM-1: additional opening of light blocking member
OP-1: Additional opening of the black pixel defining film
OPC-1: additional opening of color filter FL-SD1, FL-SD2: extension

Claims (20)

a substrate including an optical sensor area positioned in the display area;
In the display area of the substrate
a first semiconductor layer positioned on the substrate;
a first gate insulating layer positioned on the first semiconductor layer;
a first gate conductive layer positioned on the first gate insulating layer;
a second gate insulating layer positioned on the first gate conductive layer;
a second gate conductive layer positioned on the second gate insulating layer;
a first interlayer insulating film positioned on the second gate conductive layer;
an oxide semiconductor layer positioned on the first interlayer insulating film;
a third gate insulating layer positioned on the oxide semiconductor layer;
a third gate conductive layer positioned on the third gate insulating layer; and
A second interlayer insulating film positioned on the third gate conductive layer;
In the optical sensor area
The first gate insulating film, the second gate insulating film, the first interlayer insulating film, the third gate insulating film, the additional organic film pattern, and the second interlayer insulating film are sequentially stacked on the substrate,
The additional organic layer pattern overlaps the photosensor area on a plane and is located only in the photosensor area and a portion adjacent thereto. In paragraph 1,
The additional organic layer pattern is an organic insulating layer. In paragraph 2,
The additional organic layer pattern is formed in plurality,
The light emitting display device of claim 1 , wherein the additional organic layers each have an island structure and are separated from each other. In paragraph 3,
The additional organic layer pattern has a pentagonal shape. In paragraph 3,
The display area further includes a metal layer between the substrate and the first semiconductor layer and a buffer layer positioned on the metal layer,
In the photosensor region, the buffer layer is positioned between the substrate and the first gate insulating layer. In paragraph 3,
The display area is
a first data conductive layer positioned on the second interlayer insulating layer;
a first organic layer on the first data conductive layer;
a second data conductive layer positioned on the first organic layer;
a second organic layer and a third organic layer positioned on the second data conductive layer and sequentially formed; and
Further comprising an anode positioned on the third organic layer,
The light sensor area is
The light emitting display device wherein the first organic layer, the second organic layer, and the third organic layer are sequentially stacked on the second interlayer insulating layer. In paragraph 6,
The display area is
a black pixel defining layer having an opening for exposing the anode to expose the anode;
a light emitting layer within the opening for exposing the anode and positioned over the anode;
a functional layer and a cathode sequentially positioned on the black pixel-defining layer and the anode;
an encapsulation layer covering the cathode;
a light blocking member positioned on the encapsulation layer and having an opening for a color filter; and
a color filter filling an opening for the color filter of the light blocking member;
The light sensor area is
The light emitting display device wherein the functional layer, the cathode, and the encapsulation layer are sequentially stacked on the third organic layer. In paragraph 7,
The color filter includes a first color filter, a second color filter, and a third color filter,
The first color filter includes a color filter opening and is divided into an overlapping portion connecting a main portion and an adjacent main portion;
The second color filter and the third color filter are respectively positioned in the color filter opening of the first color filter. In paragraph 8,
The light emitting display device of claim 1 , wherein the black pixel defining layer, the light blocking member, and the color filter each have the additional opening overlapping the photosensor region on a plane. In paragraph 9,
The display area is
a sensing electrode positioned between the encapsulation layer and the light blocking member, overlapping the light blocking member in a plane view, and covered by the light blocking member; and
It is located between the encapsulation layer and the light blocking member, and further comprises a sensing insulating layer located above and below the sensing electrode,
The light emitting display device of claim 1 , wherein the sensing insulating layer is further stacked on the encapsulation layer in the photosensor area. In paragraph 10,
The first data conductive layer includes a first extension,
The second data conductive layer includes a second extension part,
The light emitting display device of claim 1 , wherein the first extension part and the second extension part overlap the anode on a plane, respectively. In paragraph 10,
The display area further includes a spacer positioned between the black pixel defining layer and the cathode;
The light emitting display device of claim 1 , wherein the spacer includes a stepped structure including a first portion and a second portion having a height lower than the first portion and integrally formed with the first portion. It has an optical sensor area located in the display area,
In the photosensor region, a buffer layer, a first gate insulating film, a second gate insulating film, a first interlayer insulating film, a third gate insulating film, an additional organic film pattern, a second interlayer insulating film, a first organic film, and a second organic film are sequentially formed on the substrate. is layered with
The additional organic layer pattern overlaps the photosensor area on a plane and is located only in the photosensor area and a portion adjacent thereto. In paragraph 13,
The additional organic layer pattern is an organic insulating layer. In paragraph 14,
The additional organic layer pattern is formed in plurality,
The light emitting display device of claim 1 , wherein the additional organic layers each have an island structure and are separated from each other. In paragraph 15,
The additional organic layer pattern has a pentagonal shape. In clause 16,
In the photosensor region, a third organic layer, a functional layer, a cathode, an encapsulation layer, and a sensing insulating layer are sequentially stacked on the second organic layer. In paragraph 17,
The display area is
a metal layer positioned over the substrate;
the buffer layer positioned on the metal layer;
a first semiconductor layer positioned on the buffer layer;
the first gate insulating layer positioned on the first semiconductor layer;
a first gate conductive layer positioned on the first gate insulating layer;
the second gate insulating layer positioned on the first gate conductive layer;
a second gate conductive layer positioned on the second gate insulating layer;
the first interlayer insulating film positioned on the second gate conductive layer;
an oxide semiconductor layer positioned on the first interlayer insulating film;
the third gate insulating layer positioned on the oxide semiconductor layer;
a third gate conductive layer positioned on the third gate insulating layer;
the second interlayer insulating film positioned on the third gate conductive layer;
a first data conductive layer positioned on the second interlayer insulating layer;
the first organic layer positioned on the first data conductive layer;
a second data conductive layer positioned on the first organic layer;
the second organic layer and the third organic layer positioned on the second data conductive layer and sequentially formed;
an anode positioned on the third organic layer;
a black pixel defining layer having an opening for exposing the anode to expose the anode;
a light emitting layer within the opening for exposing the anode and positioned over the anode;
the functional layer and the cathode sequentially positioned on the black pixel-defining layer and the anode;
an encapsulation layer covering the cathode;
a light blocking member positioned on the encapsulation layer and having an opening for a color filter;
a color filter filling an opening for the color filter of the light blocking member;
a sensing electrode disposed between the encapsulation layer and the light blocking member, overlapping the light blocking member in a plane view, and covered by the light blocking member; and
A light emitting display device comprising a sensing insulating layer positioned between the encapsulation layer and the light blocking member and positioned above and below the sensing electrode. In paragraph 18,
The color filter includes a first color filter, a second color filter, and a third color filter,
The first color filter includes a color filter opening and is divided into an overlapping portion connecting a main portion and an adjacent main portion;
The second color filter and the third color filter are respectively positioned in the color filter opening of the first color filter. In paragraph 19,
The light emitting display device of claim 1 , wherein the black pixel defining layer, the light blocking member, and the color filter each have the additional opening overlapping the photosensor region on a plane.

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