KR20220170671A - Storage device and operating method thereof - Google Patents

Abstract

This technology relates to electronic devices. A storage device with improved operation speed according to the present technology, comprising: a memory device connected to a plurality of word lines and including a plurality of memory blocks included in a super block; and a sudden power-off management unit which controls the memory device to perform a read operation on one of the plurality of word lines in any one of the plurality of memory blocks when sudden power-off occurs, determines one word line area based on data read from any one of the first word line area located above the one word line and the second word line area located below the one word line, controls the memory device to perform a read operation in parallel on a plurality of selected word lines among the word lines included in the determined word line area in the remaining memory blocks excluding the one memory block among the plurality of memory blocks, and detects the first erase page located at the boundary between the program page and the erase page based on the data read from the plurality of selected word lines. Accordingly, the present invention provides a storage device with improved operation speed and a method of operating the same.

Description

Storage device and its operating method {STORAGE DEVICE AND OPERATING METHOD THEREOF}

The present invention relates to an electronic device, and more particularly, to a storage device and an operating method thereof.

The storage device is a device that stores data under the control of a host device such as a computer or smart phone. The storage device may include a memory device that stores data and a memory controller that controls the memory device. Memory devices may be classified into volatile memory devices and non-volatile memory devices.

A volatile memory device may be a memory device that stores data only while power is supplied and the stored data disappears when power is cut off. Volatile memory devices may include static random access memory (SRAM), dynamic random access memory (DRAM), and the like.

Non-volatile memory devices are memory devices that do not lose data even when power is cut off, and include ROM (Read Only Memory; ROM), PROM (Programmable ROM), EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable and Programmable ROM), and flash. Flash memory, etc.

An embodiment of the present invention provides a storage device with improved operating speed and an operating method thereof.

A storage device according to an embodiment of the present invention includes a memory device including a plurality of memory blocks connected to a plurality of word lines and included in a super block, and when sudden power-off occurs, one of the plurality of memory blocks Controls the memory device to perform a read operation on any one word line among the plurality of word lines in one memory block, and controls a first word line region located above the one word line and one of the one word line region. One word line area is determined based on data read from any one of the second word line areas located below the word line of the , and the one of the plurality of memory blocks is selected. Controls the memory device to parallelly perform a read operation on a plurality of selected word lines among word lines included in the determined word line area in the remaining memory blocks, and reads from the plurality of selected word lines and a sudden power-off management unit that detects an erase page located at a boundary between a program page and an erase page based on the generated data.

According to an embodiment of the present invention, a method of operating a storage device for controlling an operation of a super block including a plurality of memory blocks connected to a plurality of word lines includes detecting sudden power-off, the plurality of memory blocks performing a read operation on a first word line located at an intermediate point among the plurality of word lines in a first memory block in which data is first programmed, a first word line area located above the first word line, and determining a word line area of a second word line area located below the first word line based on data read from the first word line; the first memory block among the plurality of memory blocks; parallelly performing a read operation on a plurality of selected word lines among word lines included in the determined word line area in second memory blocks except for and detecting the first erase page located at the boundary between the program page and the erase page based on the result.

According to the present technology, a storage device having an improved operating speed and an operating method thereof are provided.

1 is a diagram for explaining a storage device according to an exemplary embodiment of the present invention.
FIG. 2 is a diagram for explaining the memory device of FIG. 1 .
FIG. 3 is a diagram illustrating an example of the memory cell array of FIG. 2 .
FIG. 4 is a circuit diagram showing one memory block BLKa among the memory blocks BLK1 to BLKz of FIG. 3 .
FIG. 5 is a circuit diagram showing another embodiment of one memory block BLKb among the memory blocks BLK1 to BLKz of FIG. 3 .
FIG. 6 is a diagram illustrating a connection relationship between the memory controller of FIG. 1 and a plurality of memory devices by way of example.
7 is a diagram for explaining the concept of a super block, super page or stripe.
FIG. 8 is a diagram for explaining another embodiment of the super block of FIG. 7 .
9 is a diagram for explaining an example of an operation of determining an initial erase page according to an embodiment of the present invention.
10 is a diagram for explaining another example of an operation of determining an initial erase page according to an embodiment of the present invention.
11 is a diagram for explaining the configuration of a data set according to an embodiment of the present invention.
12 is a diagram for explaining a program state of memory cells according to an exemplary embodiment.
13 is a diagram for explaining an area in which page information is stored in a memory block according to an embodiment of the present invention.
14 is a diagram for explaining data values corresponding to a plurality of program states included in page information according to an embodiment of the present invention.
15 is a diagram for explaining page information values according to page states according to an embodiment of the present invention.
16 is a flowchart illustrating a method of operating a storage device according to an exemplary embodiment.
17 is a diagram for explaining an operation of determining an initial erase page according to an embodiment of the present invention.
18 is a diagram for describing a memory controller according to an exemplary embodiment.
19 is a block diagram illustrating a memory card system to which a storage device according to an embodiment of the present invention is applied.
20 is a block diagram illustrating a solid state drive (SSD) system to which a storage device according to an embodiment of the present invention is applied.
21 is a block diagram illustrating a user system to which a storage device according to an embodiment of the present invention is applied.

Specific structural or functional descriptions of the embodiments according to the concept of the present invention disclosed in the present specification or application are only exemplified for the purpose of explaining the embodiment according to the concept of the present invention, and the implementation according to the concept of the present invention Examples may be embodied in many forms and should not be construed as limited to the embodiments described in this specification or application.

1 is a diagram for explaining a storage device according to an exemplary embodiment of the present invention.

Referring to FIG. 1 , a storage device 50 may include a memory device 100 and a memory controller 200 that controls operations of the memory device. The storage device 50 stores data under the control of the host 300, such as a mobile phone, smart phone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system. It may be a device that

The storage device 50 may be manufactured as one of various types of storage devices according to a host interface, which is a communication method with the host 300 . For example, the storage device 50 may include a multimedia card in the form of SSD, MMC, eMMC, RS-MMC, and micro-MMC, secure digital in the form of SD, mini-SD, and micro-SD. card, universal serial bus (USB) storage device, universal flash storage (UFS) device, personal computer memory card international association (PCMCIA) card-type storage device, PCI (peripheral component interconnection) card-type storage device, PCI-E ( It may be configured with any one of various types of storage devices such as a PCI express card type storage device, a CF (compact flash) card, a smart media card, a memory stick, and the like.

The storage device 50 may be manufactured in any one of various types of packages. For example, the storage device 50 may include package on package (POP), system in package (SIP), system on chip (SOC), multi-chip package (MCP), chip on board (COB), wafer- level fabricated package), wafer-level stack package (WSP), and the like.

The memory device 100 may store data. The memory device 100 operates in response to control of the memory controller 200 . The memory device 100 may include a memory cell array (not shown) including a plurality of memory cells that store data.

The memory cells are single-level cells (SLC) each storing one data bit, multi-level cells (MLC) storing two data bits, and triple-level cells storing three data bits. (Triple Level Cell; TLC) or Quad Level Cell (QLC) capable of storing four data bits.

A memory cell array (not shown) may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. One memory block may include a plurality of pages. In an embodiment, a page may be a unit for storing data in the memory device 100 or reading data stored in the memory device 100 . A memory block may be a unit for erasing data.

In an embodiment, the memory device 100 may include DDR Double Data Rate Synchronous Dynamic Random Access Memory (SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), and RDRAM. (Rambus Dynamic Random Access Memory), NAND flash memory, Vertical NAND, NOR flash memory, resistive random access memory (RRAM), phase change memory (phase-change random access memory: PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin transfer torque random access memory (STT-RAM) ) and so on. In this specification, for convenience of explanation, it is assumed that the memory device 100 is a NAND flash memory.

The memory device 100 is configured to receive a command CMD and an address ADDR from the memory controller 200 and access a region selected by the address in the memory cell array. The memory device 100 may perform an operation indicated by the command CMD for an area selected by the address ADDR. For example, the memory device 100 may perform a write operation (program operation), a read operation, and an erase operation. During the program operation, the memory device 100 will program data into an area selected by the address ADDR. During a read operation, the memory device 100 reads data from an area selected by the address ADDR. During an erase operation, the memory device 100 erases data stored in the area selected by the address ADDR.

Meanwhile, although one memory device 100 is illustrated in FIG. 1 , the storage device 50 may include a plurality of memory devices according to exemplary embodiments. A connection relationship between the plurality of memory devices and the memory controller 200 will be described with reference to FIG. 2 .

The memory controller 200 may control overall operations of the storage device 50 .

When power is applied to the storage device 50 , the memory controller 200 may execute firmware (FW). When the memory device 100 is a flash memory device, the firmware FW is a Host Interface Layer (HIL) that controls communication with the host 300, and the memory controller 200 controls communication between the host 300 and the memory device. A flash translation layer (FTL) controlling communication between the memory devices 100 and a flash interface layer (FIL) controlling communication with the memory device 100 may be included.

In an embodiment, the memory controller 200 receives data and a logical block address (LBA) from the host 300, and the logical block address is used as the number of memory cells in which data included in the memory device 100 is to be stored. It can be converted to a physical block address (PBA) representing an address. In this specification, the logical block address (LBA) and “logical address” or “logical address” may be used in the same meaning. In this specification, the physical block address (PBA) and “physical address” or “physical address” may be used interchangeably.

The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, or an erase operation according to a request of the host 300 . During a program operation, the memory controller 200 may provide a write command, a physical block address, and data to the memory device 100 . During a read operation, the memory controller 200 may provide a read command and a physical block address to the memory device 100 . During an erase operation, the memory controller 200 may provide an erase command and a physical block address to the memory device 100 .

In one embodiment, the memory controller 200 may be connected to the memory device 100 through a channel. For example, the memory controller 200 may control the memory device 100 to perform a program operation, a read operation, or an erase operation by providing a command and an address to the memory device 100 through a channel.

In an embodiment, the memory controller 200 may generate commands, addresses, and data on its own and transmit them to the memory device 100 regardless of a request from the host 300 . For example, the memory controller 200 provides commands, addresses, and commands for performing read operations and program operations involved in performing wear leveling, read reclaim, garbage collection, and the like. Data may be provided to the memory device 100 .

In an embodiment, the memory controller 200 may control at least two or more memory devices 100 . In this case, the memory controller 200 may control the memory devices 100 according to an interleaving method to improve operating performance. The interleaving method may be a method of controlling operations of at least two or more memory devices 100 to overlap.

The host 300 is USB (Universal Serial Bus), SATA (Serial AT Attachment), SAS (Serial Attached SCSI), HSIC (High Speed Interchip), SCSI (Small Computer System Interface), PCI (Peripheral Component Interconnection), PCIe ( PCI express), NVMe (NonVolatile Memory express), UFS (Universal Flash Storage), SD (Secure Digital), MMC (MultiMedia Card), eMMC (embedded MMC), DIMM (Dual In-line Memory Module), RDIMM (Registered DIMM ), LRDIMM (Load Reduced DIMM), etc., may communicate with the storage device 50 using at least one of various communication methods.

In one embodiment, the memory controller 200 may include a program operation control unit 210 and a sudden power off management unit 220 .

The program operation controller 210 may control the memory device 100 to perform a program operation in response to a write request from the host 300 .

In one embodiment, the program operation control unit 210 may generate program data by scrambling and decoding data received from the host 300 during program operation. In an embodiment, the memory controller 200 detects and corrects an error in data received from the memory device 100 using an error correcting code (ECC) during a read operation, and descrambles the read data. can create

Also, the program operation controller 210 may generate one or more data sets using program data and page information data. At this time, the page information data includes basic information (for example, SLC, MLC, TLC, etc. program method) of the page where the corresponding data set is to be stored, the number of erase/program cycles, and state data for determining the program status of the corresponding page. can include During a read operation, the memory device 100 reads page information data from a data set, and uses state data of the read page information data to determine whether a corresponding page is in a programmed state, an erased state, or a state in which an SPO has occurred during a program operation. You can check whether it is. In an embodiment, the state data may include data values respectively corresponding to a plurality of program states in which program data is programmed into memory cells included in a plurality of pages. In this case, data values respectively corresponding to the plurality of program states may include data values corresponding to program cell states of memory cells or data values corresponding to erase cell states of memory cells.

In one embodiment, the program operation controller 210 may control the memory device 100 to program at least one or more data sets into a plurality of pages included in a plurality of memory blocks.

When sudden power-off occurs, the sudden power-off management unit 220 may detect the occurrence of sudden power-off and perform a sudden power-off recovery operation.

At this time, the sudden power-off recovery operation determines to what page the program operation performed before the sudden power-off situation has been programmed, and the program operation of the memory device 100 performed before the sudden power-off occurs. It may be an operation to subsequently perform.

For example, sudden power-off in which power to the storage device 50 is suddenly cut off may occur while the memory device 100 is performing a program operation. When power is supplied again after a sudden power-off situation occurs, that is, when a power-on situation occurs, the sudden power-off management unit 220 may perform a sudden power-off recovery operation.

The sudden power-off management unit 220 may determine a page in which sudden power-off occurs while a program operation is being performed. To this end, the sudden power-off management unit 220 may determine the program state or erase state of each page included in the memory block. The sudden power-off management unit 220 may search for an initial erase page. The first erase page may be an erase page adjacent to a program page in which data is stored, among erase pages in which data is empty. The sudden power-off management unit 220 may perform a read operation on some of the pages included in the corresponding memory block in order to search for the first erased page.

In one embodiment, the sudden power off management unit 220 may control the memory device 100 to perform a read operation on a specific page included in a memory block. If data read as a result of the read operation includes program data, the corresponding page may be determined to be a program page. When data read as a result of the read operation includes only erase data, the corresponding page may be determined to be an erase page.

In an embodiment, when sudden power-off occurs, the sudden power-off management unit 220 performs a read operation on one word line among a plurality of word lines in one memory block among a plurality of memory blocks. The memory device 100 may be controlled. In this case, a plurality of memory blocks may be included in one super block. The super block will be described in detail with reference to FIGS. 7 and 8 to be described later. In an embodiment, one memory block may be a memory block in which data is first programmed among a plurality of memory blocks. Also, any one word line may be a word line positioned at an intermediate point among a plurality of word lines.

In an embodiment, the sudden power off management unit 220 may determine one word line area based on data read from any one word line of the first word line area and the second word line area. In this case, the first word line area may be an area located above any one word line. The first word line region may include word lines from a start word line corresponding to a page in which data is programmed first among a plurality of word lines to any one word line. Also, the second word line area may be an area located below any one word line. The second word line region may include word lines from a last word line corresponding to a page in which data is programmed last among a plurality of word lines to any one word line.

Also, the sudden power-off management unit 220 configures the memory device 100 to parallelly perform a read operation on a plurality of selected word lines in the remaining memory blocks except for any one of the plurality of memory blocks. You can control it. In this case, the plurality of selected word lines may be included in any one word line area determined based on data read from any one word line. For example, when it is determined that a page corresponding to one word line is an erase page based on data read from one word line, the sudden power off management unit 220 may select the first word line area. . In this case, the sudden power-off management unit 220 may determine a plurality of selected word lines among word lines included in the first word line area. Also, the sudden power off management unit 220 may control the memory device 100 to perform a read operation on the plurality of selected word lines included in the first word line area in the remaining memory blocks. As another example, the sudden power off management unit 220 may select the second word line area when it is determined that a page corresponding to one word line is a program page based on data read from one word line. In this case, the sudden power off management unit 220 may determine a plurality of selected word lines among word lines included in the second word line area. Also, the sudden power-off management unit 220 may control the memory device 100 to perform a read operation on the plurality of selected word lines included in the second word line area in the remaining memory blocks.

In an embodiment, the sudden power-off management unit 220 performs a read operation on different selected word lines among a plurality of selected word lines in each of the remaining memory blocks in parallel according to an interleaving technique. can control.

In an embodiment, the sudden power-off management unit 220 may control the memory device 100 to read page information data during a read operation on one word line and a read operation on a plurality of selected word lines. . For example, the memory device 100 may read page information data from a plurality of memory blocks using a half page sensing method.

Also, the sudden power-off manager 220 may detect the first erase page based on data read from a plurality of selected word lines.

In one embodiment, if the read page information data includes a data value corresponding to a program cell state for a plurality of program states, the sudden power off management unit 220 may select a page corresponding to a word line from which the page information data is read. can be determined as a program page. Also, if the read page information data includes a data value corresponding to an erase cell state for a plurality of program states, the sudden power off management unit 220 deletes a page corresponding to a word line from which the page information data is read. can be judged by In addition, if the read page information data includes both a data value corresponding to a program cell state and a data value corresponding to an erase cell state, the sudden power-off management unit 220 determines the page corresponding to the word line from which the page information data is read. can be determined as the first erased page.

In addition, in an embodiment, the sudden power-off management unit 220, when a word line corresponding to a program page and a word line corresponding to an erase page among a plurality of selected word lines are adjacent to each other, selects the corresponding erase page as the first erase page. can be determined by

In other words, the sudden power-off management unit 220 may determine the direction of an operation for determining the first erase page based on data read from any one word line. For example, if a page corresponding to any one word line is an erase page, the sudden power off management unit 220 may determine the first erase page according to an up-turn method. In this case, the up-turn method may be to determine the first erase page in a first word line region located above any one word line. As another example, if a page corresponding to any one word line is a program page, the sudden power off management unit 220 may determine the first erased page according to a down-turn method. In this case, the down-turn method may be to determine the first erase page in a second word line area located below any one word line.

In one embodiment, the memory device 100 may include a page information detection unit 131 .

The page information detection unit 131 receives state data among page information data read from a plurality of memory blocks, and determines whether a corresponding page is a programmed page, an erased page, or an initially erased page according to a data value of the received state data. cognition can be judged. The page information detection unit 131 may update and store state data for the corresponding page according to the determination result, and output information on the first erased page to the memory controller 200 .

FIG. 2 is a diagram for explaining the memory device 100 of FIG. 1 .

Referring to FIG. 2 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 120 and a control logic 130 .

The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to the row decoder 121 through row lines RL. The plurality of memory blocks BLK1 to BLKz may be connected to the page buffer group 123 through bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. As an example embodiment, the plurality of memory cells are nonvolatile memory cells. Memory cells connected to the same word line may be defined as one page. Accordingly, one memory block may include a plurality of pages.

The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line.

The memory cells included in the memory cell array 110 are single-level cells (SLC) each storing one data bit, multi-level cells (MLC) storing two data bits, and three It can be configured as a triple level cell (TLC) that stores three data bits or a quad level cell (QLC) that can store four data bits.

The peripheral circuit 120 may be configured to perform a program operation, a read operation, or an erase operation on a selected region of the memory cell array 110 under the control of the control logic 130 . The peripheral circuit 120 may drive the memory cell array 110 . For example, the peripheral circuit 120 may apply various operating voltages to the row lines RL and the bit lines BL1 to BLm or discharge the applied voltages according to the control of the control logic 130. there is.

The peripheral circuit 120 may include a row decoder 121 , a voltage generator 122 , a page buffer group 123 , a column decoder 124 , and an input/output circuit 125 .

The row decoder 121 is connected to the memory cell array 110 through row lines RL. The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line. In an embodiment, word lines may include normal word lines and dummy word lines. In an embodiment, the row lines RL may further include a pipe selection line.

The row decoder 121 is configured to operate in response to control of the control logic 130 . The row decoder 121 receives the row address RADD from the control logic 130 .

The row decoder 121 is configured to decode the row address RADD. The row decoder 121 selects at least one memory block among the memory blocks BLK1 to BLKz according to the decoded address. Also, the row decoder 121 may select at least one word line of the selected memory block to apply the voltages generated by the voltage generator 122 to the at least one word line WL according to the decoded address.

For example, during a program operation, the row decoder 121 applies a program voltage to a selected word line and a program pass voltage lower than the program voltage to unselected word lines. During the program verify operation, the row decoder 121 applies a verify voltage to the selected word line and a higher verify pass voltage than the verify voltage to non-selected word lines. During a read operation, the row decoder 121 applies a read voltage to the selected word line and applies a read pass voltage higher than the read voltage to unselected word lines.

In an embodiment, an erase operation of the memory device 100 is performed in units of memory blocks. During an erase operation, the row decoder 121 may select one memory block according to the decoded address. During an erase operation, the row decoder 121 may apply a ground voltage to word lines connected to the selected memory block.

The voltage generator 122 operates in response to control of the control logic 130 . The voltage generator 122 is configured to generate a plurality of voltages using an external power supply voltage supplied to the memory device 100 . Specifically, the voltage generator 122 may generate various operating voltages Vop used in program, read, and erase operations in response to the operation signal OPSIG. For example, the voltage generator 122 may generate a program voltage, a verify voltage, a pass voltage, a read voltage, an erase voltage, and the like in response to control of the control logic 130 .

As an example embodiment, the voltage generator 122 may generate an internal power voltage by regulating an external power voltage. The internal power supply voltage generated by the voltage generator 122 is used as an operating voltage of the memory device 100 .

As an embodiment, the voltage generator 122 may generate a plurality of voltages using an external power supply voltage or an internal power supply voltage.

For example, the voltage generator 122 includes a plurality of pumping capacitors that receive an internal power supply voltage, and generates a plurality of voltages by selectively activating the plurality of pumping capacitors in response to a control of the control logic 130. will be.

The generated voltages may be supplied to the memory cell array 110 by the row decoder 121 .

The page buffer group 123 includes first to m th page buffers PB1 to PBm. The first to m th page buffers PB1 to PBm are connected to the memory cell array 110 through the first to m th bit lines BL1 to BLm, respectively. The first to m th page buffers PB1 to PBm operate in response to the control of the control logic 130 . Specifically, the first to m th page buffers PB1 to PBm may operate in response to the page buffer control signals PBSIGNALS. For example, the first to m th page buffers PB1 to PBm temporarily store data received through the first to m th bit lines BL1 to BLm, or during a read or verify operation, the bit lines The voltage or current of the fields BL1 to BLm may be sensed.

Specifically, during a program operation, the first to m th page buffers PB1 to PBm transfer data DATA received through the input/output circuit 125 when a program pulse is applied to a selected word line. It will be transmitted to selected memory cells through m bit lines BL1 to BLm. The memory cells of the selected page are programmed according to the transferred data DATA. A memory cell connected to a bit line to which a program allowable voltage (eg, ground voltage) is applied may have a raised threshold voltage. A threshold voltage of a memory cell connected to a bit line to which a program prohibition voltage (eg, power supply voltage) is applied may be maintained. During the program verify operation, the first to m th page buffers PB1 to PBm read page data from the selected memory cells through the first to m th bit lines BL1 to BLm.

During a read operation, the first to m th page buffers PB1 to PBm read data DATA from the memory cells of the selected page through the first to m th bit lines BL1 to BLm, and the read data ( DATA) to the input/output circuit 125 under the control of the column decoder 124.

During the erase operation, the first to m th page buffers PB1 to PBm may float the first to m th bit lines BL1 to BLm.

The column decoder 124 may transfer data between the input/output circuit 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 exchanges data with the first to m th page buffers PB1 to PBm through the data lines DL, or the input/output circuit 125 through the column lines CL. can exchange data with

The input/output circuit 125 transfers the command CMD and the address ADDR received from the memory controller 200 described with reference to FIG. 1 to the control logic 130 or transfers the data DATA to the column decoder 124. can exchange with

The sensing circuit 126 generates a reference current in response to the allow bit signal VRYBIT during a read operation or a verify operation, and uses the sensing voltage VPB received from the page buffer group 123 A pass signal PASS or a fail signal FAIL may be output by comparing the reference voltage generated by the reference current with the reference current.

The control logic 130 outputs the operation signal OPSIG, the row address RADD, the page buffer control signals PBSIGNALS, and the enable bit VRYBIT in response to the command CMD and the address ADDR to output the peripheral circuits ( 120) can be controlled. Also, the control logic 130 may determine whether the verification operation has passed or failed in response to a pass or fail signal PASS or FAIL.

In one embodiment, the control logic 130 may include a page information detection unit 131 .

The page information detection unit 131 may receive state data among page information data read by the page buffer group 123 and store the state data. The page information detection unit 131 may determine whether a corresponding page is a programmed page, an erased page, or an initially erased page according to state data. For example, the page information detector 131 may determine a corresponding page as an erased page when all data values corresponding to a plurality of program states included in the state data have a value of “1”. Also, the page information detection unit 131 may determine the corresponding page as a programmed page when all data values corresponding to a plurality of program states included in the state data have a value of “0”. Also, when at least one of data values corresponding to a plurality of program states included in the state data has a value of “0”, the page information detection unit 131 may determine the corresponding page as an initially erased page.

Also, the page information detection unit 131 may provide information that the corresponding page is a programmed page, information that the corresponding page is an erase page, or information that the corresponding page is an initially erased page to the memory controller 200 of FIG. 1 . .

FIG. 3 is a diagram illustrating an example of the memory cell array of FIG. 2 .

Referring to FIG. 3 , the memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. Each memory block may have a 3D structure. Each memory block includes a plurality of memory cells stacked on a substrate. The plurality of memory cells are arranged along the +X direction, the +Y direction, and the +Z direction. The structure of each memory block will be described in more detail with reference to FIGS. 4 and 5 .

FIG. 4 is a circuit diagram showing one memory block BLKa among the memory blocks BLK1 to BLKz of FIG. 3 .

Referring to FIG. 4 , the memory block BLKa includes a plurality of memory cell strings CS11 to CS1m and CS21 to CS2m. As an example embodiment, each of the plurality of memory cell strings CS11 to CS1m and CS21 to CS2m may be formed in a 'U' shape. Within the memory block BLKa, m memory cell strings are arranged in a row direction (ie, +X direction). In FIG. 4 , it is illustrated that two memory cell strings are arranged in a column direction (ie, a +Y direction). However, this is for convenience of description, and it will be understood that three or more memory cell strings may be arranged in a column direction.

Each of the plurality of memory cell strings CS11 to CS1m and CS21 to CS2m includes at least one source selection transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one A drain select transistor (DST) is included.

Each of the selection transistors SST and DST and the memory cells MC1 to MCn may have a similar structure. As an embodiment, each of the selection transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer. As an embodiment, a pillar for providing a channel layer may be provided to each memory cell string. As an example embodiment, a pillar for providing at least one of a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer may be provided in each memory cell string.

The source select transistor SST of each memory cell string is connected between the common source line CSL and the memory cells MC1 to MCp.

As an embodiment, source selection transistors of memory cell strings arranged in the same row are connected to source selection lines extending in a row direction, and source selection transistors of memory cell strings arranged in different rows are connected to different source selection lines. . In FIG. 4 , the source select transistors of the memory cell strings CS11 to CS1m in the first row are connected to the first source select line SSL1. Source select transistors of the memory cell strings CS21 to CS2m in the second row are connected to the second source select line SSL2.

As another example, the source select transistors of the memory cell strings CS11 to CS1m and CS21 to CS2m may be connected in common to one source select line.

The first to nth memory cells MC1 to MCn of each memory cell string are connected between the source select transistor SST and the drain select transistor DST.

The first to nth memory cells MC1 to MCn may be divided into first to pth memory cells MC1 to MCp and p+1 to nth memory cells MCp+1 to MCn. The first to pth memory cells MC1 to MCp are sequentially arranged in the +Z direction and the reverse direction, and are connected in series between the source select transistor SST and the pipe transistor PT. The p+1th to nth memory cells MCp+1 to MCn are sequentially arranged in the +Z direction and connected in series between the pipe transistor PT and the drain select transistor DST. The first to pth memory cells MC1 to MCp and the p+1 to nth memory cells MCp+1 to MCn are connected through a pipe transistor PT. Gates of the first to n th memory cells MC1 to MCn of each memory cell string are connected to the first to n th word lines WL1 to WLn, respectively.

A gate of the pipe transistor PT of each memory cell string is connected to the pipeline PL.

The drain select transistor DST of each memory cell string is connected between a corresponding bit line and memory cells MCp+1 to MCn. Memory cell strings arranged in a row direction are connected to drain select lines extending in a row direction. Drain select transistors of the memory cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. Drain select transistors of the memory cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

Memory cell strings arranged in a column direction are connected to bit lines extending in a column direction. 4 , memory cell strings CS11 and CS21 in a first column are connected to a first bit line BL1. The memory cell strings CS1m and CS2m of the mth column are connected to the mth bit line BLm.

Memory cells connected to the same word line in memory cell strings arranged in a row direction constitute one page. For example, among the memory cell strings CS11 to CS1m in the first row, memory cells connected to the first word line WL1 constitute one page. Among the memory cell strings CS21 to CS2m in the second row, memory cells connected to the first word line WL1 constitute another page. When one of the drain select lines DSL1 and DSL2 is selected, memory cell strings arranged in one row direction are selected. When one of the word lines WL1 to WLn is selected, one page of the selected memory cell strings is selected.

As another embodiment, even bit lines and odd bit lines may be provided instead of the first to m th bit lines BL1 to BLm. Among the memory cell strings CS11 to CS1m or CS21 to CS2m arranged in a row direction, even-numbered memory cell strings are connected to even bit lines, respectively, and the memory cell strings arranged in a row direction (CS11 to CS1m or CS21 Odd-numbered memory cell strings among ~CS2m) may be respectively connected to odd bit lines.

As an example embodiment, at least one of the first to n th memory cells MC1 to MCn may be used as a dummy memory cell. For example, one or more dummy memory cells are provided to reduce an electric field between the source select transistor SST and the memory cells MC1 to MCp. Alternatively, at least one or more dummy memory cells are provided to reduce an electric field between the drain select transistor DST and the memory cells MCp+1 to MCn. As more dummy memory cells are provided, the operation reliability of the memory block BLKa improves, while the size of the memory block BLKa increases. As fewer memory cells are provided, the size of the memory block BLKa decreases while the reliability of an operation of the memory block BLKa may deteriorate.

In order to efficiently control at least one or more dummy memory cells, each of the dummy memory cells may have a required threshold voltage. Program operations may be performed on all or some of the dummy memory cells before or after the erase operation on the memory block BLKa. When an erase operation is performed after a program operation is performed, the dummy memory cells may have a required threshold voltage by controlling voltages applied to dummy word lines connected to the dummy memory cells. .

FIG. 5 is a circuit diagram showing another embodiment of one memory block BLKb among the memory blocks BLK1 to BLKz of FIG. 3 .

Referring to FIG. 5 , the memory block BLKb includes a plurality of memory cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the plurality of memory cell strings CS11' to CS1m' and CS21' to CS2m' extends along the +Z direction. Each of the plurality of memory cell strings CS11' to CS1m' and CS21' to CS2m' includes at least one source select transistor SST stacked on a substrate (not shown) under the memory block BLK1'. It includes first to nth memory cells MC1 to MCn and at least one drain select transistor DST.

The source select transistor SST of each memory cell string is connected between the common source line CSL and the memory cells MC1 to MCn. Source select transistors of memory cell strings arranged in the same row are connected to the same source select line. Source select transistors of the memory cell strings CS11' to CS1m' arranged in the first row are connected to the first source select line SSL1. Source select transistors of the memory cell strings CS21' to CS2m' arranged in the second row are connected to the second source select line SSL2. As another embodiment, the source select transistors of the memory cell strings CS11' to CS1m' and CS21' to CS2m' may be connected in common to one source select line.

The first to nth memory cells MC1 to MCn of each memory cell string are connected in series between the source select transistor SST and the drain select transistor DST. Gates of the first to n th memory cells MC1 to MCn are connected to the first to n th word lines WL1 to WLn, respectively.

The drain select transistor DST of each memory cell string is connected between the corresponding bit line and the memory cells MC1 to MCn. Drain select transistors of memory cell strings arranged in a row direction are connected to drain select lines extending in a row direction. Drain select transistors of the memory cell strings CS11' to CS1m' in the first row are connected to the first drain select line DSL1. Drain select transistors of the memory cell strings CS21' to CS2m' in the second row are connected to the second drain select line DSL2.

As a result, the memory block BLKb of FIG. 5 has an equivalent circuit similar to that of the memory block BLKa of FIG. 4 except that the pipe transistor PT is excluded from each memory cell string.

As another embodiment, even bit lines and odd bit lines may be provided instead of the first to m th bit lines BL1 to BLm. In addition, among the memory cell strings CS11' to CS1m' or CS21' to CS2m' arranged in a row direction, even-numbered memory cell strings are connected to even bit lines, respectively, and the memory cell strings arranged in a row direction CS11 Odd-numbered memory cell strings among '~CS1m' or CS21'~CS2m') may be respectively connected to odd bit lines.

As an example embodiment, at least one of the first to n th memory cells MC1 to MCn may be used as a dummy memory cell. For example, one or more dummy memory cells are provided to reduce an electric field between the source select transistor SST and the memory cells MC1 to MCn. Alternatively, at least one or more dummy memory cells are provided to reduce an electric field between the drain select transistor DST and the memory cells MC1 to MCn. As more dummy memory cells are provided, the operation reliability of the memory block BLKb improves, while the size of the memory block BLKb increases. As fewer memory cells are provided, the size of the memory block BLKb decreases while the reliability of an operation of the memory block BLKb may deteriorate.

In order to efficiently control at least one or more dummy memory cells, each of the dummy memory cells may have a required threshold voltage. Program operations may be performed on all or some of the dummy memory cells before or after the erase operation on the memory block BLKb. When an erase operation is performed after a program operation is performed, the dummy memory cells may have a required threshold voltage by controlling voltages applied to dummy word lines connected to the dummy memory cells. .

FIG. 6 is a diagram illustrating a connection relationship between the memory controller of FIG. 1 and a plurality of memory devices by way of example.

Referring to FIG. 6 , the memory controller 200 may be connected to a plurality of memory devices (memory device_11 to memory device_24) through a plurality of channels CH1 to CH2. In an embodiment, it will be well understood that the number of channels or the number of memory devices connected to each channel may be variously changed. However, for convenience of description, it is assumed in this specification that the memory controller 200 is connected to memory devices through two channels and four memory devices are connected to each channel.

For convenience of description, operations of the memory device_11, memory device_12, memory device_13, and memory device_14 connected to the first channel CH1 will be described. It will be understood that the memory devices (memory device_21 to memory device_24) connected to the remaining channels CH2 are also operated in the same manner.

Memory devices_11 to memory devices_14 may be commonly connected to the first channel CH1. The memory devices_11 to memory devices_14 may communicate with the memory controller 200 through the first channel CH1. Since the memory devices_11 to memory devices_14 are commonly connected to the first channel CH1, only one memory device can communicate with the memory controller 200 at a time. However, the internal operations of the memory devices 11 to 14 may be simultaneously performed.

A storage device using a plurality of memory devices may improve performance by using the interleaving method described in FIG. 1 . For the interleaving method, memory devices may be managed in units of channels and ways. In order to maximize parallelization of memory devices connected to each channel, the memory controller 200 may distribute and allocate contiguous logical memory areas to channels and ways.

For example, the memory controller 200 may transmit a command, a control signal including an address, and data to the memory device 11 through the first channel CH1. While the memory device_11 programs the received data into memory cells included therein, the memory controller 200 may transmit control signals including commands and addresses and data to the memory device_12.

In FIG. 6 , a plurality of memory devices may be configured with four ways WAY1 to WAY4. The first way WAY1 may include a memory device_11 and a memory device_21. The second way WAY2 may include a memory device_12 and a memory device_22. The third way WAY3 may include a memory device_13 and a memory device_23. The fourth way WAY4 may include memory device_14 and memory device_24.

Each of the channels CH1 and CH2 may be a bus of signals shared and used by memory devices connected to the corresponding channels.

Although interleaving in a 2-channel/4-way structure has been described in FIG. 6, the efficiency of interleaving can be increased as the number of channels and the number of ways increase.

7 is a diagram for explaining the concept of a super block, super page or stripe.

Referring to FIG. 7 , four memory devices of memory device_11 to memory device_14 may be connected to the first channel CH1 in common.

In FIG. 7 , each memory device may include a plurality of planes. However, for convenience of description, it is assumed in this specification that one memory device includes one plane. One plane included in each of the memory devices (memory device_11 to memory device_14) may include the first memory block to the z-th memory blocks BLK1 to BLKz, and one memory block may include the first Pages through nth pages (Page 1 to Page n) may be included.

The memory controller 200 may control memory blocks included in a plurality of memory devices (memory device_11 to memory device_14) commonly connected to one channel in units of super blocks. For example, the first memory blocks BLK1 included in the memory device_11 to memory device_14 may constitute a first super block (Super Block 1). Accordingly, memory devices_11 to memory devices_14 connected to the first channel CH1 may include first to zth super blocks (Super Block 1 to Super Block z).

In an embodiment, a super block may include at least two or more memory blocks included in each memory device among memory blocks included in each of the plurality of memory devices (memory device_11 to memory device_14). The storage device 50 that stores data in units of super blocks can simultaneously perform operations on a plurality of memory devices (memory device_11 to memory device_14). For example, the storage device 50 may perform operations on a plurality of memory devices (memory device_11 to memory device_14) in parallel using an interleaving method.

One super block may be composed of a plurality of stripes. Stripe can be used interchangeably with the term “super page”.

One stripe or super page may include a plurality of pages. For example, the first pages (Page 1) respectively included in the plurality of first memory blocks (BLK1) included in the first super block (Super Block 1) are the first stripe (Stripe 1) or the first super page. (Super Page 1) can be configured.

Accordingly, one super block may include a first stripe (Stripe 1) to an n-th stripe (Stripe n). Alternatively, one super block may include a first super page (Super Page 1) to an n-th super page (Super page n).

The memory controller 200 may store or read data in stripe units or super page units when storing data or reading stored data in the memory device_11 to memory device_14.

In an embodiment, the memory controller 200 may first program a page corresponding to a lower number among the first stripe (Stripe 1) to the n-th stripe (Stripe n) included in the super block.

For example, the memory controller 200 may store data in a plurality of first pages (Page 1) included in the first stripe (Stripe 1). Then, when there is no space to store data in the plurality of first pages (Page 1), the memory controller 200 may store data in a plurality of second pages included in the plurality of first memory blocks. Accordingly, the memory controller 200 may sequentially store data from the first stripe (Stripe 1) to the n-th stripe (Stripe n) included in the super block through the above-described method.

FIG. 8 is a diagram for explaining another embodiment of the super block of FIG. 7 .

Referring to FIG. 8 , a memory device_11 represents a memory device_11 among a plurality of memory devices (memory device_11 to memory device_14) described with reference to FIG. 2 .

The memory device _11 may include a plurality of planes Plane 1 to Plane n. One plane may include a plurality of memory blocks BLK1 to BLKz.

A plane may be a unit that independently performs a program operation, a read operation, or an erase operation. Accordingly, the memory device 11 may include an address decoder and read/write circuits to be described later for each plane.

In an embodiment, the super block SUPBK may include at least two or more memory blocks included in different planes among memory blocks respectively included in a plurality of planes included in one memory device. The memory device_11 that stores data in units of super blocks (SUPBK) can simultaneously perform operations on a plurality of planes (Plane 1 to Plane n) (Multi-Plane Operation). For example, the memory device 11 may perform operations on a plurality of planes (Plane 1 to Plane n) in parallel using an interleaving method.

Meanwhile, sudden power-off may occur while the storage device 50 is sequentially storing data in a plurality of pages (Page 1 to Page n) included in the super block. In this case, the storage device 50 may perform a sudden power-off recovery operation through the sudden power-off management unit 220 included in the memory controller 200 .

At this time, the prior art searches for the first erased page using a binary search method. The binary search method refers to a method of searching for an initially erased page while dichotomizing a plurality of word lines. However, this binary search method has a problem in that the speed of an erase page search operation becomes slower as the number of word lines included in a memory block increases.

In order to solve this problem, the storage device 50 according to the embodiment utilizes a binary method, but may perform a read operation for searching for an erase page in parallel in each of a plurality of memory blocks. This will be described in detail with reference to FIGS. 9 and 10 .

9 is a diagram for explaining an example of an operation of determining an initial erase page according to an embodiment of the present invention.

Referring to FIG. 9 , the memory device 100 may include a super block. The super block SB may include at least two or more memory blocks BLK1 to BLKz included in different planes among memory blocks respectively included in a plurality of planes. In an embodiment, the plurality of memory blocks BLK1 to BLKz may be included in different planes. However, according to embodiments, each of the plurality of memory blocks BLK1 to BLKz may be included in a different memory device. In an embodiment, the memory device 100 may first program pages corresponding to a word line having a lower number among the plurality of word lines WL1 to WLn in the super block SB. Also, the memory device 100 may first program a memory block corresponding to a lower number among the plurality of memory blocks BLK1 to BLKz in the super block SB.

In an embodiment, the sudden power-off management unit 220 may be configured at an intermediate point among a plurality of word lines WL1 to WLn in a first memory block BLK in which data is first programmed among the plurality of memory blocks BLK1 to BLKz. The memory device 100 may be controlled to perform a read operation on the h1 th word line WL_h1 located at . The memory device 100 may perform a read operation on the h1th word line WL_h1 in the first memory block BLK1.

When the page corresponding to the h1 th word line WL_h1 is determined to be an erase page based on the data read from the h1 th word line WL_h1, the sudden power off management unit 220 removes the first word line area area 1 may be determined as an area for detecting the first erased page. In this case, the first word line area area 1 is an area located above the h1 th word line WL_h1, and is a word line from the first word line WL1 where data is initially programmed to the h1 th word line WL_h1. may include The second word line area area 2 is an area located under the h1 th word line WL_h1, and includes word lines from the n th word line WLn where data is programmed last to the h1 th word line WL_h1. can include

In one embodiment, the sudden power-off management unit 220 selects a plurality of selected word lines ( BLK1 to BLKz ) in the remaining memory blocks ( BLK2 to BLKz ) except for the first memory block ( BLK1 ) among the plurality of memory blocks ( BLK1 to BLKz ). The memory device 100 may be controlled to perform a read operation for WL_h2 to WL_hn). Each of the plurality of selected word lines WL_h2 to WL_hn is a word line located at an intermediate point between the first word line WL1 and the h1th word line WL_h1, or a plurality of selected word lines WL_h2 to WL_hn. It may be a word line located at an intermediate point between each of the selected word lines and the first word line WL1 and another selected word line. For example, the second memory block BLK2 may perform a read operation on the h2th word line WL_h2. The h2th word line WL_h2 may be a word line located at an intermediate point between the first word line WL1 and the h1th word line WL_h1. Also, the third memory block BLK3 may perform a read operation on the h3 th word line WL_h3. The h3th word line WL_h3 may be a word line positioned at an intermediate point between the first word line WL1 and the h2th word line WL_h2 on which a read operation is to be performed on the previous memory block BLK2. Also, the z th memory block BLKz may perform a read operation on the hz th word line WL_hz. The hz-th word line WL_hz may be a word line located at an intermediate point between the first word line WL1 and the hz-1 th word line WL_hz-1 on which a read operation is to be performed on the previous memory block BLKz-1. there is. In other words, the specific memory block may perform a read operation on a word line positioned at an intermediate point between the first word line WL1 and a word line to be performed in a memory block previous to the specific memory block.

Also, the memory device 100 may perform a read operation on the plurality of selected word lines WL_h2 to WL_hn in parallel in the remaining memory blocks BLK2 to BLKz. The memory device 100 may detect the first erase page based on data read from the plurality of selected word lines WL_h2 to WL_hn.

10 is a diagram for explaining another example of an operation of determining an initial erase page according to an embodiment of the present invention.

The memory device 100 may include a super block. The super block SB may include at least two or more memory blocks BLK1 to BLKz included in different planes among memory blocks respectively included in a plurality of planes. In an embodiment, the plurality of memory blocks BLK1 to BLKz may be included in different planes. However, according to embodiments, each of the plurality of memory blocks BLK1 to BLKz may be included in a different memory device. In an embodiment, the memory device 100 may first program pages corresponding to a word line having a lower number among the plurality of word lines WL1 to WLn in the super block SB. Also, the memory device 100 may first program a memory block corresponding to a lower number among the plurality of memory blocks BLK1 to BLKz in the super block SB.

In an embodiment, the sudden power-off management unit 220 may be configured at an intermediate point among a plurality of word lines WL1 to WLn in a first memory block BLK in which data is first programmed among the plurality of memory blocks BLK1 to BLKz. The memory device 100 may be controlled to perform a read operation on the h1 th word line WL_h1 located at . The memory device 100 may perform a read operation on the h1th word line WL_h1 in the first memory block BLK1.

When the page corresponding to the h1 th word line WL_h1 is determined to be a program page based on the data read from the h1 th word line WL_h1, the sudden power off management unit 220 controls the second word line area area 2 may be determined as an area for detecting the first erased page. In this case, the first word line area area 1 is an area located above the h1 th word line WL_h1, and is a word line from the first word line WL1 where data is initially programmed to the h1 th word line WL_h1. may include The second word line area area 2 is an area located under the h1 th word line WL_h1, and includes word lines from the n th word line WLn where data is programmed last to the h1 th word line WL_h1. can include

In one embodiment, the sudden power-off management unit 220 selects a plurality of selected word lines ( BLK1 to BLKz ) in the remaining memory blocks ( BLK2 to BLKz ) except for the first memory block ( BLK1 ) among the plurality of memory blocks ( BLK1 to BLKz ). The memory device 100 may be controlled to perform a read operation for WL_h2' to WL_hn'. Each of the plurality of selected word lines WL_h2' to WL_hn' is a word line located at an intermediate point between the n-th word line WLn and the h1-th word line WL_h1, or each of the plurality of selected word lines WL_h2' to WL_hn ') may be a word line located at an intermediate point between the selected word line different from each of the plurality of selected word lines and the n-th word line WLn. For example, the second memory block BLK2 may perform a read operation on the h2'th word line WL_h2'. The h2'th word line WL_h2' may be a word line located at an intermediate point between the nth word line WLn and the h1 th word line WL_h1. Also, the third memory block BLK3 may perform a read operation on the h3'th word line WL_h3'. The h3'th word line WL_h3' may be a word line located at an intermediate point between the nth word line WLn and the h2'th word line WL_h2' on which a read operation is to be performed on the previous memory block BLK2. Also, the zth memory block BLKz may perform a read operation on the hz'th word line WL_hz'. The hz'th word line WL_hz' is located at the midpoint of the nth word line WLn and the hz-1'th word line WL_hz-1' where a read operation is to be performed on the previous memory block BLKz-1. It may be a word line. In other words, the specific memory block may perform a read operation on a word line positioned at an intermediate point between the n-th word line WLn and a word line to be performed in a memory block previous to the specific memory block.

Also, the memory device 100 may perform a read operation on the plurality of selected word lines WL_h2' to WL_hn' in parallel in the remaining memory blocks BLK2 to BLKz. The memory device 100 may detect the first erase page based on data read from the plurality of selected word lines WL_h2' to WL_hn'.

11 is a diagram for explaining the configuration of a data set according to an embodiment of the present invention.

Referring to FIG. 11 , a data set may include a page information area and a data area.

The page information area may be created by the program operation controller 210 and may be composed of page information data. For example, the page information area may include basic information (Page Inform) of a page, state data (PV1 to PV7), and erase/program cycle number data (EW Cycle) of a corresponding page.

The data area may include user data, a cyclic redundancy code (CRC), and ECC parity.

Also, the data area is scrambled by the program operation controller 210, and the page information area may not be scrambled.

12 is a diagram for explaining a program state of memory cells according to an exemplary embodiment.

Referring to FIG. 12 , a triple level cell (TLC) has a threshold voltage distribution of an erase state (PV0) and a plurality of program states (PV1 to PV7). Program operations may be sequentially performed in the plurality of program states PV1 to PV7 during program operation.

Therefore, each of the state data PV1 to PV7 of FIG. 11 is a data value respectively corresponding to a plurality of program states of FIG. 12, and the state data PV1 to PV7 is a “0” value corresponding to the program state during program operation. can be set. The state data PV1 to PV7 may be programmed together when user data included in the data area is programmed in the selected page. For example, when data corresponding to PV1 among user data is programmed, state data PV1 is programmed, and when data corresponding to PV2 among user data is programmed, state data PV2 is programmed, and when data corresponding to PV7 among user data is programmed, state data PV7 may be programmed. Accordingly, data values included in the status data of the programmed page may indicate whether the program is executed or not and whether sudden power-off occurs during program operation. For example, when all data values included in the read status data have a value of “0”, the corresponding page may be determined to be a page that has been programmed. In addition, when data values included in the read status data all have a value of “1”, the corresponding page may be determined as an erase page. do. Also, when the data values included in the read status data are mixed with values of “0” and “1”, the corresponding page may be determined as an initially erased page.

Meanwhile, although the memory cells are described as triple-level cells in FIGS. 11 and 12, the memory cells are single-level cells (SLCs), multi-level cells (MLCs), or quad-level cells (Quad Level Cells). Cell; QLC) can be applied in the same way.

13 is a diagram for explaining an area in which page information is stored in a memory block according to an embodiment of the present invention.

Referring to FIG. 13 , a memory block (eg, BLK1) may be divided into a first block area B0 and a second block area B1, and the first block area B0 and the second block area ( B1) may divide each of a plurality of pages included in the memory block into half to distinguish them.

In an embodiment, the sudden power-off management unit 220 reads a partial area based on a half-sensing method during a read operation on one word line and a read operation on a plurality of selected word lines. can control. For example, during a half-page sensing method read operation, only a partial area (eg, B0) of the first block area B0 and the second block area B1 may be selected and the read operation may be performed.

Also, some areas of the plurality of memory blocks may store state data during a program operation. For example, a partial area of the first block area B0 selected during a read operation of the half-page sensing method is defined as a status cell area, and the status cell area corresponds to each page. The state data (PV1 to PV7) of FIG. 11 may be stored. In addition, each of the status data PV1 to PV7 may be assigned a column address Col 1 to Col 7 and stored in memory cells included in a status cell area corresponding to the corresponding column address.

14 is a diagram for explaining data values corresponding to a plurality of program states included in page information according to an embodiment of the present invention. 15 is a diagram for explaining a page information value according to a page state according to an embodiment of the present invention.

Referring to FIGS. 14 and 15 , during program operation, data values included in state data may be initially set to “0” values. Data values included in the status data read from a normally programmed page may all have a value of “0”. Data values included in state data read from a page on which a program operation is not performed may all have a value of “1”. On the other hand, data values included in state data read from a page where sudden power-off occurred during a program operation may have a mixture of “0” values and “1” values. For example, if an SPO occurs during program operation corresponding to PV4, the data values corresponding to PV1, PV2, and PV3 have "0", and the data values corresponding to PV4, PV5, PV6, and PV7 have "1". can have

16 is a flowchart illustrating a method of operating a storage device according to an exemplary embodiment.

The method shown in FIG. 16 may be performed by, for example, the storage device of FIG. 1 .

Referring to FIG. 16 , in step S1601 , the storage device 50 may detect sudden power off.

In operation S1603 , the storage device 50 may perform a read operation on a first word line positioned at an intermediate point among a plurality of word lines in a first memory block in which data is first programmed among the plurality of memory blocks.

In an embodiment, the storage device 50 may read a partial area of the first memory block based on the half sensing method. In this case, some areas may include state data.

In operation S1605 , the storage device 50 may determine one word line area among the first word line area and the second word line area based on the data read from the first word line. In this case, the first word line area may include word lines from the start word line to the first word line among the plurality of word lines. The second word line area may include word lines from the last word line to the first word line among the plurality of word lines.

In step S1607, the storage device 50 performs a read operation on a plurality of selected word lines among word lines included in the determined word line area in second memory blocks other than the first memory block among the plurality of memory blocks. can be performed in parallel. In an embodiment, the storage device 50 may read a partial area of the second memory blocks based on the half sensing method. In this case, some areas may include state data.

In step S1609, the storage device 50 may detect an initially erased page based on a result of a read operation on the plurality of selected word lines. For example, if the read state data includes a data value corresponding to a program cell state for a plurality of program states, the storage device 50 determines a page corresponding to a word line from which the state data is read as a program page. can do. Also, if the read state data includes a data value corresponding to an erase cell state for a plurality of program states, the storage device 50 may determine a page corresponding to a word line from which state data is read as an erase page. there is. In addition, if the read state data includes both a data value corresponding to the program cell state and a data value corresponding to the erase cell state, the storage device 50 converts the page corresponding to the word line from which the state data is read to the first erase page. can be judged by

17 is a diagram for explaining an operation of determining an initial erase page according to an embodiment of the present invention.

In one embodiment, FIG. 17 may be a diagram embodying step S1605 of FIG. 16 .

The method illustrated in FIG. 17 may be performed by, for example, the storage device of FIG. 1 .

Referring to FIG. 17 , in step S1701, the storage device 50 may determine whether a page corresponding to the first word line is an erase page. For example, the storage device 50 may determine a page corresponding to the first word line as an erase page or a program page based on data read from the first word line.

If the page corresponding to the first word line is an erase page according to the determination result in step S1701, the storage device 50 may determine the first word line area as one word line area in step S1703. In this case, the plurality of selected word lines may be included in the first word line area. For example, each of the plurality of selected word lines is a word line located at an intermediate point between the start word line and the first word line, or a selected word line and a start word different from each of the plurality of selected word lines among the plurality of selected word lines. It may be a word line located at an intermediate point of the word line.

According to the determination result in step S1701, if the page corresponding to the first word line is not an erased page, in step S1705, the storage device 50 may determine the second word line area as any one word line area. . In this case, the plurality of selected word lines may be included in the second word line area. For example, each of the plurality of selected word lines is a word line located at an intermediate point between the last word line and the first word line, or a selected word line different from each of the plurality of selected word lines and the last word line among the plurality of selected word lines. It may be a word line located at an intermediate point of the word line.

18 is a diagram for describing a memory controller according to an exemplary embodiment.

The memory controller 1000 of FIG. 18 may represent the memory controller 200 of FIG. 1 .

1 and 18 , the memory controller 1000 includes a processor 1010, a RAM 1020, an error correction circuit 1030, a ROM 1040, a host interface 1050, and a flash interface 1060. can include

The processor 1010 may control overall operations of the memory controller 1000 . The RAM 1020 may be used as a buffer memory, cache memory, operation memory, or the like of the memory controller 1000 .

The error correction circuit 1030 may perform error correction. The error correction circuit 1030 may perform error correction encoding (ECC encoding) based on data to be written into a memory device through the flash interface 1060 . Error correction encoded data may be transmitted to the memory device through the flash interface 1060 . The error correction circuit 1030 may perform ECC decoding on data received from the memory device through the flash interface 1060 . Illustratively, the error correction circuit 1030 may be included in the flash interface 1060 as a component of the flash interface 1060 .

The ROM 1040 may store various information required for the memory controller 1000 to operate in the form of firmware. In one embodiment, the program operation control unit 210 and the sudden power off management unit 220 described with reference to FIG. 1 may be implemented as firmware stored in the ROM 1040 .

The memory controller 1000 may communicate with an external device (eg, the host 300 or an application processor) through the host interface 1050 .

The memory controller 1000 may communicate with the memory device 100 through the flash interface 1060 . The memory controller 1000 may transmit commands, addresses, and control signals to the memory device 100 through the flash interface 1060 and may receive data. Illustratively, the flash interface 1060 may include a NAND interface.

19 is a block diagram illustrating a memory card system to which a storage device according to an embodiment of the present invention is applied.

Referring to FIG. 19 , a memory card system 2000 includes a memory controller 2100 , a memory device 2200 , and a connector 2300 .

The memory controller 2100 is connected to the memory device 2200 . The memory controller 2100 is configured to access the memory device 2200 . For example, the memory controller 2100 may be configured to control read, write, erase, and background operations of the memory device 2200 . The memory controller 2100 is configured to provide an interface between the memory device 2200 and a host. The memory controller 2100 is configured to drive firmware for controlling the memory device 2200 . The memory controller 2100 may be implemented identically to the memory controller 200 described with reference to FIG. 1 . The memory device 2200 may be implemented identically to the memory device 100 described with reference to FIG. 1 .

Illustratively, the memory controller 2100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error correction unit. can

The memory controller 2100 may communicate with an external device through the connector 2300 . The memory controller 2100 may communicate with an external device (eg, a host) according to a specific communication standard. For example, the memory controller 2100 may include universal serial bus (USB), multimedia card (MMC), embedded MMC (eMMC), peripheral component interconnection (PCI), PCI-express (PCI-E), and advanced technology attachment (ATA). ), Serial-ATA, Parallel-ATA, SCSI (small computer small interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, It is configured to communicate with an external device through at least one of various communication standards such as NVMe. Illustratively, the connector 2300 may be defined by at least one of the above-described various communication standards.

For example, the memory device 2200 may include electrically erasable and programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and STT-MRAM. (Spin Transfer Torque-Magnetic RAM) and the like.

The memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and the memory device 2200 are integrated into a single semiconductor device such as a personal computer memory card international association (PCMCIA), a compact flash card (CF), or a smart media card (SM, SMC). ), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro, eMMC), SD cards (SD, miniSD, microSD, SDHC), and universal flash memory (UFS).

20 is a block diagram illustrating a solid state drive (SSD) system to which a storage device according to an embodiment of the present invention is applied.

Referring to FIG. 20 , an SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals with the host 3100 through the signal connector 3001 and receives power through the power connector 3002 . The SSD 3200 includes an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

According to an embodiment of the present invention, the SSD controller 3210 may perform the function of the memory controller 200 described with reference to FIG. 1 .

The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal received from the host 3100 . For example, the signals may be signals based on an interface between the host 3100 and the SSD 3200 . For example, signals include universal serial bus (USB), multimedia card (MMC), embedded MMC (eMMC), peripheral component interconnection (PCI), PCI-express (PCI-E), advanced technology attachment (ATA), serial- Interfaces such as ATA, Parallel-ATA, SCSI (small computer small interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, NVMe, etc. It may be a signal defined by at least one of

The auxiliary power supply 3230 is connected to the host 3100 through a power connector 3002 . The auxiliary power supply 3230 can receive power from the host 3100 and charge it. The auxiliary power supply 3230 may provide power to the SSD 3200 when power supply from the host 3100 is not smooth. For example, the auxiliary power supply 3230 may be located inside the SSD 3200 or outside the SSD 3200 . For example, the auxiliary power supply 3230 is located on the main board and may provide auxiliary power to the SSD 3200.

The buffer memory 3240 operates as a buffer memory of the SSD 3200. For example, the buffer memory 3240 temporarily stores data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or metadata (metadata) of the flash memories 3221 to 322n. For example, a mapping table) may be temporarily stored. The buffer memory 3240 may include volatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM.

21 is a block diagram illustrating a user system to which a storage device according to an embodiment of the present invention is applied.

Referring to FIG. 21 , a user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

The application processor 4100 may drive components included in the user system 4000, an operating system (OS), or a user program. Illustratively, the application processor 4100 may include controllers, interfaces, graphic engines, and the like that control components included in the user system 4000 . The application processor 4100 may be provided as a System-on-Chip (SoC).

The memory module 4200 may operate as a main memory, working memory, buffer memory, or cache memory of the user system 4000 . The memory module 4200 includes volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDARM, LPDDR2 SDRAM, LPDDR3 SDRAM, etc., or non-volatile random access memory such as PRAM, ReRAM, MRAM, FRAM, etc. can do. For example, the application processor 4100 and the memory module 4200 may be packaged based on a package on package (POP) and provided as a single semiconductor package.

The network module 4300 may communicate with external devices. Illustratively, the network module 4300 may include code division multiple access (CDMA), global system for mobile communication (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), and long term evolution (LTE). ), wireless communication such as Wimax, WLAN, UWB, Bluetooth, Wi-Fi, etc. may be supported. For example, the network module 4300 may be included in the application processor 4100 .

The storage module 4400 may store data. For example, the storage module 4400 may store data received from the application processor 4100 . Alternatively, the storage module 4400 may transmit data stored in the storage module 4400 to the application processor 4100 . For example, the storage module 4400 is a non-volatile semiconductor memory device such as a phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash, NOR flash, or 3D NAND flash. can be implemented For example, the storage module 4400 may be provided as a removable storage medium such as a memory card or an external drive of the user system 4000 .

For example, the storage module 4400 may include a plurality of nonvolatile memory devices, and the plurality of nonvolatile memory devices may operate in the same way as the memory device 100 described with reference to FIG. 1 . The storage module 4400 may operate in the same way as the storage device 50 described with reference to FIG. 1 .

The user interface 4500 may include interfaces for inputting data or commands to the application processor 4100 or outputting data to an external device. For example, the user interface 4500 may include user input interfaces such as a keyboard, keypad, button, touch panel, touch screen, touch pad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, piezoelectric element, and the like. there is. The user interface 4500 may include user output interfaces such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a monitor.

50: storage device
100: memory device
131: page information detection unit
200: memory controller
210: program operation control unit
220: sudden power-off management unit
300: host

Claims (20)

a memory device connected to a plurality of word lines and including a plurality of memory blocks included in a super block; and
When sudden power-off occurs, controlling the memory device to perform a read operation on one word line among the plurality of word lines in one memory block among the plurality of memory blocks; Determine any one word line area based on data read from any one word line of a first word line area located above a word line and a second word line area located below any one word line; In order to perform a read operation on a plurality of selected word lines among word lines included in the determined word line area in the remaining memory blocks except for the one memory block among the plurality of memory blocks, in parallel and a sudden power-off manager configured to control a memory device and to detect an erase page initially positioned at a boundary between a program page and an erase page based on data read from the plurality of selected word lines. The method of claim 1, wherein the one memory block,
A storage device that is a memory block in which data is first programmed among the plurality of memory blocks. The method of claim 1, wherein the one word line,
A storage device that is a word line positioned at an intermediate point among the plurality of word lines. The method of claim 1 , wherein the first word line area comprises:
including word lines from a start word line corresponding to a page in which data is programmed first among the plurality of word lines to one of the word lines;
The second word line area,
and word lines from a last word line corresponding to a page where data is programmed last among the plurality of word lines to any one of the word lines. The method of claim 4 , wherein the sudden power-off management unit comprises:
When a page corresponding to any one word line is determined to be an erase page based on data read from any one word line, among word lines included in the first word line area in the remaining memory blocks A storage device that controls the remaining memory blocks to perform a read operation on a plurality of selected word lines. The method of claim 5, wherein each of the plurality of selected word lines,
A word line located at the midpoint between the start word line and any one word line, or at a midpoint between a selected word line different from each of the plurality of selected word lines among the plurality of selected word lines and the start word line. A storage device that is a located word line. The method of claim 4 , wherein the sudden power-off management unit comprises:
When a page corresponding to any one word line is determined to be a program page based on data read from any one word line, among word lines included in the second word line area in the remaining memory blocks A storage device that controls the remaining memory blocks to perform a read operation on a plurality of selected word lines. The method of claim 7, wherein each of the plurality of selected word lines,
A word line located at the midpoint between the last word line and any one word line, or at a midpoint between a selected word line different from each of the plurality of selected word lines and the last word line among the plurality of selected word lines. A storage device that is a located word line. The method of claim 1 , wherein the sudden power-off manager comprises:
and controlling the remaining memory blocks to perform a read operation on different selected word lines from among the plurality of selected word lines in parallel in each of the remaining memory blocks according to an interleaving method. According to claim 1,
During a program operation, program data is generated by scrambling and decoding data received from a host, at least one data set is generated using the program data and page information data, and the at least one data set is converted into the plurality of memory blocks. The storage device further includes a program operation control unit that controls the plurality of memory blocks to program a plurality of pages included in the storage device. 11. The method of claim 10, wherein the page information data comprises:
The data set includes basic information of the page to be stored, the number of erase/program cycles, and state data for determining the program state of the corresponding page;
The state data,
the program data includes data values respectively corresponding to a plurality of program states programmed in memory cells included in the plurality of pages;
Data values respectively corresponding to the plurality of program states,
A storage device comprising a data value corresponding to a program cell state of the memory cells or a data value corresponding to an erase cell state of the memory cells. 12. The method of claim 11, wherein some areas of the plurality of memory blocks,
Storing the state data during the program operation,
The sudden power-off management unit,
The storage device controls the plurality of memory blocks to read the partial area based on a half-sensing method during a read operation of the one word line and a read operation of the plurality of selected word lines. 12. The method of claim 11, wherein the sudden power off management unit,
and controlling the plurality of memory blocks to read the page information data during a read operation of the one word line and a read operation of the plurality of selected word lines. 14. The method of claim 13, wherein the sudden power off management unit,
if the read page information data includes a data value corresponding to the program cell state for the plurality of program states, determining a page corresponding to a word line from which the page information data is read as a program page;
if the read page information data includes a data value corresponding to the erase cell state for the plurality of program states, determining a page corresponding to a word line from which the page information data is read as an erase page;
If the read page information data includes both the data value corresponding to the program cell state and the data value corresponding to the erase cell state, the page corresponding to the word line from which the page information data was read is the first erase page. Storage device to judge. A method of operating a storage device for controlling an operation of a super block including a plurality of memory blocks connected to a plurality of word lines, the method comprising:
detecting sudden power off;
performing a read operation on a first word line located at an intermediate point among the plurality of word lines in a first memory block among the plurality of memory blocks in which data is first programmed;
One word line area is determined based on data read from the first word line among the first word line area located above the first word line and the second word line area located below the first word line. doing;
parallelly performing a read operation on a plurality of selected word lines among word lines included in the determined word line area in second memory blocks other than the first memory block among the plurality of memory blocks; and
and detecting an erase page located at a boundary between a program page and an erase page based on a result of a read operation on the plurality of selected word lines. 16. The method of claim 15, wherein the first word line area,
including word lines from a start word line corresponding to a page in which data is programmed first among the plurality of word lines to the first word line;
The second word line area,
and word lines from a last word line corresponding to a page where data is programmed last among the plurality of word lines to the first word line. 17. The method of claim 16, wherein the determining of any one word line area comprises:
determining a page corresponding to the first word line as an erase page based on data read from the first word line; and
and determining the first word line area as one of the word line areas in response to the page corresponding to the first word line being the erase page. 18. The method of claim 17, wherein each of the plurality of selected word lines,
A word line positioned at an intermediate point between the start word line and the first word line, or positioned at a midpoint between a selected word line different from each of the plurality of selected word lines among the plurality of selected word lines and the start word line. A method of operating a storage device that is a word line. 17. The method of claim 16, wherein the determining of any one word line area comprises:
determining a page corresponding to the first word line as a program page based on data read from the first word line; and
and determining the second word line area as one of the word line areas in response to the fact that the page corresponding to the first word line is the program page. 20. The method of claim 19, wherein each of the plurality of selected word lines,
A word line located at an intermediate point between the last word line and the first word line, or located at an intermediate point between a selected word line different from each of the plurality of selected word lines and the last word line among the plurality of selected word lines. A method of operating a storage device that is a word line.

Images