KR20220170146A - HDEVS based RTL design tool with co-simulator for reducing semiconductor design and verification process cost - Google Patents

Abstract

A hybrid discrete event system specification (HDEVS)-based register transfer level (RTL) design tool for reducing semiconductor design process costs and a complex simulator are disclosed. The RTL simulation system implemented as a computer device may include an HDEVS type RTL-DEVS simulator capable of simulation together with an open source RTL design tool, as functions not implemented in open source RTL design tools are added through the HDEVS-based RTL design tool.

Description

HDEVS based RTL design tool with co-simulator for reducing semiconductor design and verification process cost}

The description below describes a technique that can complement open source RTL (register transfer level) design tools.

Semiconductors are a very large-scale business worldwide, and the verification process before semiconductor wafer fabrication is a process that takes a long time and money. Various open source RTL design tools are currently being used in the industry for logic design and simulation during the semiconductor process.

These open-source RTL design tools have many functional limitations in motion design and simulation.

If a designer wants to perform motion simulation of new constraints, he or she can add a function by developing a new code of an existing open source RTL design tool. Alternatively, you can pay a license fee and use offshore commercial RTL design tools.

However, both methods require a large amount of money and a lot of time. In the case of additional development of open source, it is difficult to find a sweet spot because time and human costs are high, and when commercial RTL design tools are used, a lot of cost is incurred from the logic design stage to simulation.

Because of this, small and medium-sized fabless companies, excluding some large companies, face significant barriers from chip design to production process, and it is necessary to study ways to reduce the burden in the front-end stage.

A hybrid discrete event system specification (HDEVS)-based RTL design tool and complex simulator for reducing semiconductor design process costs may be provided.

A computer device comprising at least one processor configured to execute computer readable instructions contained in a memory, wherein the at least one processor includes a function not implemented in an open source register transfer level (RTL) design tool HDEVS ( hybrid discrete event system specification) based RTL design tool provides a computer device including an RTL-DEVS simulator in the form of HDEVS capable of simulation along with the open source RTL design tool.

According to one aspect, the at least one processor may provide integrated simulation through the open source RTL design tool and the RTL-DEVS simulator when the definition of design requirements for the semi-structured model is given as a factor.

According to another aspect, the at least one processor may perform a synthesis step when all simulations are satisfied through double validation using the open source RTL design tool and the RTL-DEVS simulator.

According to another aspect, the unimplemented function may be redefined as the RTL-DEVS model and designed as a library implementation.

According to another aspect, the at least one processor may include a converter that converts an operation of an RTL-DEVS model described in a semi-structured data format into a hardware description language (HDL).

According to an embodiment of the present invention, costs from RTL design to verification after HDL conversion among semiconductor front-end design steps can be greatly improved through a DEVS-based model capable of supplementing an open source RTL design tool.

According to an embodiment of the present invention, it is possible to minimize the situation of returning to the logic design stage in the back-end design process, and it is easy to expand new simulation functions in the future.

1 is a block diagram for explaining an example of an internal configuration of a computer device according to an embodiment of the present invention.
Figure 2 shows an outline of RTL-DEVS to which an open source non-implemented simulator function is added in one embodiment of the present invention.
3 shows RTL design and simulation steps in one embodiment of the present invention.
FIG. 4 is a flow chart of a semiconductor design process and a diagram for explaining the effect of RTL design and verification failures on the entire process according to an embodiment of the present invention.
5 is a schematic diagram of an HDEVS complex simulator with an open source simulator according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Embodiments of the present invention relate to techniques that can complement open source RTL design tools.

Embodiments including those specifically disclosed herein may provide an HDEVS-based RTL design tool and complex simulator for reducing semiconductor design process costs.

1 is a block diagram illustrating an example of a computer device according to one embodiment of the present invention. For example, the RTL simulation system according to embodiments of the present invention may be implemented by the computer device 100 shown in FIG. 1 .

As shown in FIG. 1, the computer device 100 is a component for executing the RTL simulation method according to embodiments of the present invention, and includes a memory 110, a processor 120, a communication interface 130, and an input/output. Interface 140 may be included.

The memory 110 is a computer-readable recording medium and may include a random access memory (RAM), a read only memory (ROM), and a permanent mass storage device such as a disk drive. Here, a non-perishable mass storage device such as a ROM and a disk drive may be included in the computer device 100 as a separate permanent storage device distinct from the memory 110. Also, an operating system and at least one program code may be stored in the memory 110 . These software components may be loaded into the memory 110 from a recording medium readable by a separate computer from the memory 110 . The separate computer-readable recording medium may include a computer-readable recording medium such as a floppy drive, a disk, a tape, a DVD/CD-ROM drive, and a memory card. In another embodiment, software components may be loaded into the memory 110 through the communication interface 130 rather than a computer-readable recording medium. For example, software components may be loaded into memory 110 of computer device 100 based on a computer program installed by files received over network 160 .

The processor 120 may be configured to process commands of a computer program by performing basic arithmetic, logic, and input/output operations. Instructions may be provided to processor 120 by memory 110 or communication interface 130 . For example, processor 120 may be configured to execute received instructions according to program codes stored in a recording device such as memory 110 .

The communication interface 130 may provide a function for the computer device 100 to communicate with other devices through the network 160 . For example, a request, command, data, file, etc. generated according to a program code stored in a recording device such as the memory 110 by the processor 120 of the computer device 100 is transmitted to the network ( 160) to other devices. Conversely, signals, commands, data, files, etc. from other devices may be received by the computer device 100 via the communication interface 130 of the computer device 100 via the network 160 . Signals, commands, data, etc. received through the communication interface 130 may be transmitted to the processor 120 or the memory 110, and files, etc. may be stored as storage media that the computer device 100 may further include (described above). permanent storage).

The communication method is not limited, and may include not only a communication method utilizing a communication network (eg, a mobile communication network, wired Internet, wireless Internet, and broadcasting network) that the network 160 may include, but also short-distance wired/wireless communication between devices. there is. For example, the network 160 may include a personal area network (PAN), a local area network (LAN), a campus area network (CAN), a metropolitan area network (MAN), a wide area network (WAN), and a broadband network (BBN). , one or more arbitrary networks such as the Internet. In addition, the network 160 may include any one or more of network topologies including a bus network, a star network, a ring network, a mesh network, a star-bus network, a tree or a hierarchical network, and the like. Not limited.

The input/output interface 140 may be a means for interface with the input/output device 150 . For example, the input device may include devices such as a microphone, keyboard, camera, or mouse, and the output device may include devices such as a display and a speaker. As another example, the input/output interface 140 may be a means for interface with a device in which functions for input and output are integrated into one, such as a touch screen. The input/output device 150 and the computer device 100 may be configured as one device.

Also, in other embodiments, computer device 100 may include fewer or more elements than those of FIG. 1 . However, there is no need to clearly show most of the prior art components. For example, the computer device 100 may be implemented to include at least a portion of the above-described input/output device 150 or may further include other components such as a transceiver, a camera, various sensors, and a database.

Hereinafter, specific embodiments of an HDEVS-based RTL design tool and complex simulator for reducing semiconductor design process costs will be described.

DEVS (discrete event system specification) simulation tools enable implementation of the RTL verification step.

In this embodiment, functions lacking in existing open source RTL design tools are designed as a DEVS model, and an HDEVS (hybrid DEVS) type RTL-DEVS simulator capable of simulation with existing open source RTL design tools is provided.

Accordingly, functions that cannot be provided by existing open source simulation tools can be designed and simulated with RTL-DEVS, and through this, it is possible to verify that RTL design specifications are satisfied.

Double validation using the open source RTL design tool and the RTL-DEVS simulation tool becomes possible, and only when both simulations are satisfied, it is possible to proceed to the synthesis stage.

Desired functions can be quickly described using the RTL-DEVS model. In addition, the defined model can be integrated and simulated with the existing DEVS simulator without developing a separate tool.

Through this, the license cost and verification time in the RTL design stage can be reduced, and the accuracy of operation can be increased.

Figure 2 shows an outline of RTL-DEVS to which an open source non-implemented simulator function is added in one embodiment of the present invention.

Referring to FIG. 2 , the processor 120 determines hardware description language (HDL) requirements based on the DEVS theory for semiconductor design.

The RTL-DEVS model can replace existing open source RTL design tools for some functions, and will operate in a complementary form that provides additional modeling and simulation for functions that existing open source RTL design tools cannot provide. can

First, the RTL-level design specifications to be modeled in RTL-DEVS are defined by comparing and analyzing the functions of existing open source RTL design tools and commercial RTL design tools. Through structural analysis of existing open source tools, simulation requirements for simulation operations are defined.

The implementation of the model defined in RTL-DEVS is redesigned into HDL using existing open source tools, and the simulation results of the two models are analyzed to verify the RTL-DEVS operation model.

The processor 120 performs a compiler from DEVS HDL to HDL. For synthesis, a tool called a compiler is often used. If the designer describes the operation of the RTL-DEVS Model in the form of semi-structured data, a converter that converts it to HDL is used. Semi-structured data is a data type such as json, xml, or yaml, and has the characteristics of being able to be freely and quickly described in the format. Designers can quickly define models with RTL-DEVS and validate them in the DEVS environment. After that, convert it to HDL and perform equivalence verification in the existing open source RTL tool.

Processor 120 determines a simulator for design verification. The most important verification method is simulation. HDL is used for simulation as well as hardware description.

In this embodiment, as a simulation tool, a DEVS simulator for RTL-DEVS models is used along with an open source RTL tool.

Based on the generalized model, the RTL-DEVS operation model is defined and the design tool library using the RTL-DEVS model is defined. The absent functions of existing open source tools can be redefined as RTL-DEVS model and designed as a library implementation.

Design as a library using RTL-DEVS for main functions that existing open source tools cannot provide at the HDL specification level (eg, RTL-DEVS for Gate, RTL-DEVS for UDP, etc.). It is designed as a library that supports various simulation types that existing open source tools cannot provide in the simulation operation method (for example, RTL-DEVS for MultiClock source). The HDL model that has already been developed and verified as a commercial tool is redesigned and simulated with the RTL-DEVS library, and the operation of the library is verified by comparing and analyzing it with the HDL-based model that has been previously verified.

The present embodiments provide an HDEVS-based RTL design tool that works together with an open source RTL design tool in a semiconductor process. To solve the cost issue of the front-end process during the semiconductor design process, ① RTL-DEVS model specification design, ② RTL-DEVS model operation design and verification, ③ RTL-DEVS library design and verification, ④ Through RTL-DEVS to HDL converter design and ⑤ HDEVS simulator development, the limited open-source RTL design tool can be combined with the highly scalable, low-cost HDEVS-based RTL design tool to increase design efficiency.

Modern integrated circuit design work is divided into three phases: electronic system level (ESL) design, RTL design or verification, and physical chip design. Among the design stages, RTL design is a very important stage for designing and verifying combinatorial and sequential logic.

Figure 3 shows the RTL design and simulation steps.

Despite the importance of the RTL design stage, various open source RTL design tools such as MyHDL are being used due to the problem of very expensive license fees for HDL language-based design tools.

The introduction of open source software at the semiconductor design stage theoretically has many advantages due to the use of open source, such as increased efficiency in terms of prototype development time and cost, community-based group verification, etc. The downside is that it is difficult to continuously update the latest technology.

Since various lack of verification in the RTL stage can be a factor that causes a requirement specification violation in a back-end design process such as circuit design after logic design, as many verifications as possible should be performed in the RTL design stage.

However, a high-level internal structure analysis is required to add functions equivalent to commercial design tools to open source RTL design tools, and adding new functions requires much greater time and human resources than the cost of using commercial design tools. There may be a cost.

Recently, studies to improve the cost and verification structure by applying HDEVS to the semiconductor design process after RTL are being actively conducted.

RTL design work also requires verification structure improvement for effective cost saving, and HDEVS can be a new alternative for RTL design verification. If functions that existing open source RTL design tools cannot provide can be easily extended through HDEVS-based RTL design tools, more diverse verification at the design operation design level is possible without paying expensive license fees for commercial tools.

Therefore, design utility can be increased by reducing the frequency of repeated redesign due to violation of various requirements occurring after logic synthesis.

The HDEVS-based RTL design tool, which works together with the open source RTL design tool, includes the following details (see Figure 2).

1) RTL-DEVS model specification design

2) RTL-DEVS model operation design and verification

3) Development of design tool library using RTL-DEVS

4) Design of RTL-DEVS to HDL Converter

5) HDEVS-based RTL-DEVS with open source RTL design tool simulator design

4 is a diagram for explaining the effect of a semiconductor design process flow and RTL design and verification failure on the entire process.

The present invention can provide a DEVS simulator that can operate in complementarity with an open source RTL design tool. 1) Conduct comparative evaluation of the characteristics of existing design tools and the DEVS-based simulation method. 2) Design RTL based on the DEVS model and verify whether its operation matches the existing HDL-based operation. 3) The simulator is upgraded in the form of HDEVS based on the above comparative evaluation results and verification results.

5 shows a schematic diagram of an HDEVS complex simulator with an open source simulator.

If the designer defines the design requirements for the semi-structured model and passes it as a factor, it is possible to implement an integrated simulator that automatically verifies RTL-DEVS and open source tools. can provide a simulation of

As described above, according to the embodiments of the present invention, through the DEVS-based model that can complement the open source RTL design tool, the cost of RTL design and verification after HDL conversion during the semiconductor front-end design stage can be greatly improved, and the back-end design In the process, the situation of returning to the logic design stage can be minimized.

Since model verification at the RTL level is possible through DEVS, the procedure is relatively shorter in time than using the existing open source code, and the procedure can be shortened.

DEVS describes the transition of motion as a mathematical model, which makes the motion form simpler and clearer than the design at the HDL level. Through this, it enables mathematical verification primarily and quickly at the level of specification definition and implementation. This has the advantage of preventing some design problems found in the simulation process later.

Describe the model with DEVS and verify its operation with the DEVS simulator. Therefore, no matter how complex the operation is, it can be solved simply with the design specification of the DEVS model. This can effectively reduce both the time cost of additionally developing open source tools to add features and the financial cost of paying for overseas licenses and using commercial tools.

The devices described above may be implemented as hardware components, software components, and/or a combination of hardware components and software components. For example, devices and components described in the embodiments include processors, controllers, arithmetic logic units (ALUs), digital signal processors, microcomputers, field programmable gate arrays (FPGAs), and programmable PLUs. logic unit), microprocessor, or any other device capable of executing and responding to instructions, one or more general purpose or special purpose computers. The processing device may run an operating system (OS) and one or more software applications running on the operating system. A processing device may also access, store, manipulate, process, and generate data in response to execution of software. For convenience of understanding, there are cases in which one processing device is used, but those skilled in the art will understand that the processing device includes a plurality of processing elements and/or a plurality of types of processing elements. It can be seen that it can include. For example, a processing device may include a plurality of processors or a processor and a controller. Other processing configurations are also possible, such as parallel processors.

Software may include a computer program, code, instructions, or a combination of one or more of the foregoing, which configures a processing device to operate as desired or processes independently or collectively. You can command the device. The software and/or data may be embodied in any tangible machine, component, physical device, computer storage medium or device to be interpreted by or to provide instructions or data to a processing device. there is. Software may be distributed on networked computer systems and stored or executed in a distributed manner. Software and data may be stored on one or more computer readable media.

The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer readable medium. In this case, the medium may continuously store a program executable by a computer or temporarily store the program for execution or download. In addition, the medium may be various recording means or storage means in the form of a single or combined hardware, but is not limited to a medium directly connected to a certain computer system, and may be distributed on a network. Examples of the medium include magnetic media such as hard disks, floppy disks and magnetic tapes, optical recording media such as CD-ROM and DVD, magneto-optical media such as floptical disks, and ROM, RAM, flash memory, etc. configured to store program instructions. In addition, examples of other media include recording media or storage media managed by an app store that distributes applications, a site that supplies or distributes various other software, and a server.

As described above, although the embodiments have been described with limited examples and drawings, those skilled in the art can make various modifications and variations from the above description. For example, the described techniques may be performed in an order different from the method described, and/or components of the described system, structure, device, circuit, etc. may be combined or combined in a different form than the method described, or other components may be used. Or even if it is replaced or substituted by equivalents, appropriate results can be achieved.

Therefore, other implementations, other embodiments, and equivalents of the claims are within the scope of the following claims.

Claims (5)

In a computer device,
at least one processor configured to execute computer readable instructions contained in memory;
including,
The at least one processor,
RTL-DEVS in the form of HDEVS that can be simulated together with the open source RTL design tool as functions not implemented in the open source RTL (register transfer level) design tool are added through the HDEVS (hybrid discrete event system specification)-based RTL design tool. simulator
A computer device comprising a. According to claim 1,
The at least one processor,
Providing integrated simulation through the open source RTL design tool and the RTL-DEVS simulator when the definition of design requirements for the semi-structured model is given as a factor
Characterized by a computer device. According to claim 1,
The at least one processor,
Performing a synthesis step when all simulations are satisfied through double verification using the open source RTL design tool and the RTL-DEVS simulator
Characterized by a computer device. According to claim 1,
The unimplemented function is redefined as the RTL-DEVS model and designed as a library implementation.
Characterized by a computer device. According to claim 1,
The at least one processor,
A converter that converts the operation of the RTL-DEVS model described in the form of semi-structured data into HDL (Hardware Description Language)
A computer device comprising a.

Images