KR20220162016A - Imgae sensor - Google Patents

Abstract

Provided is an image sensor with improved product reliability. The image sensor comprises: a substrate including a first surface and a second surface opposite to each other; a first focus pixel including a 1-1 sub pixel and a 1-2 sub pixel consecutively arranged in a first direction in the substrate; a first merged pixel including a 1-1 unit pixel and a 1-2 unit pixel consecutively arranged in the first direction, and a 1-3 unit pixel consecutively arranged to the 1-1 unit pixel in a second direction crossing the first direction, in the substrate; a second merged pixel including a 2-1 unit pixel and a 2-2 unit pixel consecutively arranged to the 1-2 unit pixel in the first direction, and a 2-3 unit pixel consecutively arranged to the 2-2 unit pixel in the second direction, in the substrate; a first color filter overlapping with the first focus pixel on the first surface of the substrate; a second color filter overlapping with the first merged pixel on the first surface of the substrate; a third color filter overlapping with the second merged pixel on the first surface of the substrate; a grid pattern which separates the first to third color filter and is not arranged in the first to third color filter, wherein the grid pattern is installed on the first surface of the substrate; a first micro lens covering the 1-1 sub pixel and the 1-2 sub pixel on the first color filter; and a second micro lens covering each of the 1-1 to 1-3 unit pixel and the 2-1 to 2-3 unit pixel on the second and third color filters. The 1-3 unit pixel, the first focus pixel, and the 2-3 unit pixel are consecutively arranged in the first direction, and the width of the grid pattern between the first color filter and the second color filter is wider than the width of the grid between the second color filter and the third color filter. Moreover, a semiconductor package is provided.

Description

Image sensor {IMGAE SENSOR}

The present invention relates to an image sensor.

An image sensor is one of semiconductor devices that converts optical information into electrical signals. Such an image sensor may include a charge coupled device (CCD) image sensor and a complementary metal-oxide semiconductor (CMOS) image sensor.

The image sensor may be configured in the form of a package. At this time, the package protects the image sensor and has a structure in which light can be incident to the photo receiving surface or sensing area of the image sensor. may consist of

Recently, a backside illumination (BSI) image sensor in which incident light is radiated through a back surface of a semiconductor substrate is being researched so that pixels formed in the image sensor have improved light reception efficiency and light sensitivity.

A technical problem to be solved by the present invention is to provide an image sensor with improved product reliability.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

An image sensor according to some embodiments of the present invention for achieving the above technical problem is a substrate including a first surface and a second surface that are opposite to each other, and the substrate 1-1 continuously arranged along a first direction in the substrate. and a first focus pixel composed of the 1-2 sub-pixels, the 1-1 and 1-2 unit pixels continuously arranged along the first direction within the substrate, and the 1-1 unit pixels and the first direction A first merge pixel including 1-3 unit pixels continuously arranged along a second direction crossing each other, in a substrate, 2-1 and 2-th unit pixels continuously arranged along a first direction with 1-2 unit pixels 2-2 unit pixels, and a second merge pixel including the 2-2 unit pixels and the 2-3 unit pixels continuously arranged along the second direction, on the first surface of the substrate, the first focus pixels and A first color filter overlapping, a second color filter overlapping the first merge pixel on the first side of the substrate, a third color filter overlapping the second merge pixel on the first side of the substrate, a first color filter overlapping the second merge pixel on the first side of the substrate, On one surface, a grid pattern separating first to third color filters but not disposed within the first to third color filters, a first covering the first to first and first to second subpixels on the first color filter a micro lens, and a second micro lens covering the 1-1st to 1-3th unit pixels and the 2-1st to 2-3th unit pixels on the second and third color filters, respectively; The -3 unit pixels, the first focus pixel, and the second to third unit pixels are continuously arranged along the first direction, and the width of the grid pattern between the first color filter and the second color filter is It is greater than the width of the grid between the color filters.

An image sensor according to some embodiments of the present invention for achieving the above technical problem is a substrate including a first surface and a second surface that are opposite to each other, and the substrate 1-1 continuously arranged along a first direction in the substrate. and first merge pixels including first-second unit pixels, first-first and first-second sub-pixels arranged consecutively in a first direction in a substrate, wherein the first merge pixels and the first merge pixels are arranged in a first direction. including first focus pixels arranged consecutively in a second direction intersecting the first focus pixels, second unit pixels arranged in two rows and two columns within the substrate, and successively along the first direction with the first merged pixels and the first focus pixels; Arranged second merge pixels, including third unit pixels arranged in 2 rows and 2 columns, within the substrate, and arranged consecutively with the first focus pixels in the second direction, within the substrate, arranged in 2 rows and 2 columns a fourth unit pixel, and the fourth merge pixel is sequentially arranged in a first direction with the third merge pixel, each of the 1-1 and 1-2 sub-pixels, the 1-1 and 1-2 sub-pixels in the substrate; 1-2 unit pixels, a pixel separation pattern separating second to fourth unit pixels, a first color filter overlapping a first focus pixel on a first surface of a substrate, a first color filter overlapping a first focus pixel on a first surface of a substrate, a second color filter overlapping the merge pixel, a third color filter overlapping the second merge pixel, on the first surface of the substrate, a fourth color filter overlapping the third merge pixel, on the first surface of the substrate; a fifth color filter overlapping the fourth merged pixel on the first surface of the substrate, and separating the first to fifth color filters by at least partially overlapping the pixel isolation pattern on the first surface of the substrate; A grid pattern not disposed within the 5 color filters, a first microlens covering the 1-1 and 1-2 sub-pixels on the first color filter, and each of the 1-1 and 1-2 sub-pixels on the second to fifth color filters. A second microlens covering the first and second unit pixels, the third unit pixels, and the fourth unit pixels, wherein the first color filter is the same as the second and fifth color filters or the third and fourth color filters. have color do

An image sensor according to some embodiments of the present invention for achieving the above technical problem is a substrate including a first surface and a second surface that are opposite to each other, and the substrate 1-1 continuously arranged along a first direction in the substrate. and first merge pixels including 1-2 unit pixels and 1-3 and 1-4 unit pixels continuously arranged along the first direction, within the substrate, continuously arranged along the first direction. 2-1 and 2-2 unit pixels, and 2-3 and 2-4 unit pixels continuously arranged along a first direction, and a first merge pixel and a first merged pixel are continuously arranged along a first direction. a second merge pixel, a third unit pixel, a first focus pixel, and a fourth unit pixel continuously arranged along a first direction within a substrate, a fifth unit pixel continuously arranged along a first direction; a second focus pixel and a sixth unit pixel, on the first surface of the substrate, respectively the first focus pixel, the second focus pixel, the first merge pixel, the second merge pixel, the third unit pixel, the fourth unit pixel; A fifth unit pixel and first to eighth color filters overlapping the sixth unit pixel, separating the first to eighth color filters on the first surface of the substrate but not disposed within the first to eighth color filters First focus pixels, 1-1st to 1-4th unit pixels, 2-1st to 2-4th unit pixels, and 3rd unit pixels on the grid pattern and the first to eighth color filters, respectively. , a microlens covering the first focus pixel, the fourth unit pixel, the fifth unit pixel, the second focus pixel, and the sixth unit pixel, wherein the first focus pixel is continuously arranged along the first direction; 1st and 1st-2nd subpixels, the second focus pixel is composed of 2nd-1st and 2nd-2nd subpixels arranged consecutively along the first direction, the 5th unit pixel and the 3rd unit pixel , The 1-3th unit pixels and the 1-1st unit pixels are continuously arranged along a second direction crossing the first direction, and the sixth unit pixel, the fourth unit pixel, the 2nd-4th unit pixel and the second -2 unit pixel is the second The first and second color filters include the same color filters as the fourth, fifth, and seventh color filters, or the third, sixth, and eighth color filters.

Details of other embodiments are included in the detailed description and drawings.

1 is a block diagram illustrating an image sensing device according to some embodiments.
2 is a block diagram illustrating an image sensor according to some embodiments.
3 is a schematic layout diagram illustrating a light receiving area of an image sensor according to some embodiments.
FIG. 4A is an exemplary partial layout diagram for explaining a first pixel group disposed in a first area of FIG. 3 .
FIG. 4B is an exemplary partial layout diagram for describing a first pixel group disposed in a second area of FIG. 3 .
5A is a cross-sectional view taken along line A-A' of FIG. 4A.
5B is a cross-sectional view taken along line BB′ of FIG. 4A.
6 to 8 are cross-sectional views illustrating an image sensor according to some embodiments.
9 to 17 are exemplary partial layout diagrams for describing a first pixel group disposed in a first area of FIG. 3 .
FIG. 18A is an exemplary partial layout diagram for explaining a second pixel group disposed in a first area of FIG. 3 . FIG. 18B is an exemplary partial layout diagram for describing a second pixel group disposed in a second area of FIG. 3 .
FIG. 19A is an exemplary partial layout diagram for explaining a third pixel group disposed in the first area of FIG. 3 .
FIG. 19B is an exemplary partial layout diagram for describing a third pixel group disposed in a second area of FIG. 3 .
FIG. 20 is an exemplary partial layout diagram for explaining a third pixel group disposed in the first area of FIG. 3 .
21 and 22 are exemplary partial layout diagrams for explaining a first pixel group disposed in a first area of FIG. 3 .
FIG. 23 is an exemplary partial layout diagram for describing a first pixel group disposed in a first area of FIG. 3 .
24 and 25 are exemplary partial layout diagrams for describing a third pixel group disposed in the first area of FIG. 3 .
26 and 27 are cross-sectional views illustrating an image sensor according to some embodiments.
28 is a schematic cross-sectional view illustrating an image sensor according to some embodiments.
29 is a block diagram for describing an image sensor according to some embodiments.
30 is a block diagram of an electronic device including a multi-camera module.
31 is a detailed block diagram of the camera module of FIG. 30 .

1 is a block diagram illustrating an image sensing device according to some embodiments.

Referring to FIG. 1 , an image sensing device 1 according to some embodiments may include an image sensor 10 and an image signal processor 20 .

The image sensor 10 may generate an image signal IS by sensing an image of a sensing target using light. In some embodiments, the generated image signal IS may be, for example, a digital signal, but embodiments according to the technical idea of the present invention are not limited thereto.

The image signal IS may be provided to and processed by the image signal processor 20 . The image signal processor 20 may receive the image signal IS output from the buffer unit 17 of the image sensor 10 and process or process the received image signal IS to facilitate display.

In some embodiments, the image signal processor 20 may perform digital binning on the image signal IS output from the image sensor 10 . At this time, the image signal IS output from the image sensor 10 may be a raw image signal from an active pixel sensor array (APS Array) 15 without analog binning, or analog binning has already been performed. It may also be the performed image signal IS.

In some embodiments, the image sensor 10 and the image signal processor 20 may be disposed separately from each other as shown. For example, the image sensor 10 may be mounted on a first chip and the image signal processor 20 may be mounted on a second chip to communicate with each other through a predetermined interface. However, the embodiments are not limited thereto, and the image sensor 10 and the image signal processor 20 may be implemented in one package, for example, a multi-chip package (MCP).

The image sensor 10 includes an active pixel sensor array 15, a control register block 11, a timing generator 12, a row driver 14, a read-out circuit 16, and a ramp signal generator 13 and a buffer unit 17.

The control register block 11 may control the overall operation of the image sensor 10 . In particular, the control register block 11 may directly transmit an operation signal to the timing generator 12 , the ramp signal generator 13 , and the buffer unit 17 .

The timing generator 12 may generate a signal serving as a reference for operating timings of various components of the image sensor 10 . The operation timing reference signal generated by the timing generator 12 may be transmitted to the ramp signal generator 13 , the row driver 14 , the read-out circuit 16 , and the like.

The ramp signal generator 13 may generate and transmit a ramp signal used in the read-out circuit 16 . For example, the lead-out circuit 16 may include a correlated double sampler (CDS), a comparator, and the like, and the ramp signal generator 13 may generate and transmit a ramp signal used for the correlated double sampler and the comparator.

Row driver 14 may selectively activate a row of active pixel sensor array 15 .

The active pixel sensor array 15 may sense an external image. The active pixel sensor array 15 may include a plurality of pixels.

The read-out circuit 16 samples the pixel signal provided from the active pixel sensor array 15, compares it with the ramp signal, and converts the analog image signal (data) into a digital image signal (data) based on the comparison result. can be converted

The buffer unit 17 may include, for example, a latch unit. The buffer unit 17 may temporarily store the image signal IS to be provided externally, and transmit the image signal IS to an external memory or an external device.

2 is a block diagram illustrating an image sensor according to some embodiments.

Referring to FIG. 2 , the image sensor 10 of this embodiment may include a first chip 30 and a second chip 40 stacked. The second chip 40 may be stacked on the first chip 30 in the third direction DR3 , for example.

The first chip 30 may include a sensor array area SAR, a connection area CR, and a pad area PR.

The sensor array area SAR may include an area corresponding to the active pixel sensor array 15 of FIG. 1 . For example, a plurality of pixels arranged two-dimensionally (eg, in a matrix form) may be disposed in the sensor array area SAR. The sensor array area SAR may include a light receiving area APS and a light blocking area OB. Active pixels receiving light and generating active signals may be arranged in the light receiving area APS. Optical black pixels generating an optical black signal by blocking light may be arranged in the light blocking area OB. For example, the light blocking area OB may be formed along the periphery of the light receiving area APS, but this is only exemplary.

In some embodiments, the photoelectric conversion layer may not be formed in a portion of the light blocking area OB. Also, in some embodiments, dummy pixels may be formed in the light receiving area APS adjacent to the light blocking area OB.

The connection region CR may be formed around the sensor array region SAR. The connection region CR may be formed on one side of the sensor array region SAR, but this is only exemplary. Wires may be formed in the connection region CR to transmit and receive electrical signals of the sensor array region SAR.

The pad area PR may be formed around the sensor array area SAR. The pad region PR may be formed adjacent to an edge of the image sensor according to some embodiments, but this is merely exemplary. The pad area PR may be configured to be connected to an external device and transmit/receive electrical signals between the image sensor and the external device according to some embodiments.

The connection region CR is illustrated as being interposed between the sensor array region SAR and the pad region PR, but it is only exemplary. Of course, arrangements of the sensor array region SAR, the connection region CR, and the pad region PR may vary as needed.

The second chip 40 may be disposed under the first chip 30 and may include a logic circuit area LC. The second chip 40 may be electrically connected to the first chip 30 . The logic circuit region LC of the second chip 18 may be electrically connected to the sensor array region SAR through, for example, the pad region PR of the first chip 30 .

The logic circuit area LC may include a plurality of devices for driving the sensor array area SAR. The logic circuit area LC may include, for example, the control register block 11 of FIG. 1 , the timing generator 12 , the ramp signal generator 13 , the row driver 14 , the read out circuit 16 , and the like. can

3 is a schematic layout diagram illustrating a light receiving area of an image sensor according to some embodiments. FIG. 4A is an exemplary partial layout diagram for explaining a first pixel group disposed in a first area of FIG. 3 . FIG. 4B is an exemplary partial layout diagram for describing a first pixel group disposed in a second area of FIG. 3 . 5A is a cross-sectional view taken along line A-A' of FIG. 4A. 5B is a cross-sectional view taken along line BB′ of FIG. 4A.

Referring to FIG. 3 , a plurality of pixels generating electrical signals by receiving light may be disposed in a light receiving area APS of an image sensor according to some embodiments. A plurality of pixels may be arranged two-dimensionally (eg, in a matrix form) in a plane including the first and second directions DR1 and DR2 .

The light-receiving area APS may include pixel groups PG1, PG2, and PG3 disposed in the first area and pixel groups PG1', PG2', and PG3' disposed in a second area different from the first area. .

Referring to FIG. 4A , the first pixel group PG1 disposed in the first area includes first focus pixels FP11 and PF12, first merge pixels PX11 to PX14, second merge pixels PX21 to PX24, A third merged pixel PX31 - PX33 and a fourth merged pixel PX41 - PX43 may be included. That is, the first area may be an area including the first focus pixels FP11 and FP12.

The first merged pixels PX11 - PX14 may include first unit pixels PX11 - PX14 arranged in two rows and two columns. The 1-1st and 1-2th unit pixels PX11 and PX12 may be continuously arranged along the first direction DR1, and the 1st-3rd and 1-4th unit pixels PX13 and PX14 may be continuously arranged along the first direction DR1. The 1st-3rd and 1-1st unit pixels PX113 and PX11 may be continuously arranged along the second direction DR2, and the 1st-4th and 1-2nd unit pixels PX14 and PX12 are They may be continuously arranged along two directions DR2. The first direction DR1 may be a row direction, and the negative second direction DR2 may be a column direction.

In the present specification, “arranging two unit pixels in succession” may mean that no unit pixel is disposed between the two unit pixels.

The first merge pixels PX11 to PX14 may share the first color filter RP, receive light passing through the first color filter RP, and generate electrical signals.

The first merge pixels PX11 - PX14 and the second merge pixels PX21 - PX24 may be continuously arranged along the first direction DR1 . The second merged pixels PX21 - PX24 may include second unit pixels PX21 - PX24 arranged in two rows and two columns.

The second merge pixels PX21 to PX24 may share the second color filter GP, receive light passing through the second color filter GP, and generate electrical signals.

The third merge pixels PX31 - PX33 and the first merge pixels PX11 - PX14 may be continuously arranged along the second direction DR2 . The third merged pixel PX31 - PX33 may include third unit pixels PX31 - PX34 . The 3-1st unit pixel PX31 and the 1-3rd unit pixel PX13 may be continuously arranged in the second direction DR2 . The 3-2nd and 3-1st unit pixels PX32 and PX33 may be continuously arranged along the second direction DR2, and the 3-2nd and 3-3rd unit pixels PX32 and PX33 are It may be continuously arranged along the first direction DR1.

The third merge pixels PX31 to PX33 may share the second color filter GP, receive light passing through the second color filter GP, and generate electrical signals.

The fourth merge pixels PX41 - PX43 and the second merge pixels PX21 - PX24 may be continuously arranged along the second direction DR2 . The fourth merged pixel PX41 - PX43 may include fourth unit pixels PX41 - PX43 . The 4-1st unit pixel PX41 and the 2-4th unit pixel PX24 may be continuously arranged along the second direction DR2 . The 4-2nd and 4-1st unit pixels PX42 and PX41 may be continuously arranged along the second direction DR2, and the 4-3rd and 4-2nd unit pixels PX43 and PX42 are It may be continuously arranged along the first direction DR1.

The fourth merge pixels PX41 to PX43 may share the third color filter BP, receive light passing through the third color filter BP, and generate electrical signals.

The first focus pixels FP11 and FP12 may be disposed between the third merge pixels PX31 - PX33 and the fourth merge pixels PX41 - PX43 in the first direction DR1 . The first focus pixels FP11 and FP12 may include first subpixels FP11 and FP12 arranged in one row and two columns. The 3-1st unit pixel PX31 , the first sub-pixels FP11 and FP12 , and the 4-1st unit pixel PX41 may be continuously arranged along the first direction DR1 .

The position and number of the first focus pixels FP11 and FP12 are not limited thereto. For example, the first focus pixels FP11 and FP12 may be disposed at positions of the 3-3 and 4-3 unit pixels PX33 and PX43 in FIG. 4A , and The pixels PX33 and PS43 may be disposed at positions of the first focus pixels FP11 and FP12 in FIG. 4A .

The first focus pixels FP11 and FP12 may perform an auto focus (AF) function. An auto focus function may be performed using the phase detection AF (PDAF) using the first subpixels FP11 and FP12 .

The first focus pixels FP11 and FP12 may share the second color filter GP, receive light passing through the second color filter GP, and generate electrical signals.

In some embodiments, the first color filter RP, the second color filter GP, and the third color filter BP may filter different colors. For example, the first color filter RP is a red color filter, the second color filter GP is a green color filter, and the third color filter BP is a blue color filter. can

In some embodiments, the first color filter RP, the second color filter GP, and the third color filter BP may be arranged in a Bayer pattern. For example, two second color filters GP may be arranged along a diagonal direction other than the first and second directions DR1 and DR2 . The first color filter RP may be arranged along one second color filter GP and the first direction DR1 and may be arranged along the second direction DR2 with the other second color filter GP. can In addition, the third color filter BP is arranged along one second color filter GP and the second direction DR2, and along the other second color filter GP and the first direction DR1. can be arranged The first color filter RP and the third color filter BP may be arranged along a diagonal direction other than the first and second directions DR1 and DR2 .

In some embodiments, the grid pattern 150 includes a second color filter GP disposed on the first focus pixels FP11 and FP12, first merge pixels PX11 to PX14, and second merge pixels PX21 to PX24. ), the first to third color filters RP, GP, and BP disposed on the third merge pixels PX31 to PX33 and the fourth merge pixels PX41 to PX44 may be separated. Hereinafter, it will be described in detail with reference to FIGS. 4A, 5A and 5B.

Referring to FIGS. 4A, 5A, and 5B , an image sensor according to some embodiments includes a first substrate 110, a photoelectric conversion layer 112, a first pixel separation pattern 120, and a first electronic element TR1. , a first interconnection structure IS1 , a surface insulating film 140 , a color filter 170 , a grid pattern 150 and a micro lens 180 .

The first substrate 110 may be a semiconductor substrate. For example, the first substrate 110 may be bulk silicon or silicon-on-insulator (SOI). The first substrate 110 may be a silicon substrate or may include other materials, such as silicon germanium, indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the first substrate 110 may have an epitaxial layer formed on the base substrate.

The first substrate 110 may include a first surface 110a and a second surface 110b that are opposite to each other. In embodiments described later, the first surface 110a may be referred to as a back side of the first substrate 110, and the second surface 110b may be referred to as a front side of the first substrate 110. ) can be referred to as In some embodiments, the first surface 110a of the first substrate 110 may be a light receiving surface through which light is incident. That is, the image sensor according to some embodiments may be a backside illuminated (BSI) image sensor.

The photoelectric conversion layer 112 may be formed in the first substrate 110 . The plurality of photoelectric conversion layers 112 may be arranged to correspond to the pixels FP11, FP12, PX11-PX14, PX21-PX24, PX31-PX33, and PX41-PX43. For example, the photoelectric conversion layers 112 are arranged two-dimensionally (eg, in a matrix form) in a plane including the first direction X and the second direction Y, so that each pixel FP11 , FP12, PX11-PX14, PX21-PX24, PX31-PX33, PX41-PX43). The photoelectric conversion layer 112 may generate charge in proportion to the amount of light incident from the outside.

The photoelectric conversion layer 112 may be formed by doping impurities into the first substrate 110 . For example, the photoelectric conversion layer 112 may be formed by implanting n-type impurities into the p-type first substrate 110 . In some embodiments, the photoelectric conversion layer 112 may have a potential gradient in a direction crossing the surface of the first substrate 110 (eg, the first surface 110a or the second surface 110b). have. For example, the impurity concentration of the photoelectric conversion layer 112 may decrease from the second surface 110b toward the first surface 110a.

The photoelectric conversion layer 112 may include, for example, a photo diode, a photo transistor, a photo gate, a pinned photo diode, an organic photo diode, It may include at least one of a quantum dot and a combination thereof, but is not limited thereto.

The first pixel isolation pattern 120 may be formed in the first substrate 110 . The first pixel isolation pattern 120 includes the first subpixels FP11 and FP12, the first unit pixels PX11 to PX14, the second unit pixels PX21 to PX24, and the first subpixels FP11 and FP12 in the first substrate 110 Three unit pixels PX31 - PX33 and fourth unit pixels PX41 - PX43 may be defined. For example, the first pixel separation pattern 120 is formed in a lattice shape when viewed in plan view, and each of the first subpixels FP11 and FP12 and the first unit pixels PX11 to PX14 are arranged in a matrix form. , may surround the second unit pixels PX21 - PX24 , the third unit pixels PX31 - PX33 , and the fourth unit pixels PX41 - PX43 .

In some embodiments, the first pixel isolation pattern 120 may pass through the first substrate 110 . For example, the first pixel isolation pattern 120 may continuously extend from the second surface 110b of the first substrate 110 to the first surface 110a of the first substrate 110 .

In some embodiments, the width of the first pixel isolation pattern 120 in the first direction DR1 may be constant as it moves away from the second surface 110b of the first substrate 110 . In the present specification, "same" means not only the completely same thing, but also a subtle difference that may occur due to a margin in the process.

Alternatively, in some embodiments, the width of the first pixel isolation pattern 120 may decrease as the distance from the second surface 110b of the first substrate 110 increases. This may be due to characteristics of an etching process for forming the first pixel separation pattern 120 . For example, a process of etching the first substrate 110 to form the first pixel isolation pattern 120 may be performed on the second surface 110b of the first substrate 110 .

In some embodiments, the first pixel isolation pattern 120 may include a conductive filling pattern 122 and an insulating spacer layer 124 . The conductive filling pattern 122 may pass through the first substrate 110 , and the insulating spacer layer 124 may be disposed between the conductive filling pattern 122 and the first substrate 110 .

For example, in the first substrate 110, the first subpixels FP11 and FP12, the first unit pixels PX11 to PX14, the second unit pixels PX21 to PX24, and the third unit pixels Separation trenches may be formed to define (PX31-PX33) and fourth unit pixels (PX41-PX43). An insulating spacer layer 124 may extend along side surfaces of the isolation trench. A conductive filling pattern 122 may be formed on the insulating spacer layer 124 to fill the remaining area of the isolation trench. The insulating spacer layer 124 may electrically insulate the conductive filling pattern 122 from the first substrate 110 .

The conductive filling pattern 122 may include, for example, poly-Si, but is not limited thereto. In some embodiments, a ground voltage or a negative voltage may be applied to the conductive filling pattern 122 . In this case, ESD (electrostatic discharge) bruise failure of the image sensor can be effectively prevented. Here, the ESD bruise defect refers to a phenomenon in which electric charges generated by ESD accumulate on the first substrate 110 and cause spots, such as bruises, on an image.

The insulating spacer layer 124 may include, for example, at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof, but is not limited thereto. In some embodiments, the insulating spacer layer 124 may include a low refractive index material having a lower refractive index than that of the first substrate 110 . In this case, the insulating spacer layer 124 refracts or reflects light obliquely incident to the photoelectric conversion layer 112 , thereby improving light condensing efficiency and thus improving the quality of the image sensor. In addition, the insulating spacer film 124 allows photocharges generated in specific pixels (FP11, FP12, PX11-PX14, PX21-PX24, PX31-PX33, PX41-PX43) by incident light to be adjacent to each other by random drift. It can be prevented from moving to the corresponding pixels (FP11, FP12, PX11-PX14, PX21-PX24, PX31-PX33, PX41-PX43).

The first electronic element TR1 may be formed on the second surface 110b of the first substrate 110 . The first electronic device TR1 may include various transistors for processing electrical signals generated from the pixels FP11, FP12, PX11-PX14, PX21-PX24, PX31-PX33, and PX41-PX43. For example, the first electronic element TR1 may include transistors such as a transfer transistor, a reset transistor, a source follower transistor, or a selection transistor.

In some embodiments, the first electronic device TR1 may include a vertical transfer transistor. For example, a portion of the first electronic device TR1 including the transfer transistor may extend into the first substrate 110 . Such a transfer transistor TG can reduce the area of the pixels FP11, FP12, PX11-PX14, PX21-PX24, PX31-PX33, and PX41-PX43, enabling high integration of the image sensor.

The first interconnection structure IS1 may be formed on the second surface 110b of the first substrate 110 . The first interconnection structure IS1 may include one or a plurality of interconnections. For example, the first interconnection structure IS1 may include a first interconnection insulating layer 130 and a plurality of first interconnections 132 within the first interconnection insulating layer 130 . In FIGS. 5A and 5B , the number and arrangement of layers constituting the first interconnection structure IS1 are merely illustrative, and the technical spirit of the present invention is not limited thereto.

In some embodiments, the first wiring 132 may be electrically connected to the pixels FP11, FP12, PX11-PX14, PX21-PX24, PX31-PX33, and PX41-PX43. For example, the first wire 132 may be connected to the first electronic element TR1.

The surface insulating layer 140 may be formed on the first surface 110a of the first substrate 110 . The surface insulating layer 140 may extend along the first surface 110a of the first substrate 110 . The surface insulating layer 140 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, and combinations thereof, but is not limited thereto.

In some embodiments, the surface insulating layer 140 may be formed of a multilayer. For example, the surface insulating layer 140 may include an aluminum oxide layer, a hafnium oxide layer, a silicon oxide layer, a silicon nitride layer, and a hafnium oxide layer sequentially stacked on the first surface 110a of the first substrate 110 .

The surface insulating layer 140 may function as an antireflection layer to prevent reflection of light incident on the first substrate 110 . Accordingly, the light receiving rate of the photoelectric conversion layer 112 may be improved. In addition, the surface insulating film 140 functions as a planarization film and can form the color filter 170 and the micro lens 180 to have a uniform height.

The color filter 170 may be formed on the first surface 110a of the first substrate 110 . For example, the color filter 170 may be formed on the surface insulating layer 140 . The plurality of color filters 170 may be arranged two-dimensionally (eg, in a matrix form) in a plane including the first and second directions DR1 and DR2 . A first color filter RP may be disposed on the first merge pixels PX11 - PX14 , the first focus pixels FP11 and FP12 , the second merge pixels PX21 - PX24 , and the third merge pixel PX31 . - The second color filter GP may be disposed on the PX33, and the third color filter BP may be disposed on the fourth merge pixels PX41 to PX44.

The grid pattern 150 may be formed on the first surface 110a of the first substrate 110 . For example, the grid pattern 150 may be formed on the surface insulating layer 140 .

The grid pattern 150 may surround the first focus pixels FP11 and FP12 in a plan view. The grid pattern 150 may surround the second color filter GP disposed on the first focus pixels FP11 and FP12. Accordingly, the second color filters GP disposed on the first focus pixels FP11 and FP12 may be separated from the surrounding color filters 170 by the grid pattern 150 .

In some embodiments, the grid pattern 150 may be disposed between color filters that are adjacent to each other and having different color filters, and may not be disposed between color filters that are adjacent to each other and have the same color filters.

The grid pattern 150 is formed in a lattice shape when viewed in plan view, and includes first focus pixels FP11 and FP12, first merge pixels PX11 to PX14, second merge pixels PX21 to PX24, and third merge pixels PX31. -PX33) and the fourth merged pixels PX41 -PX43, the first focus pixels FP11 and FP12, the first merged pixels PX11 -PX14, the second merged pixels PX21 -PX24, It may not be disposed inside the 3 merge pixels PX31 - PX33 and the 4 merge pixels PX41 - PX43 . For example, the grid pattern 150 includes first focus pixels FP11 and FP12, first merge pixels PX11 to PX14, second merge pixels PX21 to PX24, third merge pixels PX31 to PX33, and It may be formed to overlap the first pixel separation pattern 120 between the fourth merged pixels PX41 to PX43. Accordingly, the first color filter RP on the first merge pixels PX11 to PX14, the second color filter GP on the first focus pixels FP11 and FP12, and the second color filter GP on the second merge pixels PX21 to PX24. The two color filters GP, the second color filters GP on the third merge pixels PX31 to PX33, and the third color filters BP on the fourth merge pixels PX41 to PX44 may be separated.

In some embodiments, the width W1 between the first focus pixels FP11 and FP12 and the merge pixels PX11-PX14, PX21-PX24, PX31-PX33, and PX41-PX43 in the first direction DR1 is the merge pixel It may be greater than the width W2 between (PX11-PX14, PX21-PX24, PX31-PX33, PX41-PX43).

For example, the width W1 of the grid pattern 150 in the first direction DR1 between the first focus pixels FP11 and FP12 and the third merge pixels PX31 to PX33 is the first focus pixel ( It may be larger than the width W2 of the grid pattern 150 in the first direction DR1 between the FP11 and FP12 and the fourth merged pixels PX41 to PX43 . That is, the width W1 of the grid pattern 150 between the 1-1st subpixel FP11 and the 3-1st unit pixel PX31 is It may be greater than the width W2 of the grid pattern 150 between the pixels PX41. Accordingly, the separation ratio characteristic of the phase difference of the first focus pixels FP11 and FP12 may be improved.

The first subpixels FP11 and FP12 may share the second color filter GP, the first unit pixels PX11 to PX14 may share the first color filter RP, and The unit pixels PX21 to PX24 may share the second color filter GP, the third unit pixels PX31 to PX33 may share the second color filter GP, and the fourth unit pixel PX41 to PX43 may share the third color filter BP.

In some embodiments, the grid pattern 150 may pass through a portion of the color filter 170 , and an upper surface of the grid pattern 150 may be disposed lower than an upper surface of the color filter 170 . Alternatively, the grid pattern 150 may pass through the color filter 170 so that the top surface of the grid pattern 150 and the top surface of the color filter 170 may be substantially coplanar.

In some embodiments, grid pattern 150 may include metal pattern 152 and low refractive index pattern 154 . The metal pattern 152 and the low refractive index pattern 154 may be sequentially stacked on the surface insulating layer 140 .

The metal pattern 152 may include, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), aluminum (Al), copper (Cu), and the like. It may include at least one of the combinations of, but is not limited thereto. In some embodiments, the metal pattern 152 including the metal pattern prevents charges generated by ESD or the like from being accumulated on the surface (eg, the first surface 110a) of the first substrate 110, ESD puncture defects can be effectively prevented.

The low refractive index pattern 154 may include a low refractive index material having a lower refractive index than silicon (Si). For example, the low refractive index pattern 154 may include at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof, but is not limited thereto. The low refractive index pattern 154 refracts or reflects obliquely incident light, thereby improving light condensing efficiency, thereby improving the quality of the image sensor.

In some embodiments, a first protective layer 160 may be further formed on the surface insulating layer 140 and the grid pattern 150 . For example, the first passivation layer 160 may conformally extend along the upper surface of the surface insulating layer 140 and the profile of the side surface and upper surface of the grid pattern 150 . The first passivation layer 160 may be interposed between the surface insulating layer 140 and the color filter 170 and between the grid pattern 150 and the color filter 170 .

The first protective layer 160 may prevent damage to the surface insulating layer 140 and the grid pattern 150 . The first passivation layer 160 may include, for example, aluminum oxide, but is not limited thereto.

The micro lens 180 may be formed on the first surface 110a of the first substrate 110 . For example, the micro lenses 180 may be formed on the color filters 170 . For example, the plurality of micro lenses 180 may be arranged two-dimensionally (eg, in a matrix form) in a plane including the first and second directions DR1 and DR2 .

The plurality of micro lenses 180 may be arranged to correspond to each of the first to fourth unit pixels PX11-PX14, PX21-PX24, PX31-PX33, and PX41-PX43. The plurality of micro lenses 180 may cover each of the first to fourth unit pixels PX11 - PX14 , PX21 - PX24 , PX31 - PX33 , and PX41 - PX43 on the color filter 170 .

The micro lens 180 may be disposed on the color filter 170 to correspond to the first focus pixels FP11 and FP12. The microlens 180 may cover all of the first subpixels FP11 and FP12 on the color filter 170 . For example, the width of the microlens 180 covering the first focus pixels FP11 and FP12 in the first direction DR1 is equal to the width of each of the first to fourth unit pixels PX11-PX14, PX21-PX24, and PX31. -It may be larger than the width of the micro lens 180 covering PX33, PX41-PX43).

The micro lens 180 may have a convex shape and may have a predetermined radius of curvature. Accordingly, the micro lens 180 may condense light incident on the photoelectric conversion layer 112 . The micro lens 180 may include, for example, a light-transmitting resin, but is not limited thereto.

In some embodiments, a second passivation layer 185 may be further formed on the micro lens 180 . The second passivation layer 185 may extend along the surface of the micro lens 180 . The second passivation layer 185 may include an inorganic oxide. For example, the second passivation layer 185 may include at least one of silicon oxide, titanium oxide, zirconium oxide, hafnium oxide, and combinations thereof, but is not limited thereto. For example, the second passivation layer 185 may include low temperature oxide (LTO).

The second passivation layer 185 may protect the micro lens 180 from the outside. For example, the second passivation layer 185 including an inorganic oxide may cover and protect the micro lens 180 including an organic material such as a light-transmitting resin. In addition, the second passivation layer 185 can improve the quality of the image sensor by improving the light collecting efficiency of the micro lens 180 . For example, the second passivation layer 185 may reduce reflection, refraction, and scattering of incident light reaching the space between the micro lenses 180 by filling the space between the micro lenses 180 .

Meanwhile, referring to FIG. 4B , the first pixel group PG1' disposed in the second area includes the first merged pixels PX11-PX14, the second merged pixels PX21-PX24, and the third merged pixels PX31-PX34. ) and fourth merged pixels PX41 to PX44. That is, the first pixel group PG1' disposed in the second area may be an area that does not include the first focus pixels (FP11 and FP12 in FIG. 4A).

The first merged pixels PX11 - PX14 may include first unit pixels PX11 - PX14 arranged in two rows and two columns. The second merged pixels PX21 - PX24 may include second unit pixels PX21 - PX24 arranged in two rows and two columns. The third merged pixel PX31 - PX34 may include third unit pixels PX31 - PX34 arranged in two rows and two columns. The fourth merged pixel PX41 - PX44 may include fourth unit pixels PX41 - PX44 arranged in two rows and two columns.

In plan view, the grid pattern 150 includes the first merged pixels PX11 to PX14, the second merged pixels PX21 to PX24, the third merged pixels PX31 to PX33, and the fourth merged pixels PX41 to PX43. may surround the first merge pixel PX11-PX14, the second merge pixel PX21-PX24, the third merge pixel PX31-PX33, and the fourth merge pixel PX41-PX43. have.

In order to improve the performance of an image sensor, a merge pixel in which a plurality of adjacent unit pixels share one color filter is used. For example, such merged pixels may operate as one pixel in a dark place to provide a bright image, and may be re-mosaic in a bright place to provide a detailed image.

In a plan view, when the grid pattern 150 surrounds each unit pixel within one merged pixel, a light receiving area of each unit pixel within one merged pixel may be reduced due to the grid pattern 150 . Accordingly, sensitivity of each unit pixel may decrease and signal-to-noise ratio (SNR) characteristics may deteriorate.

However, in the image sensor according to some embodiments, the grid pattern 150 surrounds each merged pixel in a planar view and does not enclose each unit pixel within one merged pixel. Accordingly, sensitivity and/or SNR of each unit pixel in one merged pixel may be improved.

Also, from a planar perspective, the grid pattern 150 surrounds the focus pixel even if the focus pixel and the neighboring merged pixels have the same color filter. Accordingly, the auto focus performance of the focus pixel may be maintained. Accordingly, an image sensor having improved and/or improved quality may be provided.

6 to 8 are cross-sectional views illustrating an image sensor according to some embodiments. For reference, FIGS. 6 to 8 are cross-sectional views taken along A-A' of FIG. 4A. For convenience of explanation, parts overlapping with those described above with reference to FIGS. 1 to 5 are briefly described or omitted.

Referring to FIG. 6 , in some embodiments, the second pixel isolation pattern 125 may be formed in the first substrate 110 . The second pixel isolation pattern 125 may define the 3-1st unit pixel PX31 , the first sub-pixels FP11 and FP12 , and the 4-1st unit pixel PX41 . For example, the second pixel separation pattern 125 is formed in a lattice shape when viewed in plan view, and each of the first sub-pixels FP11 and FP12 arranged in a matrix form, the first unit pixels (FIG. 4A and FIG. PX11-PX14 in FIG. 4B), second unit pixels (PX21-PX24 in FIGS. 4A and 4B), third unit pixels (PX31-PX33 in FIGS. 4A and 4B) and fourth unit pixels (PX21-PX24 in FIGS. 4A and 4B). PX41-PX43 in FIG. 4b).

The second pixel separation pattern 125 may pass through a portion of the first substrate 110 . For example, the second pixel isolation pattern 125 may partially penetrate the first substrate 110 from the first surface 110a of the first substrate 110 . A lower surface of the second pixel isolation pattern 125 may be disposed in the first substrate 110 .

In some embodiments, the width of the second pixel separation pattern 125 in the first direction DR1 may be constant as it moves away from the second surface 110b of the first substrate 110 .

Alternatively, in some embodiments, the width of the second pixel isolation pattern 125 may increase as the distance from the second surface 110b of the first substrate 110 increases. This may be due to characteristics of an etching process for forming the second pixel separation pattern 125 . For example, a process of etching the first substrate 110 to form the first pixel isolation pattern 120 may be performed on the first surface 110a of the first substrate 110 .

The second pixel isolation pattern 125 may include, for example, an insulating material. The second pixel isolation pattern 125 may include, for example, at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof, but is not limited thereto. In some embodiments, the second pixel separation pattern 125 may include a low refractive index material having a lower refractive index than that of the first substrate 110 .

Referring to FIG. 7 , in some embodiments, the first pixel isolation pattern 120 and the second pixel isolation pattern 125 may be formed in the first substrate 110 . The first pixel isolation pattern 120 and the second pixel isolation pattern 125 define a 3-1st unit pixel PX31 , first sub-pixels FP11 and FP12 , and a 4-1st unit pixel PX41 . can do. For example, the first pixel isolation pattern 120 and the second pixel isolation pattern 125 are formed in a lattice shape from a plan view, and each of the first subpixels FP11 and FP12 arranged in a matrix form, 1 unit pixels (PX11-PX14 in FIGS. 4A and 4B), 2nd unit pixels (PX21-PX24 in FIGS. 4A and 4B), 3rd unit pixels (PX31-PX33 in FIGS. 4A and 4B), and It may surround the fourth unit pixels (PX41-PX43 in FIGS. 4A and 4B).

The first pixel separation pattern 120 may pass through a portion of the first substrate 110 . For example, the first pixel isolation pattern 120 may partially penetrate the first substrate 110 from the second surface 110b of the first substrate 110 . A top surface of the first pixel isolation pattern 120 may be disposed in the first substrate 110 .

The first pixel isolation pattern 120 includes the conductive filling pattern 122 partially penetrating the first substrate 110 from the second surface 110b of the first substrate 110 , and the conductive filling pattern 122 and the first pixel separation pattern 122 . An insulating spacer layer 124 disposed between the substrates 110 may be included.

In some embodiments, the first pixel isolation pattern 120 may be spaced apart from the second pixel isolation pattern 125 within the first substrate 110 . The first pixel isolation pattern 120 extends from the second surface 110b of the first substrate 110 toward the first surface 110a of the first substrate 110 at least along the second pixel isolation pattern 125 . Some may overlap.

The material of the first pixel separation pattern 120 is the same as that described above with reference to FIGS. 1 to 5 . The second pixel isolation pattern 125 is the same as that described above with reference to FIG. 6 .

Referring to FIG. 8 , in some embodiments, at least a portion of the first pixel isolation pattern 120 may contact the second pixel isolation pattern 125 within the first substrate 110 .

In some embodiments, the width of the bottom surface of the first pixel isolation pattern 120 may be the same as the width of the top surface of the second pixel isolation pattern 125 . Alternatively, the width of the lower surface of the first pixel isolation pattern 120 may be different from the width of the upper surface of the second pixel isolation pattern 125 .

The first pixel isolation pattern 120 and the second pixel isolation pattern 125 are the same as those described above with reference to FIG. 6 .

9 to 17 are exemplary partial layout diagrams for describing a first pixel group disposed in a first area of FIG. 3 . For convenience of explanation, parts overlapping with those described above with reference to FIGS. 1 to 5 are briefly described or omitted.

Referring to FIG. 9 , in the first pixel group PG1 according to some embodiments, the first focus pixels FP11 and FP12 include the first merge pixels PX11 to PX13 and the second merge pixels in the first direction DR1. (PX21-PX23).

Specifically, the first merged pixels PX11 - PX13 include the 1st-2nd and 1-1st unit pixels PX12 and PX11 continuously arranged along the second direction DR2 , and the 1st-2nd unit pixels ( PX12) and 1-1st unit pixels PX11 continuously arranged along the first direction DR1.

The second merged pixels PX21 - PX23 include the 2-3rd and 2-2nd unit pixels PX23 and PX22 and the 2-2nd unit pixels PX22 continuously arranged along the first direction DR1. 2-1 unit pixels PX21 continuously arranged along the second direction DR2 may be included.

The 1-1st unit pixel PX11 , the first focus pixels FP11 and FP12 , and the 2-1st unit pixel PX21 may be continuously arranged along the first direction DR1 .

Alternatively, the first focus pixels FP11 and FP12 may be disposed at positions of the 1-3 and 2-3 unit pixels PX13 and PX23 in FIG. 9 , and the 2-3 unit pixels PX13 and PX23 are shown in FIG. 9 may be disposed at positions of the first focus pixels FP11 and FP12.

Referring to FIG. 10 , in the image sensor according to some embodiments, the grid pattern 150 is formed by one merged pixel (PX11-PX14, PX21-PX24, PX31-PX33, PX41-PX43) having the same color filter in a plan view. ) can also be placed in

For example, the grid pattern 150 may surround the 3-1st unit pixel PX31 when viewed in plan view, and may surround the 3-2nd and 3-3rd unit pixels PX31, PX32, and PX33. can The grid pattern 150 includes the second color filter GP disposed on the 3-1st unit pixel PX31 and the 3rd color filter GP disposed on the 3-2nd and 3-3rd unit pixels PX31, PX32 and PX33. The 2 color filters (GP) can be separated.

For example, the grid pattern 150 may surround the 4-1st unit pixel PX41 and may surround the 4-2nd and 4-3rd unit pixels PX42 and PX43 when viewed in plan view. . The grid pattern 150 includes the third color filter BP disposed on the 4-1st unit pixel PX41 and the third color filter BP disposed on the 4-2nd and 4-3th unit pixels PX42 and PX43. The filter BP can be separated.

The grid pattern 150 may prevent crosstalk between unit pixels adjacent to each other within one merged pixel PX11 - PX14 , PX21 - PX24 , PX31 - PX33 , and PX41 - PX43 .

In the image sensor according to some embodiments, the grid pattern 150 forms one merged pixel (PX11-PX14, PX21-PX24, PX31-PX33, PX41- PX43). For example, from a planar perspective, the grid pattern 150 is not disposed within one merged pixel (PX11-PX14, PX21-PX24, PX31-PX33, PX41-PX43), so that the improved sensitivity and/or SNR is obtained from one merged pixel If the grid patterns 150 are arranged in (PX11-PX14, PX21-PX24, PX31-PX33, PX41-PX43) and prevented crosstalk between adjacent unit pixels is less than, the grid pattern 150 is one may be placed in the merged pixels PX11-PX14, PX21-PX24, PX31-PX33, and PX41-PX43. For example, a grid pattern 150 within one merged pixel (PX11-PX14, PX21-PX24, PX31-PX33, PX41-PX43) from a planar point of view according to the location where unit pixels are arranged in the light-receiving area (APS in FIG. 3). ) may vary.

Referring to FIG. 11 , the first pixel group PG1 according to some embodiments may further include second focus pixels FP21 and FP22. The second focus pixels FP21 and FP22 may be disposed at various locations within the first pixel group PG1.

For example, the second focus pixels FP21 and FP22 may be disposed between the first merge pixels PX11 to PX13 and the second merge pixels PX21 to PX23 in the first direction DR1 . The second focus pixels FP21 and FP22 and the first focus pixels FP11 and FP12 may be continuously arranged along the second direction DR2 .

The second focus pixels FP21 and FP22 may perform an auto focus (AF) function. An auto focus function may be performed using the phase detection AF (PDAF) using the second subpixels FP21 and FP22 .

The second focus pixels FP21 and FP22 may share the second color filter GP, receive light passing through the second color filter GP, and generate electrical signals.

The grid pattern 150 may surround the first focus pixels FP11 and FP12 and the second focus pixels FP21 and FP22 when viewed in plan view. Accordingly, the second color filter GP on the first focus pixels FP11 and FP12 may be separated from the second color filter GP on the second focus pixels FP21 and FP22 by the grid pattern 150 .

The grid pattern 150 may surround the third merge pixels PX31 and PX32 and the fourth merge pixels PX41 and PX42 in a plan view.

Referring to FIG. 12 , in a first pixel group PG1 according to some embodiments, a grid pattern 150 surrounds a 3-1st unit pixel PX31 and a 3-2nd unit pixel PX32 from a plan view, respectively. may cover the 4-1st unit pixel PX41 and the 4-2nd unit pixel PX42 respectively. Accordingly, the second color filter GP disposed on the 3-1st unit pixel PX31 and the second color filter GP disposed on the 3-2nd unit pixel PX32 form a grid pattern 150. can be separated by

Alternatively, the grid pattern 150 may be disposed only in one of the third merge pixels PX31 to PX32 and the fourth merge pixels PX41 to PX42 in a plan view.

Referring to FIG. 13 , a first group pixel PG1 according to some embodiments may include first focus pixels FP11 and FP12 and second focus pixels FP21 and FP22 . The first focus pixels FP11 and FP12 and the second focus pixels FP21 and FP22 may be disposed at various locations within the first pixel group PG1.

For example, the second focus pixels FP21 and FP22 and the first focus pixels FP11 and FP12 may be continuously arranged along the second direction DR2 .

The first focus pixels FP11 and FP12 and the second focus pixels FP21 and FP22 may share the second color filter GP, receive light passing through the second color filter GP, and generate electrical signals. can create

The fourth unit pixels PX41 - PX44 may include the fourth unit pixels PX41 - PX44 arranged in two rows and two columns. The first focus pixels FP11 and FP12, the third merge pixels PX31 - PX32 , and the fourth merge pixels PX41 - PX44 may be continuously arranged along the first direction DR1 .

Referring to FIG. 14 , a first group pixel PG1 according to some embodiments includes first focus pixels FP11 and FP12, second focus pixels FP21 and FP22, third focus pixels FP31 and FP32, and a second focus pixel FP11 and FP12. It may include 4 focus pixels FP41 and FP42. The first focus pixels FP11 and FP12, the second focus pixels FP21 and FP22, the third focus pixels FP31 and FP32, and the fourth focus pixels FP41 and FP42 are located at various positions in the first pixel group PG1. can be placed in

For example, the second focus pixels FP21 and FP22 and the first focus pixels FP11 and FP12 may be continuously arranged along the second direction DR2, and the fourth focus pixels FP41 and FP42 and The third focus pixels FP31 and FP32 may be continuously arranged along the second direction DR2 .

The second focus pixels FP21 and FP22 , the third focus pixels FP31 and FP32 , and the fourth focus pixels FP41 and FP42 may perform an auto focus (AF) function.

The first focus pixels FP11 and FP12, the second focus pixels FP21 and FP22, the third focus pixels FP31 and FP32, and the fourth focus pixels FP41 and FP42 share the second color filter GP. In addition, an electrical signal may be generated by receiving light passing through the second color filter GP.

Referring to FIG. 15 , in the first pixel group PG1 according to some embodiments, the third merged pixels PX31 to PX34 may include third unit pixels PX31 to PX34 arranged in two rows and two columns. have. The first merged pixels PX11 - PX12 may include first unit pixels PX11 - PX12 arranged in one row and two columns. The third merge pixels PX31 - PX34 , the first merge pixels PX11 - PX14 , and the first focus pixels FP11 and FP12 may be continuously arranged along the second direction DR2 . The first focus pixels FP11 and FP12 and the first merged pixels PX11 - PX12 , and the second merged pixels PX21 - PX24 may be continuously arranged along the first direction DR1 .

The fourth unit pixels PX41 - PX44 may include the fourth unit pixels PX41 - PX44 arranged in two rows and two columns.

Alternatively, the first focus pixels FP11 and FP12 may be disposed at positions of the first merge pixels PX11 to PX12 in FIG. 15 , and the first merge pixels PX11 to PX12 may correspond to the first focus pixels FP11 and PX12 in FIG. 15 . FP12) may be placed.

Referring to FIG. 16 , in an image sensor according to some embodiments, first focus pixels FP11 and FP12 may be disposed at positions corresponding to one unit pixel. For example, the first focus pixels FP11 and FP12 may be disposed at corresponding positions of one unit pixel adjacent to the 3-2 and 3-3 unit pixels PX32 and PX33.

Referring to FIG. 17 , in the image sensor according to some embodiments, each of the first focus pixels FP11 and FP12 and the second focus pixels FP21 and FP22 may be disposed at a position corresponding to one unit pixel. . For example, the first focus pixels FP11 and FP12 may be disposed at positions corresponding to one unit pixel adjacent to the 3-2 and 3-3 unit pixels PX32 and PX33, and The pixels FP21 and FP22 may be disposed at positions corresponding to one unit pixel adjacent to the 2-1st and 2-3rd unit pixels PX21 and PX23 .

The first focus pixels FP11 and FP12 may include the first-first and first-second sub-pixels FP11 and FP12 continuously arranged along the first direction DR1 , and the second focus pixel FP21 , FP22 may include the 2-2nd and 2-1st sub-pixels FP22 and FP21 continuously arranged along the second direction DR2.

FIG. 18A is an exemplary partial layout diagram for explaining a second pixel group disposed in a first area of FIG. 3 . FIG. 18B is an exemplary partial layout diagram for describing a second pixel group disposed in a second area of FIG. 3 . For convenience of explanation, parts overlapping with those described above with reference to FIGS. 1 to 5 are briefly described or omitted.

Referring to FIG. 18A , the second pixel group PG2 disposed in the first area includes first focus pixels FP11 and FP12 and first to fourth merged pixels PX11-PX19, PX21-PX29, PX31-PX38, PX41-PX48) may be included.

The first merged pixel PX11 - PX19 may include first unit pixels PX11 - PX19 arranged in 3 rows and 3 columns. The second merged pixel PX21 - PX29 may include second unit pixels PX21 - PX29 arranged in 3 rows and 3 columns.

The third merged pixel PX31 - PX38 may include third unit pixels PX31 - PX38 . The 3-1 to 3-3 unit pixels PX31 to PX33 are the same as those described above with reference to FIG. 4A. The 3-6th, 3-5th, and 3-4th unit pixels PX36 , PX35 , and PX34 may be continuously arranged along the second direction DR2 , and 3-8 unit pixels PX36, PX37, and PX38 may be continuously arranged along the first direction DR1.

The fourth merged pixel PX41 - PX48 may include fourth unit pixels PX41 - PX48 . The 4-6th, 4-5th, and 4-4th unit pixels PX46 , PX45 , and PX44 may be continuously arranged along the second direction DR2 , and 4-6 unit pixels PX48 , PX47 , and PX46 may be continuously arranged along the first direction DR1 .

The first focus pixels FP11 and FP12 may be disposed between the third merge pixels PX31 - PX33 and the fourth merge pixels PX41 - PX43 in the first direction DR1 .

The grid pattern 150 may surround the first focus pixels FP11 and FP12 and the first to fourth merge pixels PX11 to PX19, PX21 to PX29, PX31 to PX38, and PX41 to PX48 when viewed in plan view, It may not be disposed inside the first focus pixels FP11 and FP12 and the first to fourth merge pixels PX11 - PX19 , PX21 - PX29 , PX31 - PX38 , and PX41 - PX48 .

Referring to FIG. 18B , the second pixel group PG2' disposed in the second area may include first to fourth merged pixels PX11-PX19, PX21-PX29, PX31-PX39, and PX41-PX49. have. Each of the first to fourth unit pixels PX11-PX19, PX21-PX29, PX31-PX38, and PX41-PX48 are arranged in three rows and three columns, respectively. PX29, PX31-PX38, PX41-PX48).

FIG. 19A is an exemplary partial layout diagram for explaining a third pixel group disposed in the first area of FIG. 3 . FIG. 19B is an exemplary partial layout diagram for describing a third pixel group disposed in a second area of FIG. 3 . For convenience of explanation, parts overlapping with those described above with reference to FIGS. 1 to 5 are briefly described or omitted.

Referring to FIG. 19A , the first pixel group PG3 disposed in the first area includes first focus pixels FP11 and FP12 and first to fourth merged pixels PX11-PX116, PX21-PX216, PX31-PX315, PX41-PX415) may be included.

The first merged pixel PX11 - PX116 may include first unit pixels PX11 - PX116 arranged in 4 rows and 4 columns. The second merged pixels PX21 - PX216 may include fourth unit pixels PX21 - PX216 arranged in 4 rows and 4 columns.

The third merged pixel PX31 - PX315 may include third unit pixels PX31 - PX38 . The 3-1st to 3-8th unit pixels PX31 to PX33 are the same as those described above with reference to FIG. 17A. The 3-12th, 3-11th, 3-10th, and 3-9th unit pixels PX312, PX311, PX310, and PX39 may be continuously arranged along the second direction DR2, and , 3-13th, 3-14th, and 3-15th unit pixels PX312 , PX313 , PX314 , and PX315 may be continuously arranged along the first direction DR1 .

The fourth merged pixel PX41 - PX415 may include fourth unit pixels PX41 - PX415 . The 4-12th, 4-11th, 4-10th, and 4-9th unit pixels PX412, PX411, PX410, and PX49 may be continuously arranged along the second direction DR2. , 4th to 14th, 4th to 13th, and 4th to 12th unit pixels PX415 , PX414 , PX413 , and PX412 may be continuously arranged along the first direction DR1 .

The first focus pixels FP11 and FP12 may be disposed between the third merge pixels PX31 - PX315 and the fourth merge pixels PX41 - PX415 in the first direction DR1 .

The grid pattern 150 may surround the first focus pixels FP11 and FP12 and the first to fourth merge pixels PX11 to PX116, PX21 to PX216, PX31 to PX315, and PX41 to PX415 when viewed in plan view, It may not be disposed inside the first focus pixels FP11 and FP12 and the first to fourth merge pixels PX11 - PX116 , PX21 - PX216 , PX31 - PX315 , and PX41 - PX415 .

Referring to FIG. 19B , the third pixel group PG3′ disposed in the second area may include first to fourth merged pixels PX11-PX116, PX21-PX216, PX31-PX315, and PX41-PX415. have. Each of the first to fourth unit pixels PX11-PX116, PX21-PX216, PX31-PX315, and PX41-PX415 are arranged in 4 rows and 4 columns, respectively. PX216, PX31-PX315, PX41-PX415).

FIG. 20 is an exemplary partial layout diagram for explaining a third pixel group disposed in the first area of FIG. 3 . For convenience of explanation, the overlapping parts with those described above with reference to FIG. 19A are briefly described or omitted.

Referring to FIG. 20 , in some embodiments, the grid pattern 150 may include 3-1 to 3-3 unit pixels PX31 to PX33 and 4-1 to 4-3 unit pixels PX41 in a plan view. -PX43), four first unit pixels arranged in 2 rows and 2 columns within the first merge pixels PX11-PX116, and four first unit pixels arranged in 2 rows and 2 columns within the second merge pixels PX21-PX216 2 unit pixels, four third unit pixels arranged in 2 rows and 2 columns within the third merge pixels PX31-PX318, and four fourth unit pixels arranged in 2 rows and 2 columns within the fourth merge pixels PX41-PX415 Unit pixels may be surrounded. Accordingly, the first unit pixels arranged in two rows and two columns may share one first color filter RP, and the second unit pixels arranged in two rows and two columns may share one second color filter GP. Third unit pixels arranged in 2 rows and 2 columns may share one second color filter GP, and fourth unit pixels arranged in 2 rows and 2 columns may share one third color filter BP. ) can be shared.

The grid pattern 150 may surround the 3-1st to 3-3rd unit pixels PX31 - PX33 when viewed in plan view, and may surround the 4-1st to 4-3rd unit pixels PX41 - PX43 . can surround Accordingly, the 3-1 to 3-3 unit pixels PX31 - PX33 may share one second color filter GP, and the 4-1 to 4-3 unit pixels PX41 - PX33 may share one second color filter GP. PX43) may share one third color filter (BP).

21 and 22 are exemplary partial layout diagrams for explaining a first pixel group disposed in a first area of FIG. 3 . For convenience of explanation, parts overlapping with those described above with reference to FIGS. 1 to 5 are briefly described or omitted.

Referring to FIG. 21 , in some embodiments, a white color filter ( WP) can be placed. Each of the first focus pixels FP11 and FP12 and the first to fourth merge pixels PX11 - PX14 , PX21 - PX24 , PX31 - PX33 , and PX41 - PX43 may share one white color filter WP. .

Referring to FIG. 22 , in some embodiments, a white color filter ( WP) can be placed. The grid pattern 150 may surround the first focus pixels FP11 and FP12 and surround the first to fourth merge pixels PX11-PX14, PX21-PX24, PX31-PX33, and PX41-PX43 when viewed in plan view. may not be Accordingly, the first focus pixels FP11 and FP12 may share one white color filter WP, and the first to fourth merge pixels PX11 to PX14, PX21 to PX24, PX31 to PX33, and PX41 to PX43 may share one white color filter (WP). The white color filters WP on the first focus pixels FP11 and FP12 and the white color filters WP on the first to fourth merge pixels PX11 to PX14, PX21 to PX24, PX31 to PX33, and PX41 to PX43 are arranged in a grid They can be separated by pattern 150 .

FIG. 23 is an exemplary partial layout diagram for describing a first pixel group disposed in a first area of FIG. 3 .

Referring to FIG. 23 , the third merged pixels PX31 - PX32 may include third unit pixels PX31 - PX32 arranged in one row and two columns. The third merge pixel PX31 - PX32 , the first focus pixels FP11 and FP12 , and the first merge pixel PX11 - PX14 may be continuously arranged along the second direction DR2 .

The fourth unit pixels PX41 - PX44 may include the fourth unit pixels PX41 - PX44 arranged in two rows and two columns. The first focus pixels FP11 and FP12, the third merge pixels PX31 - PX32 , and the fourth merge pixels PX41 - PX44 may be continuously arranged along the first direction DR1 .

Alternatively, the first focus pixels FP11 and FP12 may be disposed at positions of the third merge pixels PX31 - PX32 in FIG. 13 , and the third merge pixels PX31 - PX32 may correspond to the first focus pixels FP11 and PX32 in FIG. 13 . FP12) may be placed.

In some embodiments, the first color filter CP1 , the second color filter CP2 , and the third color filter CP3 may filter different colors. For example, each of the first to third color filters CP1 , CP2 , and CP3 may include a red color filter, a yellow filter, and a blue color filter.

For another example, each of the first to third color filters CP1 , CP2 , and CP3 may include a red color filter, a yellow filter, and a cyan filter.

For another example, each of the first to third color filters CP1 , CP2 , and CP3 may include a magenta filter, a yellow filter, and a cyan filter.

In some embodiments, the first focus pixels FP11 and FP12 may share one color filter, and the color filter may follow a location where the first focus pixels FP11 and FP12 are disposed. For example, the first focus pixels FP11 and FP12 may be disposed at positions overlapping the second color filter CP2 . For another example, the first focus pixels FP11 and FP12 may be disposed at overlapping positions with the second color filter CP2 or the third color filter CP3.

24 and 25 are exemplary partial layout diagrams for describing a third pixel group disposed in the first area of FIG. 3 . For convenience of explanation, parts overlapping with those described above with reference to FIG. 20 are briefly described or omitted.

Referring to FIG. 24 , in some embodiments, the grid pattern 150 may separate the color filters on the first focus pixels FP11 and FP12 from neighboring color filters, and may not be disposed between the same color filters. and can be placed between different color filters.

For example, on the first unit pixels PX11 to PX116 and the fourth unit pixels PX41 to PX415, the second color filter GP runs in a diagonal direction between the first and second directions DR1 and DR2. ) may be disposed and a white color filter WP may be disposed in a diagonal direction opposite to the diagonal direction in the second direction DR2 . A first color filter RP may be disposed in the diagonal direction and a white color filter WP may be disposed in the opposite diagonal direction on the second unit pixels PX21 to PX216 . A third color filter BP may be disposed in the diagonal direction on the third unit pixels PX31 to PX315, and a white color filter WP may be disposed in the opposite diagonal direction.

Referring to FIG. 25 , white color filters WP may be disposed in the opposite diagonal direction on the first unit pixels PX11 to PX116 and the fourth unit pixels PX41 to PX415, and in the diagonal direction. A first color filter RP and a second color filter GP may be respectively disposed. A white color filter WP may be disposed in the opposite diagonal direction on the second unit pixels PX21 to PX216 and the third unit pixels PX31 to PX315, and the third color filter BP may be disposed in the diagonal direction. ) and the second color filter GP may be respectively disposed.

26 and 27 are cross-sectional views illustrating an image sensor according to some embodiments. For reference, FIGS. 26 and 27 are cross-sectional views taken along line BB' of FIG. 4B. For convenience of explanation, parts overlapping with those described above with reference to FIGS. 1 to 5 are briefly described or omitted.

Referring to FIGS. 26 and 27 , the image sensor according to some embodiments may further include a sub grid pattern 155 . The sub-grid pattern 155 may be disposed on at least a portion of one merged pixel sharing one color filter.

For example, the sub grid pattern 155 may be disposed on the pixel separation pattern 120 between the 3-2nd unit pixel PX32 and the 3-3rd unit pixel PX33 . The lower portion of the color filter 170 on the 3-2nd unit pixel PX32 and the lower portion of the color filter 170 on the 3-3rd unit pixel PX33 may be separated by the sub-grid pattern 155 .

In some embodiments, the sub-grid pattern 155 may have a lower height than the grid pattern 150 . The top surface of the sub grid pattern 155 may be disposed below the top surface of the grid pattern 150 .

Referring to FIG. 26 , in some embodiments, the sub grid pattern 155 may include the same material as the metal pattern 152 .

Referring to FIG. 27 , in some embodiments, the sub-grid pattern 155 may include the same material as the low refractive index pattern 154 .

28 is a schematic cross-sectional view illustrating an image sensor according to some embodiments. For convenience of explanation, parts overlapping with those described above with reference to FIGS. 1 to 5 are briefly described or omitted.

Referring to FIG. 28 , an image sensor according to some embodiments may include a sensor array area SAR, a connection area CR, and a pad area PR. The sensor array area SAR, connection area CR, and pad area PR may be the sensor array area SAR, connection area CR, and pad area PR of FIG. 2 , respectively. In FIG. 27 exemplarily, the cross-sectional view of FIG. 5A is shown as a cross-sectional view of the sensor array region SAR.

In some embodiments, the first wiring structure IS1 may include the first wiring 132 in the sensor array area SAR and the second wiring 134 in the connection area CR. The first wire 132 may be electrically connected to pixels of the sensor array region SAR. For example, the first wire 132 may be connected to the first electronic element TR1. At least some of the second wires 134 may be electrically connected to at least some of the first wires 132 . For example, at least a portion of the second wiring 134 may extend from the sensor array area SAR. Accordingly, the second wire 134 may be electrically connected to pixels of the sensor array region SAR.

An image sensor according to some embodiments includes a second substrate 210, a second wiring structure IS2, a first connection structure 350, a second connection structure 450 and a third connection structure 550, and a device isolation pattern. 115, a light blocking filter 270C, and a third passivation layer 380 may be further included.

The second substrate 210 may be bulk silicon or silicon-on-insulator (SOI). The second substrate 210 may be a silicon substrate or may include other materials, such as silicon germanium, indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the second substrate 210 may have an epitaxial layer formed on the base substrate.

The second substrate 210 may include a third surface 210a and a fourth surface 210b that are opposite to each other. In some embodiments, the third surface 210a of the second substrate 210 may face the second surface 110b of the first substrate 110 .

In some embodiments, the second electronic element TR2 may be formed on the third surface 210a of the second substrate 210 . The second electronic element TR2 is electrically connected to the sensor array region SAR to transmit and receive electrical signals to and from each pixel of the sensor array region SAR. For example, the second electronic element TR2 constitutes the control register block 11, timing generator 12, ramp signal generator 13, row driver 14, read-out circuit 16, etc. of FIG. It may include electronic elements that do.

The second interconnection structure IS2 may be formed on the third surface 210a of the second substrate 210 . The second interconnection structure IS2 may be attached to the first interconnection structure IS1. For example, as shown in FIG. 16 , the upper surface of the second interconnection structure IS2 may be attached to the lower surface of the first interconnection structure IS1 .

The second interconnection structure IS2 may include one or a plurality of interconnections. For example, the second interconnection structure IS2 may include a second inter-wire insulating film 230 and a plurality of wires 232 , 234 , and 236 within the second inter-wire insulating film 230 . In FIG. 15 , the number and arrangement of layers of the wires constituting the second interconnection structure IS2 are exemplary only, and are not limited thereto.

At least some of the wires 232 , 234 , and 236 of the second interconnection structure IS2 may be connected to the second electronic device TR2 . In some embodiments, the second wiring structure IS2 includes a third wiring 232 in the sensor array area SAR, a fourth wiring 234 in the connection area CR, and a fifth wiring (in the pad area PR). 236) may be included. In some embodiments, the fourth wire 234 may be the uppermost wire among the plurality of wires in the connection area CR, and the fifth wire 236 may be the uppermost wire among the plurality of wires in the pad area PR. can

The first connection structure 350 may be formed in the light blocking area OB. The first connection structure 350 may be formed on the surface insulating layer 140 of the light blocking area OB. In some embodiments, the first connection structure 350 may contact the pixel isolation pattern 120 . For example, a first trench 355t exposing the pixel isolation pattern 120 may be formed in the first substrate 110 and the surface insulating layer 140 of the light blocking region OB. The first connection structure 350 may be formed in the first trench 355t and contact the pixel isolation pattern 120 in the light-blocking area OB. In some embodiments, the first connection structure 350 may extend along profiles of side surfaces and bottom surfaces of the first trench 355t.

In some embodiments, the first connection structure 350 may be electrically connected to the conductive filling pattern 122 to apply a ground voltage or a negative voltage to the conductive filling pattern 122 . Accordingly, electric charges generated by ESD or the like may be discharged to the first connection structure 350 through the conductive filling pattern 122, and an ESD hole defect may be effectively prevented.

The second connection structure 450 may be formed in the connection region CR. The second connection structure 450 may be formed on the surface insulating layer 140 of the connection region CR. The second connection structure 450 may electrically connect the first substrate 110 and the second substrate 210 . For example, the second wiring 134 and the fourth wiring 234 are exposed in the first substrate 110, the first wiring structure IS1, and the second wiring structure IS2 of the connection region CR. A second trench 455t may be formed. The second connection structure 450 may be formed in the second trench 455t to connect the second wire 134 and the fourth wire 234 . In some embodiments, the second connection structure 450 may extend along profiles of side surfaces and bottom surfaces of the second trench 455t.

The third connection structure 550 may be formed in the pad region PR. The third connection structure 550 may be formed on the surface insulating layer 140 of the pad region PR. The third connection structure 550 may electrically connect the second substrate 210 and an external device.

For example, the third trench 550t exposing the fifth interconnection 236 is formed in the first substrate 110, the first interconnection structure IS1, and the second interconnection structure IS2 of the pad region PR. can be formed The third connection structure 550 may be formed in the third trench 550t and contact the fifth wire 236 . In addition, a fourth trench 555t may be formed in the first substrate 110 of the pad region PR. The third connection structure 550 may be formed and exposed in the fourth trench 555t. In some embodiments, the third connection structure 550 may extend along profiles of side surfaces and bottom surfaces of the third trench 550t and the fourth trench 555t.

The first connection structure 350, the second connection structure 450, and the third connection structure 550 may be, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride ( TaN), tungsten (W), aluminum (Al), copper (Cu), and at least one of combinations thereof, but is not limited thereto. In some embodiments, the first connection structure 350 , the second connection structure 450 , and the third connection structure 550 may be formed at the same level as each other. In this specification, "same level" means formed by the same manufacturing process.

In some embodiments, a first pad 355 filling the first trench 355t may be formed on the first connection structure 350 . In some embodiments, a second pad 555 filling the fourth trench 555t may be formed on the third connection structure 550 . Each of the first pad 355 and the second pad 555 is, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof. It may include, but is not limited thereto. In some embodiments, the first pad 355 and the second pad 555 may be formed at the same level as each other.

In some embodiments, a first filling insulating layer 460 filling the second trench 455t may be formed on the second connection structure 450 . In some embodiments, a second filling insulating layer 560 filling the third trench 550t may be formed on the third connection structure 550 . Each of the first filling insulating layer 460 and the second filling insulating layer 560 may include, for example, at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof, but is not limited thereto. In some embodiments, the first filling insulating layer 460 and the second filling insulating layer 560 may be formed at the same level as each other.

In some embodiments, the first passivation layer 160 may cover the first connection structure 350 , the first pad 355 , the second connection structure 450 , and the third connection structure 550 . For example, the first passivation layer 160 conformally extends along the profiles of the first connection structure 350 , the first pad 355 , the second connection structure 450 , and the third connection structure 550 . can In some embodiments, the first passivation layer 160 may expose the second pad 555 .

The device isolation pattern 115 may be formed in the first substrate 110 . For example, a device isolation trench 115t may be formed in the first substrate 110 . The device isolation pattern 115 may be formed in the device isolation trench 115t. In some embodiments, the device isolation pattern 115 may extend from the first surface 110a to the second surface 110b of the first substrate 110 . Alternatively, in some embodiments, the device isolation pattern 115 may be spaced apart from the second surface 110b of the first substrate 110 .

29 is a block diagram for describing an image sensor according to some embodiments. For convenience of explanation, the description will be made focusing on the differences from those described with reference to FIG. 2 .

Referring to FIG. 29 , the image sensor 10' may further include a memory chip 50. The memory chip 50 , the lower chip 40 , and the upper chip 30 may be sequentially stacked in the third direction DR3 . The memory chip 50 may include a memory device. For example, the memory chip 50 may include a volatile memory device such as DRAM and SRAM. The memory chip 50 may receive signals from the upper chip 30 and the lower chip 40 and process the signals through the memory device.

30 is a block diagram of an electronic device including a multi-camera module. 31 is a detailed block diagram of the camera module of FIG. 30 .

Referring to FIG. 30 , the electronic device 1000 may include a camera module group 1100, an application processor 1200, a PMIC 1300, and an external memory 1400.

The camera module group 1100 may include a plurality of camera modules 1100a, 1100b, and 1100c. Although the drawing shows an embodiment in which three camera modules 1100a, 1100b, and 1100c are disposed, the embodiments are not limited thereto. In some embodiments, the camera module group 1100 may be modified to include only two camera modules. Also, in some embodiments, the camera module group 1100 may be modified to include n (n is a natural number of 4 or more) camera modules.

Hereinafter, a detailed configuration of the camera module 1100b will be described in more detail with reference to FIG. 31 , but the following description may be equally applied to other camera modules 1100a and 1100c according to embodiments.

Referring to FIG. 31 , the camera module 1100b includes a prism 1105, an optical path folding element (hereinafter referred to as “OPFE”) 1110, an actuator 1130, an image sensing device 1140, and storage. may include section 1150 .

The prism 1105 may include a reflective surface 1107 of a light reflective material to change a path of light L incident from the outside.

In some embodiments, the prism 1105 may change the path of light L incident in the first direction X to a second direction Y perpendicular to the first direction X. In addition, the prism 1105 rotates the reflective surface 1107 of the light reflecting material in the direction A around the central axis 1106 or rotates the central axis 1106 in the direction B to move in the first direction X. A path of the incident light L may be changed in a second direction Y, which is perpendicular to the second direction Y. At this time, the OPFE 1110 may also move in a third direction (Z) perpendicular to the first direction (X) and the second direction (Y).

In some embodiments, as shown, the maximum angle of rotation of the prism 1105 in the A direction may be less than 15 degrees in the plus A direction and greater than 15 degrees in the minus A direction. However, the embodiments are not limited thereto.

In some embodiments, prism 1105 can move about 20 degrees in the plus or minus B direction, or between 10 and 20 degrees, or between 15 and 20 degrees, where the angle of movement is positive. It can move at the same angle in the (+) or minus (-) B direction, or it can move to an almost similar angle within the range of 1 degree.

In some embodiments, the prism 1105 can move the reflective surface 1106 of the light reflecting material in a third direction (eg, the Z direction) parallel to the extension direction of the central axis 1106 .

The OPFE 1110 may include, for example, optical lenses consisting of m (where m is a natural number) groups. The m lenses may move in the second direction (Y) to change the optical zoom ratio of the camera module 1100b. For example, when the basic optical zoom magnification of the camera module 1100b is Z, when m optical lenses included in the OPFE 1110 are moved, the optical zoom magnification of the camera module 1100b is 3Z or 5Z or It can be changed to an optical zoom magnification of 5Z or higher.

The actuator 1130 may move the OPFE 1110 or an optical lens (hereinafter referred to as an optical lens) to a specific position. For example, the actuator 1130 may adjust the position of the optical lens so that the image sensor 1142 is positioned at the focal length of the optical lens for accurate sensing.

The image sensing device 1140 may include an image sensor 1142 , a control logic 1144 and a memory 1146 . The image sensor 1142 may sense an image of a sensing target using light L provided through an optical lens. The control logic 1144 may control the overall operation of the camera module 1100b. For example, the control logic 1144 may control the operation of the camera module 1100b according to a control signal provided through the control signal line CSLb.

The memory 1146 may store information required for operation of the camera module 1100b, such as calibration data 1147. The calibration data 1147 may include information necessary for the camera module 1100b to generate image data using light L provided from the outside. The calibration data 1147 may include, for example, information about a degree of rotation, information about a focal length, information about an optical axis, and the like, as described above. When the camera module 1100b is implemented in the form of a multi-state camera in which the focal length changes according to the position of the optical lens, the calibration data 1147 is a focal length value for each position (or state) of the optical lens and It may include information related to auto focusing.

The storage unit 1150 may store image data sensed through the image sensor 1142 . The storage unit 1150 may be disposed outside the image sensing device 1140 and may be implemented in a stacked form with a sensor chip constituting the image sensing device 1140 . In some embodiments, the storage unit 1150 may be implemented as an electrically erasable programmable read-only memory (EEPROM), but the embodiments are not limited thereto.

Referring to FIGS. 30 and 31 together, in some embodiments, each of the plurality of camera modules 1100a, 1100b, and 1100c may include an actuator 1130. Accordingly, each of the plurality of camera modules 1100a, 1100b, and 1100c may include the same or different calibration data 1147 according to the operation of the actuator 1130 included therein.

In some embodiments, one of the plurality of camera modules 1100a, 1100b, 1100c (eg, 1100b) is a folded lens including the prism 1105 and the OPFE 1110 described above. camera module, and the remaining camera modules (eg, 1100a, 1100c) may be vertical camera modules that do not include the prism 1105 and the OPFE 1110, but embodiments are limited thereto. it is not going to be

In some embodiments, one camera module (eg, 1100c) among the plurality of camera modules 1100a, 1100b, and 1100c extracts depth information using infrared rays (IR), for example. It may be a depth camera of the form. In this case, the application processor 1200 merges image data provided from the depth camera and image data provided from other camera modules (eg, 1100a or 1100b) to obtain a 3D depth image. can create

In some embodiments, at least two camera modules (eg, 1100a, 1100b) among the plurality of camera modules 1100a, 1100b, and 1100c may have different fields of view (field of view). In this case, for example, optical lenses of at least two camera modules (eg, 1100a, 1100b) among the plurality of camera modules 1100a, 1100b, and 1100c may be different from each other, but the present invention is not limited thereto.

Also, in some embodiments, each of the plurality of camera modules 1100a, 1100b, and 1100c may have different viewing angles. In this case, optical lenses included in each of the plurality of camera modules 1100a, 1100b, and 1100c may also be different from each other, but are not limited thereto.

In some embodiments, each of the plurality of camera modules 1100a, 1100b, and 1100c may be disposed physically separated from each other. That is, the sensing area of one image sensor 1142 is not divided and used by a plurality of camera modules 1100a, 1100b, and 1100c, but an independent image inside each of the plurality of camera modules 1100a, 1100b, and 1100c. A sensor 1142 may be disposed.

Referring back to FIG. 30 , the application processor 1200 may include an image processing device 1210 , a memory controller 1220 , and an internal memory 1230 . The application processor 1200 may be implemented separately from the plurality of camera modules 1100a, 1100b, and 1100c. For example, the application processor 1200 and the plurality of camera modules 1100a, 1100b, and 1100c may be separately implemented as separate semiconductor chips.

The image processing device 1210 may include a plurality of sub image processors 1212a, 1212b, and 1212c, an image generator 1214, and a camera module controller 1216.

The image processing device 1210 may include a plurality of sub image processors 1212a, 1212b, and 1212c corresponding to the number of the plurality of camera modules 1100a, 1100b, and 1100c.

Image data generated from each of the camera modules 1100a, 1100b, and 1100c may be provided to the corresponding sub image processors 1212a, 1212b, and 1212c through separate image signal lines ISLa, ISLb, and ISLc. For example, image data generated from the camera module 1100a is provided to the sub image processor 1212a through the image signal line ISLa, and image data generated from the camera module 1100b is provided to the image signal line ISLb. Image data generated from the camera module 1100c may be provided to the sub image processor 1212c through the image signal line ISLc. Such image data transmission may be performed using, for example, a Camera Serial Interface (CSI) based on MIPI (Mobile Industry Processor Interface), but embodiments are not limited thereto.

Meanwhile, in some embodiments, one sub image processor may be arranged to correspond to a plurality of camera modules. For example, the sub image processor 1212a and the sub image processor 1212c are not separately implemented as shown, but integrated into one sub image processor, and the camera module 1100a and the camera module 1100c Image data provided from may be selected through a selection element (eg, multiplexer) and the like, and then provided to the integrated sub image processor.

Image data provided to each of the sub image processors 1212a, 1212b, and 1212c may be provided to the image generator 1214. The image generator 1214 may generate an output image using image data provided from each of the sub image processors 1212a, 1212b, and 1212c according to image generating information or a mode signal.

Specifically, the image generator 1214 merges at least some of the image data generated from the camera modules 1100a, 1100b, and 1100c having different viewing angles according to image generation information or a mode signal to obtain an output image. can create In addition, the image generator 1214 may generate an output image by selecting any one of image data generated from the camera modules 1100a, 1100b, and 1100c having different viewing angles according to image generation information or a mode signal. .

In some embodiments, the image creation information may include a zoom signal or zoom factor. Also, in some embodiments, the mode signal may be a signal based on a mode selected by a user, for example.

When the image generating information is a zoom signal (zoom factor) and each of the camera modules 1100a, 1100b, and 1100c have different fields of view (viewing angles), the image generator 1214 operates differently according to the type of zoom signal. can be performed. For example, when the zoom signal is the first signal, after merging the image data output from the camera module 1100a and the image data output from the camera module 1100c, the merged image signal and the camera module not used for merging An output image may be generated using the image data output from step 1100b. If the zoom signal is a second signal different from the first signal, the image generator 1214 does not merge the image data and uses any one of the image data output from each of the camera modules 1100a, 1100b, and 1100c. You can choose to generate an output image. However, the embodiments are not limited thereto, and a method of processing image data may be modified and implemented as needed.

In some embodiments, the image generator 1214 receives a plurality of image data having different exposure times from at least one of the plurality of sub image processors 1212a, 1212b, and 1212c, and performs a high dynamic range (HDR) operation on the plurality of image data. ) processing, it is possible to generate merged image data with increased dynamic range.

The camera module controller 1216 may provide a control signal to each of the camera modules 1100a, 1100b, and 1100c. Control signals generated from the camera module controller 1216 may be provided to corresponding camera modules 1100a, 1100b, and 1100c through separate control signal lines CSLa, CSLb, and CSLc.

One of the plurality of camera modules 1100a, 1100b, and 1100c is designated as a master camera (eg, 1100b) according to image generation information including a zoom signal or a mode signal, and the remaining camera modules (eg, 1100b) For example, 1100a and 1100c) may be designated as slave cameras. Such information may be included in the control signal and provided to the corresponding camera modules 1100a, 1100b, and 1100c through separate control signal lines CSLa, CSLb, and CSLc.

Camera modules operating as a master and a slave may be changed according to a zoom factor or an operation mode signal. For example, when the viewing angle of the camera module 1100a is wider than that of the camera module 1100b and the zoom factor indicates a low zoom magnification, the camera module 1100b operates as a master and the camera module 1100a operates as a slave. can act as Conversely, when the zoom factor indicates a high zoom magnification, the camera module 1100a may operate as a master and the camera module 1100b may operate as a slave.

In some embodiments, the control signal provided to each of the camera modules 1100a, 1100b, and 1100c from the camera module controller 1216 may include a sync enable signal. For example, when the camera module 1100b is a master camera and the camera modules 1100a and 1100c are slave cameras, the camera module controller 1216 may transmit a sync enable signal to the camera module 1100b. The camera module 1100b receiving such a sync enable signal generates a sync signal based on the provided sync enable signal, and transmits the generated sync signal to the camera modules (through the sync signal line SSL). 1100a, 1100c). The camera module 1100b and the camera modules 1100a and 1100c may transmit image data to the application processor 1200 in synchronization with the sync signal.

In some embodiments, a control signal provided from the camera module controller 1216 to the plurality of camera modules 1100a, 1100b, and 1100c may include mode information according to the mode signal. Based on this mode information, the plurality of camera modules 1100a, 1100b, and 1100c may operate in a first operation mode and a second operation mode in relation to sensing speed.

The plurality of camera modules 1100a, 1100b, and 1100c generate an image signal at a first rate (eg, generate an image signal having a first frame rate) in a first operation mode, and generate an image signal at a second frame rate higher than the first rate. encoding (eg, encoding an image signal having a second frame rate higher than the first frame rate) and transmitting the encoded image signal to the application processor 1200 . In this case, the second speed may be 30 times or less than the first speed.

The application processor 1200 stores the received image signal, that is, the encoded image signal, in the internal memory 1230 or the external storage 1400 of the application processor 1200, and then the memory 1230 or storage 1200. The encoded image signal may be read and decoded from 1400, and image data generated based on the decoded image signal may be displayed. For example, a corresponding sub-processor among the plurality of sub-processors 1212a, 1212b, and 1212c of the image processing device 1210 may perform decoding and may also perform image processing on the decoded image signal.

The plurality of camera modules 1100a, 1100b, and 1100c generate image signals at a third rate lower than the first rate in the second operation mode (eg, image signals having a third frame rate lower than the first frame rate). generation), and transmit the image signal to the application processor 1200. An image signal provided to the application processor 1200 may be an unencoded signal. The application processor 1200 may perform image processing on a received image signal or store the image signal in the memory 1230 or the storage 1400 .

The PMIC 1300 may supply power, eg, a power supply voltage, to each of the plurality of camera modules 1100a, 1100b, and 1100c. For example, the PMIC 1300 supplies first power to the camera module 1100a through the power signal line PSLa under the control of the application processor 1200, and supplies the first power to the camera module 1100a through the power signal line PSLb ( 1100b) and third power may be supplied to the camera module 1100c through the power signal line PSLc.

The PMIC 1300 may generate power corresponding to each of the plurality of camera modules 1100a, 1100b, and 1100c in response to a power control signal (PCON) from the application processor 1200, and may also adjust the level of the power. . The power control signal PCON may include a power control signal for each operation mode of the plurality of camera modules 1100a, 1100b, and 1100c. For example, the operation mode may include a low power mode, and in this case, the power control signal PCON may include information about a camera module operating in the low power mode and a set power level. Levels of the powers provided to each of the plurality of camera modules 1100a, 1100b, and 1100c may be the same or different from each other. Also, the level of power can be dynamically changed.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to the above embodiments and can be manufactured in a variety of different forms, and those skilled in the art in the art to which the present invention belongs A person will understand that the present invention may be embodied in other specific forms without changing the technical spirit or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting.

100: first substrate 140: surface insulating film
120: first pixel isolation pattern 125: second pixel isolation pattern
150; Grid Pattern 170: Color Filters
180: micro lens

Claims (20)

a substrate including first and second surfaces opposite to each other;
a first focus pixel composed of first-first and first-second sub-pixels continuously arranged in a first direction in the substrate;
In the substrate, 1-1st and 1-2th unit pixels continuously arranged along the first direction, and the 1-1st unit pixels are continuously arranged along a second direction crossing the first direction a first merge pixel including 1st to 3rd unit pixels;
In the substrate, 2-1st and 2-2nd unit pixels continuously arranged along the first direction with the 1-2th unit pixels, and continuous with the 2-2nd unit pixels along the second direction a second merge pixel including 2nd-3rd unit pixels arranged as;
a first color filter overlapping the first focus pixel on the first surface of the substrate;
a second color filter overlapping the first merge pixel on the first surface of the substrate;
a third color filter overlapping the second merge pixel on the first surface of the substrate;
a grid pattern separating the first to third color filters on the first surface of the substrate, but not disposed within the first to third color filters;
a first microlens covering the first-first and first-second sub-pixels on the first color filter; and
A second microlens covering the 1-1st to 1-3th unit pixels and the 2-1st to 2-3th unit pixels on the second and third color filters, respectively;
The first to third unit pixels, the first focus pixel, and the second to third unit pixels are continuously arranged along the first direction;
A width of the grid pattern between the first color filter and the second color filter is greater than a width of the grid between the second color filter and the third color filter. According to claim 1,
The first color filter has the same color as the second color filter and a different color from the third color filter. According to claim 1,
The first to third color filters have the same color as the image sensor. According to claim 1,
In the substrate, 3-1 and 3-2 unit pixels continuously arranged with the 1-3 unit pixels along the second direction, and continuously arranged with the 1-1 sub-pixels along the second direction A third merge pixel including 3-3 and 3-4 unit pixels arranged in
4-1st and 4-2nd unit pixels continuously arranged along the second direction with the 2-3rd unit pixels in the substrate, and continuously arranged with the 1-2th sub-pixels along the second direction A fourth merge pixel including 4th-3rd and 4th-4th unit pixels arranged in
a fourth color filter overlapping the third merge pixel on the first surface of the substrate;
a fifth color filter overlapping the fourth merge pixel on the first surface of the substrate;
a third microlens covering the 3-1st to 3-4th unit pixels and the 4-1st to 4-4th unit pixels on the fourth and fifth color filters;
The grid pattern separates the first to fifth color filters, but is not disposed within the fourth and fifth color filters. According to claim 4,
The first color filter has the same color as the second and fifth color filters;
The third color filter has a color different from that of the first and fourth color filters. According to claim 4,
The first to fifth color filters have the same color as each other. According to claim 4,
The first color filter has a color different from that of the second color filter;
The second to fifth color filters have the same color as the image sensor. According to claim 4,
a fifth merge pixel including fifth unit pixels arranged in four rows and four columns on the substrate and arranged consecutively along the first direction with the second and fourth merge pixels;
a sixth merge pixel including sixth unit pixels arranged in four rows and four columns on the substrate, and arranged consecutively with the third and fourth merge pixels along the second direction;
a seventh merge pixel including seventh unit pixels arranged in four rows and four columns in the substrate, and arranged consecutively with the sixth merge pixel along the first direction;
a sixth color filter overlapping the fifth merge pixel on the first surface of the substrate;
a seventh color filter overlapping the sixth merge pixel on the first surface of the substrate;
an eighth color filter overlapping the seventh merge pixel on the first surface of the substrate;
a fourth microlens covering the fifth to seventh unit pixels on the sixth to eighth color filters;
The grid pattern separates the first to eighth color filters, but is not disposed within the sixth to eighth color filters. According to claim 1,
Pixel separation passing through the substrate to separate the 1-1st and 1-2th sub-pixels, the 1-1st to 1-3th unit pixels, and the 2-1st to 2-3th unit pixels. Including more patterns,
The pixel separation pattern includes a conductive filling pattern penetrating the substrate, and an insulating spacer layer disposed between the conductive filling pattern and the substrate. According to claim 1,
The 1-1st and 1-2th sub-pixels, the 1-1st to 1-3th unit pixels, and the 2-1st to 2nd-th subpixels pass through a portion of the substrate from the first surface of the substrate An image sensor further comprising a first pixel separation pattern that separates 2-3 unit pixels and is made of an insulating material. According to claim 10,
The 1-1st and 1-2th sub-pixels, the 1-1st to 1-3th unit pixels, and the 2-1st to 2nd-th sub-pixels pass through a portion of the substrate from the second surface of the substrate Further comprising a second pixel separation pattern separating 2-3 unit pixels;
The second pixel separation pattern includes a conductive filling pattern penetrating a portion of the substrate, and an insulating spacer layer disposed between the conductive filling pattern and the substrate. According to claim 11,
The first pixel isolation pattern is spaced apart from the second pixel isolation pattern. According to claim 11,
The first pixel isolation pattern is in contact with the second pixel isolation pattern. a substrate including first and second surfaces opposite to each other;
a first merge pixel including first-first and first-second unit pixels continuously arranged along a first direction in the substrate;
In the substrate, 1-1st and 1-2th sub-pixels are continuously arranged along the first direction, and the first merged pixel is continuously arranged in a second direction intersecting the first direction. a first focus pixel;
a second merge pixel including second unit pixels arranged in two rows and two columns in the substrate, and arranged consecutively with the first merge pixel and the first focus pixel along the first direction;
a third merge pixel including third unit pixels arranged in two rows and two columns within the substrate, and arranged consecutively with the first focus pixel in the second direction;
a fourth merge pixel including fourth unit pixels arranged in two rows and two columns within the substrate, and arranged consecutively with the third merge pixel in the first direction;
a pixel separation pattern separating the 1-1st and 1-2th sub-pixels, the 1-1st and 1-2th unit pixels, and the second to fourth unit pixels within the substrate;
a first color filter overlapping the first focus pixel on the first surface of the substrate;
a second color filter overlapping the first merge pixel on the first surface of the substrate;
a third color filter overlapping the second merge pixel on the first surface of the substrate;
a fourth color filter overlapping the third merge pixel on the first surface of the substrate;
a fifth color filter overlapping the fourth merge pixel on the first surface of the substrate;
a grid pattern, on the first surface of the substrate, at least partially overlapping the pixel isolation pattern to separate the first to fifth color filters, but not disposed within the first to fifth color filters;
a first microlens covering the first-first and first-second sub-pixels on the first color filter; and
a second micro lens covering the 1-1st and 1-2th unit pixels, the third unit pixel, and the fourth unit pixel, respectively, on the second to fifth color filters;
The first color filter has the same color as the second and fifth color filters or the third and fourth color filters. According to claim 14,
The first color filter has the same color as the second and fifth color filters;
The third color filter has the same color as the fourth color filter. According to claim 14,
On the first surface of the substrate, any one of the second to fifth color filters is disposed so as to overlap the pixel separation pattern, and the one color filter is converted into two color filters or four color filters. An image sensor further comprising a sub-grid pattern for separating. According to claim 16,
The grid pattern is multi-layered,
The sub-grid pattern is a single layer image sensor. According to claim 16,
An upper surface of the grid pattern is disposed higher than an upper surface of the sub-grid pattern. a substrate including first and second surfaces opposite to each other;
In the substrate, including 1-1st and 1-2th unit pixels continuously arranged along a first direction, and 1-3rd and 1-4th unit pixels continuously arranged along the first direction a first merge pixel;
In the substrate, including 2-1st and 2-2nd unit pixels continuously arranged along a first direction, and 2-3rd and 2-4th unit pixels continuously arranged along the first direction; , second merge pixels arranged consecutively with the first merge pixels along the first direction;
a third unit pixel, a first focus pixel, and a fourth unit pixel continuously arranged in the substrate along the first direction;
a fifth unit pixel, a second focus pixel, and a sixth unit pixel continuously arranged in the substrate along the first direction;
On the first surface of the substrate, each of the first focus pixel, the second focus pixel, the first merge pixel, the second merge pixel, the third unit pixel, the fourth unit pixel, and the first focus pixel first to eighth color filters overlapping five unit pixels and the sixth unit pixel;
a grid pattern separating the first to eighth color filters on the first surface of the substrate, but not disposed within the first to eighth color filters; and
The first focus pixel, the 1-1st to 1-4th unit pixels, the 2-1st to 2-4th unit pixels, and the third unit pixels on the first to eighth color filters, respectively. a micro lens covering a pixel, the first focus pixel, the fourth unit pixel, the fifth unit pixel, the second focus pixel, and the sixth unit pixel;
The first focus pixel is composed of first-first and first-second subpixels continuously arranged along the first direction;
The second focus pixel is composed of 2-1st and 2-2nd sub-pixels continuously arranged along the first direction;
The fifth unit pixel, the third unit pixel, the 1-3 th unit pixel, and the 1-1 th unit pixel are continuously arranged along a second direction crossing the first direction;
The sixth unit pixel, the fourth unit pixel, the 2-4th unit pixel, and the 2-2nd unit pixel are continuously arranged along the second direction;
The first and second color filters include the same color filters as the fourth, fifth, and seventh color filters, or the third, sixth, and eighth color filters. According to claim 19,
The fifth and seventh color filters include the same color filter, and the sixth and eighth color filters include the same color filter.

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