KR20220159856A - Transmitter circuit and operating method thereof - Google Patents

Abstract

A transmitter circuit according to a technical idea of the present disclosure comprises: a clock generator that generates a plurality of first clock signals having phases different from each other; a multiplexer comprising a plurality of selection circuits, each of which selectively provides at least two or more parallel signals among a plurality of parallel signals to an output node in response to at least two or more first clock signals among the plurality of first clock signals; and an output driver that generates a serial signal by amplifying the signal of the output node. Therefore, the present invention is capable of increasing a slew rate of the serial signal.

Description

Transmitter circuit and its operating method {TRANSMITTER CIRCUIT AND OPERATING METHOD THEREOF}

The technical idea of the present disclosure relates to a transmitter circuit, and more particularly, to a transmitter circuit including two or more selection circuits for driving an output node and a method of operating the transmitter circuit.

The transmitter circuit may include a serializer that generates a serial signal by sequentially outputting a plurality of parallel signals. The serializer may sequentially output a plurality of parallel signals based on a plurality of clock signals having different phases. Performance of a serializer may be degraded due to a skew that occurs between a plurality of clock signals.

The technical idea of the present disclosure relates to a transmitter circuit, and provides a transmitter circuit and a method of operating the transmitter circuit to increase a slew rate of a serial signal by driving two or more selection circuits.

In order to achieve the above object, a transmitter circuit according to an aspect of the present disclosure includes a clock generator for generating a plurality of first clock signals having phases different from each other, and at least two or more of the plurality of first clock signals, respectively. Generating a serial signal by amplifying a signal of a multiplexer including a plurality of selection circuits including a plurality of selection circuits selectively providing at least two or more parallel signals among a plurality of parallel signals to an output node in response to the first clock signals Include the output driver.

A transmitter circuit according to another aspect of the present disclosure includes a clock generator generating a plurality of first clock signals having phases different from each other, at least one of a transition signal indicating whether the serial signal is transitioning and a plurality of parallel signals, respectively. A plurality of selection circuits receiving the above parallel signals and driving an output node based on the received signals in response to a plurality of first clock signals, and an output driver generating a serial signal by amplifying a signal of the output node. and at least two or more selection circuits among a plurality of selection circuits simultaneously drive the output node based on whether the serial signal transitions.

A method of operating a transmitter circuit according to another aspect of the present disclosure includes generating a plurality of first clock signals having different phases based on a reference clock signal, each in response to one of the plurality of first clock signals. Among a plurality of selection circuits operating and receiving two or more parallel signals among a plurality of parallel signals, sequentially outputting a plurality of parallel signals by simultaneously using two or more selection circuits to drive an output node, and a signal of the output node Generating a serial signal by amplifying .

According to an exemplary embodiment of the present disclosure, a transmitter circuit and a method of operating the transmitter circuit that increase a slew rate of a serial signal by driving two or more selection circuits may be provided.

1 is a diagram for explaining a transmitter circuit according to an exemplary embodiment of the present disclosure.
2 is a diagram illustrating a serialization operation according to an exemplary embodiment of the present disclosure.
3 is a diagram for explaining a multi-driving operation according to an exemplary embodiment of the present disclosure.
4A and 4B are diagrams for explaining a clock generator according to an exemplary embodiment of the present disclosure.
5 is a diagram explaining a duty ratio change operation according to an exemplary embodiment of the present disclosure.
6 is a circuit diagram of a duty control circuit according to an exemplary embodiment of the present disclosure.
7 is a timing diagram illustrating a serialization process according to an exemplary embodiment of the present disclosure.
8A to 8C are circuit diagrams illustrating the structure of a selection circuit according to an exemplary embodiment of the present disclosure.
9 is a diagram illustrating a transmitter circuit according to an exemplary embodiment of the present disclosure.
10 is a timing diagram illustrating an operation of a transmitter circuit according to an exemplary embodiment of the present disclosure.
11 is a flowchart illustrating a method of operating a transmitter circuit according to an exemplary embodiment of the present disclosure.
12 is a flowchart illustrating a driving mode according to an exemplary embodiment of the present disclosure.
13 is a diagram illustrating a semiconductor memory device including a multiplexer according to an embodiment of the present invention.

Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a diagram for explaining a transmitter circuit according to an exemplary embodiment of the present disclosure. 2 is a diagram illustrating a serialization operation according to an exemplary embodiment of the present disclosure.

Referring to FIG. 1 , the transmitter circuit 1 may receive first to fourth parallel signals D[1:4] in parallel and output a serial signal D_TX. Each of the first to fourth parallel signals D[1:4] may be transmitted to the multiplexer 10 through different channels, and the serial signal D_TX may be externally output through one channel. . Although it is illustrated that four parallel signals are received, the embodiment is not limited thereto, and N (N is an integer equal to or greater than 2) parallel signals may be received.

The transmitter circuit 1 may include a multiplexer 10 , an output driver 15 and a clock generator 20 .

The multiplexer 10 may output first to fourth parallel signals D[1:4] in response to first to fourth clock signals CK1 to CK4. Specifically, referring to FIG. 2 , the multiplexer 10 may output the first parallel signal D1 in response to the first clock signal CK1 and output the first parallel signal D1 in response to the second clock signal CK2. 2 parallel signals D2 may be output, the third parallel signal D3 may be output in response to the third clock signal CK3, and the fourth parallel signal D3 may be output in response to the fourth clock signal CK4. D4) can be output. That is, the multiplexer 10 may perform a serialization operation of converting the first to fourth parallel signals D[1:4] into one serial signal D_TX. The embodiment is not limited thereto, and the multiplexer 10 may convert N parallel signals into one serial signal D_TX.

The multiplexer 10 may include first to fourth selection circuits 11 to 14 . Each of the first to fourth selection circuits 11 to 14 may receive two or more parallel signals and two or more clock signals, and may receive an active level (logic high level or logic low level) or an active edge (rising edge) of the clock signal. edge or falling edge), a parallel signal can be output. For example, the first selection circuit 11 may output the first parallel signal D1 in response to an active edge of the first clock signal CK1 and respond to an active edge of the second clock signal CK2. Thus, the second parallel signal D2 may be output. The second selection circuit 12 may output the second parallel signal D2 in response to the active edge of the second clock signal CK2, and output the third parallel signal D2 in response to the active edge of the third clock signal CK3. A signal D3 can be output. The third selection circuit 13 may output the third parallel signal D3 in response to the active edge of the third clock signal CK3, and output the fourth parallel signal D3 in response to the active edge of the fourth clock signal CK4. A signal D4 can be output. The fourth selection circuit 14 may output the first parallel signal D1 in response to the active edge of the first clock signal CK1, and output the fourth parallel signal D1 in response to the active edge of the fourth clock signal CK4. A signal D4 can be output. For convenience of explanation, four clock signals are shown, but the embodiment is not limited thereto. A signal D_TX can be generated.

One parallel signal may be input to two or more selection circuits and may be output from the two or more selection circuits in response to a clock signal.

For convenience of description, the multiplexer 10 is illustrated as including four selection circuits, but the embodiment is not limited thereto. For example, multiplexer 10 may include N selection circuits, each of the N selection circuits may receive two or more parallel signals and two or more clock signals, and may receive two or more clock signals. Two or more parallel signals can be selectively output based on the signals.

The clock generator 20 may generate first to fourth clock signals CK[1:4]. The duty ratio of the first to fourth clock signals CK[1:4] may be in inverse proportion to the number of selection circuits included in the multiplexer 10 . For example, in FIG. 1 , since the number of selection circuits included in the multiplexer 10 is four, the duty ratio of the first to fourth clock signals CK[1:4] may be 25%. . However, the embodiment is not limited thereto, and when the number of selection circuits included in the multiplexer 10 is five, the duty ratio of the clock signal generated by the clock generator 20 may be 20%. The duty ratio may indicate a ratio of a time period applied to an active signal in one cycle. The first to fourth clock signals CK[1:4] may have different phases. For example, referring to FIG. 2 , the phase of the first clock signal CK1 is 0, the phase of the second clock signal CK2 is 90, the phase of the third clock signal CK3 is 180, The phase of the 4 clock signal CK4 may be 270. However, the embodiment is not limited thereto, and the clock generator 20 may generate N clock signals having a constant phase difference.

The output driver 15 may generate a serial signal D_TX by amplifying a signal received from the multiplexer 10 . The serial signal D_TX may have a signal pattern in which the first to fourth parallel signals D[1:4] are repeatedly arranged.

In the transmitter circuit 1 according to an exemplary embodiment of the present disclosure, two or more selection circuits may output the same parallel signal in response to one clock signal, and the slew rate of the signal transmitted to the output driver 15 may be reduced. can rise That is, an output signal having a high slew rate can be provided by driving the output node by two or more selection circuits.

3 is a diagram for explaining a multi-driving operation according to an exemplary embodiment of the present disclosure.

Referring to FIG. 3 , the transmitter circuit 1 may include first to fourth selection circuits 11 to 14 and an output driver 15 . Although briefly shown, as shown in FIG. 1, the first to fourth selection circuits 11 to 14 receive the first to fourth parallel signals D[1:4], and the first to fourth clock signals The first to fourth parallel signals D[1:4] may be selectively output according to CK[1:4].

The first to fourth selection circuits 11 to 14 may drive the output node Nout according to the logic level of the received parallel signal. Specifically, when the parallel signal is a logic high level, the first to fourth selection circuits 11 to 14 may precharge the output node Nout, and when the parallel signal is a logic low level, the first to fourth selection circuits 11 to 14 may precharge the output node Nout. The circuits 11 to 14 may discharge the output node Nout.

Each of the first to fourth selection circuits 11 to 14 may include a driver and a switch. For example, the first selection circuit 11 may include a first driver DR1 and a first switch SW1. The first driver DR1 may output the first or second parallel signals D1 and D2, and the first switch SW1 may be controlled by the first clock signal CK1 or the second clock signal CK2. can Specifically, the first switch SW1 may be turned on according to the active level of the first clock signal CK1, and the first parallel signal D1 output by the first driver DR1 may be output to the output node Nout. can be forwarded to

Two or more of the first to fourth selection circuits 11 to 14 may output the same parallel signal in response to one clock signal. For example, the first switch SW1 and the fourth switch SW4 may be turned on in response to the active level of the first clock signal CK1, and the first driver DR1 and the fourth driver DR4 may be turned on. may deliver the first parallel signal D1 to the output node Nout. That is, the transmitter circuit 1 can generate the serial signal D_TX by simultaneously driving two or more selection circuits.

When looking at the selection circuit from the output node Nout, each of the first to fourth selection circuits 11 to 14 may be understood as a capacitor. According to an exemplary embodiment of the present disclosure, when two or more selection circuits drive the output node Nout at the same time, the value of the output capacitance viewed from the output node Nout toward the selection circuit side may be lowered. When the value of the output capacitance decreases, the slew rate of the serial signal D_TX may increase. For example, as shown in FIG. 3 , when a multi-driving operation in which two or more selection circuits simultaneously drive the output node Nout is performed, the slew rate of the output node Nout may increase. can An operation in which one of the first to fourth selection circuits 11 to 14 drives the output node Nout may be referred to as a single-driving operation.

Compared to the single driving operation, since the slew rate of the serial signal DTX can be increased during the multi driving operation, the performance of the transmitter circuit 1 can be improved.

4A and 4B are diagrams for explaining a clock generator according to an exemplary embodiment of the present disclosure.

Referring to FIG. 4A , the clock generator 20a may include a phase locked loop (PLL) 21, a multi-phase clock generator 22a, and a duty control circuit 23. The clock generator 20a may be an example of the clock generator 20 of FIG. 1 .

The phase locked loop 21 may generate a reference clock signal Ref_CK and transfer the reference clock signal Ref_CK to the multi-phase clock generator 22 . The duty ratio of the reference clock signal Ref_CK may be 50%.

The multi-phase clock generator 22a may generate first to fourth multi-phase clock signals pCK1 to pCK4 having different phases based on the reference clock signal Ref_CK. For example, the phase of the first multi-phase clock signal pCK1 may be 0, the phase of the second multi-phase clock signal pCK2 may be 90, and the phase of the third multi-phase clock signal pCK3 may be 180, and the phase of the fourth multi-phase clock signal pCK4 may be 270. The multi-phase clock generator 22a may include a Delay Locked Loop (DLL).

The duty control circuit 23 generates first to fourth clock signals CK1 to CK4 and first to fourth inverted clock signals nCK1 to nCK4 based on the first to fourth multi-phase clock signals pCK1 to pCK4. can create Duty ratios of the first to fourth clock signals CK1 to CK4 and the first to fourth inverted clock signals nCK1 to nCK4 may be different from those of the first to fourth multi-phase clock signals pCK1 to pCK4. For example, the duty ratio of the first to fourth clock signals CK1 to CK4 and the first to fourth inverted clock signals nCK1 to nCK4 may be 25%.

The first to fourth inverted clock signals nCK1 to nCK4 may have inverted logic levels of the first to fourth clock signals CK1 to CK4 .

Referring to FIG. 4B , the clock generator 20b receives the reference clock signal Ref_CK from the memory controller 2, and generates first to fourth clock signals CK1 to CK4 and CK1 to CK4 based on the reference clock signal Ref_CK. First to fourth inverted clock signals nCK1 to nCK4 may be generated. The clock generator 20b may be an example of the clock generator 20 of FIG. 1 .

In some embodiments, the clock generator 20b may be included in a semiconductor memory device (eg, 1300 of FIG. 13 ), and the memory controller 2 transmits the reference clock signal Ref_CK to the semiconductor memory device 1300 . can be conveyed In some embodiments, the reference clock signal Ref_CK may be referred to as a write clock (WCK) signal. The semiconductor memory device 1300 may generate a serial signal by performing a serialization operation based on the write clock (WCK) signal and transfer the generated serial signal to the memory controller 2 .

5 is a diagram explaining a duty ratio change operation according to an exemplary embodiment of the present disclosure. 6 is a circuit diagram of a duty control circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 5 , the duty ratio of the first to fourth multi-phase clock signals pCK1 to pCK4 may be 50%. The phase of the first multi-phase clock signal pCK1 may be 0, the phase of the second multi-phase clock signal pCK2 may be 90, the phase of the third multi-phase clock signal pCK3 may be 180, , the phase of the fourth multi-phase clock signal pCK4 may be 270.

4 and 6 , the duty control circuit 23 may generate first to fourth clock signals CK1 to CK4 based on the first to fourth multi-phase clock signals pCK1 to pCK4. . A duty ratio of the first to fourth clock signals CK1 to CK4 may be 25%. Although not shown in FIG. 5, the duty control circuit 23 may generate first to fourth inverted clock signals nCK1 to nCK4, and the first to fourth inverted clock signals nCK1 to nCK4 may generate first to fourth inverted clock signals nCK1 to nCK4. It may have a phase opposite to that of the four clock signals CK1 to CK4.

Referring to FIG. 6 , the duty control circuit 23 may include first to fourth clock generation circuits 231 to 234 . The first clock generation circuit 231 may generate the first clock signal CK1 and the first inverted clock signal nCK1, and the second clock generation circuit 232 may generate the second clock signal CK2 and the second inverted clock signal nCK1. The third clock generation circuit 233 can generate the third clock signal CK3 and the third inverted clock signal nCK3, and the fourth clock generation circuit 234 can generate the inverted clock signal nCK2. ) may generate a fourth clock signal CK4 and a first inverted clock signal nCK4. Each of the first to fourth clock generation circuits 231 to 234 may receive the first to fourth multi-phase clock signals pCK1 to pCK4.

The first clock generation circuit 231 performs a NAND operation on the first multi-phase clock signal pCK1 and the fourth multi-phase clock signal pCK4 and inverts the result of the NAND operation, thereby generating the first clock signal CK1. can create That is, as a result, the first clock signal CK1 can be obtained through an AND operation between the first multi-phase clock signal pCK1 and the fourth multi-phase clock signal pCK4 having a phase difference of 270 degrees. The first clock generation circuit 231 inverts each of the second multi-phase clock signal pCK2 and the third multi-phase clock signal pCK3 and generates a first inverted clock signal nCK1 through a NAND operation of the inverted signals. can create That is, as a result, the first inverted clock signal nCK1 may be obtained through an OR operation between the second multi-phase clock signal pCK2 and the third multi-phase clock signal pCK3 having a phase difference of 90 degrees.

Since the second clock generator circuit 232 to the fourth clock generator circuit 234 can operate in the same way as the first clock generator circuit 231, the second clock generator circuit 232 to the fourth clock generator circuit 234 A description of may be omitted.

An embodiment of generating the first to fourth clock signals CK1 to CK4 and the first to fourth inverted clock signals nCK1 to nCK4 is not limited thereto, and a plurality of clock signals having duty ratios adjusted in various ways and Inversion signals of a plurality of clock signals may be generated.

7 is a timing diagram illustrating a serialization process according to an exemplary embodiment of the present disclosure. FIG. 7 may be described later with reference to FIG. 1 .

Referring to FIG. 7 , the first to fourth clock signals CK1 to CK4 may maintain a logic high level during a unit interval (Unit Interval, UI). Each of the first to fourth parallel signals D[1:4] may maintain the same logic level for a predetermined unit interval in order to be synchronized with active edge timings of the first to fourth clock signals CK1 to CK4. For example, each of the first to fourth parallel signals D[1:4] may maintain the same logic level for a time corresponding to four times the unit interval UI.

The multiplexer 10 may output the first parallel signal D1 as the serial signal D_TX in response to the active edge of the first clock signal CK1 at the first time point t11. Since the first parallel signal D1 indicates a logic high level, the serial signal D_TX may also indicate a logic high level. The multiplexer 10 may output the second parallel signal D2 as the serial signal D_TX in response to the active edge of the second clock signal CK2 at the second time point t12. Since the second parallel signal D2 represents the logic low level, the serial signal D_TX can transition to the logic low level. As shown in FIG. 1 , the first selection circuit 11 and the second selection circuit 12 may simultaneously output the second parallel signal D2 in response to the second clock signal CK2. Accordingly, when the serial signal D_TX transitions at the second time point t12, the slew rate may increase. Similarly, at the third time point t13, the fourth time point t14, the sixth time point t16, and the eighth time point t18, the serial signal D_TX may be transitioned, and two or more selection circuits simultaneously use the serial signal ( D_TX), the slew rate can be increased.

That is, since the two selection circuits output the same parallel signal in response to each of the first to fourth clock signals CK1 to CK4, the slew rate of the serial signal D_TX can be increased and the performance of the transmitter circuit 1 can be improved. can be improved The embodiment is not limited thereto, and the performance of the transmitter circuit 1 may be improved by outputting the same parallel signal from three or more selection circuits in response to the first to fourth clock signals CK to CK4, respectively.

8A to 8C are circuit diagrams illustrating the structure of a selection circuit according to an exemplary embodiment of the present disclosure. Specifically, FIG. 8A is a circuit diagram illustrating the selection circuit at the logic gate level, and FIGS. 8B and 8C are circuit diagrams illustrating the selection circuit at the transistor level.

Referring to FIG. 8A , the multiplexer 30 may include first to fourth selection circuits 31 to 34 . The description given below for the first selection circuit 31 can also be applied to the second to fourth selection circuits 32 to 34.

The first selection circuit 31 includes an AND-OR-INVETER (AOI) 22 circuit 311, an OR-AND-INVERTER (OAI) 22 circuit 312, a first P-type transistor P1 and a second N- type transistor N1 may be included.

The AOI22 circuit 311 may receive the first and second parallel signals D1 and D2 and the first and second clock signals CK1 and CK2 and drive the gate terminal of the first P-type transistor P1. . Specifically, the AOI22 circuit 311 turns on the first P-type transistor P1 by inverting the first parallel signal D1 of the logic high level in response to the active edge of the first clock signal CK1. can Alternatively, the AOI22 circuit 311 may turn on the first P-type transistor P1 by inverting the second parallel signal D2 of the logic high level in response to the active edge of the second clock signal CK2. have. When the first P-type transistor P1 is turned on, a logic high level serial signal D_TX may be generated. That is, the first selection circuit 31 generates the serial signal D_TX by outputting first and second parallel signals D1 and D2 having a logic high level based on the first and second clock signals CK1 and CK2. can do.

The OAI22 circuit 312 may receive the first and second parallel signals D1 and D2 and the first and second inverted clock signals nCK1 and nCK2 and drive the gate terminal of the first N-type transistor N1. have. Specifically, the OAI22 circuit 312 turns on the first N-type transistor N1 by inverting the first parallel signal D1 of the logic low level in response to the active edge of the first inverted clock signal nCK1. can make it When the first N-type transistor N1 is turned on, a logic low level serial signal D_TX may be generated. That is, the first selection circuit 31 outputs the first and second parallel signals D1 and D2 having a logic low level based on the first and second inverted clock signals nCK1 and nCK2 to obtain the serial signal D_TX. can create

The second selection circuit 32 outputs second and third parallel signals D2 and D3 having a logic high level based on the second and third clock signals CK2 and CK3, or outputs second and third inverted clock signals ( The serial signal D_TX may be generated by outputting second and third parallel signals D2 and D3 having a logic low level based on nCK2 and nCK3. The third selection circuit 33 outputs third and fourth parallel signals D3 and D4 having a logic high level based on the third and fourth clock signals CK3 and CK4, or third and fourth inverted clock signals ( The serial signal D_TX may be generated by outputting the third and fourth parallel signals D3 and D4 having a logic low level based on nCK3 and nCK4. The fourth selection circuit 34 outputs first and fourth parallel signals D1 and D4 having a logic high level based on the first and fourth clock signals CK1 and CK4, or outputs first and fourth inverted clock signals ( The serial signal D_TX may be generated by outputting first and fourth parallel signals D1 and D4 having a logic low level based on nCK1 and nCK4. That is, each of the first to fourth parallel signals D1 to D4 may be simultaneously selected by at least two or more selection circuits to form the serial signal D_TX.

The embodiment of the present invention is not limited thereto, and a multiplexer structure in which one parallel signal is simultaneously output by two or more selection circuits may be included in the embodiment of the present invention. Also, according to an embodiment of the present invention, one selection circuit may receive two or more parallel signals and output one of the two or more parallel signals in response to each of the two or more clock signals.

Referring to FIG. 8B , the multiplexer 40 may include first to fourth selection circuits 41 to 44 . In FIG. 8B, the description of the first selection circuit 41 can also be applied to the second to fourth selection circuits 42 to 44.

The first selection circuit 41 may include an AOI22 circuit 411 and an OAI22 circuit 412 . The AOI22 circuit 411 outputs the first and second parallel signals D1 and D2 having a logic high level as a serial signal D_TX in response to the first and second clock signals CK1 and CK2. It can drive transistor P1. The OAI22 circuit 412 outputs the first and second parallel signals D1 and D2 having a logic low level as serial signals D_TX in response to the first and second inverted clock signals nCK1 and nCK2. type transistor N1 can be driven.

The AOI22 circuit 411 may include a first pull-up circuit 413 and a first pull-down circuit 414 . The first pull-up circuit 413 may precharge a node connected to the gate terminal of the first P-type transistor P1, and the first pull-down circuit 414 may precharge the node of the first P-type transistor P1. A node connected to the gate stage can be discharged.

The first pull-up circuit 413 may include second to fifth P-type transistors P12 to P15. The first parallel signal D1 may be input to the gate terminal of the second P-type transistor P12, and the second parallel signal D2 may be input to the gate terminal of the third P-type transistor P13. The first clock signal CK1 may be input to the gate terminal of the fourth P-type transistor P14, and the second clock signal CK2 may be input to the gate terminal of the fifth P-type transistor P15. It can be. When the first clock signal CK1 is at a logic high level and the first parallel signal D1 is at a logic high level, the first P-type transistor P1 can be turned on so that the serial signal D_TX has a logic high level. can indicate Also, since the first P-type transistor P1 can be turned on when the second clock signal CK2 is at a logic high level and the second parallel signal D2 is at a logic high level, the serial signal D_TX is at a logic high level. level can be indicated. That is, the AOI22 circuit 411 may drive the first P-type transistor P1 so that the first and second parallel signals D1 and D2 having a logic high level are reflected in the serial signal D_TX.

The OAI22 circuit 412 may include a second pull-up circuit 415 and a second pull-down circuit 416 . The second pull-up circuit 415 may precharge a node connected to the gate terminal of the first N-type transistor N1, and the second pull-down circuit 416 may precharge the node of the first N-type transistor N1. A node connected to the gate stage can be discharged.

The second pull-up circuit 415 may include sixth to ninth P-type transistors P16 to P19. The first inverted clock signal nCK1 may be input to the gate terminal of the sixth P-type transistor P16, and the first parallel signal D1 may be input to the gate terminal of the seventh P-type transistor P17. The second inverted clock signal nCK2 may be input to the gate terminal of the eighth P-type transistor P18, and the second parallel signal D2 may be input to the gate terminal of the ninth P-type transistor P19. can be entered. When the first inverted clock signal nCK1 is at a logic low level, that is, when the first clock signal CK1 is at a logic high level and the first parallel signal D1 is at a logic low level, the first N-type transistor N1 turns - Since it can be turned on, the serial signal D_TX can indicate a logic low level. In addition, when the second inverted clock signal nCK2 is at a logic low level, that is, when the second clock signal CK2 is at a logic high level and the second parallel signal D2 is at a logic low level, the first N-type transistor N1 can be turned on, so the serial signal D_TX can indicate a logic low level. That is, the OAI22 circuit 412 may drive the first N-type transistor N1 such that the first and second parallel signals D1 and D2 having a logic low level are reflected in the serial signal D_TX.

Although the first selection circuit 41 has been described as outputting the first and second parallel signals D1 and D2 based on the first and second clock signals CK1 and CK2, the embodiment is not limited thereto. That is, the first selection circuit 41 may selectively output three or more parallel signals based on three or more clock signals. Also, the parallel signals received by the first selection circuit 41 are not limited to the first and second parallel signals D1 and D2.

Referring to FIG. 8C , the multiplexer 50 may include first to fourth selection circuits 51 to 54 . In FIG. 8C, the description of the first selection circuit 45 can also be applied to the second to fourth selection circuits 52 to 54.

The first selection circuit 51 may include an AOI22 circuit 511 and an OAI22 circuit 512 . The AOI22 circuit 511 outputs the first and second parallel signals D1 and D2 having a logic high level as a serial signal D_TX in response to the first and second clock signals CK1 and CK2. It can drive transistor P1. The OAI22 circuit 512 outputs the first and second parallel signals D1 and D2 having a logic low level as a serial signal D_TX in response to the first and second inverted clock signals nCK1 and nCK2. type transistor N1 can be driven.

The AOI22 circuit 511 may include a first driving circuit 513 and a second driving circuit 514 . The first driving circuit 513 may drive a node connected to the gate terminal of the first P-type transistor P1 based on the first input signal D1, and the second driving circuit 514 may drive a node connected to the gate terminal of the first P-type transistor P1 based on the first input signal D1. Based on (D2), a node connected to the gate terminal of the first P-type transistor P1 may be driven.

The first driving circuit 513 may include second to fourth P-type transistors P22 to P24 and second and third N-type transistors N22 and N23. The first clock signal CK1 may be input to the gate terminal of the second P-type transistor P22, and the second clock signal CK2 may be input to the gate terminal of the third P-type transistor P23. The first parallel signal D1 may be input to the gate terminal of the fourth P-type transistor P24, and the first clock signal CK1 may be input to the gate terminal of the second N-type transistor N22. and the first parallel signal D1 may be input to the gate terminal of the third N-type transistor N23. When the first clock signal CK1 is at a logic high level and the first parallel signal D1 is at a logic high level, the first P-type transistor P1 may be turned on by the first driving circuit 513, so that the series Signal D_TX may indicate a logic high level.

The second driving circuit 514 may include 5 to 7 P-type transistors P25 to P27 and 4 and 5 N-type transistors N24 and N25. The second clock signal CK2 may be input to the gate terminal of the fifth P-type transistor P25, and the first clock signal CK1 may be input to the gate terminal of the sixth P-type transistor P26. The second parallel signal D2 may be input to the gate terminal of the seventh P-type transistor P27, and the second clock signal CK2 may be input to the gate terminal of the fourth N-type transistor N24. and the second parallel signal D2 may be input to the gate terminal of the fifth N-type transistor N25. When the second clock signal CK2 is at a logic high level and the second parallel signal D2 is at a logic high level, the first P-type transistor P1 can be turned on by the second driving circuit 514, so that the series Signal D_TX may indicate a logic high level.

The OAI22 circuit 512 may include a third driving circuit 515 and a fourth driving circuit 516 . The third driving circuit 515 may drive a node connected to the gate terminal of the first N-type transistor N1 based on the first input signal D1, and the fourth driving circuit 516 may drive the second input signal Based on (D2), a node connected to the gate terminal of the first N-type transistor N1 may be driven.

The third driving circuit 515 may include eighth and ninth P-type transistors P31 to P32 and sixth and seventh N-type transistors N26 and N27. The first parallel signal D1 may be input to the gate terminal of the eighth P-type transistor P31, and the first inverted clock signal nCK1 may be input to the gate terminal of the ninth P-type transistor P32. The first inverted clock signal nCK1 may be input to the gate terminal of the sixth N-type transistor N26, and the second inverted clock signal nCK2 to the gate terminal of the seventh N-type transistor N27. ) can be entered. When the first inverted clock signal nCK1 is at a logic low level, that is, when the first clock signal CK1 is at a logic high level and the first parallel signal D1 is at a logic low level, the first N-type transistor N1 is 3 Since it can be turned on by the driving circuit 515, the serial signal D_TX can indicate a logic low level.

The fourth driving circuit 516 may include tenth and eleventh P-type transistors P33 to P34 and eighth and ninth N-type transistors N28 and N29. The second parallel signal D2 may be input to the gate terminal of the tenth P-type transistor P33, and the second inverted clock signal nCK2 may be input to the gate terminal of the eleventh P-type transistor P34. The second inverted clock signal nCK2 may be input to the gate terminal of the eighth N-type transistor N28, and the first inverted clock signal nCK1 to the gate terminal of the ninth N-type transistor N29. ) can be entered. When the second inverted clock signal nCK2 is at a logic low level, that is, when the second inverted signal CK2 is at a logic high level and the first parallel signal D1 is at a logic low level, the first N-type transistor N1 is 4 Since it can be turned on by the driving circuit 516, the serial signal D_TX can indicate a logic low level.

9 is a diagram illustrating a transmitter circuit according to an exemplary embodiment of the present disclosure.

10 is a timing diagram illustrating an operation of a transmitter circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 9 , the transmitter circuit 2 may include a multiplexer 60 , a transition signal generator circuit 70 and an output driver 15 .

The multiplexer 60 may selectively output first to fourth parallel signals D1 to D4, and the output driver 15 amplifies the output of the multiplexer 60 to generate a serial signal D_TX. can do.

The multiplexer 60 may include first to fourth selection circuits 61 to 64 . Each of the first to fourth selection circuits 61 to 64 may receive parallel signals D1 to D4 and transition signals T1 to T4. For example, the first selection circuit 61 may receive the first parallel signal D1 and the first transition signal T1, and the second selection circuit 62 may receive the second parallel signal D2 and the first transition signal T1. 2 transition signal T2 can be received, the third selection circuit 63 can receive the third parallel signal D3 and the third transition signal T3, and the fourth selection circuit 64 can receive the third parallel signal D3 and the third transition signal T3. 4 parallel signals D4 and a fourth transition signal T4 may be received.

Referring to FIG. 10 , the multiplexer 60 generates first to fourth parallel signals D1 to D4 based on first to fourth clock signals CK1 to CK4 sequentially transitioning to a logic high level (H). output, and thereby a serial signal (D_TX) can be generated.

Referring to FIGS. 9 and 10 , the transition signal generation circuit 70 may generate first to fourth transition signals T1 to T4 indicating whether the serial signal D_TX is transitioning. When the serial signal D_TX transitions, one of the first to fourth transition signals T1 to T4 may indicate a logic high level, and the remaining transition signals may indicate a logic low level.

The transition signal generating circuit 70 may include first to fourth signal generating circuits 71 to 74 .

The first signal generating circuit 71 may generate a first transition signal T1 based on the first and fourth parallel signals D1 and D4. Specifically, the first transition signal T1 may indicate whether a logic level transition has occurred between adjacent parts of the fourth parallel signal D4 and the first parallel signal D1 of the serial signal D_TX. For example, in FIG. 10 , at the fifth point in time t25 , logic level transition between adjacent parts of the fourth parallel signal D4 and the first parallel signal D1 of the serial signal D_TX does not occur. Therefore, the first transition signal T1 may indicate a logic low level.

The second signal generating circuit 72 may generate a second transition signal T2 based on the first and fourth parallel signals D1 and D4. Specifically, the second transition signal T2 may indicate whether logic level transitions have occurred in adjacent portions of the first parallel signal D1 and the second parallel signal D2 of the serial signal D_TX. For example, in FIG. 10 , at the second time point t22 and the sixth time point t26 , logic is applied to the adjacent first parallel signal D1 portion and second parallel signal D2 portion of the serial signal D_TX. Since the level transition has occurred, the second transition signal T2 can maintain the logic high level for a predetermined time (eg, unit interval).

The third signal generating circuit 73 may generate a third transition signal T3 based on the second and third parallel signals D2 and D3. Specifically, the third transition signal T3 may indicate whether logic level transitions have occurred in adjacent portions of the second parallel signal D2 and the third parallel signal D3 of the serial signal D_TX. For example, in FIG. 10, at the third time point t23, logic level transitions occur in the adjacent second parallel signal D2 and third parallel signal D3 portions of the serial signal D_TX. 3 The transition signal T3 may maintain a logic high level for a predetermined time (eg, unit interval).

The fourth signal generating circuit 74 may generate a fourth transition signal T4 based on the third and fourth parallel signals D3 and D4. Specifically, the fourth transition signal T4 may indicate whether logic level transitions have occurred in portions of the third parallel signal D3 and the fourth parallel signal D4 adjacent to each other of the serial signal D_TX. For example, in FIG. 10, at the fourth time point t24 and the eighth time point t28, logic is applied to the third parallel signal D3 part and the fourth parallel signal D4 part of the serial signal D_TX. Since the level transition has occurred, the fourth transition signal T4 can maintain the logic high level for a predetermined time (eg, unit interval).

The first selection circuit 61 responds to an active level (eg, a logic high level) or an active edge (eg, a rising edge) of the first clock signal CK1 and the second clock signal CK2. One parallel signal D1 or the second transition signal T2 can be selected. Specifically, the first selection circuit 61 may output the first parallel signal D1 in response to the active edge of the first clock signal CK1. Also, the first selection circuit 61 may drive the output node Nout based on the second transition signal T2 in response to the active edge of the second clock signal CK2. The first selection circuit 61 may not drive the output node when the logic level of the second transition signal T2 is a logic low level, and if the logic level of the second transition signal T2 is a logic high level, output You can drive a node (Nout). For example, when a logic level transition occurs from a portion of the first parallel signal D1 having a logic high level to a portion of the second parallel signal D2 having a logic low level, the first selection circuit ( 61) may discharge the output node Nout in response to an active edge of the second clock signal CK2. Alternatively, when a logic level transition occurs from a portion of the first parallel signal D1 having a logic low level to a portion of the second parallel signal D2 having a logic high level, the first selection circuit 61 generates a second clock In response to the active edge of the signal CK2, the output node Nout may be precharged.

That is, when there is a logic level transition between the first parallel signal D1 part and the second parallel signal D2 part included in the serial signal D_TX, the second selection circuit 62 ) together, the slew rate of the serial signal D_TX can be increased by driving the output node Nout.

The second selection circuit 62 responds to an active level (eg, a logic high level) or an active edge (eg, a rising edge) of the second clock signal CK2 and the third clock signal CK3. Two parallel signals D2 or a third transition signal T3 can be selected. Specifically, the second selection circuit 62 may output the second parallel signal D2 in response to an active edge of the second clock signal CK2. Also, the second selection circuit 62 may drive the output node Nout based on the third transition signal T3 in response to an active edge of the third clock signal CK3. The second selection circuit 62 may not drive the output node Nout when the logic level of the third transition signal T3 is a logic low level, and the logic level of the third transition signal T3 is a logic high level. In case of , the output node Nout can be driven. For example, when a logic level transition occurs from a portion of the second parallel signal D2 having a logic high level to a portion of the third parallel signal D3 having a logic low level, the second selection circuit ( 62) may discharge the output node Nout in response to an active edge of the third clock signal CK3. Alternatively, when a logic level transition occurs from a portion of the second parallel signal D2 having a logic low level to a portion of the third parallel signal D3 having a logic high level, the second selection circuit 62 generates a third clock In response to the active edge of the signal CK3, the output node Nout may be precharged.

That is, when there is a logic level transition between the second parallel signal D2 part and the third parallel signal D3 part included in the serial signal D_TX, the third selection circuit 63 ) together, the slew rate of the serial signal D_TX can be increased by driving the output node Nout.

The third selection circuit 63 responds to active levels (eg, logic high levels) or active edges (eg, rising edges) of the third and fourth clock signals CK3 and CK4. The 3 parallel signals D3 or the 4th transition signal T4 can be selected. Specifically, the third selection circuit 63 may output the third parallel signal D3 in response to an active edge of the third clock signal CK3. Also, the third selection circuit 63 may drive the output node Nout based on the fourth transition signal T4 in response to an active edge of the fourth clock signal CK4. The third selection circuit 63 may not drive the output node Nout when the logic level of the fourth transition signal T4 is a logic low level, and the logic level of the fourth transition signal T4 is a logic high level. In case of , the output node Nout can be driven. For example, when a logic level transition occurs from a portion of the third parallel signal D3 having a logic high level to a portion of the fourth parallel signal D4 having a logic low level, the third selection circuit ( 63) may discharge the output node Nout in response to the active edge of the fourth clock signal CK4. Alternatively, when a logic level transition occurs from a portion of the third parallel signal D3 having a logic low level to a portion of the fourth parallel signal D4 having a logic high level, the third selection circuit 63 generates a fourth clock signal. In response to the active edge of the signal CK4, the output node Nout may be precharged.

That is, when there is a logic level transition between the third parallel signal D3 and the fourth parallel signal D4 included in the serial signal D_TX, the fourth selection circuit 64 ) together, the slew rate of the serial signal D_TX can be increased by driving the output node Nout.

The fourth selection circuit 64 responds to an active level (eg, a logic high level) or an active edge (eg, a rising edge) of the fourth clock signal CK4 and the first clock signal CK1. 4 parallel signals D4 or the first transition signal T1 can be selected. Specifically, the fourth selection circuit 64 may output the fourth parallel signal D4 in response to an active edge of the fourth clock signal CK4. Also, the fourth selection circuit 64 may drive the output node Nout based on the first transition signal T1 in response to the active edge of the first clock signal CK1. The fourth selection circuit 64 may not drive the output node Nout when the logic level of the first transition signal T1 is a logic low level, and the logic level of the first transition signal T1 is a logic high level. In case of , the output node Nout can be driven. For example, when a logic level transition occurs from a portion of the fourth parallel signal D4 having a logic high level to a portion of the first parallel signal D1 having a logic low level, the fourth selection circuit ( 64) may discharge the output node Nout in response to an active edge of the first clock signal CK1. Alternatively, when a logic level transition occurs from a portion of the fourth parallel signal D4 having a logic low level to a portion of the first parallel signal D1 having a logic high level, the fourth selection circuit 64 generates a first clock In response to the active edge of the signal CK1, the output node Nout may be precharged.

That is, when there is a logic level transition between the fourth parallel signal D4 and the first parallel signal D1 included in the serial signal D_TX, the first selection circuit 61 ) together, the slew rate of the serial signal D_TX can be increased by driving the output node Nout.

According to an exemplary embodiment of the present disclosure, a slew rate of the serial signal D_TX may be increased by performing a multi-driving operation in which a plurality of selection circuits drive an output node when the logic level of the serial signal D_TX is transitioned. have. For example, referring to FIG. 10 , first through fourth transitions are performed at the second time point t22, the third time point t23, the fourth time point t24, the sixth time point t26, and the eighth time point t28. One of the signals T1 to T4 may have an active edge, and the transmitter circuit 2 may operate in a multi-driving mode in which a plurality of select circuits drive the output node.

Meanwhile, when the logic level of the serial signal D_TX does not transition, a single-drive operation in which one selection circuit drives the output node is performed, thereby reducing power consumption. For example, referring to FIG. 10 , since the first to fourth transition signals T1 to T4 do not have active edges at the first time point t21, the fifth time point t25, and the seventh time point t27, the transmitter Circuit 2 can operate in a single-driving mode in which one select circuit drives the output node.

11 is a flowchart illustrating a method of operating a transmitter circuit according to an exemplary embodiment of the present disclosure. Referring to FIG. 11 , a method of operating a transmitter circuit may include a plurality of steps S1110 to S1130. 11 may be described with reference to the aforementioned drawings.

In step S1110, the clock generator 20 may generate a plurality of clock signals CK[1:4] having different phases based on the reference clock signal. The duty ratio of the reference clock signal may be 50%, and the duty ratio of the plurality of clock signals CK[1:4] may be less than 50%. For example, the duty ratio of the plurality of clock signals CK[1:4] may be 25%. In step S1110, the above description with reference to FIGS. 4 to 6 may be performed.

In step S1120, the multiplexer 10 simultaneously uses two or more selection circuits among a plurality of selection circuits 11 to 14 operating based on a plurality of clock signals CK[1:4] to generate an output node can drive Specifically, as shown in FIGS. 1 and 3, the first and fourth selection circuits 11 and 14 simultaneously transmit the first parallel signal D1 to the output node Nout in response to the first clock signal CK1. can provide Since two or more selection circuits drive the output node, the slew rate of the serial signal D_TX can be increased and the performance of the transmitter circuit 1 can be improved.

In step S1130, the output driver 15 may generate the serial signal D_TX by amplifying the signal of the output node Nout.

12 is a flowchart illustrating a driving mode according to an exemplary embodiment of the present disclosure. The plurality of steps S1210 to S1230 described in FIG. 12 may be an embodiment of step S1120 of FIG. 11 . 12 may be described later with reference to FIGS. 9 and 10 together.

In step S1210, the transition signal generating circuit 70 may generate a plurality of transition signals T1 to T4 based on whether or not the serial signal D_TX transitions. The first transition signal T1 may indicate whether a logic level transitions between a portion of the fourth parallel signal D4 and a portion of the first parallel signal D1 of the serial signal D_TX. The second transition signal T2 may indicate whether a logic level transitions between the consecutive first parallel signal D1 portion and the second parallel signal D2 portion of the serial signal D_TX. The third transition signal T3 may indicate whether a logic level transitions between the consecutive second parallel signal D2 and third parallel signal D3 portions of the serial signal D_TX. The fourth transition signal T4 may indicate whether a logic level transitions between the consecutive third parallel signal D3 and fourth parallel signal D4 portions of the serial signal D_TX. When the serial signal D_TX transitions, step S1230 may be performed, and when the serial signal D_TX does not transition, step S1220 may be performed.

In step S1230, the transmitter circuit 2 may operate in a multi-driving mode in which two or more selection circuits among the plurality of selection circuits 61 to 64 drive the output node Nout. When two or more selection circuits simultaneously drive the output node Nout, the slew rate of the serial signal D_TX can be increased and the performance of the transmitter circuit 2 can be improved.

In step S1220, the transmitter circuit 2 may operate in a single driving mode in which one of the plurality of selection circuits 61 to 64 drives the output node Nout. When there is no transition of the logic level of the serial signal D_TX, power consumption can be reduced by operating only one selection circuit.

13 is a diagram illustrating a semiconductor memory device including a multiplexer according to an embodiment of the present invention.

Referring to FIG. 13 , the semiconductor memory device 1300 includes a control logic 1310, a refresh address generator 1315, an address buffer 1320, a bank control logic 1330, a row address multiplexer 1340, and a column address latch. 1350, a row decoder, a memory cell array, a sense amplifier unit, an input/output gating circuit 1390, a data input/output buffer 1395, and an ECC engine 1400.

The memory cell array may include first to fourth bank arrays 1380a, 1380b, 1380c, and 1380d. The row decoder may include first to fourth bank row decoders 1360a, 1360b, 1360c, and 1360d respectively connected to the first to fourth bank arrays 1380a, 1380b, 1380c, and 1380d. The column decoder may include first to fourth bank column decoders 1370a, 1370b, 1370c, and 1370d respectively connected to the first to fourth bank arrays 1380a, 1380b, 1380c, and 1380d. The sense amplifier unit may include first to fourth bank sense amplifiers 1385a, 1385b, 1385c, and 1385d respectively connected to the first to fourth bank arrays 1380a, 1380b, 1380c, and 1380d. First to fourth bank arrays 1380a, 1380b, 1380c, and 1380d, first to fourth bank row decoders 1360a, 1360b, 1360c, and 1360d, and first to fourth bank column decoders 1370a and 1370b , 1370c, 1370d) and the first to fourth bank sense amplifiers 1385a, 1385b, 1385c, and 1385d may configure the first to fourth banks, respectively. Although an example of the semiconductor memory device 1300 including four banks is shown in FIG. 13 , the semiconductor memory device 1300 may include any number of banks according to embodiments.

Also, according to an embodiment, the semiconductor memory device 1300 may include DDR Double Data Rate Synchronous Dynamic Random Access Memory (SDRAM), Low Power Double Data Rate (LPDDR) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, and Rambus Dynamic RAM (RDRAM). It may be a dynamic random access memory (DRAM) such as a random access memory) or any volatile memory device requiring a refresh operation.

The control logic 1310 may control the operation of the semiconductor memory device 1300 . For example, the control logic 1310 may generate control signals to allow the semiconductor memory device 1300 to perform a write operation or a read operation. The control logic 1310 may include a command decoder (not shown) for decoding the command CMD received from the memory controller and a mode register (not shown) for setting an operation mode of the semiconductor memory device 1300 . For example, the command decoder decodes a write enable signal (/WE), a row address strobe signal (/RAS), a column address strobe signal (/CAS), a chip select signal (/CS), etc. Corresponding control signals can be generated.

The control logic 1310 may further receive a clock CLK and a clock enable signal CKE for driving the semiconductor memory device 1300 in a synchronous manner. The control logic 1310 controls the refresh address generator 1315 to perform an auto refresh operation in response to a refresh command, or controls the refresh address generator 1315 to perform a self refresh operation in response to a self refresh entry command. can do.

The refresh address generator 1315 may generate a refresh address REF_ADDR corresponding to a memory cell row on which a refresh operation is to be performed. The refresh address generator 1315 may generate the refresh address REF_ADDR at a refresh rate longer than the refresh cycle defined in the standard for the semiconductor memory device 1300 . Accordingly, the refresh current and refresh power of the semiconductor memory device 1300 may be reduced.

The address buffer 1320 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller. In addition, the address buffer 1320 provides the received bank address BANK_ADDR to the bank control logic 1330, provides the received row address ROW_ADDR to the row address multiplexer 1340, and provides the received column address COL_ADDR ) to the column address latch 1350.

The bank control logic 1330 may generate bank control signals in response to the bank address BANK_ADDR. In response to the bank control signals, a bank row decoder corresponding to the bank address BANK_ADDR among the first to fourth bank row decoders 1360a, 1360b, 1360c, and 1360d is activated, and the first to fourth bank column decoders are activated. A bank column decoder corresponding to the bank address BANK_ADDR among the fields 1370a, 1370b, 1370c, and 1370d may be activated.

The bank control logic 1330 may generate bank group control signals in response to the bank address BANK_ADDR that determines the bank group. In response to the bank group control signals, row decoders of the bank group corresponding to the bank address BANK_ADDR among the first to fourth bank row decoders 1360a, 1360b, 1360c, and 1360d are activated, and the first to fourth row decoders are activated. Among the bank column decoders 1370a, 1370b, 1370c, and 1370d, column decoders of a bank group corresponding to the bank address BANK_ADDR may be activated.

The row address multiplexer 1340 may receive the row address ROW_ADDR from the address buffer 1320 and the refresh row address REF_ADDR from the refresh address generator 1315 . The row address multiplexer 1340 may selectively output a row address ROW_ADDR or a refresh row address REF_ADDR. The row address output from the row address multiplexer 1340 may be applied to the first to fourth bank row decoders 1360a, 1360b, 1360c, and 1360d, respectively.

A bank row decoder activated by the bank control logic 1330 among the first to fourth bank row decoders 1360a, 1360b, 1360c, and 1360d decodes the row address output from the row address multiplexer 1340 to obtain a row address The corresponding word line can be activated. For example, an activated bank row decoder may apply a word line driving voltage to a word line corresponding to a row address.

The column address latch 1350 may receive the column address COL_ADDR from the address buffer 1320 and temporarily store the received column address COL_ADDR. The column address latch 1350 may incrementally increase the column address COL_ADDR received in the burst mode. The column address latch 1350 may apply the temporarily stored or gradually increased column address COL_ADDR to the first to fourth bank column decoders 1370a, 1370b, 1370c, and 1370d, respectively.

A bank column decoder activated by the bank control logic 1330 among the first to fourth bank column decoders 1370a, 1370b, 1370c, and 1370d receives a bank address BANK_ADDR and a column address (through an input/output gating circuit 1390). COL_ADDR) can activate the corresponding sense amplifier.

The input/output gating circuit 1390 includes circuits for gating input/output data, an input data mask logic, and a read data latch for storing data output from the first to fourth bank arrays 1380a, 1380b, 1380c, and 1380d. , and a write driver for writing data to the first to fourth bank arrays 1380a, 1380b, 1380c, and 1380d.

Data to be read from one of the first to fourth bank arrays 980a, 980b, 980c, and 980d may be sensed and amplified by a sense amplifier and stored in read data latches. The data DQ stored in the read data latch may be provided to the memory controller through the data input/output buffer 1395 . Data DQ to be written in one of the first to fourth bank arrays 1380a, 1380b, 1380c, and 1380d may be provided to the data input/output buffer 1395 from the memory controller. Data DQ provided to the data input/output buffer 1395 may be written into one bank array through a write driver.

The input/output gating circuit 1390 may include a multiplexer 1391 . The multiplexer 1391 includes the multiplexer 10 described above with reference to FIG. 1, the multiplexer 30 described above with reference to FIG. 8A, the multiplexer 40 described above with reference to FIG. 8B, and FIG. It may be either the multiplexer 50 described above with reference to 8c or the multiplexer 60 described above with reference to FIG. 9 . Although not shown, the input/output gating circuit 1390 may include the transition signal generating circuit 70 of FIG. 9 . The multiplexer 1391 may convert data read in parallel from the first to fourth bank arrays 1380a, 1380b, 1380c, and 1380d into serial signals using the method described above with reference to FIGS. 1 to 12 .

As above, exemplary embodiments have been disclosed in the drawings and specifications. Although the embodiments have been described using specific terms in this specification, they are only used for the purpose of explaining the technical idea of the present disclosure, and are not used to limit the scope of the present disclosure described in the claims. . Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical scope of protection of the present disclosure should be determined by the technical spirit of the appended claims.

Claims (20)

A transmitter circuit for receiving a plurality of parallel signals and outputting a serial signal based on the plurality of parallel signals,
a clock generator generating a plurality of first clock signals having phases different from each other;
a plurality of selection circuits each comprising a plurality of selection circuits selectively providing at least two or more parallel signals among the plurality of parallel signals to an output node in response to at least two or more first clock signals among the plurality of first clock signals; plexus; and
and an output driver that generates the serial signal by amplifying the signal of the output node. According to claim 1,
At least two or more selection circuits among the plurality of selection circuits,
and providing a first parallel signal of the plurality of parallel signals to the output node in response to a predetermined one of the plurality of first clock signals. According to claim 2,
Among the plurality of selection circuits, the remaining selection circuits other than the at least two selection circuits,
wherein the two or more selection circuits are disconnected from the output node while providing the first parallel signal to the output node. According to claim 1,
The clock generator,
a multi-phase clock generator for receiving a reference clock signal from the outside and generating a plurality of second clock signals having different phases by delaying the reference clock signal; and
and a duty control circuit configured to generate the plurality of first clock signals by adjusting duty ratios of the plurality of second clock signals. According to claim 4,
The clock generator,
Transmitter circuit characterized in that for controlling the duty ratio of the plurality of first clock signals in inverse proportion to the number of the plurality of selection circuits. According to claim 1,
Each of the plurality of selection circuits,
a first P-type transistor precharging the output node based on a first logic level of a first parallel signal and a second parallel signal among the plurality of parallel signals; and
and a first N-type transistor to discharge the output node based on a second logic level of the first parallel signal and the second parallel signal. According to claim 6,
Each of the plurality of selection circuits,
The first parallel signal, a first target clock signal corresponding to the first parallel signal among the plurality of first clock signals, the second parallel signal, and the second parallel signal among the plurality of first clock signals an AND-OR-INVERTER (AOI) 22 circuit for receiving a corresponding second target clock signal and driving the first P-type transistor;
receiving a first inverted target clock signal obtained by inverting the first parallel signal and the first target clock signal, and a second inverted target clock signal obtained by inverting the second parallel signal and the second target clock signal; A transmitter circuit comprising an OR-AND-INVERTER (OAI) 22 circuit for driving a -type transistor. According to claim 7,
The AOI22 circuit,
a first sub-circuit for turning on the first P-type transistor based on the first parallel signal having a first logic level in response to the first target clock signal; and
and a second sub-circuit for turning on the first P-type transistor based on the second parallel signal having the first logic level in response to the second target clock signal. . According to claim 7,
The OAI22 circuit,
a third sub-circuit turning on the first N-type transistor based on the first parallel signal having a second logic level in response to the first clock signal to be inverted; and
and a fourth sub-circuit for turning on the first N-type transistor based on the second parallel signal having the second logic level in response to the second clock signal to be inverted. Circuit. A transmitter circuit for receiving a plurality of parallel signals and outputting a serial signal using the plurality of parallel signals,
a clock generator generating a plurality of first clock signals having phases different from each other;
Each receives a transition signal indicating whether or not the serial signal is transitioning and at least one parallel signal among the plurality of parallel signals, and outputs an output node based on signals received in response to the plurality of first clock signals. a plurality of selection circuits that drive;
an output driver generating the serial signal by amplifying the signal of the output node;
At least two or more selection circuits among the plurality of selection circuits simultaneously drive the output node based on whether the serial signal transitions or not. According to claim 10,
and a transition signal generating unit configured to generate a transition signal having an active logic level when the serial signal transitions, and to provide the transition signal to the plurality of selection circuits. According to claim 11,
Each of the plurality of selection circuits,
Transmitter characterized in that the output node is precharged or discharged based on the transition signal while another selection circuit outputs a parallel signal in response to any one of the plurality of first clock signals. Circuit. According to claim 12,
A first selection circuit among the plurality of selection circuits,
driving the output node using a first parallel signal among the plurality of parallel signals in response to a first clock signal having an active logic level among the plurality of first clock signals;
A second selection circuit among the plurality of selection circuits,
and driving the output node based on the transition signal while the first clock signal has an active logic level. According to claim 10,
When the serial signal transitions, two or more selection circuits among the plurality of selection circuits drive the output node;
and if the serial signal does not transition, one of the plurality of selection circuits drives the output node. According to claim 10,
The clock generator,
a multi-phase clock generator for receiving a reference clock signal from the outside and generating a plurality of second clock signals having different phases by delaying the reference clock signal; and
and a duty control circuit configured to generate the plurality of first clock signals by adjusting duty ratios of the plurality of second clock signals. According to claim 15,
The clock generator,
Transmitter circuit characterized in that for controlling the duty ratio of the plurality of first clock signals in inverse proportion to the number of the plurality of selection circuits. A method of operating a transmitter circuit that generates a serial signal based on a plurality of parallel signals,
generating a plurality of first clock signals having phases different from each other based on the reference clock signal;
Among a plurality of selection circuits each operating in response to one of the plurality of first clock signals and receiving two or more parallel signals among the plurality of parallel signals, two or more selection circuits are simultaneously used to drive an output node. sequentially outputting the plurality of parallel signals by doing; and
and generating the serial signal by amplifying the signal of the output node. According to claim 17,
Generating the plurality of first clock signals,
generating a plurality of second clock signals each having the same duty ratio as the reference clock signal and different phases from each other; and
and generating the plurality of first clock signals by controlling a duty ratio of the plurality of second clock signals to be in inverse proportion to the number of the plurality of selection circuits. According to claim 17,
The step of sequentially outputting the plurality of parallel signals,
and driving the output node by simultaneously using the two or more selection circuits based on whether the serial signal transitions. According to claim 19,
driving the output node using one of the plurality of selection circuits when the serial signal does not transition; and
and driving the output node by simultaneously using two or more selection circuits among the plurality of selection circuits when the serial signal transitions.

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