KR20220158413A - Design method of the ternary logic using memristors and mosfets, recording medium and device for performing the method - Google Patents

Abstract

A method of designing a ternary logic by using a memristor and a MOSFET comprises: a step of selecting a characteristic of a MOSFET-based logic gate having three logic input values; a step of setting a range of output impedance having a value as large as possible to reduce a leakage current according to the characteristic of the logic gate; a step of generating a plurality of memristor subcircuits including a combination of memristors having different series-parallel connections and different polarities satisfying a condition in which the output impedance is smaller than input impedance in the logic gate; and a step of selecting at least one memristor subcircuit according to the output strength of a target logic gate from among the plurality of memristor subcircuits. Accordingly, an impedance matching problem of a ternary logic circuit can be resolved, and design and process complexity can be reduced.

Description

Ternary logic design method using memristor and MOSFET, recording medium and device for performing this

The present invention relates to a ternary logic design method using memristors and MOSFETs, and to a recording medium and apparatus for performing the same, and more particularly, to a series/parallel connection of memristors to a logic gate circuit composed of MOSFETs. It relates to a technique for improving impedance characteristics by inserting a subcircuit composed of.

[The EDA tool was supported by the IC Design Education Center (IDEC), Korea.]

The development of binary computers has been based on the improvement of integration technology through miniaturization of devices. FinFET and Nanosheet FET are good examples of this trend. However, as the device miniaturization technology goes up to several nm, the difficulty of the technology is rapidly increasing, and various studies predict that this development will soon reach its limit. Therefore, the industry is looking for new ways to improve computational performance.

The ternary arithmetic system requires about 36.9% less operating numbers and storage space than the binary arithmetic system. The characteristics of this ternary arithmetic system enable high-density and high-performance implementation of arithmetic circuits. Due to these advantages of the ternary arithmetic system, ternary semiconductors are currently attracting great attention as a key factor for the development of computer performance.

In addition, with the development of device technology, various devices such as Tenary CMOS, CNTFET, and memristor that can design ternary computers have appeared. The emergence of these technologies provided a clear opportunity for the development of ternary computers.

Among various devices (Ternary CMOS, CNTFET, memristor, etc.) that can implement ternary logic gates, ternary logic gates composed of memristors and MOSFETs have the advantage of being the only commercial process available at present. , it has the advantage that high integration can also be achieved.

However, although memristor and MOSFET-based ternary logic gates have these advantages, signal distortion occurs due to poor input/output impedance characteristics, making commercialization difficult.

KR 10-1689159 B1 KR 10-2018-0013789 A CN 111046617 A

Therefore, the technical problem of the present invention has been focused on this point, and an object of the present invention is to provide a ternary logic design method using a memristor and a MOSFET without signal distortion.

Another object of the present invention is to provide a recording medium on which a computer program for performing the ternary logic design method using the memristor and the MOSFET is recorded.

Another object of the present invention is to provide a device for performing the ternary logic design method using the memristor and MOSFET.

A ternary logic design method using a memristor and a MOSFET according to an embodiment for realizing the object of the present invention, a ternary logic design method using a memristor and a MOSFET, has three logic input values and uses a MOSFET selecting characteristics of logic gates based thereon; setting a range of output impedance having a value as large as possible in order to reduce a leakage current according to characteristics of a logic gate; generating a plurality of memristor sub-circuits composed of memristor combinations having different polarities and serial-parallel connections that satisfy a condition that an output impedance is smaller than an input impedance in a logic gate; and selecting at least one memristor sub-circuit according to the output strength of a target logic gate from among the plurality of memristor sub-circuits.

In an embodiment of the present invention, the ternary logic design method using the memristor and the MOSFET may further include connecting the selected memristor sub-circuit to a logic gate.

In an embodiment of the present invention, the three logic input values may be -1, 0, 1 or 0, 1, 2.

In an embodiment of the present invention, the ternary logic design method using the memristor and the MOSFET may further include setting a current flowing through each memristor from V _DD to GND.

In an embodiment of the present invention, in the step of selecting the at least one memristor sub-circuit, propagation delay may be additionally taken into account when selecting the memristor sub-circuit.

In an embodiment of the present invention, the generating of the plurality of memristor sub-circuits may generate memristor sub-circuits having strengths of X1, X2, X4, X8, X16, X32, X64, and X128, respectively.

In an embodiment of the present invention, one of NTI, PTI, STI, TBUF, CONS, NCONS, TOR, TNOR, TAND, TNAND, TDEC, ANY, NANY, TSUM and TFA may be designed.

A computer program for performing a ternary logic design method using the memristor and MOSFET is recorded in a computer-readable storage medium according to an embodiment for realizing another object of the present invention.

A ternary logic design device using a memristor and a MOSFET according to an embodiment for realizing another object of the present invention described above has three logic input values and selects characteristics of a MOSFET-based logic gate selection unit; an impedance setting unit for setting a range of output impedance having a value as large as possible in order to reduce leakage current; a memristor combination unit generating a plurality of memristor sub-circuits composed of memristor combinations having different polarities and serial-parallel connections that satisfy the condition that the output impedance of the logic gate is smaller than the input impedance; and a memristor selector selecting at least one memristor sub-circuit from among the plurality of memristor sub-circuits according to a target output strength of a logic gate.

According to the ternary logic design method using the memristor and the MOSFET, it is possible to solve the impedance matching problem and reduce the complexity of the design and process through the design of the memristor subcircuit. In addition, the power consumption problem can be solved by limiting the reasonable resistance range of the memristor, and leakage can be controlled through strength design.

1 is a diagram showing an example applied to the NTI and PTI gates of the memristor sub-circuit of the present invention.
2 is examples of memristor sub-circuits according to this embodiment.
3 is a block diagram of a ternary logic design device using a memristor and a MOSFET according to an embodiment of the present invention.
4 is a diagram for explaining a relationship between an input impedance and an output impedance of a logic gate.
5 is a diagram for explaining symbols and characteristics of a memristor and schematics and symbols of TOR and TAND gates.
6 is a diagram for explaining schematics and symbols of NTI and PTI gates.
7 is a diagram for explaining strength design of an NTI gate according to an embodiment of the present invention.
8 is a diagram for explaining strength design of a TOR gate according to an embodiment of the present invention.
9 is a diagram showing schematics of STI, TBUF, and NCONS according to an embodiment of the present invention.
10 is a diagram showing schematics and symbols of a TDEC requiring impedance matching according to an embodiment of the present invention.
11 is a diagram showing schematics of TSUM and NANY according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The detailed description of the present invention which follows refers to the accompanying drawings which illustrate, by way of illustration, specific embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable one skilled in the art to practice the present invention. It should be understood that the various embodiments of the present invention are different from each other but are not necessarily mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in one embodiment in another embodiment without departing from the spirit and scope of the invention. Additionally, it should be understood that the location or arrangement of individual components within each disclosed embodiment may be changed without departing from the spirit and scope of the invention. Accordingly, the detailed description set forth below is not to be taken in a limiting sense, and the scope of the present invention, if properly described, is limited only by the appended claims, along with all equivalents as claimed by those claims. Like reference numbers in the drawings indicate the same or similar function throughout the various aspects.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the drawings.

The present invention relates to design techniques to overcome the disadvantages of memristor and MOSFET based ternary logic gates.

Referring to FIG. 1, the present invention uses a design method of inserting a subcircuit composed of series/parallel connection of memristors into a logic gate circuit composed of MOSFETs.

For example, one of X1 to X128 of FIG. 2 is inserted into the memristor subcircuit of FIG. 1 . However, these are just examples, and other forms of sub-circuits can be designed. When the sub-circuit of X1 is inserted, the propagation delay is the largest, the static current is the smallest, and the output impedance is the largest.

On the other hand, when X128 is inserted, the propagation delay is the smallest, the rated current is the highest, and the output impedance is the smallest. This design method allows the designer to properly select the impedance of the logic gate to establish the 'input impedance of B >> output impedance of A' equation, and provides a method to control power and time.

3 is a block diagram of a ternary logic design device using a memristor and a MOSFET according to an embodiment of the present invention.

The ternary logic design device (10, hereinafter) using a memristor and MOSFET according to the present invention presents the most realistic solution for designing a ternary circuit with a currently available process, and a way to solve the impedance matching problem presents

Referring to FIG. 3 , the device 10 according to the present invention includes a characteristic selection unit 110, an impedance setting unit 130, a memristor combination unit 150, and a memristor selection unit 170.

The device 10 of the present invention can be executed by installing software (application) for performing a ternary logic design using a memristor and a MOSFET, the characteristic selection unit 110, the impedance setting unit 130, Configurations of the memristor combination unit 150 and the memristor selection unit 170 may be controlled by software for performing ternary logic design using the memristor and MOSFET running in the device 10. .

The device 10 may be a separate terminal or a part of a module of the terminal. In addition, the configuration of the characteristic selection unit 110, the impedance setting unit 130, the memristor combination unit 150, and the memristor selection unit 170 may be formed as an integrated module or composed of one or more modules. can However, on the contrary, each component may be composed of a separate module.

The device 10 may be mobile or stationary. The apparatus 10 may be in the form of a server or engine, and may be a device, an apparatus, a terminal, a user equipment (UE), a mobile station (MS), or a wireless device. It can be called by other terms such as wireless device, handheld device, etc.

The device 10 may execute or manufacture various software based on an operating system (OS), that is, a system. The operating system is a system program for enabling software to use the hardware of the device, and is a mobile computer operating system such as Android OS, iOS, Windows mobile OS, Bada OS, Symbian OS, Blackberry OS, and Windows-based, Linux-based, Unix-based, It can include all computer operating systems such as MAC, AIX, and HP-UX.

The characteristic selector 110 has three logic input values and selects the characteristics of a MOSFET-based logic gate. For example, -1, 0, 1 or 0, 1, 2 can be used as the logic input value.

The impedance setting unit 130 sets a range of output impedance having a value as large as possible in order to reduce leakage current.

The memristor combination unit 150 generates a plurality of memristor subcircuits composed of memristor combinations having different polarities and serial-parallel connections that satisfy the condition that the output impedance is smaller than the input impedance of the logic gate.

The memristor selector 170 selects at least one memristor sub-circuit according to the output strength of a target logic gate from among a plurality of memristor sub-circuits.

The present invention proposes a strength design of a memristor and CMOS integrated ternary logic to solve the problem of a memristor-based ternary system. In the present invention, the design shows a design method of a ternary full-adder using V _DD as a voltage source and impedance matching to minimize process and design complexity.

The present invention can design a circuit with a process that can currently be implemented among various ternary elements, and solves the impedance matching problem in a comprehensive situation.

Based on the advantages of memristor and CMOS processes, there are studies to implement ternary logic gates that integrate memristors and CMOS, but there are problems in terms of impedance matching, design and manufacturing complexity, and static power.

Figure 4 shows the impedance matching problem in the resistor network. The input impedance (Z _I ) is the impedance viewed from the input node to the internal circuit, and the output impedance (Z _O ) is the impedance viewed from the output node to the internal circuit.

In the case of FIG. 4(a) , Z _I =R _L and Z _O =R _D . The voltage (V _I ) that the power stage can supply to the load is determined according to the ratio of Z I and Z _O. In the relationship between Z _I and Z _{O ,} it is best for Z _O to be small and Z _I to be infinite. However, memristor and CMOS based input impedances are not always infinite.

Therefore, as Z _O is smaller than Z _I and Z _I is larger than Z _O , the power stage can supply a stable voltage to the load. Such matching of Z _O , Z _I is also required in logic gate design that transfers logic values through voltages.

However, in the related art, such impedance matching has not been performed properly, and accordingly, when gates are connected in series, transmission of logic has not been performed properly. The present invention can solve the impedance matching problem by proposing and applying a strength design in a memristor and CMOS integrated ternary gate.

In addition, in the case of the conventionally proposed STI gate, V _DD /2 or/and -V _DD /2 voltage sources are used. The use of such an unusual voltage source greatly increases design and process complexity, such as making it difficult to design power tracks and place standard cells in a layout. Therefore, the present invention proposes a design that minimizes such complexity by avoiding the use of a voltage source other than V _DD .

In addition, in the case of the conventionally proposed STI gate, values of R _on and R _off cause very large static power consumption. When V _DD is applied as an input, a low impedance is formed between V _DD and GND, and a very large value of current leaks. If V _DD is continuously maintained at the input, such a large value of current continuously leaks.

Therefore, in the worst case, only integration of 10,000 gates causes leakage of several A units, making it impossible to solve the heat generation. Therefore, in the present invention, the electrostatic power problem is solved by proposing a reasonable resistance range of the memristor, and leakage is controlled through strength design.

First, the minimum logic gates necessary for the strength design of the memristor and CMOS integrated ternary logic, NTI (negative ternary inverter), PTI (positive ternary inverter), TOR, and TAND gates are described. Afterwards, the strength design is applied to the NTI and TOR gates, and the effects are explained.

The ternary logic of the present invention can be designed based on balanced ternary with three logic values, for example, (-1, 0, +1) or (0, 1, 2). Logic values (-1, 0, +1) or (0, 1, 2) can be used as one of the voltage levels (GND, V _DD /2, V _DD ).

A memristor is a passive element whose resistance changes depending on the direction of an applied current. In FIG. 5(a), when current flows from IN to OUT, the resistance of the memristor decreases until R _on . Conversely, when current flows from OUT to IN, the resistance of the memristor increases until R _off .

In the present invention, it is necessary to use as large R _on and R _off values as possible to reduce leakage current. Therefore, a memristor with R _on =100 kΩ and R _off =3.2 MΩ was used in the ternary logic design. A memristor having such a resistance range has already been reported for its fabrication possibility.

In the present invention, a MOSFET having the following state at a gate voltage (V _GS ) is used in a ternary logic design.

V _GS =0[V]: Makes NMOS OFF and PMOS ON.

V _GS = V _DD /2: Make NMOS and PMOS ON.

V _GS =V _DD : NMOS ON, PMOS OFF.

6 shows schematics and symbols of NTI and PTI gates, and operations and truth tables according to each logic input are shown in Table 1 below.

[Table 1]

In the case of the NTI gate, the NMOS is turned off and the output is pulled up only when the logic input is '-1'. For all other logic inputs, the NMOS is on and the output is pulled-down. In the case of the PTI gate, it operates in the opposite logic to the NTI.

5(b) and 5(c), schematics and symbols of TAND and TOR gates are shown, and Table 2 below shows a truth table.

[Table 2]

Current flows due to the voltage level difference between the IN1 node and the IN2 node, and the memristor resistance converges to either R _on or R _off depending on the direction of the current, and the voltage division law between the memristors causes the OUT node to The voltage level is determined. The operation of TOR/TAND according to each logic input pair is shown in Table 3 below.

[Table 3]

In the case of VIN1=VIN2, since there is no potential difference within the network, VIN1 is output as it is. In the case of VIN1≠VIN2, the output is either VIN1 or VIN2 because RM1≫RM2 or RM1≪RM2.

The present invention proposes a strength design method for memristor-based ternary logic, and as a result, not only control of propagation delay, which is a characteristic of general strength design, but also control of Z _O , Z _I leakage current It is possible.

7(a) to 7(e) are examples of strength design of the NTI gate proposed in the present invention. By connecting memristors in series or parallel, it is possible to design the strength of a memristor-based ternary gate. Changes in the characteristics of the NTI gate according to each intensity design are shown in Table 4 below.

[Table 4]

In the NTI design proposed in the present invention, the direction of the current flowing through the memristor is always constant from V _DD to GND. Therefore, in the case of designs corresponding to FIGS. 7(a), 7(b) and 7(d), each memristor resistor is fixed to R _off . Similarly, in the case of the design corresponding to FIGS. 7(c) and 7(e), each memristor resistance is fixed as R _on =R _off /32.

In addition, since the logic gate must satisfy the condition Z _O ≪ Z _I in order to fully transmit the logic, if the condition Z _O ≪ Z _I does not materialize, the designs shown in FIGS. 7(c) to 7(e) are adopted. can do. When adopting such a design, Z _O can be reduced by N/32 times, 1/N times, and 1/32 N times compared to FIG. 7(a).

On the other hand, if the delay and Z _O ≪ Z _I conditions are sufficient, the design of FIG. 7(a) can be adopted. When adopting such a design, the leakage current can be reduced by 1/N times compared to FIG. 7(a). Designers can control the device counter, leakage current, propagation delay, and Z _O by properly adjusting the polarity and connections of the memristor network.

Also, note the selection of R _on =R _off /32. In FIG. 7(d), 16 memristors should be connected in parallel in order to reduce Z _O to 1/16 times that of FIG. 7(a). However, since R _on =R _off /32, if the design of FIG. 7(c) is adopted, Z _O can be reduced by a factor of 1/16 with only two memristors.

If the advantage of the polarity conversion of the memristor is appropriately utilized, as shown in FIG. 7 and Table 5 below, it is possible to achieve strength from X1 to X128 with only a minimum amount of memristors. PTI gates can also be designed for strength by connecting memristors in series/parallel.

[Table 5]

8(a) and 8(b) show the strength design of the TOR gate proposed in the present invention, and Table 6 below shows the change in characteristics of the TOR gate according to each strength design.

[Table 6]

Similar to the strength design of the NTI gate, Z _I and Z _O leakage current can be controlled by connecting memristors in series or parallel. In the case of the design of FIG. 8(a), Z _I can be improved by connecting memristors in series or parallel. On the other hand, in the case of the design of FIG. 8(b), Z _O can be improved by connecting memristors in parallel. The TAND gate can also improve Z _I and Z _O in the same way.

Hereinafter, designing ternary logic necessary for designing a balanced ternary full-adder and finally designing a balanced ternary full-adder will be described. Strength design is applied to simple logic ternary inverter (TINV), ternary buffer (TBUF), and negative-consensus (NCONS) gates, and impedance matching is applied to the design of combinational logic 3-stage decoder (TDEC).

In ternary logic, inverters come in three variants: NTI, PTI, and STI. The NTI and PTI gates have been described above, and the STI gate will be described below. The truth table and operation of the STI gate are shown in Table 1, and the schematic is shown in Fig. 9(a). Except for logic input '0', the basic operation is the same as NTI and PTI. When the logic input is '0', both the PMOS and NMOS are turned on, and voltage is divided between M1 and M2. Since M1 and M2 have the same strength selected, the potential of the output node becomes V _DD /2.

TBUF is a gate that restores a damaged ternary signal. The schematic is composed of two STI gates connected in series as shown in FIG. 9(b).

The Consensus (CONS) gate is the logic responsible for the carry operation in ternary addition. In the case of a logic input pair (-1, -1), the output becomes a logic state '-1', and in the case of a logic input pair (+1, +1), the output becomes a logic state '+1'.

All other logic input pairs output a logic state of '0'. This CONS gate is a gate in which the output of the NCONS gate is inverted, and is composed of a connection between the NCONS gate and the STI gate. The schematic of the NCONS gate is shown in FIG. 9(c), and the truth table is shown in Table 2.

TDEC is a logic that outputs '+1' only for a specific logic input and outputs '-1' for other logic inputs. The schematic of TDEC is shown in FIG. 10(a), and the symbol is shown in FIG. 10(b).

Referring to FIG. 10(a), since the outputs of L ₁ and L ₂ do not load the gate oxide, impedance matching should be considered. Accordingly, the impedances can be matched by appropriately selecting the intensities of L ₁ , L ₂ , and L ₃ .

A Ternary summation (TSUM) gate is a logic gate responsible for the addition operation. The schematic of TSUM is shown in FIG. 11(a), and the truth table is shown in Table 1.

The negative-accept anything(NANY) logic is a logic gate in which the output of the accept anything(ANY) logic is inverted. In a balanced ternary full-adder design, it is determined whether a carry occurs from two CONS. The schematic of NANY is shown in Figure 11(b) and the truth table is shown in Table 2.

A balanced ternary full-adder may include a TSUM composed of 29 memristors and 31 transistors, and a NANY composed of 25 memristors and 27 transistors. The total number of devices used to construct the balanced ternary full-adder is 87 memristors and 97 transistors.

As a result of simulating PTI, NTI, and STI by applying the present invention, it was confirmed that propagation delay decreased as the intensity increased, and as a result of performing TDEC in consideration of impedance matching, normal operation of TDEC was confirmed.

As a result of measuring the leakage current for each intensity of the NTI, PTI, STI, and NCONS gate, it was confirmed that the leakage current decreased as the weaker intensity was selected. Therefore, memristor and CMOS-based ternary logic designers can appropriately select the strength suitable for the situation and purpose by considering power, delay, and impedance matching.

Such a ternary logic design method using a memristor and a MOSFET may be implemented as an application or implemented in the form of program commands that can be executed through various computer components and recorded on a computer-readable recording medium. The computer readable recording medium may include program instructions, data files, data structures, etc. alone or in combination.

Program instructions recorded on the computer-readable recording medium may be those specially designed and configured for the present invention, or those known and usable to those skilled in the art of computer software.

Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks and magnetic tapes, optical recording media such as CD-ROMs and DVDs, and magneto-optical media such as floptical disks. media), and hardware devices specially configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like.

Examples of program instructions include high-level language codes that can be executed by a computer using an interpreter or the like as well as machine language codes such as those produced by a compiler. The hardware device may be configured to act as one or more software modules to perform processing according to the present invention and vice versa.

Although the above has been described with reference to embodiments, those skilled in the art can variously modify and change the present invention without departing from the spirit and scope of the present invention described in the claims below. You will understand.

The ternary arithmetic system is receiving great attention as a next-generation computing technology. Since the present invention relates to the design of a logic gate, which is a key component of a ternary arithmetic unit, it can be usefully applied throughout the semiconductor industry.

10: Ternary logic design device using memristor and MOSFET
110: characteristic selection unit
130: impedance setting unit
150: memristor combination
170: memristor selection unit

Claims (9)

selecting characteristics of a logic gate having three logic input values and based on a MOSFET;
setting a range of output impedance having a value as large as possible in order to reduce a leakage current according to characteristics of a logic gate;
generating a plurality of memristor sub-circuits composed of memristor combinations having different polarities and serial-parallel connections that satisfy a condition that an output impedance is smaller than an input impedance in a logic gate; and
A ternary logic design method using memristors and MOSFETs, comprising: selecting at least one memristor sub-circuit according to the output strength of a target logic gate from among a plurality of memristor sub-circuits.
According to claim 1,
A ternary logic design method using memristors and MOSFETs, further comprising: connecting the selected memristor sub-circuit to a logic gate.
According to claim 1,
Three logic input values are -1, 0, 1 or 0, 1, 2, a ternary logic design method using memristors and MOSFETs.
According to claim 1,
Setting the current flowing through each memristor from V _DD to GND; further comprising a ternary logic design method using memristors and MOSFETs.
2. The method of claim 1, wherein selecting the at least one memristor subcircuit comprises:
A ternary logic design method using memristors and MOSFETs that additionally considers propagation delay when selecting memristor subcircuits.
The method of claim 1 , wherein the generating of the plurality of memristor sub-circuits comprises:
A ternary logic design method using memristors and MOSFETs to generate memristor subcircuits having strengths of X1, X2, X4, X8, X16, X32, X64 and X128, respectively.
According to claim 1,
Ternary logic design method using memristors and MOSFETs to design one of NTI, PTI, STI, TBUF, CONS, NCONS, TOR, TNOR, TAND, TNAND, TDEC, ANY, NANY, TSUM, and TFA.
A computer-readable storage medium on which a computer program for performing the ternary logic design method using the memristor and the MOSFET according to any one of claims 1 to 7 is recorded.
a characteristic selection unit that has three logic input values and selects characteristics of a MOSFET-based logic gate;
an impedance setting unit for setting a range of output impedance having a value as large as possible in order to reduce leakage current;
a memristor combination unit generating a plurality of memristor sub-circuits composed of memristor combinations having different polarities and serial-parallel connections that satisfy the condition that the output impedance of the logic gate is smaller than the input impedance; and
A memristor selection unit for selecting at least one memristor sub-circuit according to the output strength of a target logic gate among a plurality of memristor sub-circuits; a ternary logic design device using memristors and MOSFETs. .

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