KR20220149890A - Display device and manufacturing method thereof - Google Patents

Abstract

Disclosed is a display device which may comprise: a substrate; and a plurality of pixels provided on the substrate. Each of the plurality of the pixels includes: a pixel circuit layer provided on the substrate to include at least one transistor; a first electrode provided on the pixel circuit layer and electrically connected to the transistor; a bank provided on the first electrode to include an opening portion exposing the first electrode; a conductive pattern provided on a lateral surface of the bank surrounding the opening portion, and on the first electrode exposed; a light-emitting element disposed on the conductive pattern within the opening portion to be electrically connected to the first electrode; and a second electrode provided on the light-emitting element. The conductive pattern may be a guide member which guides light emitted by the light-emitting element to an upper part of the second electrode. Accordingly, a manufacturing process can be simplified and light-output efficiency of a pixel can be enhanced.

Description

Display device and manufacturing method thereof

The present invention relates to a display device and a method for manufacturing the same.

Recently, as interest in information display has increased, research and development of display devices is continuously being made.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display device capable of improving light output efficiency of a pixel while simplifying a manufacturing process, and a method for manufacturing the same.

A display device according to an embodiment of the present invention includes: a substrate; and a plurality of pixels provided on the substrate. Each of the plurality of pixels may include: a pixel circuit layer provided on the substrate and including at least one transistor; a first electrode provided on the pixel circuit layer and electrically connected to the transistor; a bank provided on the first electrode and including an opening exposing the first electrode; a conductive pattern provided on a side surface of the bank surrounding the opening and the exposed first electrode; a light emitting device positioned on the conductive pattern in the opening and electrically connected to the first electrode; and a second electrode provided on the light emitting device. Here, the conductive pattern may be a guide member for guiding the light emitted from the light emitting device to the upper portion of the second electrode.

In an embodiment, the light emitting device may include a first end and a second end in a longitudinal direction. The first end may be electrically connected to the conductive pattern, and the second end may be electrically connected to and in contact with the second electrode.

In an embodiment, the light emitting device includes: a bonding electrode positioned at the first end and electrically connected to the conductive pattern in contact with the conductive pattern; a third semiconductor layer positioned at the second end and electrically connected to the second electrode in contact with the second electrode; a second semiconductor layer positioned on the bonding electrode; a first semiconductor layer located between the third semiconductor layer and the second semiconductor layer; and an active layer positioned between the first semiconductor layer and the second semiconductor layer.

In an embodiment, the first semiconductor layer may be an n-type semiconductor layer doped with an n-type dopant, and the second semiconductor layer may be a p-type semiconductor layer doped with a p-type dopant.

In an embodiment, the conductive pattern may be bonded to a bonding electrode of the light emitting device.

In an embodiment, the conductive pattern may include a first layer positioned on the first electrode; and a second layer positioned on the first layer. The first layer may be in direct contact with the first electrode, and the second layer may be in direct contact with the bonding electrode.

In an embodiment, each of the first and second layers may include a metal that reflects light emitted from the light emitting device. Here, the first layer may include a metal selected from gold and tin, and the second layer may include a metal selected from titanium, copper, and nickel. The first layer and the second layer may have different thicknesses.

In an embodiment, one region of the conductive pattern located on the side surface of the bank may have a slope corresponding to an inclination angle of the side surface of the bank.

In an embodiment, one region of the conductive pattern may include a protrusion protruding toward the second electrode.

In an embodiment, each of the plurality of pixels may further include an intermediate layer positioned between the bank and the second electrode to fill the opening. The intermediate layer is a fixing member for fixing the light emitting device, has adhesiveness, and may include an organic material that is cured by heat or light.

In an embodiment, each of the plurality of pixels may include a light emitting area in which the light emitting device is disposed and a non-emission area adjacent to the light emitting area. The bank may correspond to the non-emission area, and the opening may correspond to the light-emitting area.

In an embodiment, each of the plurality of pixels may include: a cover layer disposed entirely on the second electrode; and an upper substrate positioned on the cover layer.

In one embodiment, the upper substrate may include: a base layer positioned on the cover layer so that one surface faces the light emitting device; a light conversion pattern positioned on the one surface of the base layer to correspond to the light emitting region; and a light blocking pattern positioned on the one surface of the base layer to correspond to the non-emission area.

In an embodiment, the light conversion pattern may include: a color filter positioned on the one surface of the base layer; and a color conversion layer disposed on the color filter with an insulating layer interposed therebetween to correspond to the light emitting device and including color conversion particles.

In an embodiment, the light blocking pattern may include: a first light blocking pattern located on the one surface of the base layer; and a second blocking pattern positioned on the insulating layer to correspond to the first blocking pattern.

In an embodiment, the upper substrate may further include a capping layer disposed entirely on the color conversion layer and the second light blocking pattern.

In an embodiment, the opening of the bank may have a width greater than a width of the first electrode.

In an embodiment, the pixel circuit layer may further include a passivation layer disposed on the transistor. The opening of the bank may expose the first electrode as a whole and expose a part of the passivation layer.

In an embodiment, the conductive pattern may be provided on the exposed portion of the first electrode and the exposed passivation layer.

In an embodiment, the first electrode may include a stepped groove from one surface thereof toward the pixel circuit layer. The groove may correspond to the opening of the bank.

In an embodiment, the conductive pattern may include: a third layer disposed on the exposed first electrode and side surfaces of the bank; a first layer disposed on the third layer; and a second layer disposed between the first layer and the light emitting device. The third layer may be in direct contact with the first electrode, and the second layer may be in direct contact with the light emitting device.

In an embodiment, the third layer may include a metal selected from titanium, copper, and nickel, the first layer may include aluminum, and the second layer may include a metal selected from gold and tin can do.

In one embodiment, the first layer may be located on the uppermost layer on the side of the bank.

A display device according to another embodiment of the present invention includes: a substrate; and a plurality of pixels provided on the substrate. Each of the plurality of pixels may include: a pixel circuit layer provided on the substrate and including at least one transistor; a first electrode provided on the pixel circuit layer and electrically connected to the transistor; a bank provided on the first electrode and including an opening exposing the first electrode; a conductive pattern provided on a side surface of the bank surrounding the opening and the exposed first electrode; a light emitting element positioned on the conductive pattern in the opening and electrically connected to the first electrode; and a second electrode provided on the light emitting device.

In an embodiment, the conductive pattern includes a third layer provided on the first electrode, a first layer provided on the third layer, and a second layer provided on the first layer on the first electrode. may include

In an embodiment, the first layer may be a guide member for guiding the light emitted from the light emitting device to an upper portion of the second electrode.

In an embodiment, the second layer may be a bonding member that is bonded to the light emitting device.

The above-described display device may include: forming at least one transistor on a substrate; forming a first electrode electrically connected to the transistor on the transistor; forming a photosensitive pattern exposing the insulating material layer by applying an insulating material layer and a photosensitive material layer on the first electrode and then removing the photosensitive material layer on one region of the first electrode; forming a bank including an opening exposing a region of the first electrode by removing the exposed insulating material layer by using the photosensitive pattern as an etch mask; forming a conductive layer entirely on the photosensitive pattern and the exposed region of the first electrode; forming a conductive pattern on one region of the first electrode by removing the photosensitive pattern and the conductive layer disposed on the photosensitive pattern by a lift-off method; applying a fluid intermediate layer material to the entire surface of the conductive pattern and the bank; disposing a transfer substrate to which at least one light emitting element has been transferred on the substrate, bonding the light emitting element and the conductive pattern, curing the intermediate layer material to form an intermediate layer, and then removing the transfer substrate; and forming a second electrode on the light emitting device and the intermediate layer.

In an embodiment, the conductive pattern may be a guide member for guiding the light emitted from the light emitting device to an upper portion of the second electrode.

According to an embodiment of the present invention, a conductive pattern (or "bonding electrode") positioned on the first electrode (or "pixel electrode", "anode electrode") and bonding to the light emitting device is formed by the light emitted from the light emitting device. By utilizing as a reflective member (or light guide member) for guiding (or reflecting) in the image display direction, a display device and a manufacturing method thereof in which a process for forming a separate reflective member is omitted can be provided.

In addition, according to an embodiment of the present invention, a display device in which light output efficiency of each pixel is improved by arranging a conductive pattern between the light emitting element and the first electrode to guide light traveling downward of the light emitting element in the image display direction; A method for its preparation may be provided.

Effects according to an embodiment of the present invention are not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a perspective view schematically illustrating a display device according to an exemplary embodiment.
FIG. 2 is a cross-sectional view schematically illustrating the display device of FIG. 1 .
3 is a plan view schematically illustrating a display panel according to an exemplary embodiment.
4 and 5 are cross-sectional views schematically illustrating a display panel according to an exemplary embodiment.
6 is a circuit diagram illustrating an electrical connection relationship between components included in each pixel illustrated in FIG. 3 according to an exemplary embodiment.
7 is a diagram schematically illustrating light emitting devices grown on a growth substrate.
8 and 9 schematically illustrate a pixel according to an embodiment of the present invention, and are schematic cross-sectional views illustrating a connection structure between the transistor (eg, a first transistor) shown in FIG. 6 and a light emitting device. .
10A to 10C are enlarged views of the EA area of FIG. 8 .
11 and 12 are cross-sectional views schematically illustrating a pixel according to another exemplary embodiment of the present invention.
13A to 13H are schematic cross-sectional views sequentially illustrating a method of manufacturing the pixel of FIG. 8 .
14A is a cross-sectional view taken along line I to I′ of FIG. 3 .
14B is a schematic cross-sectional view of a display device according to an exemplary embodiment.
15 to 18 are diagrams illustrating application examples of display devices according to embodiments of the present invention.
19 to 22 are cross-sectional views schematically illustrating a pixel according to another exemplary embodiment of the present invention.

Since the present invention can have various changes and can have various forms, specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention.

In describing each figure, like reference numerals have been used for like elements. In the accompanying drawings, the dimensions of the structures are enlarged than the actual size for clarity of the present invention. Terms such as first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component.

In the present application, terms such as “comprise” or “have” are intended to designate that a feature, number, step, operation, component, part, or combination thereof described in the specification exists, but one or more other features It is to be understood that it does not preclude the possibility of the presence or addition of numbers, steps, operations, components, parts, or combinations thereof. Also, when a part of a layer, film, region, plate, etc. is said to be “on” another part, this includes not only cases where it is “directly on” another part, but also cases where another part is in between. In addition, in the present specification, when a portion such as a layer, film, region, or plate is formed on another portion, the formed direction is not limited only to the upper direction, and includes those formed in the side or lower direction. . Conversely, when a part, such as a layer, film, region, plate, etc., is "under" another part, it includes not only cases where it is "directly under" another part, but also a case where another part is in between.

In the present application, "a certain component (eg 'first component') is "(functionally or communicatively) connected to another component (eg 'second component') ((operatively or communicatively) When it is referred to as "coupled with / to)" or "connected to", the certain component is directly connected to the other component, or another component (eg, a 'third component') It should be understood that it can be connected through. In addition, in the present application, "connection" or "connection" may mean a physical and/or electrical connection or connection inclusively.

Hereinafter, preferred embodiments of the present invention and other matters necessary for those skilled in the art to easily understand the contents of the present invention will be described in detail with reference to the accompanying drawings. In the description below, expressions in the singular also include the plural unless the context clearly includes only the singular.

1 is a perspective view schematically illustrating a display device DD according to an embodiment of the present invention, FIG. 2 is a cross-sectional view schematically illustrating the display device DD of FIG. 1 , and FIG. 3 is an embodiment of the present invention is a plan view schematically showing the display panel DP according to FIG. 4 and FIG. 5 are cross-sectional views schematically illustrating the display panel DP according to an exemplary embodiment of the present invention.

1 to 5 , the display device DD may include a display panel DP and a window WD.

The display device DD may be provided in various shapes. For example, the display device DD may be provided in a rectangular plate shape having two pairs of sides parallel to each other, but the present invention is not limited thereto. When the display device DD is provided in a rectangular plate shape, one pair of sides may be provided longer than the other pair of sides. Although the drawing shows that the display device DD has an angled corner portion made of a straight line, the present invention is not limited thereto. According to an exemplary embodiment, the display device DD provided in the shape of a rectangular plate may have a round shape at a corner where one long side and one short side contact each other.

In FIG. 1 , for convenience of explanation, the display device DD has a rectangular shape having a pair of long sides and a pair of short sides. The extending direction of the side is indicated by the first direction DR1 and the thickness direction of the display device DD is indicated by the third direction DR3 . The first to third directions DR1 , DR2 , and DR3 may refer to directions indicated by the first to third directions DR1 , DR2 , and DR3 , respectively.

In an embodiment, at least a portion of the display device DD may have flexibility, and may be folded at the flexible portion. The display device DD may include a display area DD_DA displaying an image and a non-display area DD_NDA provided on at least one side of the display area DD_DA. The non-display area DD_NDA is an area in which an image is not displayed. According to an exemplary embodiment, the shape of the display area DD_DA and the shape of the non-display area DD_NDA may be relatively designed.

According to an embodiment, the display device DD may include a sensing area and a non-sensing area. The display device DD may not only display an image through the sensing area, but may also sense a touch input made on the display surface (or input surface) or detect light incident from the front. The non-sensing area may surround the sensing area, but this is exemplary and not limited thereto. According to an embodiment, a partial area of the display area DD_DA may correspond to the sensing area.

The display panel DP may display an image. The display panel DP includes an organic light emitting display panel (OLED panel) using an organic light emitting diode as a light emitting device, and a nano-scale LED display panel using a micro light emitting diode as a light emitting device. , a display panel capable of self-emission such as a quantum dot organic light emitting display panel (QD OLED panel) using quantum dots and an organic light emitting diode may be used. In addition, the display panel DP includes a liquid crystal display panel (LCD panel), an electro-phoretic display panel (EPD panel), and an electro-wetting display panel (EWD panel). ) may be used. When a non-emission display panel is used as the display panel DP, the display device DD may include a backlight unit that supplies light to the display panel DP.

The display panel DP may include a substrate SUB and a plurality of pixels PXL provided on the substrate SUB.

The substrate SUB may be formed of one area having an approximately rectangular shape. However, the number of regions provided on the substrate SUB may be different from the above-described example, and the shape of the substrate SUB may have a different shape according to regions provided on the substrate SUB.

The substrate SUB may be made of an insulating material such as glass or resin. In addition, the substrate SUB may be made of a material having flexibility to be bent or folded, and may have a single-layer structure or a multi-layer structure. For example, the flexible material includes polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, and polyether. Polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, tri It may include at least one of cellulose acetate (triacetate cellulose) and cellulose acetate propionate (cellulose acetate propionate). However, the material constituting the substrate SUB is not limited to the above-described embodiments.

The substrate SUB may include a display area DA and a non-display area NDA. The display area DA is an area in which the pixels PXL are provided to display an image, and the non-display area NDA is an area in which the pixels PXL are not provided and may be an area in which an image is not displayed.

The display area DA of the substrate SUB (or the display panel DP) corresponds to the display area DD_DA of the display device DD, and the non-display area of the substrate SUB (or the display panel DP). (NDA) may correspond to the non-display area DD_NDA of the display device DD. The non-display area NDA may correspond to a bezel area of the display device DD.

The non-display area NDA may be provided on at least one side of the display area DA. The non-display area NDA may surround a circumference (or an edge) of the display area DA. A portion of the wiring unit connected to the pixels PXL and a driving unit connected to the wiring unit and driving the pixels PXL may be provided in the non-display area NDA.

The wiring unit may electrically connect the driver and the pixels PXL. A portion of the wiring unit may be a fan-out line that provides a signal to each pixel PXL and is connected to signal lines connected to each pixel PXL, for example, a scan line, a data line, and the like.

The pixels PXL may be provided in the display area DA of the substrate SUB. Each of the pixels PXL may be a minimum unit for displaying an image. The pixels PXL may include a light emitting device emitting white light and/or color light. Each of the pixels PXL may emit any one color among red, green, and blue, but is not limited thereto, and may emit colors such as cyan, magenta, and yellow.

The pixels PXL may be arranged in a matrix form along a row extending in the first direction DR1 and a column extending in a second direction DR2 crossing the first direction DR1 . However, the arrangement form of the pixels PXL is not particularly limited and may be arranged in various forms. Although the drawings show that the pixels PXL have a rectangular shape, the present invention is not limited thereto and may be modified into various shapes. Also, when a plurality of pixels PXL are provided, they may be provided to have different areas (or sizes). For example, in the case of the pixels PXL having different colors of emitted light, the pixels PXL may be provided in different areas (or sizes) or in different shapes for each color.

The driver may control driving of the pixel PXL by providing a predetermined signal and a predetermined power to each pixel PXL through the wiring unit.

As shown in FIG. 4 , the display panel DP may include a pixel circuit layer PCL, a display device layer DPL, and a cover layer CVL sequentially disposed on a substrate SUB.

The pixel circuit layer PCL is provided on the substrate SUB and may include a plurality of transistors and signal lines connected to the transistors. For example, each transistor may have a form in which a semiconductor layer, a gate electrode, a first terminal, and a second terminal are sequentially stacked with an insulating layer interposed therebetween. The semiconductor layer may include amorphous silicon, poly silicon, low temperature poly silicon, and an organic semiconductor. The gate electrode, the first terminal, and the second terminal may include one of aluminum (Al), copper (Cu), titanium (Ti), and molybdenum (Mo), but the present invention is not limited thereto. Also, the pixel circuit layer PCL may include one or more insulating layers.

A display device layer DPL may be disposed on the pixel circuit layer PCL. The display element layer DPL may include a light emitting element emitting light. The light emitting device may be, for example, an organic light emitting diode or an inorganic light emitting device including an inorganic light emitting material, or a light emitting device that emits light by changing the wavelength of light emitted using quantum dots.

A cover layer CVL may be selectively disposed on the display device layer DPL. The cover layer CVL may be in the form of an encapsulation substrate or a multilayer encapsulation film. When the cover layer CVL is in the form of the encapsulation layer, it may include an inorganic layer and/or an organic layer. For example, the cover layer CVL may have a form in which an inorganic layer, an organic layer, and an inorganic layer are sequentially stacked. The cover layer CVL may prevent external air and moisture from penetrating into the display device layer DPL and the pixel circuit layer PCL.

In some embodiments, an upper substrate U_SUB may be disposed on the cover layer CVL as shown in FIG. 5 . The upper substrate U_SUB uses quantum dots to change the wavelength (or color) of light emitted from the display element layer DPL, and also uses a color filter to selectively transmit light of a specific wavelength (or specific color). It may include a light conversion pattern (layer). The upper substrate U_SUB may be formed on the substrate SUB on which the display element layer DPL is provided through an adhesion process using an adhesive layer. The upper substrate U_SUB will be described later with reference to FIGS. 11 and 12 .

Meanwhile, although it has been described that the light conversion pattern is provided separately from the display element layer DPL, the present invention is not limited thereto. For example, the light emitting device provided in the display device layer DPL may be implemented as a light emitting device that emits light by changing the wavelength of light emitted using quantum dots.

A window WD for protecting an exposed surface of the display panel DP may be provided on the display panel DP. The window WD may protect the display panel DP from external impact and provide an input surface and/or a display surface to the user. The window WD may be coupled to the display panel DP using an optically transparent adhesive (or adhesive) member OCA.

The window WD may have a multilayer structure selected from a glass substrate, a plastic film, and a plastic substrate. Such a multi-layer structure may be formed through a continuous process or an adhesion process using an adhesive layer. The window WD may be fully or partially flexible.

A touch sensor (or an input sensing layer) may be disposed between the display panel DP and the window WD. The touch sensor may be disposed directly on a surface on which an image is emitted from the display panel DP to receive a user's touch input.

6 is a circuit diagram illustrating an electrical connection relationship between components included in each pixel PXL illustrated in FIG. 3 according to an exemplary embodiment.

For example, FIG. 6 illustrates an electrical connection relationship between components included in a pixel PXL that may be applied to an active matrix type display device according to an exemplary embodiment. However, the types of components included in the pixel PXL that can be applied to the embodiment of the present invention are not limited thereto.

In FIG. 6 , not only the components included in the pixel PXL illustrated in FIG. 3 but also an area in which the components are provided is referred to as a pixel PXL. The pixel PXL illustrated in FIG. 6 may be any one of the pixels PXL included in the display panel DP of FIG. 3 (or the display device DD of FIG. 1 ), and the pixels PXL may have substantially the same or similar structures to each other.

1 to 6 , a pixel PXL may include a light emitting unit EMU (or a light emitting unit) that generates light having a luminance corresponding to a data signal. Also, the pixel PXL may selectively further include a pixel circuit PXC for driving the light emitting unit EMU.

In some embodiments, the light emitting unit EMU includes a first power line PL1 to which a voltage of the first driving power VDD is applied and a second power line PL2 to which a voltage of the second driving power VSS is applied. It may include a light emitting device LD connected therebetween. For example, the light emitting unit EMU may include a light emitting device LD connected between the first electrode AE (or the pixel electrode) and the second electrode CE. In an embodiment, the first electrode AE may be an anode, and the second electrode CE may be a cathode.

The light emitting device LD included in the light emitting unit EMU includes a first end connected to the first driving power VDD through the first electrode AE and the second driving power VSS through the second electrode CE. ) may include a second end connected to. The first driving power VDD and the second driving power VSS may have different potentials. For example, the first driving power VDD may be set as a high potential power, and the second driving power VSS may be set as a low potential power. In this case, the potential difference between the first and second driving power sources VDD and VSS may be set to be equal to or greater than the threshold voltage of the light emitting device LD during the light emission period of the pixel PXL.

As described above, the light emitting device LD connected between the first electrode AE and the second electrode CE to which voltages of different potentials are respectively supplied constitute an effective light source and the light emitting unit EMU of each pixel PXL. ) can be implemented.

The light emitting device LD may emit light with a luminance corresponding to the driving current supplied through the pixel circuit PXC. For example, during each frame period, the pixel circuit PXC may supply a driving current corresponding to a grayscale value of the corresponding frame data to the light emitting unit EMU. The driving current supplied to the light emitting unit EMU may flow through the light emitting device LD. Accordingly, the light emitting unit EMU may emit light while the light emitting device LD emits light with a luminance corresponding to the driving current.

The pixel circuit PXC may be connected to the scan line Si and the data line Dj of the pixel PXL. For example, when it is assumed that the pixels PXL are disposed in the i (i is a natural number)-th row and j (j is a natural number)-th column of the display area DA of the display panel DP (or the substrate SUB), the The pixel circuit PXC of the pixel PXL may be connected to the i-th scan line Si and the j-th data line Dj of the display area DA. In some embodiments, the pixel circuit PXC may include first and second transistors T1 and T2 and a storage capacitor Cst. However, the structure of the pixel circuit PXC is not limited to the embodiment illustrated in FIG. 6 .

The first transistor T1 is a driving transistor for controlling a driving current applied to the light emitting unit EMU, and may be connected between the light emitting unit EMU and the first driving power VDD. Specifically, the first terminal of the first transistor T1 may be connected (or connected) to the light emitting unit EMU, and the second terminal of the first transistor T1 may be connected to the second terminal through the first power line PL1. The first driving power source VDD may be connected, and the gate electrode of the first transistor T1 may be connected (or connected) to the first node N1 . The first transistor T1 may control an amount of a driving current flowing from the first driving power VDD to the light emitting unit EMU according to a voltage connected to the first node N1 .

The second transistor T2 is a switching transistor that selects the pixel PXL in response to a scan signal applied to the scan line Si and activates the pixel PXL, and the data line Dj and the first node N1 . can be connected between A first terminal of the second transistor T2 may be connected (or connected) to the data line Dj, and a second terminal of the second transistor T2 may be connected (or connected) to the first node N1. The gate electrode of the second transistor T2 may be connected (or connected) to the scan line Si. The first terminal and the second terminal of the second transistor T2 are different terminals. For example, if the first terminal is a source electrode, the second terminal may be a drain electrode.

The second transistor T2 is turned on when a scan signal of a voltage (eg, a low voltage) capable of turning on the second transistor T2 is supplied from the scan line Si to the data line ( Dj) and the first node N1 are electrically connected. At this time, the data signal of the corresponding frame is supplied to the data line Dj, and accordingly, the data signal is transmitted to the first node N1. The data signal transferred to the first node N1 is charged in the storage capacitor Cst.

One electrode of the storage capacitor Cst may be connected (or connected) to the first driving power source VDD, and the other electrode may be connected (or connected) to the first node N1 . The storage capacitor Cst may charge the data voltage corresponding to the data signal supplied to the first node N1 and maintain the charged voltage until the data signal of the next frame is supplied.

In FIG. 6 , the second transistor T2 for transferring the data signal to the inside of the pixel PXL, the storage capacitor Cst for storing the data signal, and the driving current corresponding to the data signal to the light emitting device LD The pixel circuit PXC including the first transistor T1 for supplying is illustrated.

However, the present invention is not limited thereto, and the structure of the pixel circuit PXC may be variously changed.

7 is a diagram schematically illustrating light emitting devices LD grown on a growth substrate 101 .

1 to 7 , each light emitting device LD may be fabricated and positioned on the growth substrate 101 .

The growth substrate 101 may be formed of a conductive substrate or an insulating substrate. For example, the growth substrate 101 may be formed of at least one of sapphire, SiC, Si, GaAs, GaN, ZnO, Si, GaP, InP, Ge, and Ga ₂ O ₃ .

Each light emitting device LD may emit light according to recombination of electrons and holes according to a current flowing between the first end EP1 and the second end EP2 . Using this principle, each light emitting element LD may be used as a light source (or light source) of various light emitting devices including the pixel PXL.

Each light emitting device LD may include a first semiconductor layer 11 , a second semiconductor layer 13 , and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13 . have. In some embodiments, the light emitting device LD may further include a third semiconductor layer 15 . The third semiconductor layer 15 may be positioned on the first semiconductor layer 11 . Each light emitting device LD is a vertical type in which a third semiconductor layer 15 , a first semiconductor layer 11 , an active layer 12 , and a second semiconductor layer 13 are sequentially stacked on a growth substrate 101 . A light emitting laminate can be implemented.

The light emitting device LD may be provided in a shape extending in one direction. When the extending direction of the light emitting device LD is referred to as a longitudinal direction, the light emitting device LD may include a first end EP1 and a second end EP2 along the longitudinal direction. In an embodiment, the longitudinal direction may be parallel to the thickness direction of the growth substrate 101 . A bonding electrode BDE1 (or a first bonding electrode) disposed on the second semiconductor layer 13 may be positioned at the first end EP1 of the light emitting device LD, and the second The third semiconductor layer 15 may be positioned at the end EP2 . However, the present invention is not limited thereto, and when the third semiconductor layer 15 is omitted, the first semiconductor layer 11 may be positioned at the second end EP2 of the light emitting device LD.

The above-described light emitting device LD may include, for example, a light emitting diode (LED) manufactured to have a diameter and/or a length L of about a nano scale to a micro scale. have. In an embodiment, the light emitting device LD may have a width W of about 5 μm and a length L of about 5.5 μm, but is not limited thereto. The size of the light emitting device LD may be variously changed to meet the requirements (or design conditions) of the lighting device and the self-luminous display device to which each light emitting device LD is applied.

The third semiconductor layer 15 is a layer stacked on the growth substrate 101 and may include a gallium nitride (GaN) semiconductor material doped with a low concentration of impurities. The third semiconductor layer 15 may be provided to protect the active layer 12 from light caused by laser lift-off in the process of manufacturing the light emitting device LD, for example, the vertical light emitting device LD. It is not limited. The third semiconductor layer 15 may be selectively provided. For example, the third semiconductor layer 15 may remain in the growth substrate 101 when the light emitting devices LD are separated from the growth substrate 101 . Also, according to an embodiment, the third semiconductor layer 15 may be a semiconductor layer integrally formed with the first semiconductor layer 11 . In this case, the third semiconductor layer 15 may be an n-type semiconductor layer.

The first semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer 11 includes a semiconductor material of any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and includes a first conductive dopant (or an n-type dopant) such as Si, Ge, Sn, or the like. ) may be a doped n-type semiconductor layer. However, the material constituting the first semiconductor layer 11 is not limited thereto, and in addition to this, the first semiconductor layer 11 may be formed of various materials. In an embodiment of the present invention, the first semiconductor layer 11 may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or an n-type dopant). In some embodiments, the first semiconductor layer 11 and the third semiconductor layer 15 may constitute an n-type semiconductor layer of each of the light emitting devices LD.

In FIG. 7 , it is illustrated that the outer peripheral surface of the first semiconductor layer 11 is positioned on the same line as the outer peripheral surface of each of the active layer 11 and the second semiconductor layer 13 for convenience, but the present invention is not limited thereto. In some embodiments, the outer peripheral surface of the first semiconductor layer 11 may be provided in a form extending outward from the outer peripheral surface of each of the active layer 11 and the second semiconductor layer 13 . In this case, the first semiconductor layer 11 of one light emitting device LD may be connected to the first semiconductor layer 11 of another light emitting device LD.

The active layer 12 is disposed on the first semiconductor layer 11 and may be a region in which electrons and holes are recombinated. As electrons and holes recombine in the active layer 12 , light (or light) having a wavelength corresponding to the transition to a low energy level may be generated. The active layer 12 may include, for example, a semiconductor material having a composition formula of InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), It may be formed as a single or multiple quantum wells structure. For example, when the active layer 12 is formed in a multi-quantum well structure, the active layer 12 includes a barrier layer, a strain reinforcing layer, and a well layer as one unit. It can be repeatedly stacked periodically. However, the structure of the active layer 12 is not limited to the above-described embodiment. The active layer 12 may include a first surface in contact with the first semiconductor layer 11 and a second surface in contact with the second semiconductor layer 13 .

The second semiconductor layer 13 is disposed on the second surface of the active layer 12 and provides holes to the active layer 12 . The second semiconductor layer 13 may include a semiconductor layer of a different type from that of the first semiconductor layer 11 . For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 includes a semiconductor material of at least one of InAlGaN, GaN, AlGaN, InGaN, AlN, InN, and a dopant having a second conductivity such as Mg, Zn, Ca, Sr, Ba, etc. ( Alternatively, a p-type semiconductor layer doped with a p-type dopant may be included. However, the material constituting the second semiconductor layer 13 is not limited thereto, and various materials other than this may constitute the second semiconductor layer 13 . In an embodiment of the present invention, the second semiconductor layer 13 may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or a p-type dopant).

Each light emitting device LD may include a bonding electrode BDE1 (or a first bonding electrode) disposed on the second semiconductor layer 13 . The bonding electrode BDE1 may be bonded to the first electrode AE of the light emitting unit EMU. In some embodiments, each light emitting device LD may selectively include a separate contact electrode in ohmic contact with the second semiconductor layer 13 between the second semiconductor layer 13 and the bonding electrode BDE1 .

Each light emitting device LD may further include an insulating layer IL. However, in some embodiments, the insulating layer IL may be omitted or provided to cover only a portion of the light emitting stack.

The insulating layer IL may include a transparent insulating material. For example, the insulating film IL may include silicon oxide (SiO _x ), silicon nitride (SiN _x ), silicon oxynitride (SiO _x N _y ), aluminum oxide (AlO _x ), titanium oxide (TiO _x ), hafnium oxide ( HfO _x ), titanium strontium oxide (SrTiO _x ), cobalt oxide (Co _x O _y ), magnesium oxide (MgO), zinc oxide (ZnO), ruthenium oxide (RuO _x ), nickel oxide (NiO), tungsten oxide ( WO _x ), tantalum oxide (TaO _x ), gadolinium oxide (GdO _x ), zirconium oxide (ZrO _x ), gallium oxide (GaO _x ), vanadium oxide (V _x O _y ), ZnO:Al, ZnO:B, In _x O _y :H, niobium oxide (Nb _x O _y ), magnesium fluoride (MgF _X ), aluminum fluoride (AlF _x ), alucone polymer film, titanium nitride (TiN), tantalum nitride (TaN), aluminum nitride ( AlN _X ), gallium nitride (GaN), tungsten nitride (WN), hafnium nitride (HfN), niobium nitride (NbN), gadolinium nitride (GdN), zirconium nitride (ZrN), vanadium nitride (VN), etc. It may include one or more insulating materials selected from, but is not limited thereto, and various materials having insulating properties may be used as the material of the insulating layer IL.

The insulating layer IL may be provided in the form of a single layer (or a single layer) or may be provided in the form of a multilayer (or multilayer) including a double layer. For example, when the insulating layer IL is formed of a double layer including a first insulating layer and a second insulating layer sequentially stacked, the first insulating layer and the second insulating layer are made of different materials (or materials). and may be formed by different processes. In some embodiments, the first insulating layer and the second insulating layer may be formed of the same material by a continuous process.

The insulating layer IL may prevent an electrical short circuit that may occur when the active layer 12 comes into contact with a conductive material other than the first and second semiconductor layers 11 and 13 . The insulating layer IL may reduce surface defects of the light emitting device LD, thereby improving the lifetime and luminous efficiency of the light emitting device LD. When the plurality of light emitting devices LD are closely disposed on the growth substrate 101 , the insulating layer IL may prevent an undesirable short circuit between the light emitting devices LD. As long as the active layer 12 can prevent a short circuit with an external conductive material, whether or not the insulating layer IL is provided is not limited.

The insulating film IL may be provided in a form that completely surrounds the outer peripheral surfaces of the second semiconductor layer 13 , the active layer 12 , the first semiconductor layer 11 , and the third semiconductor layer 15 , but is limited thereto. it is not The insulating layer IL may not surround the outer peripheral surface of the bonding electrode BDE1 so that the bonding electrode BDE1 is exposed to the outside.

The plurality of light emitting devices LD formed on the growth substrate 101 are cut using a laser or the like along a cutting line or separated individually through an etching process, and a plurality of light emitting devices LD are formed by a laser lift-off process. It can be made to be separable from the growth substrate 101 .

In FIG. 7 , "P" means a pitch interval between the light emitting devices LD, "S" means a separation distance between the light emitting devices LD, and "W" means a width of the light emitting devices LD. have. 7 illustrates that the cross-sectional shape of the light emitting device LD is a rectangular shape, but is not limited thereto, and may have a cross-sectional shape other than a square cross-section according to a method of manufacturing the growth substrate 101 such as a circular cross-section. can

In the following embodiments, each light emitting device LD selectively includes a third semiconductor layer 15 , and the third semiconductor layer 15 is electrically connected to a second electrode CE to be described with reference to FIG. 8 . It will be described as an example that the impurity connected to the doped semiconductor layer.

8 and 9 schematically illustrate a pixel PXL according to an embodiment of the present invention, wherein the transistor T (eg, the first transistor T1 ) and the light emitting device LD shown in FIG. 6 . ) are schematic cross-sectional views for explaining the connection structure, and FIGS. 10A to 10C are enlarged views of the EA region of FIG. 8 .

In the exemplary embodiment of the present invention, the thickness direction of the substrate SUB on the cross-section is indicated as the third direction DR3 for convenience of description.

In addition, the term “connection” between the two components may mean that both an electrical connection and a physical connection are used inclusively, but is not limited thereto.

In describing embodiments of the present invention, "formed and/or provided on the same layer" means formed in the same process, and "formed and/or provided on a different layer" means formed in different processes. can, but is not limited thereto.

Although one pixel PXL is illustrated in a simplified manner in FIGS. 8 to 10C , the present invention is not limited thereto.

1 to 10C , the pixel PXL according to an exemplary embodiment may be provided and/or located in the pixel area PXA provided on the substrate SUB. The pixel area PXA is an area of the display area DA, and may include an emission area EMA and a non-emission area NEMA.

The aforementioned pixel PXL may include a substrate SUB, a pixel circuit layer PCL, and a display element layer DPL.

At least one insulating layer and at least one conductive layer may be disposed on the substrate SUB. The insulating layer may include, for example, a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, a passivation layer PSV, and a bank BNK sequentially provided on the substrate SUB. can The conductive layer may include conductive layers positioned between the insulating layers.

Since the substrate SUB has the same configuration as the substrate SUB described with reference to FIG. 3 , a detailed description thereof will be omitted.

The pixel circuit layer PCL may include a buffer layer BFL, a pixel circuit PXC including a transistor T provided on the buffer layer BFL, and a passivation layer PSV.

The buffer layer BFL may be provided and/or formed on one surface of the substrate SUB. The buffer layer BFL may prevent impurities from diffusing into the transistor T included in the pixel circuit PXC. The buffer layer BFL may include an inorganic insulating layer including an inorganic material. The buffer layer BFL may include at least one of a metal oxide such as silicon nitride (SiN _x ), silicon oxide (SiO _x ), silicon oxynitride (SiO _x N _y ), and aluminum oxide (AlO _x ). The buffer layer BFL may be provided as a single layer, but may also be provided as a multilayer of at least double layers. When the buffer layer BFL is provided in multiple layers, each layer may be formed of the same material or different materials. The buffer layer BFL may be omitted depending on the material and process conditions of the substrate SUB.

The transistor T may include a driving transistor for controlling a driving current of the light emitting device LD and a switching transistor electrically connected to the driving transistor. Here, the driving transistor may be the first transistor T1 described with reference to FIG. 6 , and the switching transistor may be the second transistor T2 described with reference to FIG. 6 . For convenience, only the driving transistor T corresponding to the first transistor T1 is illustrated in FIGS. 8 and 9 .

The driving transistor T may include a semiconductor pattern SCL, a gate electrode GE, a first terminal ET1 , and a second terminal ET2 . The first terminal ET1 may be one of the source electrode and the drain electrode, and the second terminal ET2 may be the other electrode of the source electrode and the drain electrode. For example, the first terminal ET1 may be a source electrode, and the second terminal ET2 may be a drain electrode.

The semiconductor pattern SCL may be provided and/or formed on the buffer layer BFL. The semiconductor pattern SCL may include a first contact area contacting the first terminal ET1 and a second contact area contacting the second terminal ET2 . A region between the first contact region and the second contact region may be a channel region. This channel region may overlap the gate electrode GE of the driving transistor T. The semiconductor pattern SCL may be a semiconductor pattern made of polysilicon, amorphous silicon, an oxide semiconductor, or the like. The channel region is, for example, a semiconductor pattern that is not doped with impurities, and may be an intrinsic semiconductor. The first contact region and the second contact region may be semiconductor patterns doped with impurities. As the impurity, for example, a p-type impurity may be used, but the present invention is not limited thereto.

A gate insulating layer GI may be provided and/or formed on the semiconductor pattern SCL.

The gate insulating layer GI may be entirely provided on the semiconductor pattern SCL and the buffer layer BFL to cover the semiconductor pattern SCL and the buffer layer BFL. The gate insulating layer GI may be an inorganic insulating layer including an inorganic material. For example, the gate insulating layer GI may include at least one of a metal oxide such as silicon nitride (SiN _x ), silicon oxide (SiO _x ), silicon oxynitride (SiO _x N _y ), and aluminum oxide (AlO _x ). can However, the material of the gate insulating layer GI is not limited to the above-described embodiments. In some embodiments, the gate insulating layer GI may be formed of an organic insulating layer including an organic material. The gate insulating layer GI may be provided as a single layer, but may also be provided as a multilayer of at least double layers.

The gate electrode GE may be provided and/or formed on the gate insulating layer GI to correspond to the channel region of the semiconductor pattern SCL. The gate electrode GE may be disposed on the gate insulating layer GI to overlap the channel region of the semiconductor pattern SCL. In an embodiment, the gate electrode GE includes copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and their Molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al) or silver (Ag), which are low-resistance materials to form a single layer or reduce wiring resistance by using a single layer selected from the group consisting of alloys or a mixture thereof It can be formed in a double-layer or multi-layer structure of

An interlayer insulating layer ILD may be provided and/or formed on the gate electrode GE.

The interlayer insulating layer ILD may include the same material as the gate insulating layer GI or may include one or more materials suitable (or selected) from the materials exemplified as the constituent materials of the gate insulating layer GI.

Each of the first terminal ET1 and the second terminal ET2 is provided and/or formed on the interlayer insulating layer ILD, and a contact hole sequentially passes through the gate insulating layer GI and the interlayer insulating layer ILD. may contact the first contact region and the second contact region of the semiconductor pattern SCL. For example, the first terminal ET1 may contact the first contact area of the semiconductor pattern SCL, and the second terminal ET2 may contact the second contact area of the semiconductor pattern SCL. Each of the first and second terminals ET1 and ET2 may include the same material as the gate electrode GE, or may include one or more materials selected from the exemplified materials of the gate electrode GE.

In the above-described embodiment, the semiconductor pattern ( Although it has been described as a separate electrode electrically connected to the semiconductor pattern SCL in contact with the SCL, the present invention is not limited thereto. In some embodiments, the first terminal ET1 of the driving transistor T may be a first contact region adjacent to one side of the channel region of the semiconductor pattern SCL, and the second terminal ET2 of the driving transistor T ) may be a second contact area adjacent to the other side of the channel area. In this case, the first terminal ET1 of the driving transistor T may be electrically connected to the light emitting device LD through a separate connection means such as a bridge electrode.

In one embodiment, the driving transistor T may be formed of a low-temperature polysilicon thin film transistor, but is not limited thereto. In some embodiments, the driving transistor T may be formed of an oxide semiconductor thin film transistor. In addition, although the case in which the driving transistor T is a thin film transistor having a top gate structure has been described as an example in the above-described embodiment, the present invention is not limited thereto, and the structure of the driving transistor T may be variously changed. have.

Although not directly illustrated in FIGS. 8 and 9 , the pixel circuit layer PCL includes signal lines (eg, including scan lines and data lines) electrically connected to the driving transistor T and power lines (one). For example, it may further include first and second power lines). As an example, the power lines may be the first and second power lines PL1 and PL2 described with reference to FIG. 6 . Each of the first and second power lines PL1 and PL2 may include a conductive material (or material). For example, each of the first and second power lines PL1 and PL2 may include copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver. Molybdenum (Mo), titanium (Ti), copper (Cu), which are low-resistance materials, to form a single layer (or a single film) or reduce wiring resistance by using (Ag) or a mixture thereof alone or a mixture thereof selected from the group consisting of (Ag) and alloys thereof. ), aluminum (Al) or silver (Ag) may be formed in a double-layer (or double-layer) or multi-layer (or multi-layer) structure. For example, each of the first power line PL1 and the second power line PL2 may be formed of a double layer (or double layer) stacked in this order of titanium (Ti)/copper (Cu).

A passivation layer PSV may be provided and/or formed on the driving transistor T.

The passivation layer PSV (also referred to as a “protective layer” or “via layer”) may be an inorganic insulating film including an inorganic material or an organic insulating film including an organic material. The inorganic insulating layer may include, for example, at least one of a metal oxide such as silicon oxide (SiO _x ), silicon nitride (SiN _x ), silicon oxynitride (SiO _x N _y ), and aluminum oxide (AlO _x ). . The organic insulating film is, for example, acrylic resin (polyacrylates resin), epoxy resin (epoxy resin), phenolic resin (phenolic resin), polyamides resin (polyamides resin), polyimide resin (polyimides rein), unsaturated poly At least one of unsaturated polyesters resin, poly-phenylen ethers resin, poly-phenylene sulfides resin, and benzocyclobutene resin may include

In some embodiments, the passivation layer PSV may include the same material as the interlayer insulating layer ILD, but is not limited thereto. The passivation layer PSV may be provided as a single layer, but may also be provided as a multilayer of at least double layers.

The passivation layer PSV may be partially opened to expose the first terminal ET1 of the driving transistor T to the outside.

A display device layer DPL may be provided and/or formed on the passivation layer PSV.

The display element layer DPL may include a first electrode AE, a light emitting element LD, and a second electrode CE.

The first electrode AE may be provided and/or formed on the pixel circuit layer PCL. The first electrode AE may be positioned under the light emitting device LD and may be electrically connected to the first end EP1 of the light emitting device LD. The second electrode CE is positioned on the light emitting device LD and may be electrically connected to the second end EP2 of the light emitting device LD. When viewed in cross section, the first electrode AE and the second electrode CE may face each other in the third direction DR3 with the light emitting device LD interposed therebetween.

The first electrode AE may be electrically connected to the first terminal ET1 of the driving transistor T through a contact hole passing through the passivation layer PSV. In an embodiment, the first electrode AE may be an anode.

The first electrode AE is formed of a conductive material having a reflectance (eg, a predetermined reflectance) in order to allow light emitted from the light emitting device LD to travel in the image display direction (or front direction) of the display device DD. or materials). The conductive material may include an opaque metal advantageous for reflecting light emitted from the light emitting elements LD in an image display direction (or a desired direction) of the display device DD. As the opaque metal, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium ( Ir), chromium (Cr), titanium (Ti), and a metal such as alloys thereof may be included. In some embodiments, the first electrode AE may include a transparent conductive material (or material). Examples of the transparent conductive material (or material) include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide, IGZO), a conductive oxide such as indium tin zinc oxide (ITZO), and a conductive polymer such as poly(3,4-ethylenedioxythiophene) (PEDOT) may be included. When the first electrode AE includes a transparent conductive material (or material), a separate layer made of an opaque metal for reflecting the light emitted from each of the light emitting elements LD in the image display direction of the display device DD A conductive layer may be added. However, the material of the first electrode AE is not limited to the above-described materials.

The first electrode AE may be provided and/or formed as a single layer, but is not limited thereto. According to an embodiment, the first electrode AE may be provided and/or formed as a multilayer in which at least two or more of metals, alloys, conductive oxides, and conductive polymers are stacked. The first electrode AE may be formed of at least two or more multi-layers in order to minimize distortion due to signal delay when transmitting a signal (or voltage) to the first end EP1 of the light emitting device LD.

A bank BNK may be provided and/or formed on the first electrode AE.

The bank BNK may be positioned in the non-emission area NEMA to form a pixel defining layer that partitions the light emission area EMA of the pixel PXL. The bank BNK may include an opening OP exposing a portion of the first electrode AE. That is, the bank BNK may be partially opened to expose a portion of the first electrode AE. In an embodiment, the emission area EMA of the pixel PXL and the opening OP of the bank BNK may correspond to each other.

The bank BNK may include at least one light blocking material and/or a reflective material (or a scattering material) to prevent light leakage between adjacent pixels PXL. In some embodiments, the bank BNK may be an organic insulating layer including an organic material. For example, the bank (BNK) is made of an organic insulating film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc. can Also, according to an embodiment, the bank BNK may include a transparent material. The transparent material may include, for example, polyamides resin, polyimides resin, and the like, but the present invention is not limited thereto. According to another embodiment, a reflective material layer may be separately provided and/or formed on the bank BNK to further improve the efficiency of light emitted from the pixel PXL.

A conductive pattern BDE2 (or a second bonding electrode) may be provided and/or formed in the opening OP of the bank BNK.

The conductive pattern BDE2 may be provided and/or formed on the side surface of the bank BNK and the first electrode AE in the opening OP to surround the opening OP. The conductive pattern BDE2 may be a medium for electrically connecting the driving transistor T and the light emitting device LD by bonding to the bonding electrode BDE1 of the light emitting device LD. In an embodiment, the conductive pattern BDE2 may be used as a reflective member RMTL for guiding the light emitted from the light emitting device LD in the image display direction of the display device DD. To this end, the conductive pattern BDE2 may be formed of an opaque conductive material having a predetermined reflectivity. For example, the conductive pattern BDE2 may include the same material as that of the first electrode AE or may include one or more materials suitable (or selected) from materials exemplified as constituent materials of the first electrode AE.

The conductive pattern BDE2 may include a first portion A1 and a second portion A2 . For example, the conductive pattern BDE2 may include a first portion A1 positioned on a side surface of the bank BNK and a second portion A2 positioned on the first electrode AE. The second part A2 may be positioned on the upper surface of the first electrode AE to have a flat profile, and the first part A1 may be positioned on the side surface of the bank BNK and correspond to the shape of the side surface of the bank BNK. You can have a profile that says For example, the first portion A1 may have a predetermined inclination. In particular, as shown in FIGS. 10A and 10C , when the side surface of the bank BNK has a predetermined inclination angle θ (or inclination), the first portion A1 of the conductive pattern BDE2 is also BNK) may have a predetermined slope corresponding to the side inclination angle θ. In this case, the side inclination angle θ of the bank BNK may be close to 90 degrees, but is not limited thereto.

The side surface of the bank BNK may be designed so that the conductive pattern BDE2 has a relatively steep inclination angle θ to guide the light emitted from the light emitting device LD in the image display direction.

As described above, when the first portion A1 of the conductive pattern BDE2 has a predetermined slope, the light emitted from the active layer 12 of the light emitting element LD is transmitted by the conductive pattern BDE2 to the display device ( DD) in the image display direction. That is, the first portion A1 of the conductive pattern BDE2 induces the light emitted radially (or radially) from the light emitting device LD to the image display area (or the target area), so that the light output efficiency of the pixel PXL. can improve

When the side surface of the bank BNK has an inclination angle θ (or inclination), the width of the opening OP may be different along the third direction DR3 . Here, the width of the opening OP may mean a distance between two sides of the bank BNK facing each other with the opening OP interposed therebetween. In an embodiment, the first width W1 and the second width W2 of the opening OP may be different from each other. The first width W1 may be greater than the second width W2 . The second width W2 means a distance between two side surfaces of the bank BNK contacting the first electrode AE with the opening OP interposed therebetween, and the first width W1 is the opening OP. It may mean a distance between two side surfaces of the bank BNK in contact with the intermediate layer CTL between them. The first and second widths W1 and W2 may be greater than the width W of the light emitting device LD. For example, the first and second widths W1 and W2 may be 5 μm or more, the first width W1 may be 6 μm, and the second width W2 may be 5 μm, but is limited thereto. it is not The opening OP may be designed to have a width (or size) sufficient to allow the light emitting device LD to be sufficiently inserted.

In the above-described embodiment, it has been described that the side surface of the bank BNK has an inclination angle θ (or inclination) in an oblique direction inclined to the third direction DR3, but the present invention is not limited thereto. In some embodiments, the side surface of the bank BNK may have a side parallel to the third direction DR3 and perpendicular to the top surface of the first electrode AE, as shown in FIG. 10B . In this case, the first portion A1 of the conductive pattern BDE2 may also have a side that is perpendicular to the first electrode AE.

In an embodiment, the second portion A2 of the conductive pattern BDE2 is positioned on the first electrode AE and is together with the first electrode AE in the active layer 12 of the light emitting device LD. Light traveling in the circuit layer PCL direction may be reflected in the image display direction.

The above-described conductive pattern BDE2 is bonded to the bonding electrode BDE1 of the light emitting device LD to electrically connect the light emitting device LD and the first electrode AE, and is emitted from the light emitting device LD. It can be utilized as a reflective member (BRML) that guides and collimates the collected light in the image display direction.

According to an embodiment, the conductive pattern BDE2 may be provided to include the protrusion PRT protruding from one region of the intermediate layer CTL along the side surface of the bank BNK. The protrusion PRT may be formed in a manufacturing process of forming the conductive pattern BDE2 . When the conductive pattern BDE2 is provided to include the protrusion PRT, the first portion A1 located on the side of the bank BNK extends to one region of the intermediate layer CTL and is emitted from the light emitting device LD. The light output efficiency of the pixel PXL may be further improved by guiding (or reflecting) the light in the image display direction. When the conductive pattern BDE2 includes the protrusion PRT, the length L1 of the first portion A1 of the conductive pattern BDE2 is the distance L1 between the top surface of the bank BNK and the first electrode AE1. d) may be greater. For example, when the distance d between the top surface of the bank BNK and the first electrode AE1 is 2 μm, the length L1 of the first portion A1 of the conductive pattern BDE2 is greater than 2 μm. can

According to an embodiment, the conductive pattern BDE2 may not include the protrusion PRT as illustrated in FIG. 10C . In this case, the end of the first part A1 of the conductive pattern BDE2 may be positioned on the same line (or on the same plane) as the top surface of the bank BNK.

In an embodiment, the conductive pattern BDE2 is a double layer including a first layer FL and a second layer SL positioned on the first layer FL, as shown in FIGS. 10A to 10C . can be configured.

The first layer FL may be positioned on the side surfaces of the first electrode AE and the bank BNK to directly contact the side surfaces of the first electrode AE and the bank BNK. The first layer FL is a metal layer that is in direct contact with the first electrode AE and is electrically connected to the first electrode AE, and may be selected from titanium (Ti), copper (Cu), nickel (Ni), or the like. . The first layer FL may have a thickness greater than or equal to a certain level in order to reduce a step difference between the first electrode AE and the light emitting device LD, but is not limited thereto.

The second layer SL may be a metal layer that is in direct contact with the bonding electrode BDE1 of the light emitting device LD and is electrically connected to the light emitting device LD. The second layer SL includes an intermetallic compound between the second layer SL and the bonding electrode BDE1 of the light emitting device LD when bonding to the bonding electrode BDE1 of the light emitting device LD. It may be selected from gold (Au), tin (Sn), etc. having excellent bonding strength (or adhesive strength) to facilitate the formation and growth of . According to an embodiment, the conductive pattern BDE2 may be configured as a single layer including only the second layer SL.

The conductive pattern BDE2 including the above-described first layer FL and second layer SL may have a thickness of about 1 μm to 1.5 μm in the third direction DR3, but is not limited thereto.

An intermediate layer CTL may be provided and/or formed on the bank BNK and the conductive pattern BDE2 .

The intermediate layer CTL may be entirely coated on the bank BNK and the conductive pattern BDE2 through spin coating. In an embodiment, the intermediate layer CTL may be provided on the bank BNK and the conductive pattern BDE2 to fill the opening OP.

The intermediate layer CTL may include an organic material that enhances adhesion between the light emitting device LD and the conductive pattern BDE2 while stably fixing the light emitting device LD. For example, the intermediate layer CTL may be a transparent adhesive layer (or an adhesive layer), but is not limited thereto. According to an exemplary embodiment, the intermediate layer CTL may be a refractive index converting layer for improving the luminance of light emitted from the pixel PXL by converting the refractive index of light emitted from the light emitting device LD and traveling in the image display direction.

In an embodiment, the intermediate layer CTL may be formed of an organic material. The organic material may include, for example, at least one of a photocurable resin including a photopolymerization initiator that is crosslinked and cured by light such as UV, or a thermosetting polymer resin including a thermal polymerization initiator that initiates a curing reaction by heat. For example, the thermosetting resin may include an epoxy resin composed of an organic material, an amino resin, a phenol resin, a polyester resin, and the like. The intermediate layer CTL may be cured by light or heat while the light emitting device LD and the conductive pattern BDE2 are bonded to each other. Accordingly, the intermediate layer CTL may prevent the light emitting device LD from being separated while stably fixing the light emitting device LD.

The light emitting device LD may be provided and/or positioned on the intermediate layer CTL. In an embodiment, each pixel PXL may include one light emitting device LD. That is, one light emitting device LD may be provided as a light source of each pixel PXL. However, the present invention is not limited thereto.

The light emitting device LD includes a light emitting laminate in which a bonding electrode BDE1, a second semiconductor layer 13, an active layer 12, a first semiconductor layer 11, and a third semiconductor layer 15 are sequentially stacked. can be implemented In this case, the bonding electrode BDE1 may be positioned at the first end EP1 of the light emitting device LD, and the third semiconductor layer 15 may be positioned at the second end EP2 of the light emitting device LD. can In this case, the bonding electrode BDE1 may directly contact the second layer SL of the conductive pattern BDE2 to be bonded to the conductive pattern BDE2 . The third semiconductor layer 15 may directly contact the second electrode CE to be electrically connected to the second electrode CE.

According to an embodiment, as shown in FIG. 9 , the light emitting device LD includes the bonding electrode BDE1 , the second semiconductor layer 13 , and the active layer along the third direction DR3 from the conductive pattern BDE2 . 12), and the first semiconductor layer 11 may be implemented as a light emitting laminate sequentially stacked in this order. In this case, the bonding electrode BDE1 may be positioned at the first end EP1 of the light emitting device LD, and the first semiconductor layer 11 may be positioned at the second end EP2 of the light emitting device LD. can In this case, the bonding electrode BDE1 may be in direct contact with the second layer SL of the conductive pattern BDE2 to be bonded to the conductive pattern BDE2 , and the first semiconductor layer 11 may be the second electrode CE. may be in direct contact with the second electrode CE and may be electrically connected to the second electrode CE.

According to an exemplary embodiment, as shown in FIG. 9 , the first semiconductor layer 11 of the light emitting device LD is entirely disposed on the intermediate layer CTL and a common electrode (not shown) disposed in the non-display area NDA. city) can be electrically connected to. In this case, the first semiconductor layer 11 of the light emitting devices LD disposed in the pixels PXL may be connected to the common electrode. For example, when three pixels PXL are disposed in the display area DA, the first semiconductor layer ( 11), the first semiconductor layer 11 of the light emitting device LD disposed in the other one of the three pixels PXL, and the other one of the three pixels PXL. The first semiconductor layer 11 of the light emitting device LD disposed on the PXL may be connected to the common electrode. A more detailed description related thereto will be described later with reference to FIG. 14B .

After the light emitting device LD transferred to the transfer substrate by the transfer mechanism is moved to the upper portion of the intermediate layer CTL to correspond to the opening OP of the bank BNK, it can be re-transferred into the opening OP. have. During this process, the bonding electrode BDE1 of the light emitting device LD may directly contact the conductive pattern BDE2 as the intermediate layer CTL composed of a fluid organic material filling the inside of the opening OP moves.

A bonding method may be used to electrically connect the light emitting device LD and the first electrode AE. As bonding methods, AFC (anisotropic conductive film) bonding method, LAB (Laser assist bonding) method using laser, ultrasonic bonding method, bump-ball surface mounting method (Ball Grid Array, BGA), pressure and heat bonding method (TC) , Thermo compression bonding) and the like may be used. In the pressurized and heat bonding method, the bonding electrode BDE1 and the conductive pattern BDE2 are brought into contact, then heated to a temperature higher than the melting point of the bonding electrode BDE1 and the conductive pattern BDE2, and then bonded by applying pressure. It may refer to a method of electrically and physically connecting the electrode BDE1 and the conductive pattern BDE2 .

As described above, after the light emitting element LD is positioned in the opening OP to contact the bonding electrode BDE1 and the conductive pattern BDE2, a bonding process using a pressurization and heat bonding method is performed to proceed with the bonding electrode BDE1. ) and the conductive pattern BDE2 may be electrically connected. When heat and pressure are applied to bond the bonding electrode BDE1 and the conductive pattern BDE2 to each other, an intermetallic compound may be generated and grown between the bonding electrode BDE1 and the conductive pattern BDE2 . The light emitting device LD and the first electrode AE may be electrically and physically connected to each other with such an intermetallic compound.

The second electrode CE may be provided and/or formed on the light emitting device LD bonded to the first electrode AE.

The second electrode CE may be entirely formed on the second end EP2 and the intermediate layer CTL of the light emitting device LD. The second electrode CE may contact the second end EP2 of the light emitting device LD and may be electrically connected to the second end EP2 of the light emitting device LD. For example, the second electrode CE may be electrically connected to the third semiconductor layer 15 (or the first semiconductor layer) positioned at the second end EP2 of the light emitting device LD.

The second electrode CE may be formed of various transparent conductive materials to allow light emitted from the light emitting device LD to travel in an image display direction without loss. For example, the second electrode CE may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium gallium zinc oxide (indium gallium zinc oxide). , IGZO), indium tin zinc oxide (ITZO), and the like, including at least one of various transparent conductive materials (or materials), and is substantially transparent or translucent to satisfy a predetermined light transmittance (or transmittance). can be configured. However, the material of the second electrode CE is not limited to the above-described embodiment.

The above-described second electrode CE may be electrically connected to the second power line PL2 . Accordingly, the voltage of the second driving power VSS applied to the second power line PL2 may be transferred to the second electrode CE. In an embodiment, the second electrode CE may be a cathode.

In the above-described embodiment, the second electrode CE is made of a separate conductive material and the third semiconductor layer 15 (or the first semiconductor layer 11 ) is positioned at the second end EP2 of the light emitting device LD. )) and was described as being electrically connected, but is not limited thereto. That is, the contact structure between the second electrode CE and the first semiconductor layer 11 of the light emitting device LD is not limited to the above-described embodiment. In some embodiments, the second electrode CE may be formed in the same process as the first semiconductor layer 11 of the light emitting device LD and may be electrically connected to a common electrode (not shown) located in the non-display area NDA. have.

In some embodiments, a cover layer CVL may be provided and/or formed on the second electrode CE as shown in FIG. 9 .

The cover layer CVL may be an encapsulation substrate or an encapsulation film formed of multiple layers. In this case, the cover layer CVL may prevent external oxygen and moisture from flowing into the display element layer DPL and the pixel circuit layer PCL. According to an embodiment, the cover layer CVL may be a planarization layer that relieves a step difference generated by the components disposed thereunder.

In one embodiment of the present invention, when the conductive pattern BDE2 is disposed to surround the opening OP so as to be respectively positioned on the side surface of the bank BNK and the first electrode AE, the active layer ( 12 ) may face the first portion A1 of the conductive pattern BDE2 . In this case, the light emitted from the active layer 12 of the light emitting device LD may be guided in the image display direction by the conductive pattern BDE2 . In this case, light traveling in the pixel circuit layer PCL direction from the active layer 12 of the light emitting device LD may also be reflected in the image display direction by the second portion A2 of the conductive pattern BDE2 . As a result, light emitted from the light emitting device LD and guided (or propagated) in the image display direction by the conductive pattern BDE2 increases, so that the light output efficiency of the pixel PXL may be improved.

In addition, in the above-described embodiment, the conductive pattern BDE2 is bonded to the bonding electrode BDE1 to electrically connect the light emitting device LD and the first electrode AE, and light emitted from the light emitting device LD is emitted. As it is used as the reflective member BMTL that guides in the image display direction, the manufacturing process for forming the existing reflective member is omitted, so that the display device DD may be implemented with a simplified manufacturing process.

11 and 12 are cross-sectional views schematically illustrating a pixel PXL according to another exemplary embodiment.

The pixel PXL illustrated in FIGS. 11 and 12 has a configuration substantially the same as or similar to that of the pixel PXL of FIG. 9 , except that the upper substrate U_SUB is disposed on the display element layer DPL. can have

11 and 12 illustrate different embodiments with respect to whether the capping layer CPL is provided or not. For example, in FIG. 11 , the upper substrate U_SUB does not include the capping layer CPL, and in FIG. 12 , the upper substrate U_SUB includes the capping layer CPL.

Accordingly, in FIGS. 11 and 12 , different points from the above-described exemplary embodiment will be mainly described in order to avoid overlapping descriptions.

8 to 12 , an upper substrate U_SUB may be provided on the display element layer DPL of the pixel PXL.

The upper substrate U_SUB may be provided on the display device layer DPL to cover the pixel area PXA.

The upper substrate U_SUB may include a base layer BSL, a light conversion pattern LCP, and a light blocking pattern LBP.

The base layer BSL may be a rigid substrate or a flexible substrate, and the material or properties thereof are not particularly limited. The base layer BSL may be formed of the same material as the substrate SUB or may be formed of a material different from that of the substrate SUB.

The light conversion pattern LCP may be disposed on one surface of the base layer BSL to correspond to the emission area EMA of the pixel PXL. The light conversion pattern LCP may include a color conversion layer CCL and a color filter CF corresponding to a predetermined color.

The color conversion layer CCL may include color conversion particles QD corresponding to a predetermined color. The color filter CF may selectively transmit light of a predetermined color.

The color conversion layer CCL is disposed on one surface of the insulating layer INS to face the light emitting device LD, and transmits light emitted from the light emitting device LD and reflected by the conductive pattern BDE2 to light of a specific color. It may include color conversion particles (QDs) that convert to . For example, when the light emitting device LD emits blue light (hereinafter, referred to as “blue light”), the color conversion layer CCL is a white quantum dot color conversion particle that converts blue light into white light. may include QDs. Here, the color conversion particles QD of the white quantum dot may include the red quantum dot and the green quantum dot to convert the blue light of the light emitting device LD into white light. However, the configuration of the color conversion layer CCL is not limited to the above-described embodiment.

The color filter CF is disposed on one surface of the base layer BSL to face the color conversion layer CCL, and selects the white light converted by the color conversion layer CCL into red light, green light, or blue light. can be transmitted through When the pixel PXL is a red pixel, the color filter CF may include a red color filter. When the pixel PXL is a green pixel, the color filter CF may include a green color filter. Also, when the pixel PXL is a blue pixel, the color filter CF may include a blue color filter.

The light conversion pattern LCP including the color conversion layer CCL and the color filter CF may be positioned in the emission area EMA of the pixel PXL. In addition, the color conversion layer CCL and the color filter CF may correspond to the conductive pattern BDE2 surrounding the opening OP of the bank BNK.

An insulating layer INS may be provided and/or formed between the color filter CF and the color conversion layer CCL.

The insulating layer INS may be disposed on the color filter CF to protect the color filter CF. The insulating layer INS may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material.

The light blocking pattern LBP may be positioned adjacent to the light conversion pattern LCP. In an embodiment, the light blocking pattern LBP may be disposed on one surface of the base layer BSL to correspond to the non-emission area NEMA of the pixel PXL. The light blocking pattern LBP may correspond to the bank BNK of the display element layer DPL.

The light blocking pattern LBP may include a first light blocking pattern LBP1 and a second light blocking pattern LBP2 .

The first light blocking pattern LBP1 may be disposed on one surface of the base layer BSL and may be disposed adjacent to the color filter CF. The first light blocking pattern LBP1 may include at least one black matrix material (eg, at least one currently known light blocking material) among various types of black matrix materials, and/or a color filter material of a specific color. have.

According to an exemplary embodiment, the first light blocking pattern LBP1 is provided in the form of a multi-layer in which at least two or more color filters that selectively transmit different colors of light among a red color filter, a green color filter, and a blue color filter are overlapped. it might be For example, the first light blocking pattern LBP1 includes a red color filter, a green color filter positioned on the red color filter to overlap the red color filter, and a green color filter positioned on the green color filter to overlap the green color filter. It may be provided in a form including a blue color filter. That is, the first light blocking pattern LBP1 may be provided in the form of a structure in which a red color filter, a green color filter, and a blue color filter are sequentially stacked. In this case, in the non-emission area NEMA of the pixel area PXA, the red color filter, the green color filter, and the blue color filter may be used as the first light blocking pattern LBP1 blocking light transmission.

The insulating layer INS may be provided and/or formed on the first light blocking pattern LBP1. The insulating layer INS may be entirely disposed on the first light blocking pattern LBP1 and the color filter CF.

The second light blocking pattern LBP2 may be provided and/or formed on one surface of the insulating layer INS to correspond to the first light blocking pattern LBP1 . The second light blocking pattern LBP2 may be a black matrix. The first blocking pattern LBP1 and the second blocking pattern LBP2 may include the same material. In an embodiment, the second light blocking pattern LBP2 may be a structure that finally defines the emission area EMA of the pixel PXL. For example, in the step of supplying the color conversion layer CCL including the color conversion particles QD, the second light blocking pattern LBP2 may finally define the emission area EMA to which the color conversion layer CCL is to be supplied. It may be a defining dam structure.

The above-described upper substrate U_SUB may be disposed on the cover layer CVL to be coupled to the display device layer DPL. To this end, the cover layer CVL may include a transparent adhesive layer (or an adhesive layer) for strengthening the adhesive force between the display element layer DPL and the upper substrate U_SUB.

In some embodiments, the upper substrate U_SUB may further include a capping layer CPL formed entirely on the color conversion layer CCL and the second light blocking pattern LBP2 as shown in FIG. 12 . .

The capping layer CPL may include at least one of a metal oxide such as silicon nitride (SiN _x ), silicon oxide (SiO _x ), silicon oxynitride (SiO _x N _y ), and aluminum oxide (AlO _x ). The capping layer CPL is positioned on the color conversion layer CCL to protect the color conversion layer CCL from external moisture and moisture, thereby further improving the reliability of the color conversion layer CCL.

As described above, in the display device (refer to “DD” in FIG. 1 ) according to an exemplary embodiment of the present invention, the light conversion pattern LCP is disposed on the light emitting element LD, and the light conversion pattern LCP passes through the light conversion pattern LCP. Light output efficiency may be improved by emitting light having excellent color reproducibility.

13A to 13H are schematic cross-sectional views sequentially illustrating a method of manufacturing the pixel PXL of FIG. 8 .

In the present specification, some manufacturing steps of the display device are described as being sequentially performed according to a cross-sectional view, but unless the spirit of the invention is changed, some steps shown to be performed consecutively are performed simultaneously or the order of each step is changed It is obvious that, some steps may be omitted, or other steps may be further included between each step.

13A to 13H, different points from the above-described exemplary embodiment will be mainly described in order to avoid overlapping descriptions.

Referring to FIGS. 8 and 13A , an insulating material layer PDL′ corresponding to a base material of the bank BNK is formed on the first electrode AE. A photosensitive material layer PR is formed on the insulating material layer PDL'. Here, the photosensitive material layer PR may include a negative photosensitive material.

8, 13A, and 13B, after a mask (not shown) is disposed on the photosensitive material layer PR, a series of processes such as exposure and development are performed to prevent light from being transmitted by the mask A photosensitive pattern PRP exposing a portion of the insulating material layer PDL' is formed.

A portion of the exposed insulating material layer PDL' may correspond to one region of the first electrode AE.

8 and 13A to 13C , an etching process using the photosensitive pattern PRP as an etching mask is performed to remove a portion of the insulating material layer PDL′, and the bank BNK including the opening OP is performed. ) to form The etching process may be performed using dry etching.

Due to the above-described process, a portion of the first electrode AE corresponding to the opening OP of the bank BNK may be exposed. Also, due to the above-described process, the photosensitive pattern PRP may be partially etched in the third direction DR3 .

8 and 13A to 13D , the conductive layer CL was deposited on the photosensitive pattern PRP, the exposed first electrode AE, and the bank BNK by E-beam evaporation. form entirely.

8 and 13A to 13E, a lift-off process is performed so that only the conductive layer CL located in the opening OP remains, and the photosensitive pattern PRP and the conductive layer located thereon ( CL) is removed. The conductive layer CL located in the opening OP is positioned on the side of the bank BNK to surround the opening OP and the conductive pattern BDE2 is positioned on the exposed first electrode AE ( or a second bonding electrode).

Both ends of the conductive pattern BDE2 may extend to the upper surface of the bank BNK along the side surface of the bank BNK by the above-described lift-off process. That is, the conductive pattern BDE2 may include the protrusion PRT protruding upward from the top surface of the bank BNK.

Referring to FIGS. 8 and 13A to 13F , an intermediate layer CTL is formed entirely on the conductive pattern BDE2 and the bank BNK by using a spin coating method.

The intermediate layer CTL may be entirely coated on the conductive pattern BDE2 and the bank BNK in a liquid form having viscosity. The intermediate layer (CTL) is made of an organic material that is transparent and has adhesive (or adhesiveness), and is cured by heat and/or light in the bonding process between the conductive pattern (BDE2) and the light emitting device (LD) to form the light emitting device (LD). It is stably fixed and the step difference due to the components positioned below the second electrode CE to be formed thereon has a flat surface may be alleviated.

When the above-described intermediate layer CTL is provided in a liquid form, the intermediate layer CTL is transferred to the opening OP of the bank BNK during a subsequent process (a light emitting device LD transfer process) by the light emitting device LD to be transferred into the opening OP. While moving (or being pushed) naturally, the conductive pattern BDE2 positioned thereunder may be exposed to the outside, and the light emitting device LD may contact the exposed conductive pattern BDE2 . In this case, the position of the light emitting device LD may be temporarily fixed on the conductive pattern BDE2 . The intermediate layer CTL may be cured by heat or pressure applied in a bonding process performed after the transfer process of the light emitting device LD to stably fix the light emitting device LD. A detailed description thereof will be described later with reference to FIG. 13G .

Referring to FIGS. 8 and 13A to 13G , the transfer substrate 1 to which the light emitting device LD is transferred is disposed at a preset position in the pixel PXL. For example, the transfer substrate 1 to which the light emitting device LD is transferred is disposed in the pixel PXL so that the bonding electrode BDE1 of the light emitting device LD contacts the conductive pattern BDE2 . For example, the light emitting device LD transferred to the transfer substrate 1 may be located in the opening OP. In this case, the third semiconductor layer 15 of the light emitting device LD may be attached to contact the transfer substrate 1 , and the bonding electrode BDE1 of the light emitting device LD may contact the conductive pattern BDE2 . have.

The transfer substrate 1 may be a translucent substrate including sapphire (Al ₂ O ₃ ), glass, polyimide, or the like. Accordingly, the transfer substrate 1 may transmit laser light irradiated from the upper and/or lower portions. A sacrificial layer (not shown) may be provided on the transfer substrate 1 . The light emitting device LD may be formed on the sacrificial layer on the transfer substrate 1 . As the sacrificial layer, materials that are easily peeled off by an irradiated laser from among materials having adhesiveness (or adhesiveness) may be selected. When the laser is irradiated onto the transfer substrate 1 , the sacrificial layer and the light emitting device LD may be physically separated. Illustratively, the sacrificial layer may lose its adhesion function when laser is irradiated.

The first electrode AE and the light emitting device LD are electrically connected by bonding the bonding electrode BDE1 and the conductive pattern BDE2 of the light emitting device LD by performing a bonding process using a bonding method such as heating and pressurization. do.

During the above-described bonding process, the intermediate layer CTL is cured to stably fix the light emitting device LD bonded to the first electrode AE. In this case, the thickness (or height) of the intermediate layer CTL may be smaller than the length L of the light emitting device LD.

Referring to FIGS. 8 and 13A to 13H , after the bonding process, a laser is irradiated to the upper portion of the transfer substrate 1 to separate the transfer substrate 1 from the light emitting device LD to form a third of the light emitting device LD. The semiconductor layer 15 is exposed to the outside.

After the above-described process, the second electrode CE may be entirely formed on the third semiconductor layer 15 and the intermediate layer CTL of the light emitting device LD. The second electrode CE may be electrically connected to the third semiconductor layer 15 . The contact structure between the second electrode CE and the first semiconductor layer 11 of the light emitting device LD is not limited to the above-described embodiment. In some embodiments, the second electrode CE may be formed in the same process as the first semiconductor layer 11 of the light emitting device LD and may be electrically connected to a common electrode (not shown) located in the non-display area NDA. have.

In the display device formed through the above-described manufacturing method, a process for forming a separate reflective member is performed by using the conductive pattern BDE2 bonding the light emitting element LD and the first electrode AE as the reflective member BMTL. It may be omitted to simplify the manufacturing process. In addition, the conductive pattern BDE2 is disposed to surround the opening OP along the side surface of the bank BNK so that the conductive pattern BDE2 faces the active layer 12 of the light emitting device LD. ) may be guided in the image display direction to further improve the light output efficiency of the pixel PXL.

14A is a cross-sectional view taken along line I to I′ of FIG. 3 .

In order to avoid overlapping descriptions with respect to the first to third pixels PXL1 to PXL3 of FIG. 14A , differences from the above-described exemplary embodiment will be mainly described. In one embodiment of the present invention, parts not specifically described are in accordance with the above-described embodiment, and like numerals denote like elements and similar numbers denote similar elements.

3 and 14A , only a partial configuration of each of the first to third pixels PXL1 to PXL3 is illustrated for convenience.

3 and 14A , a first pixel PXL1 (or a first sub-pixel), a second pixel PXL2 (or a second sub-pixel), and a third pixel PXL3 in a first direction DR1 ) (or the third sub-pixel) may be arranged. Each of the first to third pixels PXL1 , PXL2 , and PXL3 may have the same configuration as the pixel PXL described with reference to FIGS. 8 and 12 .

The display area DA of the substrate SUB includes a first pixel area PXA1 in which the first pixel PXL1 is provided (or provided), and a second pixel area PXA1 in which the second pixel PXL2 is provided (or provided). PXA2 , and a third pixel area PXA3 in which the third pixel PXL3 is provided (or provided). In an embodiment, the first pixel PXL1 may be a red pixel, the second pixel PXL2 may be a green pixel, and the third pixel PXL3 may be a blue pixel. However, the present invention is not limited thereto, and according to embodiments, the second pixel PXL2 may be a red pixel, the first pixel PXL1 may be a green pixel, and the third pixel PXL3 may be a blue pixel. have. Also, according to another exemplary embodiment, the third pixel PXL3 may be a red pixel, the first pixel PXL1 may be a green pixel, and the second pixel PXL2 may be a blue pixel.

Each of the first, second, and third pixels PXL1 , PXL2 , and PXL3 may include an emission area EMA. In addition, each of the first, second, and third pixels PXL1 , PXL2 , and PXL3 may include a non-emission area NEMA adjacent to the emission area EMA of the corresponding pixel PXL. A bank BNK (or barrier rib) may be positioned in the non-emission area NEMA.

Each of the first, second, and third pixels PXL1 , PXL2 , and PXL3 may include a substrate SUB, a pixel circuit layer PCL, and a display device layer DPL.

The display element layer DPL of the first pixel PXL1 includes a first electrode AE, a conductive pattern BDE2 , a bank BNK, a first light emitting element LD1 , an intermediate layer CTL, and a second electrode (CE) may be included. Each of the bank BNK, the intermediate layer CTL, and the second electrode CE may be provided in common to the first, second, and third pixels PXL1 , PXL2 , and PXL3 . For example, each of the bank BNK, the intermediate layer CTL, and the second electrode CE may be a common layer (film) provided to the adjacent pixels PXL.

The conductive pattern BDE2 may be bonded to the bonding electrode BDE1 of the first light emitting device LD1 to electrically connect the first light emitting device LD1 and the first electrode AE. In addition, the conductive pattern BDE2 is positioned on the side surface of the bank BNK and the first electrode AE to surround the opening OP of the bank BNK, respectively, to image the light emitted from the light emitting device LD. The light output efficiency of the first pixel PXL1 may be improved by guiding it in the display direction. During the bonding process between the first electrode AE and the first light emitting device LD1 , the intermediate layer CTL may be cured. In this case, the first light emitting device LD1 may be stably fixed to be more securely electrically and/or physically connected to the first electrode AE. The intermediate layer CTL includes the third semiconductor layer 15 of the first light emitting device LD1 so that the second end EP2 of the first light emitting device LD1 is electrically connected to the second electrode CE. It may have a thickness (or height) enough to be exposed to the outside. For example, the intermediate layer CTL may have a thickness (or height) smaller than the length of the first light emitting device LD1 in the third direction DR3 .

In the above-described exemplary embodiment, one first light emitting device LD1 may be bonded to the first electrode AE in the first pixel PXL1 . Accordingly, one first light emitting device LD1 may be provided in the first pixel PXL1 .

An upper substrate U_SUB may be positioned on the display element layer DPL of the first pixel PXL1 . The upper substrate U_SUB may include a light conversion pattern LCP, a light blocking pattern LBP, and a base layer BSL. The light conversion pattern LCP includes a first color filter CF1 positioned on one surface of the base layer BSL and a first color conversion pattern positioned on the first color filter CF1 with the insulating layer INS interposed therebetween. layer CCL1 may be included. Here, the first color conversion layer CCL1 may include first color conversion particles QD1 . The first color filter CF1 may be a red color filter. The first color filter CF1 and the first color conversion layer CCL1 described above may be positioned in the emission area EMA of the first pixel PXL1 .

The display element layer DPL of the second pixel PXL2 includes a first electrode AE, a conductive pattern BDE2 , a bank BNK, a second light emitting element LD2 , an intermediate layer CTL, and a second electrode (CE) may be included.

The conductive pattern BDE2 may be bonded to the bonding electrode BDE1 of the second light emitting device LD2 to electrically connect the second light emitting device LD2 and the first electrode AE. In addition, the second bonding electrode BDE2 is disposed on the side surface of the bank BNK and the first electrode AE to surround the opening OP of the bank BNK, respectively, and is emitted from the second light emitting device LD2 . The light output efficiency of the second pixel PXL2 may be improved by guiding the emitted light in the image display direction.

An upper substrate U_SUB may be positioned on the display element layer DPL of the second pixel PXL2 . The upper substrate U_SUB may include a light conversion pattern LCP, a light blocking pattern LBP, and a base layer BSL. The light conversion pattern LCP includes a second color filter CF2 positioned on one surface of the base layer BSL and a second color conversion pattern positioned on the second color filter CF2 with the insulating layer INS interposed therebetween. layer CCL2. The second color conversion layer CCL2 may include second color conversion particles QD2 . The second color filter CF2 may be a green color filter. The second color filter CF2 and the second color conversion layer CCL2 described above may be positioned in the emission area EMA of the second pixel PXL2 .

One second light emitting device LD2 may be bonded to the first electrode AE in the second pixel PXL2 . Accordingly, one second light emitting device LD2 may be provided in the second pixel PXL2 .

The display element layer DPL of the third pixel PXL3 includes a first electrode AE, a conductive pattern BDE2 , a bank BNK, a third light emitting element LD3 , an intermediate layer CTL, and a second electrode (CE) may be included.

The conductive pattern BDE2 may be bonded to the bonding electrode BDE1 of the third light emitting device LD3 to electrically connect the third light emitting device LD3 and the first electrode AE. In addition, the conductive pattern BDE2 is positioned on the side surface of the bank BNK and the first electrode AE to surround the opening OP of the bank BNK, respectively, and the light emitted from the third light emitting device LD3 is provided. may be induced in the image display direction to improve light output efficiency of the third pixel PXL3 .

An upper substrate U_SUB may be positioned on the display element layer DPL of the third pixel PXL3 . The upper substrate U_SUB may include a light conversion pattern LCP, a light blocking pattern LBP, and a base layer BSL. The light conversion pattern LCP includes a third color filter CF3 positioned on one surface of the base layer BSL and a third color conversion pattern positioned on the third color filter CF3 with the insulating layer INS interposed therebetween. layer CCL3. The third color conversion layer CCL3 may include third color conversion particles QD3 . The third color filter CF3 may be a green color filter. The third color filter CF3 and the third color conversion layer CCL3 described above may be positioned in the emission area EMA of the third pixel PXL3 .

In the third pixel PXL3 , one third light emitting device LD3 may be bonded to the first electrode AE. Accordingly, one third light emitting device LD3 may be provided in the third pixel PXL3 .

A light blocking pattern LBP may be positioned in the non-emission area NEMA of each of the first, second, and third pixels PXL1 , PXL2 , and PXL3 . The light blocking pattern LBP may include a first light blocking pattern LBP1 and a second light blocking pattern LBP2 . The first light blocking pattern LBP1 may be disposed on one surface of the base layer BSL to be adjacent to the color filter CF of each of the first, second, and third pixels PXL1 , PXL2 , and PXL3 . For example, the first blocking pattern LBP1 may be formed between the first color filter CF1 and the second color filter CF2 and between the second color filter CF2 and the third color filter CF3 on one surface of the base layer BSL. ) can be located between The second light blocking pattern LBP2 may be disposed on one surface of the insulating layer INS to be adjacent to the color conversion layer CCL of each of the first, second, and third pixels PXL1 , PXL2 , and PXL3 . . For example, the second light blocking pattern LBP2 may be formed between the first color conversion layer CCL1 and the second color conversion layer CCL2 and between the second color conversion layer CCL2 and the third color on one surface of the insulating layer INS. It may be positioned between the conversion layers CCL3 .

14B is a schematic cross-sectional view of a display device according to an exemplary embodiment.

In order to avoid overlapping descriptions with respect to the first to third pixels PXL1 to PXL3 of FIG. 14B , differences from the above-described exemplary embodiment will be mainly described. In one embodiment of the present invention, parts not specifically described are in accordance with the above-described embodiment, and like numerals denote like elements and similar numbers denote similar elements.

In FIG. 14B , only a partial configuration of each of the first to third pixels PXL1 , PXL2 , and PXL3 is illustrated for convenience.

3 and 14B , a first pixel PXL1 (or a first sub-pixel), a second pixel PXL2 (or a second sub-pixel), and a third pixel in one direction in the display area DA (PXL3) (or a third sub-pixel) may be arranged. Each of the first to third pixels PXL1 , PXL2 , and PXL3 may have a configuration substantially similar to that of the pixel PXL described with reference to FIGS. 8 to 12 .

Each of the first, second, and third pixels PXL1 , PXL2 , and PXL3 may include an emission area EMA.

Each of the first, second, and third pixels PXL1 , PXL2 , and PXL3 may include a substrate SUB, a pixel circuit layer PCL, and a display device layer DPL.

The pixel circuit layer PCL of each of the first, second, and third pixels PXL1 , PXL2 , and PXL3 may include a second conductive pattern BDE2 provided on the substrate SUB. Since the second conductive pattern BDE2 has the same configuration as the conductive pattern BDE2 described with reference to FIGS. 8 to 14A , a detailed description thereof will be omitted.

A third conductive pattern BDE3 may be provided and/or formed in the non-display area NDA. The third conductive pattern BDE3 may be electrically connected to the common electrode CELT. The third conductive pattern BDE3 may be electrically connected to the common electrode CELT through the bump BUM and the second conductive connector CE2 . In an embodiment, the second conductive pattern BDE2 and the third conductive pattern BDE3 may be formed by the same process. Here, the bump BUM and the second conductive connector CE2 may be positioned in the non-display area NDA.

The display device layer DPL of each of the first, second, and third pixels PXL1 , PXL2 , and PXL3 may include a first conductive connector CE1 and a light emitting device LD.

The first conductive connector CE1 may include a conductive material. The first conductive connector CE1 may be a connecting member that couples the separately provided second conductive pattern BDE2 to the bonding electrode BDE1 of the light emitting device LD. In some embodiments, the first conductive connector CE1 may be an intermetallic compound generated and grown in a bonding process between the light emitting device LD and the second conductive pattern BDE2 , but is not limited thereto.

The bonding electrode BDE1 of the light emitting device LD electrically connects the light emitting device LD provided in the form of a chip to the pixel circuit layer PCL of each of the first, second, and third pixels PXL1, PXL2, and PXL3. It may be a configuration for connecting to The bonding electrode BDE1 of the light emitting device LD may have the same configuration as the bonding electrode BDE1 of the light emitting device LD described with reference to FIGS. 8 to 14A .

The light emitting device LD may include a first semiconductor layer 11 , an active layer 12 , and a second semiconductor layer 13 . The light emitting device LD may have a pillar shape, but is not limited thereto. In addition, the light emitting device LD may further include an insulating layer 14 surrounding the outer peripheral surfaces of the first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer 13 . The insulating layer 14 may have the same configuration as the insulating layer IL with reference to FIGS. 8 to 14A .

The first semiconductor layer 11 may be electrically connected to the common electrode CELT formed in the non-display area NDA. The first semiconductor layer 11 may receive an electrical signal applied from the third conductive pattern BDE3 through the common electrode CELT. In an embodiment, the common electrode CELT may be formed by the same process as that of the first semiconductor layer 11 .

In an embodiment, the first semiconductor layer 11 of the light emitting device LD disposed in the first pixel PXL1 and the first semiconductor layer 11 of the light emitting device LD disposed in the second pixel PXL2 ) and the first semiconductor layer 11 of the light emitting device LD disposed in the third pixel PXL3 may be connected to the common electrode CELT.

In an embodiment, the display device layer DPL may further include a reflective barrier rib REF. The reflective barrier rib REF may be disposed on an outer circumferential surface of the light emitting device LD. The reflective barrier rib REF may be disposed on the insulating layer 14 formed on the outer circumferential surface of the light emitting device LD. The reflective barrier rib REF may include a reflective material.

The display device according to the above-described embodiment includes a smartphone, a television, a tablet PC, a mobile phone, a video phone, an e-book reader, a desktop PC, a laptop PC, a netbook computer, a workstation, a server, a PDA, a portable multimedia player (PMP), The present invention may be applied to any electronic device in which a display surface is applied to at least one surface, such as an MP3 player, a medical device, a camera, or a wearable device.

Hereinafter, an application field of the display device (refer to “DD” of FIG. 1 ) according to an exemplary embodiment will be described with reference to FIGS. 15 to 18 .

15 to 18 are diagrams illustrating application examples of display devices according to embodiments of the present invention.

First, referring to FIGS. 1 and 15 , the display device DD may be applied to the smart watch 1200 including the display unit 1220 and the strap unit 1240 .

The smart watch 1200 is a wearable electronic device and may have a structure in which the strap unit 1240 is mounted on a user's wrist. Here, the display device DD may be applied to the display unit 1220 to provide image data including time information to the user.

1 and 16 , the display device DD may be applied to an automotive display 1300 . Here, the automotive display 1300 may refer to an electronic device provided inside or outside the vehicle to provide image data.

For example, the display device DD includes an infotainment panel 1310 , an infotainment panel 1310 , a cluster 1320 , a co-driver display 1330 , and a head-up display 1340 provided in the vehicle. , a head-up display), a side mirror display 1350, and a rear-seat display may be applied to at least one.

1 and 17 , the display device DD may be applied to smart glasses including a frame 170 and a lens unit 171 . Smart glasses are wearable electronic devices that can be worn on a user's face, and may have a structure in which a part of the frame 170 is folded or unfolded. For example, the smart glasses may be a wearable device for augmented reality (AR).

The frame 170 may include a housing 170b supporting the lens unit 171 and a leg unit 170a for wearing by a user. The leg portion 170a is connected to the housing 170b by a hinge and may be folded or unfolded.

A battery, a touch pad, a microphone, a camera, and the like may be built in the frame 170 . In addition, a projector for outputting light, a processor for controlling an optical signal, etc. may be built in the frame 170 .

The lens unit 171 may be an optical member that transmits light or reflects light. The lens unit 171 may include glass, a transparent synthetic resin, or the like.

In addition, the lens unit 171 reflects the image by the optical signal transmitted from the projector of the frame 170 by the rear surface of the lens unit 171 (for example, the surface in the direction toward the user's eyes) to reflect the user's eyes. can be recognizable in For example, as shown in the drawing, the user may recognize information such as time and date displayed on the lens unit 171 . That is, the lens unit 171 is a kind of display device, and the display device DD may be applied to the lens unit 171 .

1 and 18 , the display device DD may be applied to a head mounted display (HMD) including a head mounting band 180 and a display storage case 181 . A head mounted display is a wearable electronic device that can be worn on a user's head.

The head mounting band 180 is connected to the display storage case 181 to fix the display storage case 181 . In the drawings, the head mounting band 180 is shown to be able to surround the upper surface and both sides of the user's head, but the present invention is not limited thereto. The head mounting band 180 is for fixing the head mounted display to the user's head, and may be formed in the form of an eyeglass frame or a helmet.

The display storage case 181 accommodates the display device DD and may include at least one lens. At least one lens is a part that provides an image to a user. For example, the display device DD may be applied to a left eye lens and a right eye lens implemented in the display storage case 181 .

19 to 22 are cross-sectional views schematically illustrating a pixel PXL according to still another exemplary embodiment.

19 shows a modified embodiment of the embodiment of FIG. 9 in relation to the opening OP of the bank BNK, and the like, and FIG. 20 is a modified embodiment of the embodiment of FIG. 9 in relation to the first electrode AE, etc. , and FIG. 21 shows a modified example of the embodiment of FIG. 9 in relation to the conductive pattern BDE2 and the like. Also, FIG. 22 shows a modified example of the embodiment of FIG. 21 in relation to the first electrode AE and the like.

19 to 22, points different from the above-described embodiment will be mainly described in order to avoid overlapping description.

19 to 22 , the thickness direction of the substrate SUB on the cross-section is indicated by the third direction DR3 .

1, 3, and 19 , the pixel PXL may include a substrate SUB, a pixel circuit layer PCL, and a display element layer DPL.

The pixel circuit layer PCL may include a substrate SUB and at least one transistor T disposed on the substrate SUB. The transistor T may be a driving transistor T. Since the pixel circuit layer PCL is the same as the pixel circuit layer PCL described with reference to FIGS. 8 to 10C , a detailed description thereof will be omitted.

The display element layer DPL may include a first electrode AE, a bank BNK, a conductive pattern BDE2 , an intermediate layer CTL, a light emitting element LD, and a second electrode CE.

The first electrode AE may be electrically connected to the first terminal ET1 of the driving transistor T of the pixel circuit layer PCL.

The bank BNK may be positioned in the non-emission area NEMA to form a pixel defining layer that partitions the light emission area EMA of the pixel PXL. The bank BNK may include at least one light blocking material and/or a reflective material (or a scattering material) to prevent light leakage between adjacent pixels PXL. In some embodiments, the bank BNK may be an organic insulating layer including an organic material.

The bank BNK may include an opening OP exposing the first electrode AE. For example, the bank BNK may be partially opened to include an opening OP that entirely exposes the first electrode AE positioned on the pixel circuit layer PCL. The emission area EMA of the pixel PXL and the opening OP of the bank BNK may correspond to each other.

The width W3 of the opening OP of the bank BNK in one direction crossing the third direction DR3 (eg, a horizontal direction on the cross-section) is greater than the width W4 of the first electrode AE1 . can Accordingly, one region of the passivation layer PSV may be exposed. In this case, the width W3 of the opening OP of the bank BNK may mean a distance between two side surfaces of the bank BNK facing each other with the opening OP interposed therebetween.

A conductive pattern BDE2 (or a second bonding electrode) may be provided and/or formed in the opening OP of the bank BNK.

The conductive pattern BDE2 may be provided and/or formed on the side surface of the bank BNK, one region of the exposed passivation layer PSV, and the first electrode AE to surround the opening OP. The conductive pattern BDE2 may be a medium for electrically connecting the driving transistor T and the light emitting device LD by bonding to the bonding electrode BDE1 of the light emitting device LD. The conductive pattern BDE2 may be used as a reflective member RMTL for guiding the light emitted from the light emitting device LD in the image display direction of the display device DD. To this end, the conductive pattern BDE2 may be formed of an opaque conductive material having a predetermined reflectivity.

In an embodiment, the conductive pattern BDE2 may include a first portion A1 , a second portion A2 , and a third portion A3 . For example, the conductive pattern BDE2 is formed on the first portion A1 located on the side surface of the bank BNK, the second portion A2 located on the first electrode AE, and the exposed passivation layer PSV. It may include a positioned third part A3.

The conductive pattern BDE2 may be entirely formed on the first electrode AE by the opening OP of the bank BNK having a width W3 that is wider than that of the first electrode AE in the one direction. It may be formed on one region of the exposed passivation layer PSV. In this case, the area of the conductive pattern BDE2 bonding to the light emitting device LD may increase.

When the area of the conductive pattern BDE2 is increased, it is transferred to the transfer substrate in a transfer process performed before the bonding process (eg, a process of electrically connecting the light emitting device LD and the first electrode AE). When the light emitting device LD is re-transferred onto the first electrode AE, the light emitting device LD may be easily (or sufficiently) inserted into the opening OP of the bank BNK. Accordingly, misalignment of the light emitting device LD that may occur in the above-described transfer process is prevented, so that the light emitting device LD may be precisely aligned at a desired position.

1, 3, and 20 , the first electrode AE may include a groove HM corresponding to the opening OP of the bank BNK. The groove HM may be an area of the first electrode AE positioned in the emission area EMA.

In an embodiment, the groove portion HM may be a stepped area from one surface (eg, an upper surface) of the first electrode AE in the direction of the passivation layer PSV. The groove portion HM is formed by forming a bank BNK including an opening OP on the first electrode AE, and then etching a portion of the first electrode AE exposed by the opening OP through an etching process. It may be a stepped area of the first electrode AE formed by removing the first electrode AE. Accordingly, the first electrode AE including the groove portion HM may have a thickness smaller than that of the first electrode AE not including the groove portion HM.

As the first electrode AE includes the groove HM in the emission area EMA, the opening OP may extend to the groove HM in the third direction DR3 . Accordingly, the depth h of the opening OP of the bank BNK may increase in the third direction DR3 .

Due to the aforementioned groove HM, the first electrode AE may have at least two thicknesses in the third direction DR3 . For example, the first electrode AE has a first thickness d1 from one surface of the passivation layer PSV to the upper surface of the first electrode AE in the third direction DR3 , and a first thickness d1 of the driving transistor T A second thickness d2 from one surface of the terminal ET1 to the top surface of the first electrode AE, and a third thickness d3 from one surface of the passivation layer PSV to the groove HM. . The first thickness d1 , the second thickness d2 , and the third thickness d3 may be different from each other. For example, the second thickness d2 may be the thickest and the third thickness d3 may be the thinnest.

A conductive pattern BDE2 may be provided and/or formed on the first electrode AE including the groove portion HM.

As described above, as the first electrode AE corresponding to the opening OP of the bank BNK includes the groove portion HM, the second portion A2 of the conductive pattern BDE2 positioned thereon is formed as described above. A thickness equal to the thickness of the first electrode AE removed in one etching process may be further secured. Accordingly, the second portion A2 of the conductive pattern BDE2 positioned on the first electrode AE has a thickness greater than or equal to a certain level to more stably connect the light emitting device LD and the first electrode AE in the bonding process. It can be electrically connected.

In addition, as the depth h of the opening OP of the bank BNK is increased by the groove HM of the first electrode AE, the light emitting device LD is more deeply inserted into the opening OP. can do. Accordingly, the first portion A1 of the conductive pattern BDE2 is located closer to the active layer 12 of the light emitting device LD, so that the area of the conductive pattern BDE2 corresponding to the active layer 12 is further increased. The light output efficiency of the pixel PXL may be further increased by further guiding the light emitted from the active layer 12 in a desired direction.

1, 3, and 21 , the conductive pattern BDE2 may include a first layer FL, a second layer SL, and a third layer TL.

The third layer TL may be provided and/or formed on the side surface of the bank BNK and the first electrode AE within the opening OP of the bank BNK to surround the opening OP. The third layer TL may be positioned on the side surfaces of the first electrode AE and the bank BNK to directly contact the side surfaces of the first electrode AE and the bank BNK.

In an embodiment, the third layer TL is a metal layer electrically connected to the first electrode AE in direct contact with the first electrode AE, and includes titanium (Ti), copper (Cu), and nickel (Ni). etc. can be selected. The third layer TL may have a thickness greater than or equal to a certain level in order to reduce a step difference between the first electrode AE and the light emitting device LD. For example, the third layer TL may include a double layer stacked in the order of titanium (Ti)/copper (Cu), but is not limited thereto. When the third layer TL is composed of a double layer stacked in the order of titanium (Ti)/copper (Cu), the thickness of the third layer TL is secured to a certain level or more by controlling the thickness of copper (Cu). can be The third layer TL may have the same or substantially similar configuration to the first layer FL described with reference to FIGS. 10A to 10C .

In addition, the above-described third layer TL may be a barrier metal layer for preventing diffusion that may occur in the process of forming the first layer FL positioned thereon.

The first layer FL may be positioned between the third layer TL and the second layer SL. The first layer FL may be formed of a conductive material having a reflectance to guide the light emitted from the light emitting device LD in the image display direction (or the front direction) of the display device DD. The conductive material may include an opaque metal advantageous for reflecting light emitted from the light emitting elements LD in an image display direction (or a desired direction) of the display device DD. As the opaque metal, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium ( Ir), chromium (Cr), titanium (Ti), and a metal such as alloys thereof may be included. For example, the first layer FL may include aluminum (Al).

The second layer SL may be a metal layer that is in direct contact with the bonding electrode BDE1 of the light emitting device LD and is electrically connected to the light emitting device LD. When the second layer SL is bonded to the bonding electrode BDE1 of the light emitting device LD, an intermetallic compound is generated and grown between the second layer SL and the bonding electrode BDE1 of the light emitting device LD. To facilitate this, gold (Au), tin (Sn), etc. having excellent bonding strength (or adhesive strength) may be selected. For example, the second layer SL may include gold (Au). In an embodiment, the second layer SL may have the same or substantially similar configuration to the second layer SL described with reference to FIGS. 10A to 10C .

The second layer SL may not be disposed on the side surface of the bank BNK within the opening OP of the bank BNK, but may be disposed only on one surface of the first layer FL corresponding to the first electrode AE. have. Accordingly, on the side of the bank BNK, the first layer FL may be located on the uppermost layer.

In the conductive pattern BDE2 including the triple layer stacked in this order of the third layer TL, the first layer FL, and the second layer SL from one surface of the first electrode AE, the first layer The FL is located on the side of the bank BNK and may be used as a reflective member RMTL for guiding light emitted from the light emitting device LD in the direction of the display device DD, and the second layer SL is located on the uppermost layer among the components positioned on the first electrode AE exposed in the opening OP of the bank BNK and is directly connected to the bonding electrode BDE1 of the light emitting device LD for bonding. can be used as

1, 3, and 22 , the first electrode AE may include a groove HM corresponding to the opening OP of the bank BNK. The first electrode AE may have at least two thicknesses in the third direction DR3 . For example, the first electrode AE may have a first thickness d1 , a second thickness d2 , and a third thickness d3 different from each other in the third direction DR3 . Since the first electrode AE is the same as the first electrode AE described with reference to FIG. 20 , a detailed description thereof will be omitted.

As the first electrode AE includes the groove portion HM in the emission area EMA, the opening OP of the bank BNK may extend to the groove portion HM in the third direction DR3 . Accordingly, the depth h of the opening OP of the bank BNK may increase in the third direction DR3 .

A conductive pattern BDE2 may be provided and/or formed on the first electrode AE including the groove portion HM.

The conductive pattern BDE2 may include a triple layer stacked in this order of a third layer TL, a first layer FL, and a second layer SL from one surface of the first electrode AE. Since the conductive pattern BDE2 is the same as the conductive pattern BDE2 described with reference to FIG. 21 , a detailed description thereof will be omitted.

As described above, as the depth h of the opening OP of the bank BNK is increased by the groove HM of the first electrode AE, the light emitting element LD is inserted into the opening OP. It can be inserted even deeper. Accordingly, the first layer FL of the conductive pattern BDE2 positioned on the side surface of the bank BNK is positioned more adjacent to the active layer 12 of the light emitting device LD, so that the first layer corresponding to the active layer 12 is located. Since the area of the layer FL is further secured, the light emitted from the active layer 12 is further guided in a desired direction, so that the light output efficiency of the pixel PXL can be further increased.

Although the above has been described with reference to the preferred embodiment of the present invention, those skilled in the art or those having ordinary knowledge in the technical field will not depart from the spirit and technical scope of the present invention described in the claims to be described later. It will be understood that various modifications and variations of the present invention can be made without departing from the scope of the present invention.

Accordingly, the technical scope of the present invention is not limited to the content described in the detailed description of the specification, but should be defined by the claims.

SUB: Substrate
LD: light emitting element
PXL: Pixel
PXA: pixel area
EMA: luminous area
NEMA: non-emissive area
PCL: pixel circuit layer
DPL: display element layer
BNK: bank
OP: opening
AE, CE: first and second electrodes
BDE1: bonding electrode (or first bonding electrode)
BDE2: conductive pattern (or second bonding electrode)
FL: first layer
SL: second layer
TL: 3rd layer
CCL: color conversion layer
CF: color filter

Claims (28)

Board; and
a plurality of pixels provided on the substrate;
Each of the plurality of pixels,
a pixel circuit layer provided on the substrate and including at least one transistor;
a first electrode provided on the pixel circuit layer and electrically connected to the transistor;
a bank provided on the first electrode and including an opening exposing the first electrode;
a conductive pattern provided on a side surface of the bank surrounding the opening and the exposed first electrode;
a light emitting device positioned on the conductive pattern in the opening and electrically connected to the first electrode; and
A second electrode provided on the light emitting device,
The conductive pattern is a guide member for guiding the light emitted from the light emitting device to an upper portion of the second electrode. The method of claim 1,
The light emitting device includes a first end and a second end in the longitudinal direction,
The first end is electrically connected to the conductive pattern, and the second end is electrically connected to the second electrode. 3. The method of claim 2,
The light emitting device,
a bonding electrode positioned at the first end and electrically connected to the conductive pattern in contact with the conductive pattern;
a third semiconductor layer positioned at the second end and electrically connected to the second electrode in contact with the second electrode;
a second semiconductor layer positioned on the bonding electrode;
a first semiconductor layer located between the third semiconductor layer and the second semiconductor layer; and
an active layer positioned between the first semiconductor layer and the second semiconductor layer;
The display device of claim 1, wherein the first semiconductor layer is an n-type semiconductor layer doped with an n-type dopant, and the second semiconductor layer is a p-type semiconductor layer doped with a p-type dopant. 4. The method of claim 3,
and the conductive pattern is bonded to a bonding electrode of the light emitting device. 5. The method of claim 4,
The conductive pattern is
a first layer located on the first electrode; and
a second layer positioned on the first layer;
The first layer is in direct contact with the first electrode, and the second layer is in direct contact with the bonding electrode. 6. The method of claim 5,
Each of the first and second layers includes a metal that reflects light emitted from the light emitting device. 7. The method of claim 6,
The first layer includes a metal selected from gold and tin,
The second layer includes a metal selected from titanium, copper, and nickel,
and the first layer and the second layer have different thicknesses. 3. The method of claim 2,
The one region of the conductive pattern positioned on the side surface of the bank has a slope corresponding to a side inclination angle of the bank. 9. The method of claim 8,
The one region of the conductive pattern includes a protrusion protruding toward the second electrode. 3. The method of claim 2,
Each of the plurality of pixels may further include an intermediate layer positioned between the bank and the second electrode to fill the opening. 11. The method of claim 10,
The intermediate layer is a fixing member for fixing the light emitting element, and includes an organic material that has adhesiveness and is cured by heat or light. 3. The method of claim 2,
Each of the plurality of pixels includes a light emitting area in which the light emitting element is disposed and a non-emission area adjacent to the light emitting area,
the bank corresponds to the non-emission region, and the opening corresponds to the light emitting region. 13. The method of claim 12,
Each of the plurality of pixels,
a cover layer disposed entirely on the second electrode; and
The display device further comprising an upper substrate positioned on the cover layer. 14. The method of claim 13,
The upper substrate is
a base layer positioned on the cover layer so that one surface faces the light emitting device;
a light conversion pattern positioned on the one surface of the base layer to correspond to the light emitting region; and
and a light blocking pattern positioned on the one surface of the base layer to correspond to the non-emission area. 15. The method of claim 14,
The light conversion pattern is
a color filter positioned on the one surface of the base layer; and
and a color conversion layer including color conversion particles disposed on the color filter with an insulating layer interposed therebetween to correspond to the light emitting element. 16. The method of claim 15,
The light blocking pattern is
a first light blocking pattern located on the one surface of the base layer; and
and a second blocking pattern positioned on the insulating layer to correspond to the first blocking pattern. 17. The method of claim 16,
The upper substrate may further include a capping layer disposed entirely on the color conversion layer and the second light blocking pattern. The method of claim 1,
and the opening of the bank has a width greater than a width of the first electrode. 19. The method of claim 18,
The pixel circuit layer further includes a passivation layer disposed on the transistor,
The opening of the bank entirely exposes the first electrode and partially exposes the passivation layer. 20. The method of claim 19,
The conductive pattern is provided on the exposed portion of the first electrode and the exposed passivation layer. The method of claim 1,
the first electrode includes a stepped groove from one surface thereof toward the pixel circuit layer;
and the groove portion corresponds to the opening portion of the bank. 22. The method of claim 21,
The conductive pattern is
a third layer disposed on the exposed first electrode and side surfaces of the bank;
a first layer disposed on the third layer; and
a second layer disposed between the first layer and the light emitting device,
The third layer is in direct contact with the first electrode, and the second layer is in direct contact with the light emitting element. 23. The method of claim 22,
The third layer includes a metal selected from among titanium, copper, and nickel;
the first layer comprises aluminum;
The second layer includes a metal selected from among gold and tin. 24. The method of claim 23,
and the first layer is located at an uppermost layer on a side surface of the bank. Board; and
a plurality of pixels provided on the substrate;
Each of the plurality of pixels,
a pixel circuit layer provided on the substrate and including at least one transistor;
a first electrode provided on the pixel circuit layer and electrically connected to the transistor;
a bank provided on the first electrode and including an opening exposing the first electrode;
a conductive pattern provided on a side surface of the bank surrounding the opening and the exposed first electrode;
a light emitting element positioned on the conductive pattern in the opening and electrically connected to the first electrode; and
a second electrode provided on the light emitting device,
The conductive pattern includes a third layer provided on the first electrode, a first layer provided on the third layer, and a second layer provided on the first layer on the first electrode,
The first layer is a guide member for guiding the light emitted from the light emitting device to the upper portion of the second electrode,
The second layer is a bonding member bonding to the light emitting element. forming at least one transistor on a substrate;
forming a first electrode electrically connected to the transistor on the transistor;
forming a photosensitive pattern exposing the insulating material layer by applying an insulating material layer and a photosensitive material layer on the first electrode and then removing the photosensitive material layer on one region of the first electrode;
forming a bank including an opening exposing a region of the first electrode by removing the exposed insulating material layer by using the photosensitive pattern as an etch mask;
forming a conductive layer entirely on the photosensitive pattern and the exposed region of the first electrode;
forming a conductive pattern on one region of the first electrode by removing the photosensitive pattern and the conductive layer disposed on the photosensitive pattern by a lift-off method;
applying a fluid intermediate layer material to the entire surface of the conductive pattern and the bank;
disposing a transfer substrate onto which at least one light emitting element has been transferred, bonding the light emitting element and the conductive pattern to the substrate, curing the intermediate layer material to form an intermediate layer, and then removing the transfer substrate; and
Comprising the step of forming a second electrode on the light emitting device and the intermediate layer,
The conductive pattern is a guide member for guiding the light emitted from the light emitting device to an upper portion of the second electrode. 27. The method of claim 26,
The light emitting device,
a bonding electrode electrically connected to the conductive pattern in contact with the conductive pattern;
a third semiconductor layer in contact with the second electrode and electrically connected to the second electrode;
a second semiconductor layer positioned on the bonding electrode;
a first semiconductor layer located between the third semiconductor layer and the second semiconductor layer; and
an active layer positioned between the first semiconductor layer and the second semiconductor layer;
The method of claim 1 , wherein the first semiconductor layer is an n-type semiconductor layer doped with an n-type dopant, and the second semiconductor layer is a p-type semiconductor layer doped with a p-type dopant. 28. The method of claim 27,
The conductive pattern is
a first layer located on the first electrode; and
a second layer positioned on the first layer;
The method of claim 1 , wherein the first layer is in direct contact with the first electrode, and the second layer is in direct contact with the bonding electrode.

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