KR20220149880A - Display device and method of manufacturing the display device - Google Patents

Abstract

A display device and a manufacturing method thereof are provided. The display device comprises light emitting elements disposed on a substrate. Each of the light emitting elements comprises a first semiconductor layer, an active layer disposed on the first semiconductor layer, a second semiconductor layer disposed on the active layer, and a porous layer disposed on the second semiconductor layer.

Description

Display device and manufacturing method thereof

The present invention relates to a light emitting display device and a method for manufacturing the same.

Recently, as interest in information display has increased, research and development of display devices is continuously being made.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display device capable of improving light output efficiency of a display panel and simplifying a manufacturing process, and a manufacturing method thereof.

The problems of the present invention are not limited to the problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

A display device according to an exemplary embodiment includes a light emitting device disposed on a substrate, and the light emitting devices include a first semiconductor layer, an active layer disposed on the first semiconductor layer, and an active layer on the active layer, respectively. A second semiconductor layer disposed on, and a porous layer disposed on the second semiconductor layer.

The porous layer may include nanoscale pores.

The porous layer may include the same material as the second semiconductor layer.

The display device may further include bank patterns disposed on the substrate, and the light emitting devices may be disposed between the bank patterns, respectively.

The bank patterns may include the same material as the light emitting devices.

The display device may further include a color conversion layer disposed on the light emitting elements.

The display device may further include a reflective layer disposed between the light emitting elements.

The display device may further include an insulating layer disposed between the light emitting elements and the reflective layer.

The light emitting devices may include a first light emitting device emitting a first color, a second light emitting device emitting a second color, and a third light emitting device emitting a third color.

According to an exemplary embodiment, a method of manufacturing a display device for solving the above problems includes forming a semiconductor layer, forming a porous layer by at least partially etching the semiconductor layer, and forming a light emitting laminate on the porous layer. and providing to form light emitting devices.

In the step of etching the semiconductor layer, nanoscale pores may be formed.

The forming of the light emitting devices may further include etching the porous layer and the light emitting laminate.

The light emitting laminate may include a first semiconductor layer, a second semiconductor layer formed on the first semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer.

The second semiconductor layer may be formed of the same material as the porous layer.

The method of manufacturing the display device may further include etching the porous layer and the light-emitting laminate to form bank patterns.

The bank patterns may be formed simultaneously with the light emitting devices.

The semiconductor layer may include a second semiconductor layer provided between the porous layer and the light-emitting laminate.

The providing of the light emitting laminate may include providing an active layer on the second semiconductor layer, and providing a first semiconductor layer on the active layer.

The display device may further include forming a planarization layer between the light emitting devices.

The display device may further include forming a reflective layer between the light emitting elements.

The details of other embodiments are included in the detailed description and drawings.

According to an embodiment of the present invention, the porous region included in the light emitting devices may scatter light emitted from the light emitting region, thereby improving light output efficiency. Accordingly, since the scattering layer separately provided in the pixel may be omitted, the manufacturing process may be simplified and cost may be reduced.

Effects according to the embodiments are not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a plan view illustrating a display device according to an exemplary embodiment.
2 is a circuit diagram of a pixel according to an exemplary embodiment.
3 and 4 are cross-sectional views illustrating a pixel according to an exemplary embodiment.
5 is a cross-sectional view illustrating a pixel according to another exemplary embodiment.
6 is a cross-sectional view illustrating a pixel according to another exemplary embodiment.
7 to 16 are cross-sectional views of a process step-by-step process of a method of manufacturing a display device according to an exemplary embodiment.
17 to 26 are cross-sectional views illustrating steps of a method of manufacturing a display device according to another exemplary embodiment.
27 to 30 are exemplary views illustrating electronic devices according to various embodiments.

Advantages and features of the present invention, and a method of achieving the same, will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various different forms. These embodiments are provided so that the disclosure of the present invention is complete, and to fully inform those of ordinary skill in the art to which the present invention belongs, the scope of the invention, and the present invention will be defined by the scope of the claims. only

The terminology used herein is for the purpose of describing the embodiments and is not intended to limit the present invention. In this specification, the singular also includes the plural unless otherwise specified. As used herein, “comprises” and/or “comprising” refers to the presence of one or more other components, steps, operations and/or elements in a referenced element, step, operation and/or element. or addition is not excluded.

In addition, "connection" or "connection" may mean a physical and/or electrical connection or connection inclusively. It may also refer generically to a direct or indirect connection or connection and an integral or non-integral connection or connection.

Reference to an element or layer "on" of another element or layer includes any intervening layer or other element directly on or in the middle of the other element or layer. Like reference numerals refer to like elements throughout.

Although the first, second, etc. are used to describe various elements, these elements are not limited by these terms, of course. These terms are only used to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may be the second component within the spirit of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view illustrating a display device according to an exemplary embodiment.

1 illustrates a display device that can use a light emitting element as a light source, particularly a display panel PNL provided in the display device.

For convenience of description, the structure of the display panel PNL is briefly illustrated with reference to the display area DA in FIG. 1 . However, according to an exemplary embodiment, at least one driving circuit unit (eg, at least one of a scan driver and a data driver), wires, and/or pads (not shown) may be further disposed on the display panel PNL.

Referring to FIG. 1 , the display panel PNL may include a substrate SUB and a pixel unit PXU disposed on the substrate SUB. The pixel unit PXU may include first pixels PXL1 , second pixels PXL2 , and/or third pixels PXL3 . Hereinafter, when at least one pixel among the first pixels PXL1 , the second pixels PXL2 , and the third pixels PXL3 is arbitrarily referred to or when two or more types of pixels are collectively referred to, “pixel PXL” )" or "pixels (PXL)".

The substrate SUB constitutes the base member of the display panel PNL, and may be a rigid or flexible substrate or film. For example, the substrate SUB may be made of a rigid substrate made of glass or tempered glass, or a flexible substrate (or thin film) made of plastic or metal, and the material and/or physical properties of the substrate SUB are not particularly limited. does not

The display panel PNL and the substrate SUB for forming the same may include a display area DA for displaying an image and a non-display area NDA excluding the display area DA. Pixels PXL may be disposed in the display area DA. Various wires, pads, and/or built-in circuits connected to the pixels PXL of the display area NDA may be disposed in the non-display area NDA. The pixels PXL may be regularly arranged according to a stripe or PENTILE ^TM arrangement structure. However, the arrangement structure of the pixels PXL is not necessarily limited thereto, and the pixels PXL may be arranged in the display area DA in various structures and/or methods.

According to an exemplary embodiment, two or more types of pixels PXL emitting light of different colors may be disposed in the display area DA. For example, in the display area DA, first pixels PXL1 emitting light of a first color, second pixels PXL2 emitting light of a second color, and light of a third color are provided in the display area DA. Third pixels PXL3 may be arranged. At least one of the first to third pixels PXL1 , PXL2 , and PXL3 adjacent to each other may constitute one pixel unit PXU capable of emitting light of various colors. For example, each of the first to third pixels PXL1 , PXL2 , and PXL3 may be a sub-pixel emitting light of a predetermined color. According to an exemplary embodiment, the first pixel PXL1 is a red pixel emitting red light, the second pixel PXL2 is a green pixel emitting green light, and the third pixel PXL3 is a blue light emitting light. It may be a blue pixel emitting, but is not limited thereto.

In an embodiment, each of the first pixel PXL1 , the second pixel PXL2 , and the third pixel PXL3 includes light emitting devices emitting light of the same color as each other, and disposed on each of the light emitting devices By including the color conversion layer and/or the color filter of different colors, light of the first color, the second color, and the third color may be emitted, respectively. In another embodiment, each of the first pixel PXL1 , the second pixel PXL2 , and the third pixel PXL3 uses the light emitting device of the first color, the light emitting device of the second color, and the light emitting device of the third color as light sources. By providing, the light of the first color, the second color and the third color may be emitted, respectively. However, the color, type, and/or number of the pixels PXL constituting the pixel unit PXU are not particularly limited. That is, the color of the light emitted by each pixel PXL may be variously changed.

The pixel PXL may include at least one light source driven by a predetermined control signal (eg, a scan signal and a data signal) and/or a predetermined power supply (eg, a first power supply and a second power supply). . In an embodiment, the light source may include ultra-small columnar light emitting devices having a size as small as a nanometer scale to a micrometer scale. However, the present invention is not necessarily limited thereto, and various types of light emitting devices may be used as the light source of the pixel PXL.

In an embodiment, each pixel PXL may be configured as an active pixel. However, the types, structures, and/or driving methods of the pixels PXL applicable to the display device are not particularly limited. For example, each pixel PXL may be configured as a pixel of a passive or active type light emitting display device having various structures and/or driving methods.

2 is a circuit diagram of a pixel according to an exemplary embodiment.

FIG. 2 illustrates an electrical connection relationship between components included in a pixel PXL that can be applied to an active display device. However, the types of components included in the pixel PXL are not necessarily limited thereto.

According to an exemplary embodiment, the pixel PXL illustrated in FIG. 2 may be any one of the first pixel PXL1 , the second pixel PXL2 , and the third pixel PXL3 provided in the display panel PNL of FIG. 1 . can The first pixel PXL1 , the second pixel PXL2 , and the third pixel PXL3 may have substantially the same or similar structure to each other.

Referring to FIG. 2 , each pixel PXL may include a light emitting unit EMU that generates light having a luminance corresponding to a data signal. Also, the pixel PXL may further include a pixel circuit PXC for driving the light emitting unit EMU.

According to an embodiment, the light emitting unit EMU is disposed between the first power line PL1 to which the voltage of the first power VDD is applied and the second power line PL2 to which the voltage of the second power VSS is applied. It may include at least one light emitting device LD electrically connected. For example, the light emitting unit EMU connects the first electrode ET1 connected to the first power source VDD via the pixel circuit PXC and the first power line PL1 to the second power line PL2 . It may include a second electrode ET2 connected to the second power source VSS through the light emitting device LD connected between the first electrode ET1 and the second electrode ET2. In an embodiment, the first electrode ET1 may be an anode electrode, and the second electrode ET2 may be a cathode electrode.

The light emitting device LD may include one end connected to the first power source VDD and the other end connected to the second power source VSS. In some embodiments, one end of the light emitting device LD may be provided integrally with the first electrode ET1 to be connected to the first electrode ET1 , and the other end of the light emitting device LD may have a second electrode ET2 . ) and may be provided integrally to be connected to the second electrode ET2. The first power source VDD and the second power source VSS may have different potentials. In this case, the potential difference between the first and second power sources VDD and VSS may be set to be equal to or greater than the threshold voltage of the light emitting device LD during the light emission period of the pixel PXL.

The light emitting element LD may constitute an effective light source of the light emitting unit EMU. The light emitting device LD may emit light with a luminance corresponding to the driving current supplied through the pixel circuit PXC. For example, during each frame period, the pixel circuit PXC may supply a driving current corresponding to a grayscale value of the corresponding frame data to the light emitting unit EMU. The driving current supplied to the light emitting unit EMU may flow through the light emitting device LD. Accordingly, the light emitting unit EMU may emit light while the light emitting device LD emits light with a luminance corresponding to the driving current.

The pixel circuit PXC may be connected to the scan line Si and the data line Dj of the pixel PXL. For example, when the pixel PXL is disposed in the i (i is a natural number)-th row and j (j is a natural number)-th column of the display area DA, the pixel circuit PXC of the pixel PXL is the display area DA ) may be connected to the i-th scan line Si and the j-th data line Dj. In some embodiments, the pixel circuit PXC may include first and second transistors T1 and T2 and a storage capacitor Cst. However, the structure of the pixel circuit PXC is not limited to the embodiment illustrated in FIG. 2 .

The pixel circuit PXC may include first and second transistors T1 and T2 and a storage capacitor Cst.

A first terminal of the first transistor T1 (driving transistor) may be connected to the first power source VDD, and a second terminal may be electrically connected to the light emitting device LD. The gate electrode of the first transistor T1 may be connected to the first node N1 . The first transistor T1 controls the amount of driving current supplied to the light emitting device LD in response to the voltage of the first node N1 .

A first terminal of the second transistor T2 (switching transistor) may be connected to the j-th data line Dj, and a second terminal may be connected to the first node N1. Here, the first terminal and the second terminal of the second transistor T2 are different terminals. For example, if the first terminal is a source electrode, the second terminal may be a drain electrode. In addition, the gate electrode of the second transistor T2 may be connected to the i-th scan line Si.

The second transistor T2 is turned on when a scan signal of a voltage at which the second transistor T2 can be turned on is supplied from the i-th scan line Si, and is connected to the j-th data line Dj and The first node N1 may be electrically connected. In this case, the data signal of the corresponding frame may be supplied to the j-th data line Dj, and accordingly, the data signal may be transmitted to the first node N1. The data signal transferred to the first node N1 may be charged in the storage capacitor Cst.

The storage capacitor Cst may charge a voltage corresponding to the data signal supplied to the first node N1 , and maintain the charged voltage until the data signal of the next frame is supplied.

In FIG. 2 , a second transistor T2 for transferring a data signal into the pixel PXL, a storage capacitor Cst for storing the data signal, and a driving current corresponding to the data signal are applied to the light emitting device LD. ), the pixel circuit PXC including the first transistor T1 is illustrated, but the present invention is not limited thereto, and the structure of the pixel circuit PXC may be variously changed. For example, the pixel circuit PXC adjusts the emission time of the transistor device for compensating the threshold voltage of the first transistor T1 , the transistor device for initializing the first node N1 , and/or the light emitting devices LDs. At least one transistor element, such as a transistor element for controlling, or other circuit elements such as a boosting capacitor for boosting the voltage of the first node N1 may be further included. Also, the first and second transistors T1 and T2 of the pixel circuit PXC are not limited to FIG. 2 , and may be variously changed to NMOS or PMOS.

3 and 4 are cross-sectional views illustrating a pixel according to an exemplary embodiment.

3 and 4 schematically illustrate cross-sectional structures of a first pixel PXL1 , a second pixel PXL2 , and a third pixel PXL3 adjacent to each other.

3 and 4 , a pixel PXL and a display device having the same include a substrate SUB, bank patterns BNP disposed on the substrate SUB, light emitting elements LD, and a color conversion layer. (CCL), and a color filter layer (CFL).

The substrate SUB may be a driving substrate including circuit elements including transistors constituting the pixel circuit (PXC of FIG. 2 ) of each pixel PXL. For example, the substrate SUB may be a driving substrate manufactured in a wafer state. The substrate SUB may use a CMOS substrate including a combination of NMOS and PMOS, but is not limited thereto.

The bank patterns BNP may be disposed on a boundary between the first to third pixels PXL1 , PXL2 , and PXL3 on the substrate SUB. Each of the bank patterns BNP may be provided in a shape extending in one direction. For example, each of the bank patterns BNP may be provided on the substrate SUB in a shape extending in the third direction (Z-axis direction) from the substrate SUB.

The bank patterns BNP may include a first semiconductor layer B1 , an active layer B2 , a second semiconductor layer B3 , and a porous layer BP. For example, the first semiconductor layer B1 , the active layer B2 , the second semiconductor layer B3 , and the porous layer BP of the bank patterns BNP are disposed on the substrate SUB in a third direction (Z-axis direction). ) can be sequentially stacked along the

The first semiconductor layer B1 of the bank patterns BNP may include, for example, at least one p-type semiconductor layer. For example, the first semiconductor layer B1 of the bank patterns BNP includes at least one semiconductor material of GaN, InGaN, InAlGaN, AlGaN, or AlN, and includes Mg, Zn, Ca, Sr, Ba, etc. A p-type semiconductor layer doped with a first conductive dopant (or a p-type dopant) may be included. For example, the first semiconductor layer B1 of the bank patterns BNP may include a GaN semiconductor material doped with a first conductive dopant (or a p-type dopant), but is not necessarily limited thereto. The material may constitute the first semiconductor layer B1 of the bank patterns BNP.

The active layer B2 of the bank patterns BNP may be disposed between the first semiconductor layer B1 and the second semiconductor layer B3 . The active layer B2 of the bank patterns BNP includes any one of a single well structure, a multi-well structure, a single quantum well structure, a multi quantum well (MQW) structure, a quantum dot structure, or a quantum wire structure. can, but is not necessarily limited thereto. The active layer B2 of the bank patterns BNP may include GaN, InGaN, InAlGaN, AlGaN, or AlN, and various other materials may form the active layer B2 of the bank patterns BNP.

The second semiconductor layer B3 of the bank patterns BNP is disposed on the active layer B2 , and may include a semiconductor layer of a different type from that of the first semiconductor layer B1 . In an embodiment, the second semiconductor layer B3 of the bank patterns BNP may include at least one n-type semiconductor layer. For example, the second semiconductor layer B3 of the bank patterns BNP includes any one semiconductor material of GaN, InGaN, InAlGaN, AlGaN, or AlN, and has a second conductivity such as Si, Ge, Sn, etc. The n-type semiconductor layer may be doped with a dopant (or an n-type dopant). For example, the second semiconductor layer B3 of the bank patterns BNP may include a GaN semiconductor material doped with a second conductive dopant (or an n-type dopant). However, the material constituting the second semiconductor layer B3 of the bank patterns BNP is not limited thereto, and in addition, the second semiconductor layer B3 of the bank patterns BNP may be formed of various materials. .

The porous layer BP of the bank patterns BNP may be disposed on the second semiconductor layer B3 . The porous layer BP of the bank patterns BNP may include the same material as the second semiconductor layer B3 , but is not limited thereto. For example, the porous layer BP of the bank patterns BNP may include at least one n-type semiconductor layer. For example, the porous layer BP of the bank patterns BNP includes a semiconductor material such as GaN, InGaN, InAlGaN, AlGaN, or AlN, and a dopant (or n) having a second conductivity such as Si, Ge, Sn, or the like. type dopant) may be a doped n-type semiconductor layer. For example, the porous layer BP of the bank patterns BNP may include a GaN semiconductor material doped with a second conductive dopant (or an n-type dopant). However, the material constituting the porous layer BP of the bank patterns BNP is not limited thereto, and in addition, the porous layer BP of the bank patterns BNP may be formed of various materials.

The porous layer BP of the bank patterns BNP may include a plurality of pores P. The pores P may be nanoscale pores P formed through electrochemical etching, but is not limited thereto. A detailed description thereof will be described later with reference to FIG. 8 .

The bank patterns BNP may further include mask layers MK1 and MK2 disposed on the porous layer BP. The mask layers MK1 and MK2 may include a first mask layer MK1 disposed on the porous layer BP and a second mask layer MK2 disposed on the first mask layer MK1 . The first mask layer MK1 and the second mask layer MK2 may be formed of different materials. For example, the first mask layer MK1 may include silicon oxide (SiOx) and the second mask layer MK2 may include nickel (Ni), but is not limited thereto.

In some embodiments, as shown in FIG. 4 , the bank patterns BNP may further include a semiconductor layer B4 disposed between the porous layer BP and the mask layers MK1 and MK2 . The semiconductor layer B4 may include, but is not limited to, a semiconductor material such as undoped GaN, InGaN, InAlGaN, AlGaN, or AlN. The thickness of the semiconductor layer B4 in the third direction (Z-axis direction) may be smaller than the thickness of the porous layer BP in the third direction (Z-axis direction), but is not limited thereto.

The light emitting devices LD may be respectively disposed in the first to third pixels PXL1 , PXL2 , and PXL3 . The light emitting devices LD may be disposed between the bank patterns BNP on the substrate SUB.

Each of the light emitting devices LD may be provided in various shapes. For example, the light emitting devices LD may have a long rod-like shape (ie, an aspect ratio greater than 1) in the third direction (Z-axis direction) or a bar-like shape. However, it is not necessarily limited thereto. For example, each of the light emitting devices LD may have a pillar shape in which a diameter of one end and a diameter of the other end are different from each other. In addition, the light emitting devices LD may be light emitting diodes (LEDs) manufactured so as to have a diameter and/or length on a nanometer scale to a micrometer scale scale. However, the present invention is not necessarily limited thereto, and the size of the light emitting device LD may be variously changed to meet the requirements (or design conditions) of a lighting device or a display device to which the light emitting device LD is applied.

Each of the light emitting devices LD may include a light emitting area EA and a porous area PA. The light emitting area EA may be provided between the substrate SUB and the porous area PA.

The light emitting area EA may include a first semiconductor layer L1 , a second semiconductor layer L3 , and an active layer L2 interposed between the first and second semiconductor layers L1 and L3 . For example, the first semiconductor layer L1 , the active layer L2 , and the second semiconductor layer L3 of the light emitting devices LD are sequentially stacked on the substrate SUB in the third direction (Z-axis direction). can be

The first semiconductor layer L1 of the light emitting devices LD may include, for example, at least one p-type semiconductor layer. For example, the first semiconductor layer L1 of the light emitting devices LD includes a semiconductor material such as GaN, InGaN, InAlGaN, AlGaN, or AlN, and includes a first semiconductor material such as Mg, Zn, Ca, Sr, Ba, or the like. It may include a p-type semiconductor layer doped with a conductive dopant (or a p-type dopant). For example, the first semiconductor layer L1 of the light emitting devices LD may include a GaN semiconductor material doped with a first conductive dopant (or a p-type dopant), but is not necessarily limited thereto. The material may constitute the first semiconductor layer L1 of the light emitting devices LD.

The active layer L2 of the light emitting devices LD may be disposed between the first semiconductor layer L1 and the second semiconductor layer L3 . The active layer L2 of the light emitting devices LD includes any one of a single well structure, a multi well structure, a single quantum well structure, a multi quantum well (MQW) structure, a quantum dot structure, or a quantum wire structure. can, but is not necessarily limited thereto. The active layer L2 of the light emitting devices LD may include GaN, InGaN, InAlGaN, AlGaN, or AlN, and various other materials may form the active layer L2 of the light emitting devices LD.

When a predetermined signal (or voltage) is applied to each end of the light emitting devices LD, electron-hole pairs are combined in the active layer L2 of the light emitting devices LD, and each light emitting device LD emits light. By controlling the light emission of each light emitting element LD using this principle, the light emitting element LD can be used as a light source of various light emitting devices including the pixel PXL of a display device.

In some embodiments, an electron blocking layer (EBL) may be further disposed between the active layer L2 and the first semiconductor layer L1 of the light emitting devices LD. The electron blocking layer may block the flow of electrons supplied from the second semiconductor layer L3 from escaping to the first semiconductor layer L1 , thereby increasing the electron-hole recombination probability in the active layer L2 . The energy bandgap of the electron blocking layer may be greater than that of the active layer L2 and/or the first semiconductor layer L1, but is not limited thereto.

In some embodiments, a super lattices layer (SLs) may be further disposed between the active layer L2 and the second semiconductor layer L3 of the light emitting devices LD. The superlattice layer relieves the stress of the active layer L2 and the second semiconductor layer L3 to improve the quality of the light emitting devices LD. For example, the superlattice layer may be formed in a structure in which InGaN and GaN are alternately stacked, but is not limited thereto.

The second semiconductor layer L3 of the light emitting devices LD is disposed on the active layer L2 and may include a semiconductor layer of a different type from that of the first semiconductor layer L1 . In an embodiment, the second semiconductor layer L3 of the light emitting devices LD may include at least one n-type semiconductor layer. For example, the second semiconductor layer L3 of the light emitting devices LD includes a semiconductor material such as GaN, InGaN, InAlGaN, AlGaN, or AlN, and includes a second conductive dopant (eg, Si, Ge, Sn, etc.) Alternatively, it may be an n-type semiconductor layer doped with an n-type dopant. For example, the second semiconductor layer L3 of the light emitting devices LD may include a GaN semiconductor material doped with a second conductive dopant (or an n-type dopant). However, the material constituting the second semiconductor layer L3 of the light emitting devices LD is not limited thereto, and various materials may be used to form the second semiconductor layer L3 of the light emitting devices LD. .

The porous area PA may be provided on the second semiconductor layer L3 of the light emitting area EA. For example, the porous area PA may be directly formed on the second semiconductor layer L3 of the light emitting area EA. The porous region PA may include the same material as the second semiconductor layer L3 , but is not limited thereto.

The porous region PA may include a porous layer LP. The porous layer LP of the light emitting devices LD may include the same material as the second semiconductor layer L3 , but is not limited thereto. For example, the porous layer LP of the light emitting devices LD may include at least one n-type semiconductor layer. For example, the porous layer LP of the light emitting devices LD includes a semiconductor material such as GaN, InGaN, InAlGaN, AlGaN, or AlN, and a dopant (or n) having a second conductivity such as Si, Ge, Sn, or the like. type dopant) may be a doped n-type semiconductor layer. For example, the porous layer LP of the light emitting devices LD may include a GaN semiconductor material doped with a second conductive dopant (or an n-type dopant). However, the material constituting the porous layer LP of the light emitting devices LD is not limited thereto, and various materials may be used to form the porous layer LP of the light emitting devices LD.

The porous region PA may include a plurality of pores P present in the porous layer LP. The pores (P) may be nanoscale pores (P) formed through electrochemical etching, but is not necessarily limited thereto. A detailed description thereof will be described later with reference to FIG. 8 .

The porous area PA may be provided on the light emitting area EA to scatter light emitted from the light emitting area EA to improve light output efficiency. For example, the refractive index of the porous area PA may be reduced due to the plurality of pores P, and thus light extraction efficiency may be increased. That is, the porous region PA may function as a scattering layer. As such, when the porous region PA is included in the light emitting devices LD, a scattering layer separately provided in the pixel PXL may be omitted, thereby simplifying the manufacturing process and reducing costs. In addition, the porous area PA may be provided between the light emitting area EA and the color conversion layer CCL to be described later to effectively prevent the color conversion layer CCL from being damaged due to heat generation of the light emitting area EA. have.

In an embodiment, the light emitting devices LD and the bank patterns BNP may include the same material. For example, the first semiconductor layer L1 , the active layer L2 , the second semiconductor layer L3 , and/or the porous layer LP of the light emitting devices LD may each have the above-described bank patterns BNP). may include the same material as the first semiconductor layer B1, the active layer B2, the second semiconductor layer B3, and/or the porous layer BP. In this case, each of the first semiconductor layer L1 , the active layer L2 , the second semiconductor layer L3 , and/or the porous layer LP of the light emitting devices LD is the first of the bank patterns BNP. The semiconductor layer B1, the active layer B2, the second semiconductor layer B3, and/or the porous layer BP may be simultaneously formed in the same process. Accordingly, the manufacturing process of the display device may be simplified to secure process economics. A detailed description thereof will be described later with reference to FIG. 12 .

The light emitting devices LD may be disposed on the first electrode ET1 provided on the substrate SUB. For example, the first semiconductor layer L1 of the light emitting devices LD may be disposed on the first electrode ET1 to be electrically connected to the first electrode ET1 . The first electrode ET1 may include a metal or a metal oxide. For example, the first electrode ET1 may include copper (Cu), gold (Au), chromium (Cr), titanium (Ti), aluminum (Al), nickel (Ni), indium tin oxide (ITO), and these It may include an oxide or an alloy, but is not necessarily limited thereto.

In some embodiments, connection electrodes CE1 and CE2 may be further disposed between the substrate SUB and the light emitting devices LD and/or the bank patterns BNP. The connection electrodes CE1 and CE2 are a first connection electrode CE1 provided between the light emitting elements LD and the substrate SUB and a second connection electrode CE1 provided between the bank patterns BNP and the substrate SUB. CE2).

The first connection electrode CE1 may be disposed between the first semiconductor layer L1 of the light emitting devices LD and the first electrode ET1 provided on the substrate SUB. The light emitting devices LD may be electrically connected to the first electrode ET1 provided on the substrate SUB through the first connection electrode CE1 .

The second connection electrode CE2 may include the same material as the first connection electrode CE1 . For example, each of the first and second connection electrodes CE1 and CE2 may include a metal or a metal oxide. For example, each of the first and second connection electrodes CE1 and CE2 may include copper (Cu), gold (Au), chromium (Cr), titanium (Ti), aluminum (Al), nickel (Ni), and indium tin oxide. (ITO) and oxides or alloys thereof, and the like, but is not necessarily limited thereto. The second connection electrode CE2 may be simultaneously formed in the same process as the first connection electrode CE1 , but is not limited thereto.

A hard mask layer HM may be further disposed between the bank patterns BNP and the second connection electrode CE2 . The hard mask layer HM may be disposed between the first semiconductor layer B1 and the second connection electrode CE2 of the bank patterns BNP. The hard mask layer HM may be omitted in some embodiments.

An insulating layer INS may be provided on the surfaces of the light emitting devices LD and/or the bank patterns BNP. The insulating layer INS may be provided on side surfaces of the light emitting devices LD and/or the bank patterns BNP. The insulating layer INS may prevent an electrical short that may occur when the active layer L2 of the light emitting devices LD comes into contact with conductive materials other than the first and second semiconductor layers L1 and L3 . In addition, the insulating layer INS may minimize surface defects of the light emitting devices LD, thereby improving lifespan and luminous efficiency of the light emitting devices LD.

The insulating layer INS covers side surfaces of the light emitting devices LD and/or the bank patterns BNP, but may be partially removed to expose top surfaces of the light emitting devices LD and/or the bank patterns BNP. can For example, the insulating layer INS may cover side surfaces of the light emitting devices LD, but may be partially removed to expose the porous area PA of the light emitting devices LD, that is, the porous layer LP.

The insulating layer INS includes silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), aluminum oxide (AlOx), aluminum nitride (AlNx), zirconium oxide (ZrOx), and hafnium. Oxide (HfOx) or titanium oxide (TiOx) may be included, but is not necessarily limited thereto.

A second electrode ET2 may be disposed on the light emitting devices LD. The second electrode ET2 may be directly disposed on top surfaces of the light emitting devices LD exposed by the insulating layer INS. For example, the second electrode ET2 may be directly disposed on the porous area PA of the light emitting devices LD, that is, the porous layer LP. The second electrode ET2 may be disposed across the first to third pixels PXL1 , PXL2 , and PXL3 .

The second electrode ET2 may be formed of various transparent conductive materials. For example, the second electrode ET2 may include indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), zinc tin oxide ( ZTO), or at least one of various transparent conductive materials including gallium tin oxide (GTO), and may be implemented to be substantially transparent or translucent to satisfy a predetermined light transmittance. Accordingly, the light emitted from the light emitting devices LD may pass through the second electrode ET2 and be emitted to the outside of the display panel PNL.

A color conversion layer CCL may be disposed on the light emitting devices LD. The color conversion layer CCL may be disposed between the bank patterns BNP. That is, the color conversion layer CCL may be provided in a space or an opening defined by the bank patterns BNP.

The color conversion layer CCL may include quantum dots as a color conversion material that converts light emitted from the light emitting devices LD of each pixel PXL into light of a specific color. For example, the color conversion layer CCL may include a plurality of quantum dots dispersed in a predetermined matrix material such as a base resin.

In an embodiment, the first to third pixels PXL1 , PXL2 , and PXL3 may include light emitting devices LD that emit light of the same color as each other. For example, the first to third pixels PXL1 , PXL2 , and PXL3 may include light emitting devices LD emitting a third color (or blue). The color conversion layer CCL may include quantum dots that convert blue light emitted from the light emitting device LD into white light. For example, the color conversion layer CCL may include a first quantum dot that converts blue light emitted from the blue light emitting device into red light and a second quantum dot that converts blue light into green light. However, it is not necessarily limited thereto. When a quantum dot is used as a color conversion material, the absorption coefficient of the quantum dot may be increased by injecting blue light having a relatively short wavelength among the visible light region into the quantum dot. Accordingly, the light efficiency finally emitted from the pixels PXL may be improved and excellent color reproducibility may be secured. In addition, the light emitting unit EMU of the first to third pixels PXL1 , PXL2 , and PXL3 is configured using the light emitting devices LD (eg, blue light emitting devices) of the same color, thereby manufacturing the display device. efficiency can be increased. However, the present invention is not limited thereto, and the first to third pixels PXL1 , PXL2 , and PXL3 may include light emitting devices LD that emit light of different colors. For example, the first pixel PXL1 includes a first color (or red) light emitting device LD, and the second pixel PXL2 includes a second color (or green) light emitting device LD. In addition, the third pixel PXL3 may include a third color (or blue) light emitting device LD.

In some embodiments, a reflective layer RF may be disposed between the bank patterns BNP and the color conversion layer CCL. The reflective layer RF may reflect light emitted from the light emitting devices LD to improve light output efficiency of the display panel PNL. In addition, the reflective layer RF may be disposed on side surfaces of the bank patterns BNP to prevent color mixing between adjacent pixels PXL. The material of the reflective layer RF is not particularly limited, and may include various reflective materials.

A passivation layer PSV may be disposed on the color conversion layer CCL. The passivation layer PSV may directly cover the color conversion layer CCL. The passivation layer PSV may be disposed over the first to third pixels PXL1 , PXL2 , and PXL3 . The passivation layer PSV may prevent impurities such as moisture or air from penetrating from the outside to damage or contaminate the color conversion layer CCL. One surface of the passivation layer PSV may be in contact with the color conversion layer CCL, and the other surface of the passivation layer PSV may be in contact with a color filter layer CFL, which will be described later.

The protective layer (PSV) is made of acrylates resin, epoxy resin, phenolic resin, polyamides resin, polyimides rein, polyester resin ( polyesters resin), polyphenylenesulfides resin, or an organic material such as benzocyclobutene (BCB), but is not necessarily limited thereto.

In some embodiments, the passivation layer PSV may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), aluminum oxide (AlOx), aluminum nitride (AlNx), zirconium. It may include an inorganic material such as oxide (ZrOx), hafnium oxide (HfOx), or titanium oxide (TiOx).

A color filter layer CFL may be disposed on the passivation layer PVS. The color filter layer CFL may be disposed between the bank patterns BNP. The color filter layer CFL may include color filters CF1 , CF2 , and CF3 matching the color of each pixel PXL. A full-color image may be displayed by disposing color filters CF1 , CF2 , and CF3 corresponding to colors of the first to third pixels PXL1 , PXL2 , and PXL3 respectively.

The color filter layer CFL is disposed in the first pixel PXL1 and is disposed in the first color filter CF1 and the second pixel PXL2 that selectively transmits light emitted from the first pixel PXL1 and the second pixel A second color filter CF2 that selectively transmits the light emitted from the PXL2, and a third color filter that is disposed on the third pixel PXL3 and selectively transmits the light emitted from the third pixel PXL3 ( CF3).

In an embodiment, the first color filter CF1 , the second color filter CF2 , and the third color filter CF3 may be a red color filter, a green color filter, and a blue color filter, respectively, but are not necessarily limited thereto. not. Hereinafter, when referring to any color filter among the first color filter CF1 , the second color filter CF2 , and the third color filter CF3 , or generically referring to two or more types of color filters, “color filter” (CF)” or “color filters (CF)”.

The first color filter CF1 may overlap the light emitting element LD and the color conversion layer CCL of the first pixel PXL1 in the third direction (Z-axis direction). The first color filter CF1 may include a color filter material that selectively transmits light of a first color (or red). For example, when the first pixel PXL1 is a red pixel, the first color filter CF1 may include a red color filter material.

The second color filter CF2 may overlap the light emitting element LD and the color conversion layer CCL of the second pixel PXL2 in the third direction (Z-axis direction). The second color filter CF2 may include a color filter material that selectively transmits light of the second color (or green). For example, when the second pixel PXL2 is a green pixel, the second color filter CF2 may include a green color filter material.

The third color filter CF3 may overlap the light emitting element LD and the color conversion layer CCL of the third pixel PXL3 in the third direction (Z-axis direction). The third color filter CF3 may include a color filter material that selectively transmits light of a third color (or blue). For example, when the third pixel PXL3 is a blue pixel, the third color filter CF3 may include a blue color filter material.

According to the above-described exemplary embodiment, the manufacturing process of the display device may be simplified by simultaneously forming the light emitting elements LD and the bank patterns BNP. In addition, the porous area PA embedded in the light emitting devices LD scatters light emitted from the light emitting area EA, thereby improving light output efficiency. Accordingly, since the scattering layer separately provided in the pixel PXL may be omitted, the manufacturing process may be simplified and cost may be reduced. In addition, as the porous area PA is provided between the light-emitting area EA and the color conversion layer CCL, it is possible to effectively prevent the color conversion layer CCL from being damaged due to heat generation of the light-emitting area EA. .

Hereinafter, another embodiment will be described. In the following embodiments, the same components as those already described are referred to by the same reference numerals, and repeated descriptions will be omitted or simplified.

5 is a cross-sectional view illustrating a pixel according to another exemplary embodiment.

Referring to FIG. 5 , the color conversion layer CCL according to the present exemplary embodiment includes a first color conversion layer CC1 disposed on the first pixel PXL1 and a second color conversion layer disposed on the second pixel PXL2. It is distinguished from the exemplary embodiment of FIGS. 1 to 4 in that it includes CC2 and the light transmitting layer LS disposed on the third pixel PXL3.

In an embodiment, the first to third pixels PXL1 , PXL2 , and PXL3 may include light emitting devices LD that emit light of the same color as each other. For example, the first to third pixels PXL1 , PXL2 , and PXL3 may include light emitting devices LD that emit light of a third color (or blue). A color conversion layer CCL including color conversion particles may be disposed on the first to third pixels PXL1 , PXL2 , and PXL3 , so that a full-color image may be displayed.

When the first pixel PXL1 is a red pixel, the first color conversion layer CC1 may include a first quantum dot that converts blue light emitted from the blue light emitting device into red light. The first quantum dot may absorb blue light and shift a wavelength according to an energy transition to emit red light. Meanwhile, when the first pixel PXL1 is a pixel of a different color, the first color conversion layer CC1 may include a first quantum dot corresponding to the color of the first pixel PXL1 .

When the second pixel PXL2 is a green pixel, the second color conversion layer CC2 may include a second quantum dot that converts blue light emitted from the blue light emitting device into green light. The second quantum dot may absorb blue light and shift a wavelength according to energy transition to emit green light. Meanwhile, when the second pixel PXL2 is a pixel of a different color, the second color conversion layer CC2 may include a second quantum dot corresponding to the color of the second pixel PXL2 .

Absorption coefficients of the first quantum dot and the second quantum dot may be increased by respectively injecting blue light having a relatively short wavelength in the visible light region to the first quantum dot and the second quantum dot. Accordingly, the light efficiency finally emitted from the first pixel PXL1 and the second pixel PXL2 may be improved, and excellent color reproducibility may be secured. In addition, the light emitting unit EMU of the first to third pixels PXL1 , PXL2 , and PXL3 is configured using the light emitting devices LD (eg, blue light emitting devices) of the same color, thereby manufacturing the display device. efficiency can be increased.

The light transmitting layer LS may be provided to efficiently use the light of the third color (or blue) emitted from the light emitting device LD. For example, when the light emitting device LD is a blue light emitting device emitting blue light and the third pixel PXL3 is a blue pixel, the light transmitting layer LS efficiently transmits light emitted from the light emitting device LD. It may include, but is not limited to, light scattering particles for use. In some embodiments, the light transmitting layer LS may be omitted or a transparent polymer may be provided instead of the light transmitting layer LS.

6 is a cross-sectional view illustrating a pixel according to another exemplary embodiment.

Referring to FIG. 6 , the first to third pixels PXL1 , PXL2 and PXL3 according to the present exemplary embodiment include first to third light emitting devices LD1 , LD2 and LD3, respectively, and a color conversion layer ( It is distinguished from the embodiment of FIGS. 1 to 5 in that CCL of FIG. 3 and the like) and bank patterns (BNP of FIG. 3 etc.) are omitted.

Specifically, the light emitting devices LD include the first light emitting device LD1 disposed in the first pixel PXL1 , the second light emitting device LD2 disposed in the second pixel PXL2 , and the third pixel PXL3 . ) may include a third light emitting device LD3 disposed in the .

Each of the first to third light emitting devices LD1 , LD2 , and LD3 may include a light emitting area EA and a porous area PA. The light emitting area EA may be provided between the substrate SUB and the porous area PA.

The light emitting area EA of each of the first to third light emitting devices LD1 , LD2 , and LD3 may emit light of different colors. For example, the first light emitting device LD1 includes a light emitting area EA that emits a first color (or red), and the second light emitting device LD2 emits a second color (or green). light emitting area EA, and the third light emitting device LD3 may include a light emitting area EA emitting a third color (or blue). As described above, since the first to third light emitting devices LD1 , LD2 , and LD3 each include the light emitting area EA emitting light of different colors, a full color image may be displayed. Accordingly, since the color conversion layer and/or the color filter layer separately provided in each of the first to third pixels PXL1, PXL2, and PXL3 may be omitted, the manufacturing process may be simplified and cost may be reduced.

The light emitting area EA may include a first semiconductor layer L1 , a second semiconductor layer L3 , and an active layer L2 interposed between the first and second semiconductor layers L1 and L3 . For example, the first semiconductor layer L1 , the active layer L2 , and the second semiconductor layer L3 of each of the first to third light emitting devices LD1 , LD2 , and LD3 are disposed on the substrate SUB in the third direction. (Z-axis direction) may be sequentially stacked.

The first semiconductor layer L1 of each of the first to third light emitting devices LD1 , LD2 , and LD3 may include at least one p-type semiconductor layer. For example, the first semiconductor layer L1 includes a semiconductor material such as GaN, InGaN, InAlGaN, AlGaN, AlN, AlGaAs, GaAsP, AlGaInP, or GaP, and includes a material such as Mg, Zn, Ca, Sr, Ba, etc. A p-type semiconductor layer doped with a dopant of one conductivity (or a p-type dopant) may be included. As an example, the first semiconductor layer L1 may include a GaN semiconductor material doped with a first conductive dopant (or a p-type dopant), but is not limited thereto. In addition, various materials may be used in the first semiconductor layer ( L1) can be configured.

The active layer L2 of each of the first to third light emitting devices LD1 , LD2 , and LD3 may be disposed between the first semiconductor layer L1 and the second semiconductor layer L3 , respectively. The active layer L2 may include any one of a single well structure, a multi-well structure, a single quantum well structure, a multi quantum well (MQW) structure, a quantum dot structure, or a quantum wire structure, but is limited thereto. it's not going to be The active layer L2 may include GaN, InGaN, InAlGaN, AlGaN, AlN, AlGaAs, GaAsP, AlGaInP, or GaP. In addition, various materials may constitute the active layer L2 .

When a predetermined signal (or voltage) is applied to each end of the first to third light emitting devices LD1 , LD2 and LD3 , the active layer L2 of each of the first to third light emitting devices LD1 , LD2 and LD3 is applied. ), the light emitting device LD emits light as the electron-hole pairs combine. By controlling the light emission of each light emitting element LD using this principle, the light emitting element LD can be used as a light source of various light emitting devices including the pixel PXL of a display device.

In some embodiments, an electron blocking layer (EBL) may be further disposed between the active layer L2 and the first semiconductor layer L1 . The electron blocking layer may block the flow of electrons supplied from the second semiconductor layer L3 from escaping to the first semiconductor layer L1 , thereby increasing the electron-hole recombination probability in the active layer L2 . The energy bandgap of the electron blocking layer may be greater than that of the active layer L2 and/or the first semiconductor layer L1, but is not limited thereto.

According to an embodiment, a super lattices layer (SLs) may be further disposed between the active layer L2 and the second semiconductor layer L3 , respectively. The superlattice layer relieves the stress of the active layer L2 and the second semiconductor layer L3 to improve the quality of the light emitting devices LD. The superlattice layer may be formed in a structure in which InGaN and GaN are alternately stacked, but is not limited thereto.

The second semiconductor layer L3 of each of the first to third light emitting devices LD1 , LD2 , and LD3 is disposed on the active layer L2 and includes a semiconductor layer of a different type from that of the first semiconductor layer L1 . can In an embodiment, the second semiconductor layer L3 may include at least one n-type semiconductor layer. For example, the second semiconductor layer L3 includes a semiconductor material such as GaN, InGaN, InAlGaN, AlGaN, AlN, AlGaAs, GaAsP, AlGaInP, or GaP, and a second conductive dopant such as Si, Ge, Sn, or the like. (or an n-type dopant) may be a doped n-type semiconductor layer. For example, the second semiconductor layer L3 may include a GaN semiconductor material doped with a second conductive dopant (or an n-type dopant). However, the material constituting the second semiconductor layer L3 is not limited thereto, and other materials may be used to form the second semiconductor layer L3 of the light emitting devices LD.

The porous area PA of each of the first to third light emitting devices LD1 , LD2 , and LD3 may be provided on the second semiconductor layer L3 of the light emitting area EA. For example, the porous area PA may be directly formed on the second semiconductor layer L3 of the light emitting area EA. The porous region PA may include the same material as the second semiconductor layer L3 , but is not limited thereto.

The porous region PA may include a porous layer LP and a plurality of pores P present in the porous layer LP. The porous area PA may be provided on the light emitting area EA to scatter light emitted from the light emitting area EA to improve light output efficiency. For example, the refractive index of the porous area PA may be reduced due to the plurality of pores P, and thus light extraction efficiency may be increased. That is, the porous region PA may function as a scattering layer. As described above, when the porous region PA is included in the light emitting devices LD, the scattering layer separately provided in the pixel PXL may be omitted, thereby simplifying the manufacturing process and reducing costs. like a bar Since the porous layer LP and the pores P including the porous region PA have been described in detail with reference to FIG. 3 and the like, overlapping content will be omitted.

The first to third light emitting devices LD1 , LD2 , and LD3 may be respectively disposed on the first electrode ET1 provided on the substrate SUB. For example, the first semiconductor layer L1 of the light emitting devices LD may be disposed on the first electrode ET1 to be electrically connected to the first electrode ET1 .

In some embodiments, a connection electrode CE may be further disposed between the substrate SUB and the light emitting devices LD. The connection electrode CE may be disposed between the first semiconductor layer L1 of the light emitting devices LD and the first electrode ET1 provided on the substrate SUB. The light emitting devices LD may be electrically connected to the first electrode ET1 provided on the substrate SUB through the connection electrode CE. The connection electrode CE may include a metal or a metal oxide. For example, the connection electrode CE may include copper (Cu), gold (Au), chromium (Cr), titanium (Ti), aluminum (Al), nickel (Ni), indium tin oxide (ITO), and oxides thereof or It may include an alloy and the like, but is not necessarily limited thereto.

An insulating layer INS and a reflective layer RF may be disposed between the first to third light emitting devices LD1 , LD2 , and LD3 . The insulating layer INS may be provided between the light emitting devices LD and the reflective layer RF.

The insulating layer INS may be provided on the surfaces of the light emitting devices LD. The insulating layer INS may be provided on side surfaces of the light emitting devices LD. The insulating layer INS may prevent an electrical short that may occur when the active layer L2 of the light emitting devices LD comes into contact with conductive materials other than the first and second semiconductor layers L1 and L3 . In addition, the insulating layer INS may minimize surface defects of the light emitting devices LD, thereby improving lifespan and luminous efficiency of the light emitting devices LD.

The insulating layer INS covers side surfaces of the light emitting devices LD, but may be partially removed to expose top surfaces of the light emitting devices LD. For example, the insulating layer INS may cover side surfaces of the light emitting devices LD, but may be partially removed to expose one surface of the porous area PA of the light emitting devices LD.

The reflective layer RF may be disposed between the light emitting devices LD. The reflective layer RF may be disposed at a boundary between the first to third pixels PXL1 , PXL2 , and PXL3 on the substrate SUB. The reflective layer RF may be disposed between the light emitting devices LD to reflect light emitted from the light emitting devices LD to improve light output efficiency of the display panel PNL. Also, the reflective layer RF is disposed at the boundary between the first to third pixels PXL1 , PXL2 , and PXL3 to prevent color mixing between adjacent pixels PXL.

A second electrode ET2 may be disposed on the first to third light emitting devices LD1 , LD2 , and LD3 , respectively. The second electrode ET2 may be directly disposed on top surfaces of the light emitting devices LD exposed by the insulating layer INS. For example, the second electrode ET2 may be directly disposed on the porous area PA of the light emitting devices LD, that is, the porous layer LP. The second electrode ET2 may be disposed in the first to third pixels PXL1 , PXL2 , and PXL3 , respectively.

According to the above-described embodiment, as the first to third light emitting devices LD1 , LD2 , and LD3 each include the light emitting area EA emitting light of different colors, a color conversion layer and/ Alternatively, since the color filter layer may be omitted, the manufacturing process may be simplified and cost may be reduced. In addition, as described above, the porous region PA is embedded in the light emitting devices LD to improve light output efficiency of the display panel PNL and to simplify the manufacturing process.

Subsequently, a method of manufacturing the display device according to the above-described exemplary embodiment will be described.

7 to 16 are cross-sectional views of a process step-by-step process of a method of manufacturing a display device according to an exemplary embodiment. 7 to 16 are cross-sectional views illustrating a method of manufacturing the display device of FIG. 3 . Components substantially the same as those of FIG. 3 are denoted by the same reference numerals, and detailed reference numerals are omitted.

Referring to FIG. 7 , first, a base layer BSL is prepared, and a semiconductor layer PL′ is formed on the base layer BSL. The base layer BSL may use a sapphire substrate, a silicon (Si) substrate, or a silicon carbide (SiC) substrate, but is not limited thereto, and a single crystal substrate having a lattice structure may be used. The base layer BSL may further include a buffer layer formed on one surface.

The semiconductor layer PL′ may include at least one n-type semiconductor layer. For example, the semiconductor layer PL′ includes a semiconductor material such as GaN, InGaN, InAlGaN, AlGaN, or AlN, and is doped with a second conductive dopant (or n-type dopant) such as Si, Ge, Sn, etc. It may be an n-type semiconductor layer. For example, the semiconductor layer PL′ may include a GaN semiconductor material doped with a second conductive dopant (or an n-type dopant). However, the material constituting the semiconductor layer PL′ is not limited thereto, and the semiconductor layer PL′ may be formed of various other materials.

Referring to FIG. 8 , the porous layer PL is formed by etching the semiconductor layer PL′. For example, the semiconductor layer PL′ may be electrochemically etched to form nanoscale pores P of the porous layer PL. During the electrochemical etching of the semiconductor layer PL′, the size, shape, and distribution of the pores P may be variously adjusted according to an etchant, a voltage, and/or a doping concentration.

Referring to FIG. 9 , the light-emitting laminates 11 , 12 , and 13 are formed on the porous layer PL. The light-emitting laminates 11 , 12 , and 13 may be formed by growing seed crystals by an epitaxial method. In this case, since the stress of the light emitting stacks 11 , 12 , and 13 may be relieved by the porous structure of the porous layer PL, the quality of the light emitting devices LD may be improved.

In some embodiments, the light emitting stacks 11 , 12 , and 13 may be formed by metal organic chemical vapor deposition (MOCVD). However, the present invention is not necessarily limited thereto, and the light-emitting laminates 11 , 12 , and 13 may be formed by electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), or plasma laser deposition (plasma). It may be formed by various methods such as laser deposition (PLD), dual-type thermal evaporation, sputtering, or metal organic chemical vapor deposition (MOCVD).

The light emitting stacks 11 , 12 , and 13 may include an epitaxially grown first semiconductor layer 11 , an active layer 12 , and a second semiconductor layer 13 .

The second semiconductor layer 13 is provided on the porous layer PL and may be formed of the same material as the porous layer PL. For example, the second semiconductor layer 13 may include at least one n-type semiconductor layer. For example, the second semiconductor layer 13 includes a semiconductor material of any one of GaN, InGaN, InAlGaN, AlGaN, and AlN, and includes a second conductive dopant (or n-type dopant) such as Si, Ge, Sn, or the like. may be a doped n-type semiconductor layer. For example, the second semiconductor layer 13 may include a GaN semiconductor material doped with a second conductive dopant (or an n-type dopant). However, the material constituting the second semiconductor layer 13 is not limited thereto, and in addition, the second semiconductor layer 13 may be formed of various materials. The second semiconductor layer 13 may be directly formed on the porous layer PL, but is not limited thereto.

The active layer 12 is provided on the second semiconductor layer 13, and has any one of a single well structure, a multi-well structure, a single quantum well structure, a multi quantum well (MQW) structure, a quantum dot structure, or a quantum wire structure. It may include one structure, but is not necessarily limited thereto. The active layer 12 may include GaN, InGaN, InAlGaN, AlGaN, or AlN, and in addition, various materials may constitute the active layer 12 of the bank patterns active layer 12 .

The first semiconductor layer 11 is provided on the active layer 12 and may include at least one p-type semiconductor layer. For example, the first semiconductor layer 11 includes a semiconductor material such as GaN, InGaN, InAlGaN, AlGaN, or AlN, and a dopant (or p-type) having a first conductivity such as Mg, Zn, Ca, Sr, Ba, or the like. dopant) may include a doped p-type semiconductor layer. As an example, the first semiconductor layer 11 may include a GaN semiconductor material doped with a first conductive dopant (or a p-type dopant), but is not necessarily limited thereto. In addition, various materials may be used in the first semiconductor layer ( 11) can be configured.

Referring to FIG. 10 , the light emitting laminates 11 , 12 , and 13 and the porous layer PL are then bonded to the substrate SUB. The substrate SUB is a driving substrate including circuit elements including transistors constituting the pixel circuit (PXC of FIG. 2 ) of each pixel PXL, and includes a first electrode ET1 , a connection electrode layer CEL, and/ Alternatively, a hard mask layer HM may be provided.

The first electrode ET1 may be formed at a position where light emitting devices LD, which will be described later, are provided. The connection electrode layer CEL may be formed over the entire surface of the substrate SUB, but is not limited thereto. The hard mask layer HM may be formed at a position where the bank patterns BNP will be provided to form a lower end of the bank patterns BNP, which will be described later. However, the present invention is not necessarily limited thereto, and the hard mask layer HM may be omitted in some embodiments.

The first semiconductor layer 11 of the light emitting stacks 11 , 12 , and 13 may be coupled to the first electrode ET1 formed on the substrate SUB. The first semiconductor layer 11 may be easily bonded to the first electrode ET1 provided on the substrate SUB through the connection electrode layer CEL. The connection electrode layer CEL may be formed of a metal or a metal oxide.

After the light-emitting laminates 11 , 12 , and 13 and the porous layer PL are bonded to the substrate SUB, the base layer BSL may be separated from one surface of the porous layer PL.

Referring to FIG. 11 , first and second mask layers MK1 and MK2 are formed on the light emitting stacks 11 , 12 , and 13 and the porous layer PL. The first and second mask layers MK1 and MK2 may be directly formed on the porous layer PL, but are not limited thereto.

The first mask layer MK1 may be partially formed at a position where light emitting devices LD and bank patterns BNP, which will be described later, are provided. The second mask layer MK2 may be formed on the first mask layer MK1 . The second mask layer MK2 may be selectively formed at positions where the bank patterns BNP are to be provided.

The first mask layer MK1 and the second mask layer MK2 may be formed of different materials. For example, the first mask layer MK1 may include silicon oxide (SiOx) and the second mask layer MK2 may include nickel (Ni), but is not limited thereto.

Referring to FIG. 12 , the light emitting stacks 11 , 12 , and 13 and the porous layer PL are patterned to form light emitting devices LD and bank patterns BNP. The bank patterns BNP may be formed at a boundary between the first to third pixels PXL1 , PXL2 , and PXL3 . The light emitting devices LD may be respectively formed in the first to third pixels PXL1 , PXL2 , and PXL3 between the bank patterns BNP.

In the process of patterning the light emitting stacks 11 , 12 , and 13 and the porous layer PL, the first semiconductor layer 11 is formed of the first semiconductor layer L1 and the bank patterns BNP of the light emitting devices LD. of the first semiconductor layer B1, the active layer 12 is separated into the active layer L2 of the light emitting devices LD and the active layer B2 of the bank patterns BNP, ) may be separated into the second semiconductor layer L3 of the light emitting devices LD and the second semiconductor layer B3 of the bank patterns BNP. Similarly, the porous layer PL may be separated into a porous layer LP of the light emitting devices LD and a porous layer BP of the bank patterns BNP. The porous layer LP of the light emitting devices LD may constitute the porous area PA of the light emitting devices LD. The first semiconductor layer L1 , the active layer L2 , and the second semiconductor layer L3 of the light emitting devices LD may constitute the light emitting area EA of the light emitting devices LD.

In the process of patterning the light emitting stacks 11 , 12 , and 13 and the porous layer PL, light emission having different thicknesses is used by using the difference in etch selectivity between the first mask layer MK1 and the second mask layer MK2 . The devices LD and the bank patterns BNP may be simultaneously formed.

In some embodiments, the connection electrode layer CEL may be separated into the first connection electrode CE1 and the second connection electrode CE2 in the process of patterning the light emitting laminates 11 , 12 , 13 and the porous layer PL. can For example, the connection electrode layer CEL may be separated into a first connection electrode CE1 under the light emitting elements LD and a second connection electrode CE2 under the hard mask layer HM.

Referring to FIG. 13 , an insulating layer INS is formed on the light emitting devices LD and/or the bank patterns BNP. The insulating layer INS may be partially formed on side surfaces of the light emitting devices LD and/or the bank patterns BNP. After the insulating layer INS is formed across the first to third pixels PXL1 , PXL2 , and PXL3 , the insulating layer INS may be partially removed to expose top surfaces of the light emitting devices LD and/or the bank patterns BNP. In an embodiment, when the light emitting devices LD and/or the bank patterns BNP are formed in the third direction (Z-axis direction), that is, perpendicular to the substrate SUB, the insulating layer INS is etched separately. The insulating layer INS provided on the upper surfaces of the light emitting devices LD and/or the bank patterns BNP may be etched without a mask of .

Referring to FIG. 14 , a second electrode ET2 is formed on the light emitting devices LD. The second electrode ET2 may be directly formed on the upper surfaces of the light emitting devices LD exposed by the insulating layer INS and may be in contact with the porous layer LP of the light emitting devices LD.

The second electrode ET2 may be formed across the first to third pixels PXL1 , PXL2 , and PXL3 . That is, the second electrode ET2 may be formed to at least partially cover the bank patterns BNP, but is not limited thereto.

The second electrode ET2 may be formed of various transparent conductive materials. For example, the second electrode ET2 may include indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), zinc tin oxide ( ZTO), or formed of at least one of various transparent conductive materials including gallium tin oxide (GTO), and may be implemented to be substantially transparent or translucent to satisfy a predetermined light transmittance. Accordingly, the light emitted from the light emitting devices LD may pass through the second electrode ET2 and be emitted to the outside of the display panel PNL.

Referring to FIG. 15 , a reflective layer RF is then formed on the bank patterns BNP. The reflective layer RF may be partially formed on side surfaces of the bank patterns BNP. The reflective layer RF may reflect light emitted from the light emitting devices LD to improve light output efficiency of the display panel PNL. In addition, the reflective layer RF may be disposed on side surfaces of the bank patterns BNP to prevent color mixing between adjacent pixels PXL. The material of the reflective layer RF is not particularly limited and may be formed of various reflective materials.

Referring to FIG. 16 , a color conversion layer CCL is then formed on the light emitting devices LD. The color conversion layer CCL may be formed between the bank patterns BNP. That is, the color conversion layer CCL may be formed in a space or an opening defined by the bank patterns BNP. The color conversion layer CCL may include quantum dots as a color conversion material that converts light emitted from the light emitting devices LD of each pixel PXL into light of a specific color. Since the color conversion layer CCL has been described in detail with reference to FIG. 3 and the like, overlapping content will be omitted.

Subsequently, the display device of FIG. 3 may be completed by forming the passivation layer PSV1 and the color filter layer CFL on the color conversion layer CCL. The passivation layer PSV may be formed over the first to third pixels PXL1 , PXL2 , and PXL3 . The passivation layer PSV may directly cover the color conversion layer CCL. The passivation layer PSV may prevent impurities such as moisture or air from penetrating from the outside to damage or contaminate the color conversion layer CCL.

The color filter layer CFL may include color filters CF1 , CF2 , and CF3 matching the color of each pixel PXL. Since the color filter layer CFL has been described in detail with reference to FIG. 3 and the like, overlapping content will be omitted.

According to the above-described exemplary embodiment, the manufacturing process of the display device may be simplified by simultaneously forming the light emitting elements LD and the bank patterns BNP. In addition, as described above, the porous region PA is embedded in the light emitting devices LD to improve light output efficiency of the display panel PNL and to simplify the manufacturing process.

Hereinafter, another embodiment will be described. In the following embodiments, the same components as those already described are referred to by the same reference numerals, and repeated descriptions will be omitted or simplified.

17 to 26 are cross-sectional views illustrating steps of a method of manufacturing a display device according to another exemplary embodiment. 17 to 26 are cross-sectional views illustrating a method of manufacturing the display device of FIG. 6 . Components substantially the same as those of FIG. 6 are denoted by the same reference numerals and detailed reference numerals are omitted.

Referring to FIG. 17 , first, a base layer BSL is prepared, and a semiconductor layer PL′ is formed on the base layer BSL. Since the base layer BSL and the semiconductor layer PL' have been described in detail with reference to FIG. 7 , overlapping content will be omitted.

Referring to FIG. 18 , the semiconductor layer PL′ is then patterned to form a semiconductor layer PL′ in each of the first to third pixels PXL1 , PXL2 , and PXL3 . The semiconductor layer PL′ of the first to third pixels PXL1 , PXL2 , and PXL3 may be formed at a position where light emitting devices LD, which will be described later, are provided, respectively.

Referring to FIG. 19 , a porous layer LP is formed by at least partially etching the semiconductor layer PL′ of each of the first to third pixels PXL1 , PXL2 , and PXL3 . For example, the semiconductor layer PL′ may be electrochemically etched to form nanoscale pores P of the porous layer PL. During the electrochemical etching of the semiconductor layer PL′, the size, shape, and distribution of the pores P may be variously adjusted according to an etchant, a voltage, and/or a doping concentration. The porous layer LP of each of the first to third pixels PXL1, PXL2, and PXL3 may constitute a porous area PA of each of the first to third light emitting devices LD1, LD2, and LD3 to be described later. . The unetched region of the semiconductor layer PL' is the second semiconductor layer L3, and the first to third light emitting devices LD1, together with the first semiconductor layer L1 and the active layer L2 formed in a subsequent process. Each of LD2 and LD3 may constitute an emission area EA.

Referring to FIG. 20 , a first semiconductor layer L1 and an active layer L2 are formed on the porous layer LP and the second semiconductor layer L3 of each of the first to third pixels PXL1 , PXL2 , and PXL3 . to form The first semiconductor layer L1 and/or the active layer L2 of each of the first to third pixels PXL1 , PXL2 , and PXL3 may be formed by growing a seed crystal by an epitaxial method.

The first semiconductor layer L1 , the active layer L2 , and the second semiconductor layer L3 provided on the porous layer LP of each of the first to third pixels PXL1 , PXL2 , and PXL3 is a light emitting stack. , may constitute the emission area EA of each of the first to third pixels PXL1 , PXL2 , and PXL3 . As described above, the light emitting area EA of each of the first to third light emitting devices LD1 , LD2 , and LD3 may be formed to emit light of different colors. For example, the light emitting area EA of the first light emitting device LD1 emits a first color (or red), and the light emitting area EA of the second light emitting device LD2 emits a second color (or, red). green), and the light emitting area EA of the third light emitting device LD3 may emit a third color (or blue). As described above, since the first to third light emitting devices LD1 , LD2 , and LD3 each include the light emitting area EA emitting light of different colors, a full color image may be displayed. Accordingly, since the color conversion layer and/or the color filter layer separately provided in each of the first to third pixels PXL1, PXL2, and PXL3 may be omitted, it is possible to simplify the manufacturing process and reduce costs, as described above. same.

Referring to FIG. 21 , a planarization layer PN is then formed between the first to third light emitting devices LD1 , LD2 , and LD3 . The planarization layer PN may be formed at a boundary between the first to third pixels PXL1 , PXL2 , and PXL3 . The planarization layer PN may be formed between the light emitting devices LD and serve to planarize the steps of the light emitting devices LD. The planarization layer PN may be formed on side surfaces of the light emitting devices LD. That is, the planarization layer PN may cover side surfaces of the light emitting devices LD, but expose top surfaces of the light emitting devices LD.

In one embodiment, the planarization layer (PN) is an acrylic resin (acrylates resin), epoxy resin (epoxy resin), phenolic resin (phenolic resin), polyamide-based resin (polyamides resin), polyimide-based resin (polyimides rein), It may be formed of an organic material such as polyesters resin, polyphenylenesulfides resin, or benzocyclobutene (BCB), but is not necessarily limited thereto.

In some embodiments, the planarization layer PN may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), aluminum oxide (AlOx), aluminum nitride (AlNx), zirconium. It may be formed of an inorganic material such as oxide (ZrOx), hafnium oxide (HfOx), or titanium oxide (TiOx).

Referring to FIG. 22 , the connection electrode CE is then formed on the first to third light emitting devices LD1 , LD2 , and LD3 and the planarization layer PN. The connection electrode CE may be formed across the first to third pixels PXL1 , PXL2 , and PXL3 . The connection electrode CE may be formed of a metal or a metal oxide. For example, the connection electrode CE may include copper (Cu), gold (Au), chromium (Cr), titanium (Ti), aluminum (Al), nickel (Ni), indium tin oxide (ITO), and oxides thereof or It may be formed of an alloy or the like, but is not necessarily limited thereto.

Referring to FIG. 23 , the first to third light emitting devices LD1 , LD2 , and LD3 are coupled to the substrate SUB. The substrate SUB is a driving substrate including circuit elements including transistors constituting the pixel circuit (PXC of FIG. 2 ) of each pixel PXL, and a first electrode ET1 may be provided.

The first semiconductor layer L1 of each of the first to third light emitting devices LD1 , LD2 , and LD3 may be coupled to the first electrode ET1 formed on the substrate SUB. The first semiconductor layer L1 may be easily bonded to the first electrode ET1 provided on the substrate SUB through the connection electrode CE. After bonding the first to third light emitting devices LD1 , LD2 , and LD3 to the substrate SUB, the base layer BSL may be separated from one surface of the porous layer LP.

Referring to FIG. 24 , a second electrode layer ET2 ′ is formed on the first to third light emitting devices LD1 , LD2 , and LD3 . The second electrode layer ET2 ′ is directly formed on the upper surfaces of the light emitting devices LD exposed by the planarization layer PN, and thus the porous area PA of the light emitting devices LD, that is, the porous layer LP. can be contacted with The second electrode layer ET2 ′ may be formed over the first to third pixels PXL1 , PXL2 , and PXL3 .

The second electrode layer ET2 ′ may be formed of various transparent conductive materials. For example, the second electrode layer ET2' may include indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), or zinc tin oxide. It is formed of at least one of various transparent conductive materials including (ZTO) or gallium tin oxide (GTO), and may be substantially transparent or translucent to satisfy a predetermined light transmittance.

Referring to FIG. 25 , a second electrode ET2 is formed on each of the first to third light emitting devices LD1 , LD2 and LD3 by patterning the second electrode layer ET2 ′, and a planarization layer PN is formed. to remove

Referring to FIG. 26 , an insulating layer INS is formed on the first to third light emitting devices LD1 , LD2 , and LD3 . The insulating layer INS may be partially formed on side surfaces of the light emitting devices LD and/or the bank patterns BNP. After the insulating layer INS is formed over the first to third pixels PXL1 , PXL2 , and PXL3 , the insulating layer INS may be partially removed to expose top surfaces of the light emitting devices LD. In an embodiment, when the light emitting devices LD are formed in the third direction (Z-axis direction), that is, perpendicular to the substrate SUB, the light emitting devices LD without a separate mask when the insulating layer INS is etched. The insulating layer INS provided on the top surface of the INS may be etched.

Subsequently, the reflective layer RF is formed between the first to third light emitting elements LD1 , LD2 , and LD3 to complete the display device of FIG. 6 . The reflective layer RF may reflect light emitted from the light emitting devices LD to improve light output efficiency of the display panel PNL. Also, the reflective layer RF is disposed at the boundary between the first to third pixels PXL1 , PXL2 , and PXL3 to prevent color mixing between adjacent pixels PXL. The material of the reflective layer RF is not particularly limited and may be formed of various reflective materials.

According to the above-described embodiment, as the first to third light emitting devices LD1 , LD2 , and LD3 each include the light emitting area EA emitting light of different colors, a color conversion layer and/ Alternatively, since the color filter layer may be omitted, the manufacturing process may be simplified and cost may be reduced. In addition, as described above, the porous region PA is embedded in the light emitting devices LD to improve light output efficiency of the display panel PNL and to simplify the manufacturing process.

Hereinafter, an electronic device to which the display devices of the above-described embodiments can be applied will be described.

27 to 30 are exemplary views illustrating electronic devices according to various embodiments.

Referring to FIG. 27 , the display device according to the above-described embodiments may be applied to smart glasses. The smart glass may include a frame 111 and a lens unit 112 . The smart glasses are wearable electronic devices that can be worn on a user's face, and may have a structure in which a part of the frame 111 is folded or unfolded. For example, the smart glasses may be a wearable device for augmented reality (AR).

The frame 111 may include a housing 111b supporting the lens unit 112 and a leg unit 111a for wearing by a user. The leg part 111a is connected to the housing 111b by a hinge and may be folded or unfolded.

A battery, a touch pad, a microphone, and/or a camera may be embedded in the frame 111 . In addition, a projector for outputting light and/or a processor for controlling an optical signal may be embedded in the frame 111 .

The lens unit 112 may be an optical member that transmits light or reflects light. The lens unit 112 may include glass and/or a transparent synthetic resin.

The display device according to the above-described embodiments may be applied to the lens unit 112 . For example, the user may recognize the image displayed by the optical signal transmitted from the projector of the frame 111 through the lens unit 112 . For example, the user may recognize information such as time and date displayed on the lens unit 112 .

Referring to FIG. 28 , the display device according to the above-described embodiments may be applied to a head mounted display (HMD). The head mounted display may include a head mounted band 121 and a display storage case 122 . For example, the head mounted display may be a wearable electronic device that can be worn on a user's head.

The head mounting band 121 may be connected to the display storage case 122 to fix the display storage case 122 . The head mounted band 121 includes a horizontal band and a vertical band for fixing the head mounted display to the user's head, as shown in FIG. 28 , the horizontal band surrounds the side of the user's head, and the vertical band includes the user's head. It may be provided to surround the upper part of the head. However, the present invention is not necessarily limited thereto, and the head mounting band 121 may be implemented in the form of an eyeglass frame or a helmet.

The display storage case 122 accommodates the display device and may include at least one lens. At least one lens may provide an image to the user. For example, the display device according to the above-described embodiments may be applied to a left eye lens and a right eye lens implemented in the display storage case 122 .

Referring to FIG. 29 , the display device according to the above-described embodiments may be applied to a smart watch. The smart watch may include a display unit 131 and a strap unit 132 . The smart watch is a wearable electronic device, and the strap unit 132 may be mounted on the user's wrist. The display device according to the above-described embodiments may be applied to the display unit 131 . For example, the display unit 131 may provide image data including information such as time and date.

Referring to FIG. 30 , the display device according to the above-described embodiments may be applied to an automotive display. For example, the automotive display may refer to an electronic device provided inside and outside a vehicle to provide image data.

For example, the display device according to the above-described embodiments includes an infotainment panel 141 , an infotainment panel 141 , a cluster 142 , a co-driver display 143 , and a head- It may be applied to at least one of an up display (144, head-up display), a side mirror display (145), and a rear-seat display (146, rear seat display).

Those of ordinary skill in the art related to the present embodiment will understand that it can be implemented in a modified form within a range that does not deviate from the essential characteristics of the above description. Therefore, the disclosed methods are to be considered in an illustrative rather than a restrictive sense. The scope of the present invention is indicated in the claims rather than the foregoing description, and all differences within an equivalent scope should be construed as being included in the present invention.

SUB: Substrate
LD: light emitting element
L1: first semiconductor layer
L2: active layer
L3: second semiconductor layer
LP: porous layer

Claims (20)

including light emitting devices disposed on a substrate;
Each of the light emitting devices,
a first semiconductor layer;
an active layer disposed on the first semiconductor layer;
a second semiconductor layer disposed on the active layer; and
and a porous layer disposed on the second semiconductor layer. The method of claim 1,
The porous layer includes nanoscale pores. The method of claim 1,
The porous layer includes the same material as the second semiconductor layer. The method of claim 1,
Further comprising bank patterns disposed on the substrate,
Each of the light emitting elements is disposed between the bank patterns. 5. The method of claim 4,
The bank patterns may include the same material as the light emitting devices. The method of claim 1,
The display device further comprising a color conversion layer disposed on the light emitting elements. The method of claim 1,
The display device further comprising a reflective layer disposed between the light emitting elements. 8. The method of claim 7,
and an insulating layer disposed between the light emitting elements and the reflective layer. The method of claim 1,
The light emitting devices are
a first light emitting element emitting a first color;
a second light emitting element emitting a second color; and
A display device including a third light emitting element emitting a third color. forming a semiconductor layer;
at least partially etching the semiconductor layer to form a porous layer; and
and providing a light emitting laminate on the porous layer to form light emitting devices. 11. The method of claim 10,
A method of manufacturing a display device in which nanoscale pores are formed in the step of etching the semiconductor layer. 11. The method of claim 10,
The forming of the light emitting devices may further include etching the porous layer and the light emitting laminate. 13. The method of claim 12,
The light emitting laminate,
a first semiconductor layer;
a second semiconductor layer formed on the first semiconductor layer; and
and an active layer formed between the first semiconductor layer and the second semiconductor layer. 14. The method of claim 13,
wherein the second semiconductor layer is formed of the same material as the porous layer. 13. The method of claim 12,
and etching the porous layer and the light emitting laminate to form bank patterns. 16. The method of claim 15,
The method of manufacturing a display device in which the bank patterns are simultaneously formed with the light emitting devices. 11. The method of claim 10,
and the semiconductor layer includes a second semiconductor layer provided between the porous layer and the light emitting laminate. 18. The method of claim 17,
Providing the light-emitting laminate comprises:
providing an active layer on the second semiconductor layer; and
and providing a first semiconductor layer on the active layer. 11. The method of claim 10,
The method of claim 1 , further comprising forming a planarization layer between the light emitting elements. 11. The method of claim 10,
The method of claim 1 , further comprising forming a reflective layer between the light emitting elements.

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