KR20220146937A - Parallel processing apparatus for supporting variable bit number - Google Patents

Abstract

According to an embodiment of the present invention, a parallel processing device includes: a pre-processing part including pre-processing units and receiving first signals and second signals; and a main processing part with adders. Each of the pre-processing units includes a shift operation part. The shift operation part transmits signals which are obtained by shifting a corresponding first signal among the first signals to a corresponding adder among the adders according to the bits of a corresponding second signal among the second signals, wherein according to a division selection signal, some bits of the shifted signals are controlled to become 0.

Description

Parallel processing unit supporting variable number of bits

The techniques described below relate to parallel processing units.

In order to achieve high data processing performance, many studies on parallel processing devices have been conducted. An example of a parallel processing device is a multi-core processor. A multi-core processor is a processor having a plurality of cores (processing units), and the reason why the multi-core processor is used is to increase the number of cores, thereby improving the performance of the entire processor. However, for various reasons, even if the number of cores is increased, the performance of the entire processor does not increase proportionally.

The inventor of the present invention is performing continuous development to improve these problems, and based on this, Korean Patent Publication Nos. 10-2019-0132295, 10-2018-0057950, 10-2018-0058166, No. 10-2018-0058167, 10-2018-0007523, 10-2018-0007652, and Korean Patent Registration No. 10-1859294 have performed the invention.

Korean Patent Publication Nos.: 10-2019-0132295, 10-2018-0057950, 10-2018-0058166, 10-2018-0058167, 10-2018-0007523, 10-2018-0007652 Korean Patent Registration No.: 10-1859294

The parallel processing apparatus according to the prior art has an adder and a multiplier separately. This lowers the efficiency of the parallel processing unit. More specifically, when a lot of multiplication operations are required, all multipliers of the parallel processing unit are utilized, but some adders are not utilized. Also, when many addition operations are required, all adders of the parallel processing unit are utilized, but some multipliers are not utilized. In addition, the parallel processing apparatus according to the prior art has an aspect in which data exchange between processing units is not easy. This degrades the overall performance of the parallel processing unit.

The present disclosure is to solve the problems of the prior art, and aims to increase the efficiency of the parallel processing apparatus by designing a processing unit of the parallel processing apparatus to perform both a multiplication operation and an addition operation. The present disclosure also aims to increase the efficiency of the overall parallel processing unit by facilitating data exchange between processing units. In addition, the present disclosure aims to increase the efficiency of the overall parallel processing unit by allowing each processing unit to perform various operations according to time. In addition, the present disclosure aims to not significantly increase the complexity of the overall hardware despite having the above-described improvements.

The present disclosure also aims to support an input having a variable number of bits. An input with a variable number of bits is required for various reasons. For example, in a deep learning algorithm such as ANN (Artificial Neural Network), DNN (Deep Neural Network), CNN (Convolution Neural Network), RNN (Recurrent Neural Network), bit of input data and weight The number affects performance, processing speed, required memory capacity, etc. Therefore, the number of bits in the input data and weights needs to be adjusted according to the requirements. Also, even in a parallel processing unit that performs a lot of mathematical operations, in some cases it may be appropriate to perform a 16-bit operation, and in other cases, it may be appropriate to perform a 32-bit operation. In this case, when a processor is designed according to the maximum number of bits, if a smaller number of bits is performed, a significant part of the processor does not operate, and thus the efficiency of the processor is reduced. For example, performing a 16-bit multiplication using a 32-bit multiplier only uses approximately 25% of the total processor.

A parallel processing apparatus according to an embodiment includes a preprocessing unit including preprocessing units, and a preprocessing unit receiving first signals and second signals; and a main processing unit including summers. Each of the pre-processing units includes a shift operation unit. The shift operation unit transfers the shifted signals of a corresponding first signal from among the first signals to a corresponding summer among the summers according to bits of a corresponding second signal among the second signals, Controlled so that some bits of the shifted signals become 0 according to the signal.

The parallel processing apparatus according to the present disclosure has high parallel processing efficiency because a unit unit can perform both a multiplication operation and an addition operation. In addition, the parallel processing device has an advantage that it can additionally perform a displacement operation and a shift operation. In addition, the parallel processing apparatus has the advantage of enabling easy data exchange between processing units. In addition, the parallel processing apparatus has an advantage that each processing unit can perform various operations according to time. In addition, the parallel processing apparatus has an advantage that the complexity of hardware does not significantly increase in spite of the above-described improvement.

In addition, the parallel processing apparatus according to the present disclosure has an advantage in that it can support an input having a variable number of bits.

1 is a diagram showing a parallel processing apparatus according to a first embodiment.
2 is a view for explaining an example of the i-th pre-processing unit of the first embodiment.
3 is a diagram showing a parallel processing apparatus according to the second embodiment.
Fig. 4 is a diagram showing a parallel processing apparatus according to the third embodiment.
5 is a diagram for explaining an example of the i-th pre-processing unit of the third embodiment.
Fig. 6 is a diagram showing a parallel processing apparatus according to the fourth embodiment.

Since the technology to be described below can have various changes and can have various embodiments, specific embodiments are illustrated in the drawings and described in detail. However, this is not intended to limit the technology described below to specific embodiments, and it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the technology described below.

Terms such as first, second, A, and B may be used to describe various components, but the components are not limited by the above terms, and only for the purpose of distinguishing one component from other components. used only as For example, a first component may be named as a second component, and similarly, the second component may also be referred to as a first component without departing from the scope of the technology to be described below. and/or includes a combination of a plurality of related listed items or any of a plurality of related listed items.

In terms of terms used herein, the singular expression should be understood to include a plural expression unless the context clearly dictates otherwise, and terms such as "comprises" include the described feature, number, step, operation, and element. , parts or combinations thereof are to be understood, but not to exclude the possibility of the presence or addition of one or more other features or numbers, step operation components, parts or combinations thereof.

Prior to a detailed description of the drawings, it is intended to clarify that the classification of the constituent parts in the present specification is merely a division according to the main function that each constituent unit is responsible for. That is, two or more components to be described below may be combined into one component, or one component may be divided into two or more for each more subdivided function. In addition, each of the constituent units to be described below may additionally perform some or all of the functions of other constituent units in addition to the main function it is responsible for. Of course, it can also be performed by being dedicated to it.

In addition, in performing the method or operation method, each process constituting the method may occur differently from the specified order unless a specific order is clearly described in context. That is, each process may occur in the same order as specified, may be performed substantially simultaneously, or may be performed in the reverse order.

1 is a diagram showing a parallel processing apparatus according to a first embodiment. Referring to FIG. 1 , the parallel processing device receives first to N-th inputs {X1, Y1}, {X2, Y2}, ... {XN, YN}), and outputs first to N-th outputs It outputs (M1, M2, ... MN). Here, N means a natural number equal to or greater than 4, for example, N may be 32. The first to Nth inputs {X1, Y1}, {X2, Y2}, ... {XN, YN}) are the first signals (X1, X2, ... XN) and the second signals ( Y1, Y2, ... YN). The parallel processing apparatus includes a pre-processing unit 100 and a main processing unit 200 . The parallel processing apparatus may further include a delay unit 300 and a selection unit 400 .

When the preprocessor 100 operates in the summing mode, the first signal Xi of the i-th input {Xi, Yi} is converted to the i-th bits of the second signals Y1, Y2, ... YN. (Y1[i], Y2[i], ... YN[i]) are transmitted to the summers SUM1, SUM2, ... SUMN of the main processing unit 200, respectively. Here, i is a natural number greater than or equal to 1 and less than or equal to N. The inputs of the first summer SUM1 are S1_1, S1_2, ... S1_N, the inputs of the second summer SUM2 are S2_1, S2_2, ... S2_N, the inputs of the third summer SUM3 are Let S3_1, S3_2, ... S3_N. In this case, the operation in the summing mode of the preprocessor 100 may be expressed as, for example, a pseudo code as follows.

[Equation 1]

(Y1[1] ? X1: 0) => S1_1,

(Y1[2] ? X2: 0) => S1_2,

...

(Y1[N] ? XN : 0) => S1_N,

(Y2[1] ? X1: 0) => S2_1,

(Y2[2] ? X2: 0) => S2_2,

...

(Y2[N] ? XN : 0) => S2_N,

...

(YN[1] ? X1 : 0) => SN_1,

(YN[2] ? X2: 0) => SN_2,

...

(YN[N] ? XN : 0) => SN_N

In the above equation, [(YN[N] ? XN: 0) => SN_N] indicates that when YN[N] is 1, XN is transferred to SN_N, and when YN[N] is 0, 0 is transferred to SN_N. it means. In addition, YN[1] means the 1st bit (least significant bit), and YN[N] means the Nth bit (most significant bit).

When the preprocessor 100 operates in the multiplication mode, the first signals X1, X2, ... XN are shifted signals by (i-1) bits ((X1<<(i-1)) , (X2<<(i-1)), ... (XN<<(i-1))) of the i-th bits Y1[i] of the second signals Y1, Y2, ... YN ], Y2[i], ... YN[i]) to the summers SUM1, SUM2, ... SUMN, respectively. The multiplication mode operation of the preprocessor 100 may be expressed in pseudo code as follows, for example.

[Equation 2]

(Y1[1] ? (X1 << 0) : 0)=> S1_1,

(Y1[2] ? (X1 << 1) : 0)=> S1_2,

...

(Y1[N] ? (X1 << (N-1)) : 0)=> S1_N,

(Y2[1] ? (X2 << 0) : 0)=> S2_1,

(Y2[2] ? (X2 << 1) : 0)=> S2_2,

...

(Y2[N] ? (X2 << (N-1)) : 0)=> S2_N,

...

(YN[1] ? (XN << 0) : 0)=> SN_1,

(YN[2] ? (XN << 1) : 0)=> SN_2,

...

(YN[N] ? (XN << (N-1)) : 0)=> SN_N

In the above equation, [(XN << (N-1)] means shifting XN to the left (in the most significant bit direction) by (N-1) bits.

For example, the preprocessor 100 operates in the summing mode or the multiplication mode according to the operation mode selection signals SF1, SF2, ... SFN. For example, one operation mode selection signal may be allocated to the entire parallel processing unit. In this case, the entire parallel processing unit must operate in the summing mode or the multiplication mode. As another example, N operation mode selection signals SF1, SF2, ... SFN may be allocated. In this case, it may be set such that some of the N outputs M1, M2, ... MN are results obtained according to the summing mode, and the rest are results obtained according to the multiplication mode. For example, when N is 4, the operation mode selection signals SF1 , SF2 , SF3 , and SF4 may be set so that M1 , M2 , and M3 operate in a multiplication mode and M4 operates in a summation mode.

For example, the preprocessor 100 includes a plurality of preprocessing units 150_1 , 150_2 , ... 150_N. The plurality of preprocessing units 150_1 , 150_2 , ... 150_N include selection operation units 110_1 , 110_2 , ... 110_N and shift operation units 120_1 , 120_2 , ... 120_N. The preprocessing unit 150_i includes a selection operation unit 110_i and a shift operation unit 120_i.

The selection operation unit 110_i operates when the pre-processing unit 150_i operates in the summing mode. The selection operation unit 110_i applies the first signals X1, X2, ... XN to the bits Yi[1], Yi[2], ... Yi[N] of the second signal Yi. It performs the function of transmitting to the summer (SUMi). In this case, the operation of the selection operation unit 110_i may be expressed in pseudo code as follows, for example.

[Equation 3]

(Yi[1] ? X1: 0) => Si_1,

(Yi[2] ? X2: 0) => Si_2,

...

(Yi[N] ? XN : 0) => Si_N,

The shift operation unit 120_i operates when the pre-processing unit 150_i operates in the multiplication mode. The shift operation unit 120_i calculates the signals ((Xi<<0), (Xi<<1), ... ( Xi<<(N-1))) to the summer SUMi according to the bits (Yi[1], Yi[2], ... Yi[N]) of the second signal Yi. carry out In this case, the operation of the shift operation unit 120_i may be expressed in pseudo code as follows, for example.

[Equation 4]

(Yi[1] ? (Xi << 0) : 0)=> Si_1,

(Yi[2] ? (Xi << 1) : 0)=> Si_2,

...

(Yi[N] ? (Xi << (N-1)) : 0)=> Si_N,

The preprocessing unit 150_i operates the selection operation unit 110_i or the shift operation unit 120_i according to the operation mode selection signal SFi. For example, when SFi is 0 means the operation of the selection operation unit 110_i, and when 1 indicates the operation of the shift operation unit 120_i, SF1 = 0, SF2 = 0, and SFN = 1 are the first This means that the pre-processing unit 150_1 , the second pre-processing unit 150_2 , and the N-th pre-processing unit 150_N operate the selection operation unit 120_1 , the selection operation unit 110_2 , and the shift operation unit 110_N, respectively.

The main processing unit 200 includes summers SUM1, SUM2, ... SUMN. The i-th summer Mi sums the transmitted signals Si_1, Si_2, ... Si_N, and outputs the summed result as the i-th output Mi. The operation of the main processing unit 200 may be expressed by, for example, the following pseudo code.

[Equation 5]

S1_1 + S1_2 + ... S1_N => M1,

S2_1 + S2_2 + ... S2_N => M2,

...

SN_1 + SN_2 + ... SN_N => MN,

The delay unit 300 delays and outputs the first to Nth outputs M1 , M2 , ... MN according to the clock signal CLK. To this end, the delay unit 300 includes a plurality of delay units DU1, DU2, ... DUN. The signals D1, D2, ... DN output from the delay unit 300 correspond to the first to N-th outputs M1, M2, ... MN, respectively.

The selector 400 controls input from among the signals R1, R2, ... RN transmitted from the memory (not shown) and the signals D1, D2, ... DN output from the delay unit 300 . Signals selected according to the signals SI1, SI2, ... SIN are output as first signals X1, X2, ... XN. For example, as shown in the figure, the first signal Xi may be a signal selected according to the input control signal SIi from among the signal Ri transmitted from the memory and the signal Di output from the delay unit 300 . have. As another example, the first signal Xi is selected according to the input control signal SIi from among the signal Ri transmitted from the memory and the two signals D(i-1) and Di output from the delay unit 300 . It could be a signal. That is, the first signal Xi includes a signal Ri transmitted from the memory, a delay unit output signal Di corresponding to the i-th output Mi, and an (i-1)-th output M(i-1). It may be a signal selected according to the input control signal SIi from among the delay unit output signals D(i-1) corresponding to . A memory (not shown) may include, for example, a plurality of banks. For example, the memory may have N banks, each of which may be connected to N inputs {X1, Y1}, {X2, Y2}, ... {XN, YN}. In addition, the memory has 2*N banks, of which N banks are respectively connected to N first signals X1, X2, ... XN, and the remaining N banks are connected to N second signals. It can be connected to (Y1, Y2, ... YN) respectively.

Since the parallel processing device has such a configuration, it is possible to perform various operations with one piece of hardware. For example, the parallel processing unit may perform a partial summation operation. Here, the partial summation means summing all or part of the first signals X1, X2, ... XN. In order to perform the partial summation operation, the preprocessor 100 must operate in the summation mode. At this time, the i-th output Mi is the bits Yi[1], Yi[2], ... Yi[ of the second signal Yi among the first signals X1, X2, ... XN. N]), corresponding to the summation of the selected signals. For example, if N is 4 and the second signals Y1, Y2, Y3, Y4 are 1011, 1100, 0010, 0111 in binary, the outputs M1, M2, M3, M4 are X4+X2+X1, Corresponds to X4+X3, X2, and X3+X2+X1, respectively. As described above, when the preprocessor 100 operates in the summation mode, N partial summation operations may be performed at the same time.

When the preprocessor 100 operates in the summing mode, a displacement operation may also be performed. Here, the displacement operation means changing the position in transferring the first signal Xi to the output signals M1, M2, ... MN. For example, if N is 4 and the second signals Y1, Y2, Y3, Y4 are 1000, 0100, 0010, 0001 in binary, the outputs M1, M2, M3, M4 are X4, X3, X2, X1 each corresponds to Accordingly, the first signals X1, X2, X3, and X4 are transmitted to the outputs M1, M2, M3, and M4, but their positions are changed and transmitted.

As described above, when the parallel processing apparatus performs the partial sum operation and the displacement operation, data exchange between processing units is facilitated. Here, the i-th processing unit is a concept including the i-th pre-processing unit and the i-th summer. For example, the first processing unit 150_1 , SUM1 may receive the first first signal X1 as well as the second to N-th first signals X2 , ... XN and perform partial summation. In addition, the second processing units 150_2 and SUM2 may receive the N-th first signal XN as an example of a first signal other than the second first signal X2 .

For example, the parallel processing unit may perform a multiplication operation. In order to perform a multiplication operation, the preprocessor 100 must operate in a multiplication mode. In this case, the i-th output Mi corresponds to the product (Xi*Yi) of the first signal Xi and the second signal Yi. For example, if N is 4, outputs M1, M2, M3, and M4 correspond to X1*Y1, X2*Y2, X3*Y3, and X4*Y4, respectively. As described above, when the preprocessor 100 operates in the multiplication mode, N multiplications may be simultaneously performed.

When the preprocessor 100 operates in the multiplication mode, a shift operation may also be performed. For example, if N is 4 and the second signals Y1, Y2, Y3, Y4 are 1000, 0100, 0010, 0001 in binary, the outputs M1, M2, M3, M4 are (X1<<3), It corresponds to (X2<<2), (X3<<1), and (X4<<0), respectively.

The parallel processing unit may perform various operations simultaneously. For example, when N is 4, the following operations can be simultaneously performed.

M1 = X2 + X3 + X4 [partial sum operation]

M2 = X1 [displacement operation]

M3 = X3 * Y3 [multiplication operation]

M4 = (X4 << 2) [shift operation]

To this end, the selection signals SF1 and SF2 must be set so that the first and second preprocessing units 150_1 and 150_2 are in the summing mode, and the third and fourth preprocessing units 150_3 and 150_4 are in the multiplication mode. The selection signals SF3 and SF4 should be set so as to be possible. In addition, Y1 must be set to 1110 so that the partial sum operation can be performed as above, Y2 must be set to 0001 so that the displacement operation can be performed as above, and Y4 must be set to 0100 so that the shift operation can be performed as above. should be set

In addition, the parallel processing apparatus may independently change the operation of the parallel processing apparatus every time by changing the selection signal SFi and the second signal Yi. For example, as described above in the first turn, after M1, M2, M3, and M4 perform partial summation, displacement, multiplication, and shift operations, respectively, in the second turn, multiplication, multiplication, partial summation and partial summation operations are performed as follows. A summation operation can be performed.

M1 = X1 * Y1 [multiplication operation]

M2 = X2 * Y2 [multiplication operation]

M3 = X1 + X2 + X3 + X4 [partial sum operation]

M4 = X2 + X4 [partial sum operation]

To this end, the selection signals SF1 and SF2 must be set so that the first and second preprocessing units 150_1 and 150_2 are in multiplication mode, and the third and fourth preprocessing units 150_3 and 150_4 are in the summing mode. The selection signals SF3 and SF4 should be set so as to be possible. In addition, Y3 and Y4 must be set to 1111 and 1010, respectively, so that the partial sum operation can be performed as described above.

As described above, in the parallel processing apparatus according to the first embodiment, N independent operations may be simultaneously performed, and N operations may be independently changed every turn. This can maximize the efficiency of the parallel processing unit.

Parallel having a partial summation parallel processing unit performing a plurality of partial summation operations, a displacement parallel processing unit performing a plurality of displacement operations, a multiplication parallel processing unit performing a plurality of multiplication operations, and a shift parallel processing unit performing a plurality of shift operations Assuming there is a processing unit, the multiplication parallel processing unit can be utilized 100% at the moment when a lot of multiplication operations are required, but the utilization of the partial summation parallel processing unit, the displacement parallel processing unit and the shift parallel processing unit will be low. In addition, the partial sum parallel processing unit can be utilized 100% at the moment when a lot of partial sum operation is required, but the utilization of the displacement parallel processing unit, multiplication parallel processing unit, and shift parallel processing unit will be low.

Contrary to this, the parallel processing apparatus according to the first embodiment can maximize the utility of the parallel processing apparatus by changing the operations performed by the preprocessing units 150_1, 150_2, ... 150_N at every moment. For example, at a moment when a lot of multiplication operations are required, many of the preprocessing units 150_1, 150_2, ... 150_N perform a multiplication operation and the remaining parts perform other operations by setting the preprocessing units 150_1, Most of 150_2, ... 150_N) can be utilized. In addition, at a moment when a lot of partial summation operations are required, many of the preprocessing units 150_1, 150_2, ... 150_N perform partial summation operations, and the remaining parts perform other operations by setting the preprocessing units ( Most of 150_1, 150_2, ... 150_N) can be utilized.

2 is a view for explaining an example of the i-th pre-processing unit of the first embodiment. Referring to FIG. 2 , the preprocessing unit includes a selection operation unit 110_i and a shift operation unit 120_i.

The selection operation unit 110_i includes a plurality of demultiplexers DM1, DM2, ... DMN. The plurality of demultiplexers DM1, DM2, ... DMN includes bits Yi[1], The signals selected according to Yi[2], ... Yi[N]) are respectively output. For example, the first demultiplexer DM1 outputs a signal selected according to the first bit (Yi[1]) of the second signal Yi from among the first signal X1 and 0, and the second demultiplexer DM2 ) outputs a signal selected according to the second bit (Yi[2]) of the second signal Yi among the first signal X2 and 0, and the N-th demultiplexer DMN includes the first signal XN and A signal selected according to the Nth bit (Yi[N]) of the second signal Yi among 0 is output.

The shift operation unit 120_i includes a plurality of shift units SH1, SH2, ... SHN. The plurality of shift units SH1, SH2, ... SHN include bits of the first signal Xi shifted and the second signal Yi among 0 bits Yi[1], Yi[2], ... each of the signals selected according to Yi[N]) is output. For example, the first shift unit SH1 is selected according to the first bit Yi[1] of the second signal Yi among the signal Xi<<0) in which the first signal Xi is shifted by 0 bits and 0 The signal is output, and the second shift unit SH2 is configured to generate a signal Xi<<1 in which the first signal Xi is shifted by one bit and a second bit (Yi[2]) of the second signal Yi among 0. Outputs a signal selected according to , and the N-th shift unit SHN generates a second signal (Xi<<(N-1)) in which the first signal Xi is shifted by (N-1) bits and a second signal ( A signal selected according to the Nth bit (Yi[N]) of Yi) is output.

Any one of the selection operation unit 110_i and the shift operation unit 120_i operates according to the selection signal SFi. For example, when the selection signal SFi is 0, the selection operation unit 110_i operates, and the shift operation unit 120_i does not operate. At this time, the selection operator 110_i transfers the signals output from the demultiplexers DM1, DM2, ... DMN to the summer SUMi as the summer inputs Si_1, Si_2, ... Si_N, and shifts them. The operation unit 120_i outputs high impedance signals. Also, when the selection signal SFi is 1, the selection operation unit 110_i does not operate, and the shift operation unit 120_i operates. In this case, the selection operation unit 110_i outputs high impedance signals, and the shift operation unit 120_i applies signals output from the shift units SH1, SH2, ... SHN to the summer inputs Si_1. , Si_2, ... Si_N) to the summer SUMi.

Unlike the drawing, some of the outputs of the selection operation unit 110_i and the shift operation unit 120_i may be selected according to the selection signal SFi by adding separate demultiplexers. For example, when the selection signal SFi means the summing mode, separate demultiplexers transfer the outputs of the selection operator 110_i to the summer SUMi, and when the selection signal SFi means the multiplication mode, the separate demultiplexers use the shift operator The (120_i) outputs may be transferred to the summer SUMi.

3 is a diagram showing a parallel processing apparatus according to the second embodiment. Referring to FIG. 3 , the parallel processing unit performs first to Pth inputs {X1, Y1}, ... {X(p-1), Y(p-1)}, {Xp, Yp}, { X(p+1), Y(p+1)}, ... {XP, YP}) are received, and the first to Pth outputs M1, ... M(p-1), Mp, Output M(p+1) ... MP). Here, P means a natural number equal to or greater than 4, for example, P may be 1024. In addition, p means a natural number that is 1 or more and P or less. 1st to Pth inputs ({X1, Y1}, ... {X(p-1), Y(p-1)}, {Xp, Yp}, {X(p+1), Y(p +1)}, ... {XP, YP}) are the first signals X1, ... X(p-1), Xp, X(p+1), ... XP) and the second signal and Y1, ... Y(p-1), Yp, Y(p+1) ... YP. The parallel processing apparatus includes a preprocessing unit 100A and a main processing unit 200A. The parallel processing apparatus may further include a delay unit 300A and a selection unit 400A.

The preprocessor 100A includes a plurality of preprocessing units ... 150_(p-1), 150_p, 150(p+1), ...). The plurality of preprocessing units (... 150_(p-1), 150_p, 150(p+1), ...) are selected by the selection operation units (... 110_(p-1), 110_p, 110_(p+). 1), ...) and shift operation units (... 120_(p-1), 120_p, 120_(p+1), ...). The preprocessing unit 150_p includes a selection operation unit 110_p and a shift operation unit 120_p.

The selection operation unit 110_p operates when the pre-processing unit 150_p operates in the summing mode. The selection operation unit 110_p includes a first signal Xp corresponding to the preprocessing unit 150_p and first signals adjacent thereto (eg, X(p-Q/2+1), ... X(p-1), X (p+1), ... X(p+Q/2) according to the bits of the second signal Yp (Yp[1], Yp[2], ... Yp[Q]). (SUMp), where Q means an even number greater than or equal to 4, and for example, Q may be 32. Also, q means a natural number greater than or equal to 1 and less than or equal to Q. In this case, the selection operator (110_p) The operation of can be expressed in pseudo code as follows as an example.

[Equation 6]

(Yp[1] ? X(p-Q/2+1) : 0) => Si_1,

(Yp[2] ? X(p-Q/2+2) : 0) => Si_2,

...

(Yp[Q] ? X(p+Q/2) : 0) => Si_Q,

The shift operation unit 120_p operates when the pre-processing unit 150_p operates in the multiplication mode. The shift operation unit 120_p calculates the signals ((Xp<<0), (Xp<<1), ... ( Xp<<(Q-1))) to the summer SUMp according to the bits Yp[1], Yp[2], ... Yp[Q]) of the second signal Yp carry out In this case, the operation of the shift operation unit 120_p may be expressed in pseudo code as follows, for example.

[Equation 7]

(Yp[1] ? (Xp << 0) : 0)=> Sp_1,

(Yp[2] ? (Xp << 1) : 0)=> Sp_2,

...

(Yp[Q] ? (Xp << (Q-1)) : 0)=> Sp_Q,

The preprocessing unit 150_p operates the selection operation unit 110_p or the shift operation unit 120_p according to the operation mode selection signal SFp.

The main processing unit 200A includes summers ... SUM(p-1), SUMp, SUM(p+1), ...). The p-th summer Mp sums the transmitted signals Sp_1, Sp_2, ... Si_Q, and outputs the summed result as the p-th output Mp. The operation of the main processing unit 200A may be expressed as, for example, the following pseudo code.

[Equation 8]

...

S(p-1)_1 + S(p-1)_2 + ... S(p-1)_Q => M(p-1),

Sp_1 + Sp_2 + ... Sp_Q => Mp, ...

S(p+1)_1 + S(p+1)_2 + ... S(p+1)_Q => M(p+1),

...

The delay unit 300A delays and outputs the outputs (... M(p-1), Mp, M(p+1), ...) according to the clock signal CLK. To this end, the delay unit 300A includes a plurality of delay units (... DU(p-1), DUp, DU(p+1), ...). The signals ... D(p-1), Dp, D(p+1), ...) output from the delay unit 300A are the outputs ... M(p-1), Mp, M(p+1), ...) respectively.

The selector 400A includes signals (... R(p-1), Rp, R(p+1), ...) transmitted from a memory (not shown) and a signal output from the delay unit 300A. of the input control signals (... SI(p-1), SIp, SI(p+1), The signals selected according to ...) are output as first signals ... X(p-1), Xp, X(p+1), ...). For example, the memory may include P banks, each of which may be connected to P inputs {X1, Y1}, {X2, Y2}, ... {XP, YP}. In addition, the memory has 2P banks, of which P banks are respectively connected to P first signals X1, X2, ... XP, and the remaining P banks are connected to P second signals Y1. , Y2, ... YP) respectively.

Fig. 4 is a diagram showing a parallel processing apparatus according to the third embodiment. Referring to FIG. 4 , the parallel processing device receives first to N-th inputs {X1, Y1}, {X2, Y2}, ... {XN, YN}), and outputs first to N-th outputs It outputs (M1, M2, ... MN). Here, N means a natural number of 8 or more, for example, N may be 32. The first to Nth inputs {X1, Y1}, {X2, Y2}, ... {XN, YN}) are the first signals (X1, X2, ... XN) and the second signals ( Y1, Y2, ... YN). The parallel processing apparatus includes a pre-processing unit 100B and a main processing unit 200 . The parallel processing apparatus may further include a delay unit 300 and a selection unit 400 .

The preprocessor 100B includes a plurality of preprocessing units 150B_1, 150B_2, ... 150B_N. The plurality of preprocessing units 150B_1, 150B_2, ... 150B_N includes selection operation units 110B_1, 110B_2, ... 110B_N and shift operation units 120B_1, 120B_2, ... 120B_N. The preprocessing unit 150B_i includes a selection operation unit 110B_i and a shift operation unit 120B_i.

The selection operation unit 110B_i operates when the pre-processing unit 150B_i operates in the summing mode. The selection operation unit 110B_i applies the first signals X1, X2, ... XN to the bits Yi[1], Yi[2], ... Yi[N] of the second signal Yi. Accordingly, the bits are transmitted to the summer SUMi, but some bits of the first signals X1, X2, ... XN are shifted according to the division selection signal DSi and transmitted to the summer SUMi.

When the division selection signal DSi is a signal corresponding to division by 1 (a signal corresponding to not division), the selection operation unit 110B_i shifts all bits of the first signals X1, X2, ... XN. It is passed to the summer (SUMi) without doing so.

The number of bits of the first signals X1, X2, ... XN is N (N is an even number of 8 or more), the number of bits of the second signal Yi is N, and the division selection signal DSi is divided into two. If it is a corresponding signal, the selection operation unit 110B_i shifts the most significant (N/2) bits of the first signals X1, X2, ... XN by (N/2) bits, and the first signals X1, The least significant (N/2) bits of X2, ... XN) are shifted by 0 bits (without shifting) and passed to the summer (SUMi).

The number of bits of the first signals X1, X2, ... XN is N (N is 8 or more and is a multiple of 4), the number of bits of the second signal Yi is N, and the division selection signal DSi If is a signal corresponding to division by 4, the selection operation unit 110B_i converts N to (N*3/4+1) bits of the first signals X1, X2, ... XN to (N*3/4) bit shifting, (N*3/4) to (N*2/4+1) bits of the first signals X1, X2, ... XN bit shifting (N*2/4) bits, 1 (N*2/4) to (N*1/4+1) bits of the signals X1, X2, ... XN are bit shifted (N*1/4), and the first signals X1 , X2, ... XN) are transferred to the summer (SUMi) by shifting (N*1/4) to 1 bits by 0 bits (without shifting).

The operation of the selection operation unit 110B_i may be expressed in pseudo code as follows, for example.

[Equation 9]

(Yi[1] ? XX1 : 0) => Si_1,

(Yi[2] ? XX2: 0) => Si_2,

...

(Yi[N] ? XXN : 0) => Si_N,

In the above formula, XX1, XX2, ... XXN are determined according to the first signals X1, X2, ... XN and the division selection signal DSi. Examples of XXi when N is 8 and 16 are shown in Tables 1 and 2, respectively.

XXi 1 division (no division) {00000000, Xi[8:1]} 2 division {0000, Xi[8:5], 0000, Xi[4:1]} 4 divisions {00, Xi[8:7], 00, Xi[6:5], 00, Xi[4:3], 00, Xi[2:1]}

XXi 1 division (no division) {0000000000000000, Xi[16:1]} 2 division {00000000, Xi[16:9], 00000000, Xi[8:1]} 4 divisions {0000, Xi[16:13], 0000 Xi[12:9], 0000, Xi[8:5], 0000, Xi[4:1]}

In the table above, {0000, Xi[8:5], 0000, Xi[4:1]} is 0000 for the most significant 4 bits, Xi[8:5] for the next 4 bits, 0000 for the next 4 bits, and 0000 for the least significant 4 bits It means the total number of 16 bits composed of Xi[4:1]. A person of ordinary skill in the art can easily predict the operation of the selection operation unit 110B_i in 8 divisions, 16 divisions, and more divisions from the above description, so a description thereof will be omitted for convenience of description. .

The shift operation unit 120B_i operates when the pre-processing unit 150B_i operates in the multiplication mode. The shift operation unit 120B_i calculates the signals ((Xi<<0), (Xi<<1), ... ( Xi<<(N-1))) to the summer SUMi according to the bits Yi[1], Yi[2], ... Yi[N]) of the second signal Yi, Controls some bits of the shifted signals ((Xi<<0), (Xi<<1), ... (Xi<<(N-1))) to become 0 according to the division selection signal DSi .

If the division selection signal DSi is a signal corresponding to division by one (a signal corresponding to not division), the shifted signals ((Xi<<0), (Xi<<1), ... (Xi< Some bits of <(N-1))) are not set to 0.

If the number of bits of the first signal Xi is N (N is an even number of 8 or more), the number of bits of the second signal Yi is N, and the division selection signal DSi is a signal corresponding to division into two, the shift operation unit ( 120B_i) is a signal (Xi<<0), (Xi<<1), ... (Xi<<(N/) 2-1))) are controlled so that the most significant (N/2) bits become 0, and signals (Xi<< The least significant (N/2) bits of (N/2)), (Xi<<(N/2+1)), ... (Xi<<(N-1))) are controlled to be 0.

If the number of bits of the first signal Xi is N (N is 8 or more and is a multiple of 4), the number of bits of the second signal Yi is N, and the division selection signal DSi is a signal corresponding to division by 4 , the shift operation unit 120B_i calculates the signals ((Xi<<0), (Xi<<1), ... ( The most significant (N*3/4) bits of Xi<<(N*1/4-1))) are controlled to be 0, and the first signal Xi is from (N*1/4) bits to (N* 2/4-1) bit-shifted signals ((Xi<<(N*1/4)), (Xi<<(N*1/4+1)), ... (Xi<<(N*) 2/4-1))), the most significant (N*2/4) bits and the least significant (N*1/4) bits are controlled to be 0, and the first signal Xi is (N*2/4) Bit to (N*3/4-1) bit shifted signals ((Xi<<(N*2/4)), (Xi<<(N*2/4+1)), ... (Xi Control so that the most significant (N*1/4) bits and the least significant (N*2/4) bits of <<(N*3/4-1))) become 0, and the first signal Xi is (N *3/4) bit to (N-1) bit shifted signals ((Xi<<(N*3/4)), (Xi<<(N*3/4+1)), ... ( The least significant (N*3/4) bits of Xi<<(N-1))) are controlled to be 0.

The operation of the shift operation unit 120B_i may be expressed in pseudo code as follows, for example.

[Equation 10]

(Yi[1] ? ((Xi & DC1) << 0) : 0)=> Si_1,

(Yi[2] ? ((Xi & DC2) << 1) : 0)=> Si_2,

...

(Yi[N] ? ((Xi & DCN) << (N-1)) : 0)=> Si_N

In the above equation, (Xi & DCN) means that a bitwise AND operation is performed on Xi and DCN in bits. The division constants DC1 to DCN are determined according to the division selection signal DSi. Examples of division constants DC1 to DCN when N is 8 and 16 are shown in Tables 3 and 4, respectively.

1 division
(do not split) 2 division 4 divisions DC1 11111111 00001111 00000011 DC2 11111111 00001111 00000011 DC3 11111111 00001111 00001100 DC4 11111111 00001111 00001100 DC5 11111111 11110000 00110000 DC6 11111111 11110000 00110000 DC7 11111111 11110000 1100000 DC8 11111111 11110000 1100000

1 division
(do not split) 2 division 4 divisions DC1 11111111111111111 00000000111111111 0000000000001111 DC2 11111111111111111 00000000111111111 0000000000001111 DC3 11111111111111111 00000000111111111 0000000000001111 DC4 11111111111111111 00000000111111111 0000000000001111 DC5 11111111111111111 00000000111111111 0000000011110000 DC6 11111111111111111 00000000111111111 0000000011110000 DC7 11111111111111111 00000000111111111 0000000011110000 DC8 11111111111111111 00000000111111111 0000000011110000 DC9 11111111111111111 1111111100000000 0000111100000000 DC10 11111111111111111 1111111100000000 0000111100000000 DC11 11111111111111111 1111111100000000 0000111100000000 DC12 11111111111111111 1111111100000000 0000111100000000 DC13 11111111111111111 1111111100000000 11110000000000000 DC14 11111111111111111 1111111100000000 11110000000000000 DC15 11111111111111111 1111111100000000 11110000000000000 DC16 11111111111111111 1111111100000000 11110000000000000

A person of ordinary skill in the art can easily predict the operation of the shift operation unit 120B_i when dividing 8, 16, or more from the above description, so a description thereof is omitted for convenience of description. do. The preprocessing unit 150B_i operates the selection operation unit 110B_i or the shift operation unit 120B_i according to the operation mode selection signal SFi. For example, when SFi is 0 means the operation of the selection operation unit 110B_i, and when 1 indicates the operation of the shift operation unit 120B_i, SF1 = 0, SF2 = 0, and SFN = 1 are the first This means that the pre-processing unit 150B_1, the second pre-processing unit 150B_2, and the N-th pre-processing unit 150B_N operate the selection operation unit 120B_1, the selection operation unit 110B_2, and the shift operation unit 110B_N, respectively.

Operations of the main processing unit 200 , the delay unit 300 , and the selection unit 400 are the same as those of FIG. 1 and the description thereof, and thus will be omitted for convenience of description.

Since the parallel processing device has such a configuration, it is possible to perform various operations with one piece of hardware. For example, the parallel processing unit may perform a partial sum operation, a displacement operation, a multiplication operation, and a shift operation. Since the description of such an operation has already been performed in FIG. 1 and the description thereof, it will be omitted for convenience of description.

Also, by having such a configuration, the parallel processing apparatus can perform multiplication and addition operations on inputs of various bits. As an example, the preprocessing unit 150B_i operates in the summing mode, and the first signals X1, X2, ... X8 composed of 8 bits are {a1_8, a1_7, a1_6, a1_5, a1_4, a1_3, a1_2, a1_1}, {a2_8, a2_7, a2_6, a2_5, a2_4, a2_3, a2_2, a2_1}, ... {a8_8, a8_7, a8_6, a8_5, a8_4, a8_3, a8_2, a8_1}, and the 8-bit second signal (Yi) is Assume {b8, b7, b6, b5, b4, b3, b2, b1}. If the division selection signal DSi is a signal corresponding to division 1, according to Equation 9 and Table 1, the output Mi[16:1] is b1*{a1_8, a1_7, a1_6, a1_5, a1_4, a1_3, a1_2 , a1_1} + b2*{a2_8, a2_7, a2_6, a2_5, a2_4, a2_3, a2_2, a2_1} + ... + the value of b8*{a8_8, a8_7, a8_6, a8_5, a8_4, a8_3, a8_2, a8 have

Also, if the division selection signal DSi is a signal corresponding to division into 2, the output (Mi[16:9]) according to Equation 9 and Table 1 is b1*{a1_8, a1_7, a1_6, a1_5} + b2*{ With values of a2_8, a2_7, a2_6, a2_5} + ... + b8*{a8_8, a8_7, a8_6, a8_5}, the output (Mi[8:1]) is b1*{a1_4, a1_3, a1_2, a1_1} + b2*{a2_4, a2_3, a2_2, a2_1} + ... + b8*{a8_4, a8_3, a8_2, a8_1}. To generalize this, we get: The number of bits of the first signals X1, X2, ... XN is N (N is an even number of 8 or more), the number of bits of the second signal Yi is N, and the division selection signal DSi is divided into two. If it is a corresponding signal, the most significant N bits of the output Mi of the summing unit SUMi are the most significant (N) bits of the first signals selected according to the second signal Yi among the first signals X1, X2, ... N/2) corresponds to the sum of bits, and the least significant N bits of the output Mi of the summing unit SUMi are selected according to the second signal Yi from among the first signals X1, X2, ... XN. It corresponds to the sum of least significant (N/2) bits of the first signals. The parallel processing apparatus according to the present embodiment uses a summer that receives eight first signals (each first signal has 8 bits) in a general manner (eg, eight first signals (each first signal has 8 bits)). 4 bits), that is, as the first signals X1, X2, ... XN, {0000, a1_4, a1_3, a1_2, a1_1}, {0000, a2_4, a2_3, a2_2, a2_1} , ... {0000, a8_4, a8_3, a8_2, a8_1} is input, and {b8, b7, b6, b5, b4, b3, b2, b1} is received as the second signal (Yi) to perform addition. case), the utilization of hardware of the summer SUMi is increased, and the number of effective bits of the first signal Xi, the second signal Yi, and the output Mi is increased.

Also, if the division selection signal DSi is a signal corresponding to division into 4, the output Mi[16:13] according to Equation 9 and Table 1 is b1*{a1_8, a1_7} + b2*{a2_8, a2_7} + ... + b8*{a8_8, a8_7}, the output (Mi[12:9]) is b1*{a1_6, a1_5} + b2*{a2_6, a2_5} + ... + b8*{ It has values of a8_6, a8_5}, and the output (Mi[8:5]) has values of b1*{a1_4, a1_3} + b2*{a2_4, a2_3} + ... + b8*{a8_4, a8_3} , the output (Mi[4:1]) has a value of b1*{a1_2, a1_1} + b2*{a2_2, a2_1} + ... + b8*{a8_2, a8_1}. To generalize this, we get: The number of bits of the first signals X1, X2, ... XN is N (N is 8 or more and is a multiple of 4), the number of bits of the second signal Yi is N, and the division selection signal DSi If is a signal corresponding to division by 4, 2N to (N*3/2+1) bits of the output Mi of the summing unit SUMi are the second among the first signals X1, X2, ... XN. Corresponds to the sum of N to (N*3/4+1) bits of the first signals selected according to the signal Yi, and (N*3/2) to (N) of the output Mi of the summing unit SUMi *2/2+1) bits are (N*3/4) to (N*2/) of the first signals selected according to the second signal Yi among the first signals X1, X2, ... XN 4+1) corresponds to the sum of bits, and (N*2/2) to (N*1/2+1) bits of the output Mi of the summing unit SUMi are the first signals X1, X2, ... XN) corresponds to the sum of (N*2/4) to (N*1/4+1) bits of the first signals selected according to the second signal Yi from among XN) (N*1/2) to 1 bits of (Mi) are (N*1/4) of the first signals selected according to the second signal Yi among the first signals X1, X2, ... XN to the sum of 1 bits. The parallel processing apparatus according to the present embodiment uses a summer that receives eight first signals (each first signal has 8 bits) in a general manner (eg, eight first signals (each first signal has 8 bits)). 2 bits), that is, as the first signals X1, X2, ... XN, {000000, a1_2, a1_1}, {000000, a2_2, a2_1}, ... {000000, a8_2 , a8_1} and {b8, b7, b6, b5, b4, b3, b2, b1} as the second signal Yi) and increase the number of effective bits of the first signal Xi, the second signal Yi, and the output Mi. However, since an overflow may occur when the division selection signal DSi is a signal corresponding to 4 divisions or more divisions (eg 8 divisions, 16 divisions, etc.), (eg, b1*{a1_2, a1_1} + b2* The size of {a2_2, a2_1} + ... + b8*{a8_2, a8_1} exceeds 4 bits, which affects the output (Mi[4:1]) as well as the output (Mi[8:5]). Development) The number of 1's included in the second signal Yi must be managed so as not to exceed a predetermined number.

As an example, the preprocessing unit 150B_i operates in the multiplication mode, the first signal Xi composed of 8 bits is {a8, a7, a6, a5, a4, a3, a2, a1}, and the second signal composed of 8 bits ( Let Yi) be {b8, b7, b6, b5, b4, b3, b2, b1}. If the division selection signal DSi is a signal corresponding to division 1, according to Equation 10 and Table 3, the output Mi[16:1] is {a8, a7, a6, a5, a4, a3, a2, a1 }*{b8, b7, b6, b5, b4, b3, b2, b1}. At this time, 100% of the hardware (eg, adder) constituting the summer (SUMi) is utilized.

In addition, if the division selection signal DSi is a signal corresponding to division by 2, the output (Mi[16:9]) according to Equation 10 and Table 3 is {a8, a7, a6, a5}*{b8, b7, It has values of b6, b5}, and the output (Mi[8:1]) has values of {a4, a3, a2, a1}*{b4, b3, b2, b1}. This can be generalized and expressed as follows. If the number of bits of the first signal Xi is N (N is an even number of 8 or more), the number of bits of the second signal Yi is N, and the division selection signal DSi is a signal corresponding to division by two, the summer ( The most significant N bits of the output Mi of SUMi) correspond to the product of the most significant (N/2) bits of the first signal Xi and the most significant (N/2) bits of the second signal Yi, and the summer The least significant N bits of the output Mi of (SUMi) correspond to the product of the least significant (N/2) bits of the first signal Xi and the least significant (N/2) bits of the second signal Yi. At this time, 50% of the hardware constituting the summer SUMi is utilized, and 100% of the effective bits of the first signal Xi, the second signal Yi, and the output Mi are utilized. On the other hand, in the case of performing 4-bit multiplication using an 8-bit multiplier, {0000, a4, a3, a2, a1} is input as the first signal Xi, and the second signal Yi ) as {0000, b4, b3, b2, b1} and performing multiplication), 25% of the hardware constituting the summer (SUMi) is utilized, and the first signal (Xi), the first signal (Xi), 2 50% of the valid bits of the signal Yi and the output Mi are utilized. Therefore, when dividing into two, the parallel processing apparatus according to the present embodiment can double the hardware utilization of the summer Mi compared to the prior art, and the first signal Xi, the second signal Yi and The effective bits of the output Mi can also be doubled.

In addition, if the division selection signal DSi is a signal corresponding to division into 4, the output Mi[16:13] according to Equation 10 and Table 3 has a value of {a8, a7}*{b8, b7} , the output (Mi[12:9]) has the values {a6, a5}*{b6, b5}, and the output (Mi[8:5]) has the values {a4, a3}*{b4, b3} , and the output (Mi[4:1]) has a value of {a2, a1}*{b2, b1}. This can be generalized and expressed as follows. If the number of bits of the first signal Xi is N (N is 8 or more and is a multiple of 4), the number of bits of the second signal Yi is N, and the division selection signal DSi is a signal corresponding to division by 4 , 2N to (N*3/2+1) bits of the output Mi of the summer SUMi are the N to (N*3/4+1) bits of the first signal Xi and the second signal ( Yi) corresponds to the product of N to (N*3/4+1) bits, and (N*3/2) to (N*2/2+1) bits of the output Mi of the summer SUMi. (N*3/4) to (N*2/4+1) bits of the first signal Xi and (N*3/4) to (N*2/4+) bits of the second signal Yi 1) Corresponding to the product of bits, (N*2/2) to (N*1/2+1) bits of the output Mi of the summer SUMi are (N*2) bits of the first signal Xi /4) to (N*1/4+1) bits and corresponding to the product of (N*2/4) to (N*1/4+1) bits of the second signal Yi, and the summer ( (N*1/2) to 1 bits of the output Mi of SUMi) are (N*1/4) to 1 bits of the first signal Xi and (N*1/2) of the second signal Yi 4) to the product of 1 bits. At this time, 25% of the hardware constituting the summer SUMi is utilized, and 100% of the effective bits of the first signal Xi, the second signal Yi, and the output Mi are utilized. On the other hand, in the case of performing 2-bit multiplication using an 8-bit multiplier, {000000, a2, a1} is input as the first signal Xi and {000000 as the second signal Yi. . 25% of the significant bits of Mi) are utilized. Therefore, when dividing into 4, the parallel processing apparatus according to the present embodiment can increase the hardware utilization of the summer Mi by 4 times compared to the prior art, and the first signal Xi, the second signal Yi and The effective bits of the output Mi can also be increased by a factor of four.

As such, in the parallel processing apparatus according to the third embodiment, N independent operations can be simultaneously performed, the N operations can be independently changed every turn (according to time), and input of various bit numbers can be operated on. This can maximize the efficiency of the parallel processing unit.

5 is a diagram for explaining an example of the i-th pre-processing unit of the third embodiment. Referring to FIG. 5 , the preprocessing unit includes a selection operation unit 110B_i and a shift operation unit 120B_i.

The selection operation unit 110B_i includes a plurality of first transform units T1_1, T1_2, ... T1_N and a plurality of demultiplexers DM1, DM2, ... DMN. The first converters T1_1 , T1_2 , ... T1_N shift some bits of the plurality of first signals X1 , X2 , ... XN according to the division selection signal DSi. When the division selection signal DSi is a signal corresponding to division by 1 (a signal corresponding to not division), the first conversion units T1_1, T1_2, ... T1_N may convert the first signals X1, X2, . .. XN) outputs all bits without shifting.

The number of bits of the first signals X1, X2, ... XN is N (N is an even number of 8 or more), the number of bits of the second signal Yi is N, and the division selection signal DSi is divided into two. If it is a corresponding signal, the first conversion units T1_1, T1_2, ... T1_N shift the most significant (N/2) bits of the first signals X1, X2, ... XN by (N/2) bits and shift the least significant (N/2) bits of the first signals X1, X2, ... XN by 0 bits.

The number of bits of the first signals X1, X2, ... XN is N (N is 8 or more and is a multiple of 4), the number of bits of the second signal Yi is N, and the division selection signal DSi If is a signal corresponding to division by 4, the first transforming units T1_1, T1_2, ... T1_N may convert N to (N*3/4+1) of the first signals X1, X2, ... XN. Bit shift (N*3/4) bits, and (N*3/4) to (N*2/4+1) bits of the first signals (X1, X2, ... XN) to (N* 2/4) bit shift, and (N*1/4) bits of (N*2/4) to (N*1/4+1) bits of the first signals X1, X2, ... XN is shifted, and (N*1/4) to 1 bits of the first signals X1, X2, ... XN are shifted by 0 bits.

The plurality of demultiplexing units DM1, DM2, ... DMN includes outputs of the first transform units T1_1, T1_2, ... T1_N and bits Yi[1] of the second signal Yi among zeros. , Yi[2], ... Yi[N]) and outputs the selected signals, respectively.

The shift operation unit 120_i includes a plurality of second transform units T2_1 , T2_2 , ... T2_N and a plurality of shift units SH1 , SH2 , ... SHN. The second conversion units T2_1 , T2_2 , ... T2_N set some bits of the first signal Xi to 0 according to the division selection signal DSi.

When the division selection signal DSi is a signal corresponding to division by 1 (a signal corresponding to not division), the second conversion units T2_1, T2_2, ... T2_N convert some bits of the first signal Xi. Do not set to 0.

If the number of bits of the first signal Xi is N (N is an even number of 8 or more), the number of bits of the second signal Yi is N, and the division selection signal DSi is a signal corresponding to division into two, the second transformation The parts T2_1, ... T2_(N/2) control the most significant (N/2) bits of the first signal Xi to be 0, and the second transform units T2_(N/2+1), ... T2_N) controls the least significant (N/2) bits of the first signal Xi to be 0.

If the number of bits of the first signal Xi is N (N is 8 or more and is a multiple of 4), the number of bits of the second signal Yi is N, and the division selection signal DSi is a signal corresponding to division by 4 , the second conversion units T2_1, ... T2_(N*1/4)) control the most significant (N*3/4) bits of the first signal Xi to be 0, and the second conversion units T2_ (N*1/4+1), ... T2_(N*2/4)) is the most significant (N*2/4) bits and the least significant (N*1/4) bits of the first signal Xi are controlled to be 0, and the second conversion units T2_(N*2/4+1), ... T2_(N*3/4)) are the most significant (N*1/4) of the first signal Xi. ) bits and the least significant (N*2/4) bits are controlled to be 0, and the second conversion units T2_(N*3/4+1), ... T2_N) are the least significant bits of the first signal Xi. (N*3/4) Controls bits to be 0.

The plurality of shift units SH1 , SH2 , ... SHN are the bits of the second signal Yi among the signals from which the outputs of the second transform units T2_1 , T2_2 , ... T2_N are shifted and 0 The signals selected according to Yi[1], Yi[2], ... Yi[N]) are respectively output.

Any one of the selection operation unit 110_i and the shift operation unit 120_i operates according to the selection signal SFi.

Fig. 6 is a diagram showing a parallel processing apparatus according to the fourth embodiment. Referring to FIG. 6 , the parallel processing unit receives first to Pth inputs {X1, Y1}, ... {X(p-1), Y(p-1)}, {Xp, Yp}, { X(p+1), Y(p+1)}, ... {XP, YP}) are received, and the first to Pth outputs M1, ... M(p-1), Mp, Output M(p+1) ... MP). Here, P means a natural number equal to or greater than 4, for example, P may be 1024. In addition, p means a natural number that is 1 or more and P or less. 1st to Pth inputs ({X1, Y1}, ... {X(p-1), Y(p-1)}, {Xp, Yp}, {X(p+1), Y(p +1)}, ... {XP, YP}) are the first signals X1, ... X(p-1), Xp, X(p+1), ... XP) and the second signal and Y1, ... Y(p-1), Yp, Y(p+1) ... YP. The parallel processing apparatus includes a preprocessing unit 100C and a main processing unit 200A. The parallel processing apparatus may further include a delay unit 300A and a selection unit 400A.

The preprocessor 100C includes a plurality of preprocessing units ... 150C_(p-1), 150C_p, 150C_(p+1), ...). The plurality of preprocessing units (... 150C_(p-1), 150C_p, 150_C(p+1), ...) are selected from the selection operators (... 110C_(p-1), 110C_p, 110C_(p+). 1), ...) and shift operation units (... 120C_(p-1), 120C_p, 120C_(p+1), ...). The preprocessing unit 150C_p includes a selection operation unit 110C_p and a shift operation unit 120C_p.

The selection operation unit 110C_p operates when the pre-processing unit 150C_p operates in the summing mode. The selection operation unit 110C_p includes a first signal Xp corresponding to the preprocessing unit 150C_p and first signals adjacent thereto (eg, X(p-Q/2+1), ... X(p-1), X (p+1), ... X(p+Q/2) according to the bits of the second signal Yp (Yp[1], Yp[2], ... Yp[Q]). The first signal Xp and adjacent first signals (eg, X(p-Q/2+1), ... X(p-1) , X(p+1), ... X(p+Q/2)) is shifted and passed to the summer, where Q means an even number greater than or equal to 4, for example, Q may be 32 Also, q means a natural number greater than or equal to 1 and less than or equal to Q.

The shift operation unit 120C_p operates when the pre-processing unit 150C_p operates in the multiplication mode. The shift operation unit 120C_p calculates the signals ((Xp<<0), (Xp<<1), ... ( Xp<<(Q-1))) to the summer SUMp according to the bits Yp[1], Yp[2], ... Yp[Q]) of the second signal Yp, Controls some bits of the shifted signals ((Xp<<0), (Xp<<1), ... (Xp<<(Q-1))) to become 0 according to the division selection signal DSi .

The preprocessing unit 150C_p operates the selection operation unit 110C_p or the shift operation unit 120C_p according to the operation mode selection signal SFp.

Those of ordinary skill in the art can sufficiently predict the detailed operations of the selection operation unit 110C_p and the shift operation unit 120C_p with reference to the second and third embodiments, so for convenience of description, a detailed description thereof is provided. omit Operations of the main processing unit 200A, the delay unit 300A, and the selection unit 400A are the same as those of FIG. 3 and the description thereof, and thus will be omitted for convenience of description.

Claims (14)

a pre-processing unit including pre-processing units and receiving first and second signals; and
a main processing unit including summers;
Each pre-processing unit among the pre-processing units includes a shift operation unit,
The shift operation unit transfers the shifted signals of a corresponding first signal from among the first signals to a corresponding summer among the summers according to bits of a corresponding second signal among the second signals, A parallel processing device for controlling some bits of the shifted signals to be 0 according to a signal. The method of claim 1,
When the number of bits of the corresponding first signal is N (N is an even number equal to or greater than 8), the number of bits of the corresponding second signal is N, and the division selection signal is a signal corresponding to division by two, the shift operation unit is The corresponding first signal is controlled so that the most significant (N/2) bits of the signals shifted by 0 bits to (N/2-1) bits become 0, and the corresponding first signal is controlled to be 0 bits to (N/2) bits to (N/2) bits N-1) A parallel processing device that controls the least significant (N/2) bits of the bit-shifted signals to be 0. 3. The method of claim 2,
If the number of bits of the corresponding first signal is N (N is an even number greater than or equal to 8), the number of bits of the corresponding second signal is N, and the division selection signal is a signal corresponding to division by two, the corresponding summer the most significant N bits of the output of the corresponding first signal correspond to the product of the most significant (N/2) bits of the corresponding first signal and the most significant (N/2) bits of the corresponding second signal, The least significant N bits of the output correspond to the product of the least significant (N/2) bits of the corresponding first signal and the least significant (N/2) bits of the corresponding second signal. The method of claim 1,
If the number of bits of the corresponding first signal is N (N is greater than or equal to 8 and is a multiple of 4), the number of bits of the corresponding second signal is N, and the division selection signal is a signal corresponding to division by 4, the The shift operation unit controls the most significant (N*3/4) bits of the signals shifted from 0 bits to (N*1/4-1) bits of the corresponding first signal to be 0, and the corresponding first signal is (N*1/4) bit to (N*2/4-1) bit-shifted signals, controlling the most significant (N*2/4) bits and least significant (N*1/4) bits to be 0, Most significant (N*1/4) bits and least significant (N*2/4) bits of the signals in which the corresponding first signal is shifted by (N*2/4) bits to (N*3/4-1) bits Parallel processing for controlling to be 0, and controlling the least significant (N*3/4) bits of the signals in which the corresponding first signal is shifted by (N*3/4) bits to (N-1) bits to be 0 Device. 5. The method of claim 4,
If the number of bits of the corresponding first signal is N (N is greater than or equal to 8 and is a multiple of 4), the number of bits of the corresponding second signal is N, and the division selection signal is a signal corresponding to division by 4, the 2N to (N*3/2+1) bits of the output of the corresponding summer are N to (N*3/4+1) bits of the corresponding first signal and N to (N*3/4+1) bits of the corresponding second signal (N*3/4+1) bits correspond to a product of bits, and (N*3/2) to (N*2/2+1) bits of the output of the corresponding summer are the corresponding first signal Corresponds to the product of (N*3/4) to (N*2/4+1) bits of and (N*3/4) to (N*2/4+1) bits of the corresponding second signal and (N*2/2) to (N*1/2+1) bits of the output of the corresponding summer are (N*2/4) to (N*1/ 4+1) bits and (N*2/4) to (N*1/4+1) bits of the corresponding second signal, corresponding to the product of (N*2/4) to (N*1/4+1) bits of the output of the corresponding summer 1/2) to 1 bits are parallel corresponding to the product of (N*1/4) to 1 bits of the corresponding first signal and (N*1/4) to 1 bits of the corresponding second signal processing unit. The method of claim 1,
The shift operation unit includes conversion units and shift units,
The converters set some bits of the first signal to 0 according to the division selection signal,
The shift units are parallel processing units for outputting signals selected according to bits of the second signal from among the shifted signals and 0's of the outputs of the converters. The method of claim 1,
Each of the pre-processing units further includes a selection operation unit,
The selection operation unit operates when a corresponding pre-processing unit among the pre-processing units operates in a summing mode, and transmits the first signals to the corresponding summer according to bits of the corresponding second signal, wherein the division Shifting some bits of the first signals according to a selection signal and transferring them to the corresponding summer,
The shift operation unit operates when the corresponding pre-processing unit operates in a multiplication mode. 8. The method of claim 7,
When the number of bits of the first signals is N (N is an even number greater than or equal to 8), the number of bits of the corresponding second signal is N, and the division selection signal is a signal corresponding to division into two, the selection operation unit is the first A parallel processing device for shifting most significant (N/2) bits of signals (N/2) bits and shifting least significant (N/2) bits of the first signals by 0 bits and passing them to the corresponding summer. 9. The method of claim 8,
If the number of bits of the first signals is N (N is an even number greater than or equal to 8), the number of bits of the corresponding second signal is N, and the division selection signal is a signal corresponding to division by 2, then the most significant N of the output of the summing unit The bits correspond to the sum of most significant (N/2) bits of first signals selected according to the corresponding second signal among the first signals, and the least significant N bits of the output of the summing unit are selected from among the first signals. A parallel processing device corresponding to the sum of least significant (N/2) bits of the first signals selected according to the corresponding second signal. 8. The method of claim 7,
If the number of bits of the first signals is N (N is greater than or equal to 8 and is a multiple of 4), the number of bits of the corresponding second signal is N, and the division selection signal is a signal corresponding to division by 4, the selection operation addition shifts N to (N*3/4+1) bits of the first signals (N*3/4) bits, and (N*3/4) to (N*2/4+) bits of the first signals 1) bit shifting (N*2/4) bits, and shifting (N*1/4) bits of (N*2/4) to (N*1/4+1) bits of the first signals, A parallel processing device for shifting (N*1/4) to 1 bits of the first signals by 0 bits and transferring them to the corresponding summer. 11. The method of claim 10,
If the number of bits of the first signals is N (N is greater than or equal to 8 and is a multiple of 4), the number of bits of the corresponding second signal is N, and the division selection signal is a signal corresponding to division by 4, the summing unit 2N to (N*3/2+1) bits of the output correspond to the sum of N to (N*3/4+1) bits of first signals selected according to the corresponding second signal among the first signals and (N*3/2) to (N*2/2+1) bits of the output of the summing unit are (N*3/) bits of the first signals selected according to the corresponding second signal among the first signals. 4) to (N*2/4+1) correspond to the sum of bits, and (N*2/2) to (N*1/2+1) bits of the output of the summing unit are Corresponds to the sum of (N*2/4) to (N*1/4+1) bits of the first signals selected according to the corresponding second signal, and (N*1/2) to 1 of the output of the summing unit The bits correspond to the sum of (N*1/4) to 1 bits of the first signals selected according to the corresponding second signal among the first signals. 8. The method of claim 7,
The selection operation unit includes transformation units and demultiplexing units,
The converters shift some bits of the first signals according to the division selection signal,
The demultiplexing units output signals selected according to bits of the second signal from among outputs of the transform units and 0's. The method of claim 1,
Each of the pre-processing units further includes a selection operation unit,
The selection operation unit operates when a corresponding pre-processing unit of the pre-processing units operates in the summation mode, and performs the corresponding first signals among the first signals according to bits of the corresponding second signal. transfer to the summer, shifting some bits of the corresponding partial first signals according to the division selection signal and transferring the bits to the corresponding summer;
The shift operation unit operates when the corresponding pre-processing unit operates in a multiplication mode. The method of claim 1,
a delay unit for delaying and outputting outputs of the summers according to a clock signal; and
The parallel processing apparatus further comprising: a selector configured to output, as the first signals, signals respectively selected according to input control signals from among the signals transmitted from the memory and the signals output from the delay unit.

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