KR20220143536A - Method and apparatus for determining a self-test inserting node for a scan chain - Google Patents

Abstract

Disclosed are a method for determining an insertion node for a self-test of a scan chain and an apparatus therefor. According to an embodiment of the present invention, the method for determining an insertion node for a self-test of a scan chain may comprise: a step of determining one or more control point candidates by considering a control burden index for each of a plurality of nodes included in a scan chain; a step of determining one or more observation point candidates different from the control point candidates by considering an observation burden index on each of the plurality of nodes included in the scan chain; a step of generating control point-observation point pair candidates by using the control point candidates and the observation point candidates; and a step of determining an insertion node for a self-test of the scan chain for the control point-observation point pair candidates to be inserted. The present invention is able to greatly reduce test cost.

Description

METHOD AND APPARATUS FOR DETERMINING A SELF-TEST INSERTING NODE FOR A SCAN CHAIN

The present invention relates to a method for determining an insertion node for self-testing of a scan chain. More particularly, the present invention relates to a method for determining a control point and an observation point insertion node for self-testing of a scan chain.

The content described in this section merely provides background information for the present embodiment and does not constitute the prior art.

As safety-critical and mission-critical fields such as automotive, medical, and aerospace grow, the safety and reliability of semiconductors used in these fields are also becoming more important.

Semiconductors put into the field must be guaranteed to be free from defects, not only during production, but also during use. To this end, most semiconductors employ self-test with built-in logic so that they can test themselves, and research to reduce the cost is being actively conducted.

Research using the PRPG inserted in the logic built-in self-test by sharing it with a decompressor used when applying an external test. Researches have been conducted to compress and observe with one scan cell.

Studies related to the test point area have been mainly conducted on the control point (CP), and for the observation point (OP), only the degree of data compression using the XOR gate has been studied, so research related to OP optimization was insufficient.

Embodiments of the present invention reduce the area overhead of logic for testing by introducing a test point of a new structure, and as a result, enable higher quality self-test through the secured area margin.

In the present invention, the area overhead can be reduced by inserting each pair of test points as a combined test point, and the corresponding test point pair can be found by analyzing the logic cone. As the number of combined test points increases, the area overhead becomes very small, leaving room for more test points or test logic targeting other issues such as X-masking. Since the area overhead is less and the functions are the same, the density of test logic is increased.

Other objects not specified in the present invention may be additionally considered within the scope that can be easily inferred from the following detailed description and effects thereof.

In order to solve the above problems, a method for determining an insertion node for self-test of a scan chain according to an embodiment of the present invention includes a method for determining an insertion node for self-test of a scan chain in a built-in self-test circuit performed by a processor calculating a control burden index for each node for a plurality of nodes included in the scan chain, and determining at least one control point candidate according to the calculated control burden index; calculating an observation burden index for each node for a plurality of nodes included in the scan chain, and determining at least one observation point candidate different from a control point candidate according to the calculated observation burden index; generating control point-observation point pair candidates using the control point candidate and the observation point candidate; and determining an insertion node for self-test of a scan chain into which the control point-observation point pair candidate is to be inserted.

Here, the control point-observation point pair candidate is characterized in that it consists of a control point candidate and an observation point candidate having complementarity.

Here, the determining of the observation point candidate includes the control point candidate and the control point candidate located at the input terminal of a fan-out free gate connected from a node different from the control point candidate, and at the same time a node different from the control point candidate In the case in which a fault propagates is blocked, a node different from the control point candidate is excluded from the observation point candidate.

Here, the control burden index is calculated based on the following <Equation>,

<Equation>

(for CP-1)

(for CP-1)

(for CP-0)

(for CP-0)

CP _Burden represents the control burden index, and |BlockedFaults| represents the number of failures in which propagation is blocked when the value of the node into which the corresponding control point (CP) is inserted is '0' or '1'. Ctrl indicates the probability of '1' appearing at the node,

The observation burden index is,

It is calculated according to the <Equation> below,

<Equation>

OP _Burden represents the observation burden index, |FaninCone| represents the number of failures that exist inside the logic cone connected to the input terminal of the gate into which the corresponding observation point (OP) is inserted, and Obs is the number of failures of the corresponding node. It is characterized in that it is propagated to the output of the circuit and means the probability that the user can observe it.

Here, the step of determining the insertion node for the self-test of the scan chain is characterized in that the complementary control point-observation point pair is inserted into the determined insertion node.

Here, the step of determining the control point candidate includes determining at least one node belonging to the first threshold range having a predetermined control burden index as a control point candidate, and the determining of the observation point candidate includes: It is characterized in that at least one node belonging to the second threshold range is determined as an observation point candidate.

Here, the control point-observation point pair candidate includes the control point candidate and the observation point candidate, and two gates are connected between the control point candidate and the observation point candidate.

Here, the two gates include a first gate that is an AND gate that connects the node determined as the control point candidate to an input terminal, and a second gate that is an OR gate that connects the output of the first gate to an input terminal. do.

Here, the step of determining the observation point candidate comprises:

Determining the node providing the closest value to the control capability calculated according to the following <Equation> as the observation point candidate,

<Equation>

(for CP-1)

(for CP-1)

(for CP-0)

(for CP-0)

Ctrlreq represents a control capability value required to propagate failures related to the node of the corresponding control point (CP), B represents the number of '1's required to propagate failures related to the control point candidate node, and b is Indicates the number of '0's required to propagate a failure related to the control point candidate node, and |FaninCone| indicates the number of failures existing inside a logic cone connected to the input terminal of the corresponding control point (CP). , CP-1 indicates the type of control point for controlling as 1, and CP-0 indicates the type of control point for controlling as 0.

A computer program according to a preferred embodiment of the present invention for achieving the above technical problem is stored in a computer-readable storage medium, and any one of the insertion node determination methods for self-test of the scan chain is executed in the computer.

In order to achieve the above object, an insertion node determination device for self-test of a scan chain according to a preferred embodiment of the present invention is an insertion node determination device for self-test of a scan chain, and an insertion node for self-test of the scan chain a memory storing one or more programs for determining and one or more processors that perform an operation for determining an insertion node for self-test of a scan chain according to the one or more programs stored in the memory, wherein the processor includes a plurality of nodes included in the scan chain. determining at least one control point candidate in consideration of the control burden index for each node; determining at least one observation point candidate different from the control point candidate in consideration of the observation burden index for each node with respect to a plurality of nodes included in the scan chain; generating control point-observation point pair candidates using the control point candidate and the observation point candidate; and determining an insertion node for self-test of the scan chain in consideration of the control burden index and the observation burden index of the control point-observation point pair candidates.

Here, the determining of the observation point candidate includes the control point candidate and the control point candidate located at the input terminal of a fan-out free gate connected from a node different from the control point candidate, and at the same time a node different from the control point candidate In the case in which a fault propagates is blocked, a node different from the control point candidate is excluded from the observation point candidate.

Here, the control point-observation point pair candidate includes the control point candidate and the observation point candidate, and two gates are connected between the control point candidate and the observation point candidate.

Here, the control burden index is calculated based on the following <Equation>,

<Equation>

(for CP-1)

(for CP-1)

(for CP-0)

(for CP-0)

CP _Burden represents the control burden index, and |BlockedFaults| represents the number of failures in which propagation is blocked when the value of the node into which the corresponding control point (CP) is inserted is '0' or '1'. Ctrl indicates the probability of '1' appearing at the node,

The observation burden index is,

It is calculated according to the <Equation> below,

<Equation>

OP _Burden represents the observation burden index, |FaninCone| represents the number of failures that exist inside the logic cone connected to the input terminal of the gate into which the corresponding observation point (OP) is inserted, and Obs represents the number of failures in the corresponding node. It is characterized in that it is propagated to the output of the circuit and means the probability that the user can observe it.

According to an embodiment of the present invention, the function of inserting the existing individual test points in the self-test environment within the logic is maintained through the test points of the new structure, but the test cost can be greatly reduced by greatly reducing the area overhead.

In addition, according to an embodiment of the present invention, if the reduced area cost is used for other test costs, the quality of the self-test can be improved.

Even if effects not explicitly mentioned herein, the effects described in the following specification expected by the technical features of the present invention and their potential effects are treated as described in the specification of the present invention.

1 is a block diagram schematically showing the structure of a basic logic built-in self-test system as a prior art.
2 is a convex configuration diagram schematically illustrating a structure in which an insertion node determining device for self-test of a scan chain is connected to a logic-embedded self-test system according to a preferred embodiment of the present invention.
3 is a block diagram schematically showing the structure of a processor of a logic self-test built-in circuit according to a preferred embodiment of the present invention.
4 is a flowchart illustrating a method of determining an insertion node for self-test of a scan chain according to a preferred embodiment of the present invention.
5 is a diagram for explaining an example of a control point with complementarity according to a preferred embodiment of the present invention.
6 is a view for explaining an example of an observation point with complementarity according to a preferred embodiment of the present invention.
7 is a diagram for explaining an example of inserting a coupling point for a control point-observation point pair with complementarity according to a preferred embodiment of the present invention.
8 is a diagram for explaining Algorithm 1 for finding a node that can be used as a control point-observation point pair according to a preferred embodiment of the present invention.
9 is a diagram for explaining Algorithm 2 for excluding observation points that cannot constitute a control point-observation point pair according to a preferred embodiment of the present invention.
10 is a diagram for explaining an example of an observation point that cannot constitute a control point-observation point pair according to a preferred embodiment of the present invention.
11 is a diagram for explaining an example of an observation point that cannot constitute a control point-observation point pair according to a preferred embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments published below, but may be implemented in various different forms, and only the present embodiments allow the publication of the present invention to be complete, and are common in the technical field to which the present invention pertains. It is provided to fully inform those with knowledge of the scope of the invention, and the present invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout.

Unless otherwise defined, all terms (including technical and scientific terms) used herein may be used with the meaning commonly understood by those of ordinary skill in the art to which the present invention belongs. In addition, terms defined in a commonly used dictionary are not to be interpreted ideally or excessively unless clearly specifically defined.

In the present specification, terms such as “first” and “second” are for distinguishing one component from other components, and the scope of rights should not be limited by these terms. For example, a first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

In the present specification, identification symbols (eg, a, b, c, etc.) in each step are used for convenience of description, and identification numbers do not describe the order of each step, and each step is clearly specified in a specific order in context. Unless stated otherwise, it may occur differently from the specified order. That is, each step may occur in the same order as specified, may be performed substantially simultaneously, or may be performed in the reverse order.

In this specification, expressions such as “have”, “may have”, “include” or “may include” indicate the presence of a corresponding feature (eg, a numerical value, function, operation, or component such as a part). and does not exclude the presence of additional features.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a preferred embodiment of a method and apparatus for determining an insertion node for self-testing of a scan chain of a logic self-test embedded circuit performed by a processor according to the present invention will be described in detail with reference to the accompanying drawings.

First, the problems of the prior art will be described first with reference to FIG. 1 .

1 is a block diagram schematically showing the structure of a basic logic built-in self-test system as a prior art.

1, the logic built-in self-test system applies the pseudo-random pattern generated by the PRPG (Pseudo Random Pattern Generator) 100 to the scan chain 110 and compares the signature of the MISR 120 with the previously stored signature. Determine whether there is a fault in the circuit. If Random Pattern Resistant Faults exist in the circuit, the faults are difficult to detect by the random pattern, and eventually lead to deterioration of test coverage.

Here, the scan chain 110 refers to hardware that helps apply a test pattern to a logic gate in a circuit, but is not limited thereto.

The test point increases the likelihood that a random pattern immunity fault will be detected. The propagation of random pattern-tolerant faults can be facilitated by inserting a control point (CP), and by inserting an observation point (OP), unobserved faults can be directly observed. The additional logic required per control point (CP) is two gates and one flip-flop, and observation point (OP) requires one flip-flop insertion. The area occupied by the test point occupies a high proportion of 30-50% of the logic embedded self-test.

The test point preferably refers to, but is not limited to, a location in an electronic circuit used to monitor the state of the circuit or inject a test signal.

2 is a convex configuration diagram schematically illustrating a structure in which an insertion node determining device for self-test of a scan chain is connected to a logic-embedded self-test system according to a preferred embodiment of the present invention.

The insertion node determining device 300 for self-test of the scan chain according to the present embodiment is performed by the processor 310 and includes a Pseudo Random Pattern Generator (PRPG) 220, a Phase Shifter 230, and a MISR ( 240 ), a built-in self-test 250 , and a scan chain 260 may be connected to a built-in logic self-test system. Not all blocks shown in FIG. 2 are essential components, and in another embodiment, some blocks included in the insertion node determining device 300 for self-test of the scan chain may be added, changed, or deleted. On the other hand, the insertion node determination device 300 for self-test of the scan chain may be implemented as a computing device that determines the insertion node for self-test of the scan chain, and the insertion node determination device 300 for self-test of the scan chain ) may be implemented as separate software devices, or as separate hardware devices combined with software.

The insertion node determining device 300 for self-test of the scan chain applies the pseudo random pattern generated by the PRPG (Pseudo Random Pattern Generator) 220 to the scan chain 110 through the Phase Shifter 230 . The signature of the MISR 240 is compared with a previously stored signature to determine whether a circuit has failed, but the present invention is not limited thereto.

The insertion node determining device 300 for self-test of the scan chain is described as being a separate device from the logic-embedded self-test system, but is not necessarily limited thereto, and may be implemented as a module included in the system shown in FIG. 2 . have. For example, the insertion node determining apparatus 300 for self-test of the scan chain may be implemented as a node determining module (not shown) for determining the insertion node.

The processor 310, which performs the entire algorithm, checks all the test points before inserting the test points to determine the points that can be paired with each other and the points to be individually inserted, and is not inserted into the circuit. It exists outside, but is not necessarily limited thereto.

3 is a block diagram schematically showing the structure of a processor of a built-in self-test circuit according to a preferred embodiment of the present invention.

The processor 310 of the apparatus 300 for determining an insertion node for self-test of a scan chain according to the present embodiment performs an operation for determining an insertion node. The processor 310 according to the present embodiment may include a first determiner 311 , a second determiner 312 , a pair candidate generator 233 , and a third determiner 314 . The processor 310 of FIG. 3 is according to an embodiment, and not all blocks shown in FIG. 3 are essential components, and in other embodiments, some blocks included in the processor 310 may be added, changed, or deleted. have. Meanwhile, each component included in the processor 310 may be implemented as a separate software device or as a separate hardware device combined with software.

The first determiner 311 calculates a control burden index for each node for a plurality of nodes included in the scan chain 260, and determines at least one control point candidate according to the calculated control burden index. It is preferred, but not necessarily limited thereto.

Controllability refers to the probability that a corresponding node can have a logic '1' value. If the control ability value is low, it means that the probability of '1' is low, and if it is high, the probability of '0' is low. The sum of the probability of a '1' and the probability of a '0' is always 1. Therefore, the probability that '0' appears in the corresponding node can be expressed as 1-Ctrl. The control burden index refers to an index calculated through control capability, which is a probability value, in order to find a node to insert a control point (CP).

A control point (CP) is inserted into a node whose value is almost fixed as '1' or '0', and is hardware that helps the node to have both '1' and '0' values. There are two types, CP-0 and CP-1. For example, if the value of node A is only '0', CP-1 is inserted to make '1'. At this time, when the value of the existing node A is fixed to 0, the greater the number of failures in which radio waves are blocked, the greater the importance of the corresponding control point CP.

The test point insertion targets all logic gates except the scan chain, and the scan chain is hardware that helps apply the test pattern to the logic gates in the circuit, so the meaning of a plurality of nodes included in the scan chain is under the jurisdiction of the scan chain. It means a plurality of logic gate nodes, but is not necessarily limited thereto.

The second determination unit 312 calculates an observation burden index for each node for a plurality of nodes included in the scan chain 260, and according to the calculated observation burden index, at least one observation different from the control point candidate It is preferable to determine a point candidate, but the present invention is not limited thereto.

Preferably, the pair candidate generator 313 generates control point-observation point pair candidates by using the control point candidate and the observation point candidate, but is not limited thereto.

The third determining unit 314 determines an insertion node for self-testing of the scan chain into which the control point-observation point pair candidates are to be inserted, in consideration of the control burden index and the observation burden index of the control point-observation point pair candidates. Preferably, but not necessarily limited thereto.

The memory unit 320 performs a function of storing one or more processors that perform an operation for determining an insertion node for self-test of the scan chain.

As an embodiment of the present invention, a memory storing one or more programs for determining an insertion node for self-test of a scan chain and determining an insertion node for self-test of a scan chain according to the one or more programs stored in the memory for determining at least one control point candidate in consideration of the control burden index for each node with respect to a plurality of nodes included in the scan chain, wherein the processor determines at least one control point candidate The first determining unit 311 performing the step determines at least one observation point candidate different from the control point candidate by considering the observation burden index for each node with respect to a plurality of nodes included in the scan chain. a second determiner 312 performing the step of performing the step of generating a control point-observation point pair candidate using the control point candidate and the observation point candidate, and a pair candidate generator 313 performing the step of generating the control point- In consideration of the control burden index and the observation burden index of the observation point pair candidates, the third determination unit 314 performs the step of determining the insertion node for the self-test of the scan chain into which the control point-observation point pair candidates are to be inserted. We propose a device for determining an insertion node for self-test of a scan chain, characterized in that each operation is performed.

4 is a flowchart illustrating a method of determining an insertion node for self-test of a scan chain according to a preferred embodiment of the present invention.

In step S110, the processor 310 calculates a control burden index for each node for a plurality of nodes included in the scan chain, and determines at least one control point candidate according to the calculated control burden index. carry out

In step S120, the processor 310 calculates an observation burden index for each node for a plurality of nodes included in the scan chain, and at least one observation point different from the control point candidate according to the calculated observation burden index Steps to determine a candidate are performed.

In step S130 , the processor 310 generates control point-observation point pair candidates by using the control point candidate and the observation point candidate.

In step S140, the processor 310 considers the control burden index and the observation burden index of the control point-observation point pair candidates, and determines the insertion node for the self-test of the scan chain into which the control point-observation point pair candidates are inserted. carry out

Although it is described that each step is sequentially executed in FIG. 4 , the present invention is not limited thereto. In other words, since it may be applicable by changing and executing the steps described in FIG. 4 or executing one or more steps in parallel, FIG. 4 is not limited to a time-series order.

The method for determining the insertion node for self-test of the scan chain according to the present embodiment described in FIG. 4 may be implemented as an application (or program) and recorded in a terminal device (or computer) readable recording medium. An application (or program) for implementing a method for determining an insertion node for self-test of a scan chain according to the present embodiment is recorded, and a terminal device (or computer) readable recording medium is data readable by a computing system It includes any kind of recording device or medium on which it is stored.

The pair candidate generation unit 313 of the processor 310 of the apparatus 300 for determining an insertion node for self-testing of the scan chain according to the present embodiment calculates the control point-observation point pair candidate's control burden index and observation burden index. In consideration of this, in the step of determining the insertion node for self-test of the scan chain into which the control point-observation point pair candidates are to be inserted, the case where the control point and the observation point have complementarity is determined as the insertion node. can

An embodiment of the present invention combines a complementary related control point (CP) and an observation point (OP) and inserts them into one test point, thereby improving the existing test quality using minimal additional logic. Suggest ways to improve.

First, the controllability and observability of each gate input and output of the gate-level synthesized circuit and the probability that a single fixed failure can be detected (failure detection rate) are calculated. Estimate the expected test coverage of In addition, controllability and observability are collectively referred to as testability.

In addition, by calculating the burden index (Burden) for each type, a control point (CP) is inserted into a node with a large control burden index (CP Burden) and an observation point (OP) is inserted into a node with a large observation burden index (OP Burden). Improve testability.

The first determining unit 311 of the processor 310 of the apparatus 300 for determining the insertion node for self-test of the scan chain according to the present embodiment calculates the control burden index according to the following <Equation 1>,

(for CP-0)

(for CP-0)

In Equation 1, the CP _Burden represents the control burden index, and the |BlockedFaults| is when the value of the node into which the corresponding control point (CP) is inserted is '0' or '1', propagation is blocked. The number of failures is indicated, and the Ctrl indicates controllability as the probability that '1' appears in the corresponding node.

The second determination unit 312 may calculate the control burden index according to the following <Equation 2>.

In Equation 2, the OP _Burden represents the observation burden index, and the |FaninCone| represents the number of failures existing inside the logic cone connected to the input terminal of the gate into which the corresponding observation point OP is inserted, The Obs represents the observability of the corresponding node.

Observability refers to the probability that the failure of the node is propagated to the output of the circuit and can be observed by the user. The observation burden index refers to an index calculated through the observation ability, which is a probability value, in order to find a node to insert an observation point (OP).

(for CP-1) 수학식을 통하여 제어부담지수가 산출되고, 제어 포인트가 삽입되는 노드의 값이 '1'인 경우, '0'으로 제어하기 위해

(for CP-0) 수학식을 통하여 제어부담지수가 산출된다.In the case of Equation 1, when the value of the node into which the control point is inserted is '0', in order to control it as '1'

(for CP-1) When the control burden index is calculated through the equation and the value of the node into which the control point is inserted is '1', in order to control it to '0'

(for CP-0) The control burden index is calculated through the equation.

In the case of a control point (CP), when the value of the node is concentrated at one value, the number of failures that block radio waves is large, and when the control ability is low, the value of the control burden index (CP Burden) increases. It becomes a strong candidate for inserting a control point (CP).

When the number of failures propagated through a node is large and the observability is low, the observation burden index (OP Burden) increases, making it a strong candidate for insertion of an observation point (OP).

5 is a diagram for explaining an example of a control point with complementarity according to a preferred embodiment of the present invention. 6 is a view for explaining an example of an observation point with complementarity according to a preferred embodiment of the present invention.

On the other hand, among the nodes requiring the insertion of the control point (CP), the control point insertion candidate node whose observability is higher than the threshold set by the designer and the observation point insertion with excellent controllability among the nodes requiring the insertion of the observation point (OP) If there is a candidate node, that is, a node whose controllability is within the critical range set by the designer, it can be expressed that the two are complementary.

That is, a control point insertion candidate node having an observation capability higher than a threshold set by a designer and lacking in control capability may supplement the observation capability of an observation point insertion candidate node lacking in observation capability. In this case, if the control capability of the observation point insertion candidate node lacking the observation capability falls within the critical range set by the designer, the control capability of the control point insertion candidate node lacking the control capability can be supplemented. It can be expressed that there is

For example, if the threshold value of the observation capability set by the designer is 0.8, a control point insertion candidate node that has an observation capability higher than 0.8 but lacks control capability can compensate for the insufficient observation capability of the observation point insertion candidate node. . On the other hand, in this case, if the control capability of the observation point insertion candidate node with insufficient observation capability corresponds to 0.5 with a value between 0.3 and 0.7, which is the critical range of the control capability preset by the designer, it has excellent controllability. It can be said that these two are complementary because they can supplement the control ability of this insufficient control point insertion candidate node.

Effect of inserting two test points into one test point if joint test points are inserted to share mutual complementary capabilities without inserting test points into the control point insertion candidate node and the observation point insertion candidate node respectively can pay

In order to check the complementarity, the control point (CP) candidates are tested for observability and the observation point (OP) candidates are tested for controllability. If the observability of the control point (CP) candidate is greater than the threshold value, it is determined that there is complementarity as a control point (CP) candidate to be generated as a control point (CP)-observation point (OP) pair candidate. In the case of an observation point (OP) candidate, the control point (OP) candidate must be a value that corresponds to a value between the two critical values to be generated as a control point (CP)-observation point (OP) pair candidate. judged to be complementary.

For example, referring to FIG. 5 , in the x node 510 of FIG. 5 , the failure propagation is blocked 520 by some logic, so that the observability is low, while the output of the scan cell 500 is low. It has excellent controllability because it transmits For example, referring to FIG. 6 , the y-node 640 of FIG. 6 transfers the output of the 32-input AND gate 630 , so the logic '1' control capability (Ctrl_1) is low, while the scan cell 620 ) can propagate the failure, so the observability is high. A pair of test points in such a complementary relationship can share each other's capabilities through a binding point.

7 is a diagram for explaining an example of inserting a coupling point for a control point-observation point pair with complementarity according to a preferred embodiment of the present invention.

The pair candidate generator 313 of the processor 310 of the apparatus 300 for determining an insertion node for self-test of the scan chain according to the present embodiment includes a control point candidate and an observation point candidate as a control point-observation point pair candidate. Including, two gates are connected between the control point candidate and the observation point candidate to generate a control point-observation point pair candidate.

The pair candidate generator 313 of the processor 310 of the apparatus 300 for determining an insertion node for self-test of the scan chain according to the present embodiment generates two gates connected between the control point candidate and the observation point candidate. A control point-observation point pair candidate comprising a first gate that is an AND gate that connects the node determined as the control point candidate to an input terminal and a second gate that is an OR gate that connects the output of the first gate to an input terminal can be generated have.

Cone preferably means that the gate arrangement has a triangular shape, but is not limited thereto.

According to the direction of the triangular shape of the gate arrangement structure, it can be classified into a fan-in cone and a fan-out cone, and a fan-out free gate It is preferable to mean an output gate positioned at the end of the fan-out cone structure, but is not limited thereto.

For example, referring to FIG. 7 , the control logic for the y-node 720 is configured by connecting the x-node 730 with excellent controllability to the TP_Gating 750 input in order to use it as a CP driver. The value of xnode 730 propagates to path 1 through TP 760 to facilitate propagation of the Fan-in cone 770 failure of G ₂ 780 . At the same time, failures that have not been propagated through the existing x-node 730 are propagated to the scan cell 790 through the new path path_2, which facilitates observation. The area overhead is greatly reduced because the logic required to insert one coupled test point is only two gates. When the TP_Enable signal is turned OFF, it is converted to the normal operation mode (Functional Mode) rather than the test mode and operates the same as the existing circuit.

8 is a diagram for explaining Algorithm 1 for finding a node that can be used as a control point-observation point pair according to a preferred embodiment of the present invention. 9 is a diagram for explaining Algorithm 2 for excluding observation points that cannot constitute a control point-observation point pair according to a preferred embodiment of the present invention.

In the step of determining the insertion node for self-test of the scan chain according to the present embodiment, the first determining unit 311 of the processor 310 of the apparatus 300 determines the control point candidate, the control burden index is determined in advance. The step of determining at least one node belonging to one critical range as a control point candidate is performed, and the second determining unit 312 of the processor 310 determines the observation point candidate in the second predetermined observation burden index. Determining at least one node belonging to the critical range as an observation point candidate may be performed.

The first predetermined threshold range is set in advance by the designer to determine whether the control capability of the corresponding node corresponds to the control capability of the observation point (OP) candidate to be generated as a control point (CP)-observation point (OP) pair candidate. It refers to the threshold range (Ctrl_1 Threshold and Ctrl_0 Threshold).

The second predetermined threshold range is set in advance by the designer to determine whether the observation capability of the corresponding node corresponds to the observation capability of the control point (CP) candidate to be generated as a control point (CP)-observation point (OP) pair candidate. It means to exclude anything lower than the Obs Threshold.

The control burden index and the observation burden index are convenient indices for explaining the existing test point insertion method, and are not used in the algorithm proposed by the embodiment of the present invention, but control capability and observation capability threshold values are used, but are not necessarily limited thereto. .

Preferred threshold values and threshold ranges depend on the number of target test patterns, circuit design methods, and complexity. For example, the control capability of the observation point candidate node of any arbitrary circuit may be between 0.001 and 0.999. Preferably, the control capability of the observation point candidate node of any arbitrary circuit is between 0.2 and 0.8. The observability of the control point candidate node of any arbitrary circuit may be between 0.001 and 1. The observability of the control point candidate node is preferably between 0.7 and 1. Observation points whose control capability value is less than 0.2 or greater than 0.8 have a problem of poor complementarity as an observation point (OP) candidate to be generated as a control point (CP)-observation point (OP) pair candidate. If it is less than 0.7, there is a problem of poor complementarity as a control point (CP) candidate for generating a control point (CP)-observation point (OP) pair candidate. Points that do not complement the above two points must be inserted separately.

Pairs that can be inserted as binding test points are searched through the algorithms of FIGS. 8 and 9 . First, test point classification is performed through the algorithm of FIG. 8 in order to find a test point that can be used as a binding pair. In the case of a control point (CP) for a coupled pair, if the observability is lower than the threshold set by the designer (Obs Threshold) and is greater than 0, it is removed and the control point (CP) is easy to propagate failure through the corresponding path. leave only Similarly, the observation point (OP) node for the coupled pair should be easy to control the logic '0' and '1', so the observation point (OP) whose control ability is outside the critical range (Ctrl_1 Threshold and Ctrl_0 Threshold) set by the designer ) to leave only the nodes that are easy to control.

After the test point classification is finished, the observation point OP that cannot be combined for each control point CP is deleted through the logic cone analysis of the remaining control points CP. The corresponding algorithm is shown in FIG. 9 . If there is a fan-out free gate starting from the control point (CP) and a converging observation point (OP), add whether the observation point (OP) simultaneously controls the converging gate and control point (CP). Analyze. When the value of the observation point OP controls the control point CP, the failures of the Fan-out Free gate are propagated, and the observation point OP is simultaneously Fan-out Free. This is because, by controlling the gate, the failure propagation of the cone may be blocked.

10 is a diagram for explaining an example of an observation point that cannot constitute a control point-observation point pair according to a preferred embodiment of the present invention.

The second determining unit 312 of the processor 310 of the apparatus 300 for determining an insertion node for self-test of the scan chain according to the present embodiment determines the observation point candidate, the control point candidate and the control point candidate It is located at the input terminal of a fan-out free gate connected from a node other than the control point candidate and at the same time a control point candidate and another node block the path through which the failure propagates. exclusion can be done.

For example, referring to FIG. 10 , when the value of the x node 1020, which is the position of the observation point (OP), is '1', the y node 1010, which is the position of the control point (CP), is controlled to control the cone (Cone) ( 1050), at which time the fan-out free gate (G ₃ ) 1060 is simultaneously controlled by the observation point (OP) to block the only path through which the fault propagates. As a result, when Algorithm 2 of FIG. 9 is performed, an observation point (OP) candidate that causes failure to propagate is removed, and a combinable observation point (OP) candidate list for each control point (CP) is completed.

11 is a diagram for explaining an example of an observation point that cannot constitute a control point-observation point pair according to a preferred embodiment of the present invention.

When Algorithm 1 of FIG. 8 and Algorithm 2 of FIG. 9 are performed, the remaining observation point (OP) candidates become final candidates, and an additional process is required to find an optimal candidate.

By calculating the controllability required for the control point (CP) node, the observation point (OP) that can provide the most approximate value is determined as the final pair. Through the controllability shared from the observation point (OP), the fault propagation of the fan-out stage is advantageous, but at the same time, it blocks the propagation of other faults.

The second determination unit 312 of the processor 310 of the apparatus 300 determines an insertion node for self-test of the scan chain according to the present embodiment, in the step of determining the observation point candidate, according to the following <Equation 3> An insertion node determination method for self-testing of a scan chain, characterized in that a node providing the closest value to the calculated controllability is determined as the observation point candidate.

(for CP-0)

(for CP-0)

In Equation 3, the Ctrlreq represents a control capability value required to propagate failures related to the node of the corresponding control point (CP), and B represents a value of '1' required to propagate the failures related to the control point candidate node. represents the number, b represents the number of '0's required to propagate a failure related to the control point candidate node, and the |FaninCone| number, CP-1 indicates the type of control point for controlling as 1, and CP-0 indicates the type of control point for controlling as 0.

(for CP-1) 수학식을 통하여 제어능력값이 산출되고, 제어 포인트가 삽입되는 노드의 값이 '1'인 경우, '0'으로 제어하기 위해

(for CP-0)수학식을 통하여 제어능력값이 산출된다.In the case of Equation 3, when the value of the node into which the control point is inserted is '0', in order to control it as '1'

(for CP-1) When the control capability value is calculated through the equation and the value of the node into which the control point is inserted is '1', in order to control it to '0'

The control capability value is calculated through the (for CP-0) equation.

For example, referring to FIG. 11 , the observation point OP is located at the x node 1130 , and provides control capability to the y node 1160 through the TP 1120 . '1' In order to activate the failure of the cone ₃ (Cone ₃ ) 1180, the failure propagation was blocked by the G ₁ 1110, which is difficult to control, '1' is required in the x node 1130. In addition, in order to propagate the failure of the cone ₂ ( 1140 ) and the failure of the cone ₁ ( Cone ₁ ) ₁₀₀ , which was propagated through the existing control point (CP), '0' to the x node 1130 I need this. Here, by calculating how many '1's or '0s are needed, controllability required for the control point (CP) node is calculated.

Among the OP candidates, the OP having the closest value to the required controllability is finally combined with the corresponding control point (CP).

The test point removed in Algorithm 1 of FIG. 8 and the test point not paired in Algorithm 2 of FIG. 9 are inserted separately.

The operations according to the present embodiments may be implemented in the form of program instructions that can be performed through various computer means and recorded in a computer-readable storage medium. Computer-readable storage medium represents any medium that participates in providing instructions to a processor for execution. A computer-readable storage medium may include program instructions, data files, data structures, or a combination thereof. For example, there may be a magnetic medium, an optical recording medium, a memory, and the like. A computer program may be distributed over a networked computer system so that computer readable code is stored and executed in a distributed manner. Functional programs, codes, and code segments for implementing the present embodiment may be easily inferred by programmers in the technical field to which the present embodiment belongs.

The present embodiments are for explaining the technical idea of the present embodiment, and the scope of the technical idea of the present embodiment is not limited by these embodiments. The protection scope of this embodiment should be interpreted by the claims below, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present embodiment.

100: PRPG (Pseudo Random Pattern Generator)
110: scan chain 120: MISR
300: Insertion node determining device for self-test of scan chain
310: processor
311: first determining unit 312: second determining unit
313: pair candidate generating unit 314: third determining unit
220: PRPG (Pseudo Random Pattern Generator)
230: phase shifter 240: MISR
250: BIST (Built-In Self-Test)

Claims (13)

A method of determining an insertion node for self-test of a scan chain in an embedded self-test circuit performed by a processor, the method comprising:
calculating a control burden index for each node for a plurality of nodes included in the scan chain, and determining at least one control point candidate according to the calculated control burden index;
calculating an observation burden index for each node for a plurality of nodes included in the scan chain, and determining at least one observation point candidate different from a control point candidate according to the calculated observation burden index;
generating at least one control point-observation point pair candidate using the control point candidate and the observation point candidate; and
and determining an insertion node for self-test of a scan chain into which the control point-observation point pair candidate is to be inserted. According to claim 1,
The control point-observation point pair candidate is,
Characterized in that it consists of a control point candidate and an observation point candidate with complementarity,
How to determine the insertion node for self-testing of the scan chain. According to claim 1,
The step of determining the observation point candidate comprises:
When the control point candidate and the control point candidate are located at the input terminal of a fan-out free gate connected from a node different from the control point candidate, and at the same time, a node other than the control point candidate blocks a path through which a failure is propagated. Characterized in excluding nodes other than control point candidates from observation point candidates,
How to determine the insertion node for self-testing of the scan chain. According to claim 1,
The control burden index is,
It is calculated based on the <Equation> below,
<Equation>

(for CP-1)

(for CP-0)
CP _Burden represents the control burden index, and |BlockedFaults| represents the number of failures in which propagation is blocked when the value of the node into which the corresponding control point (CP) is inserted is '0' or '1'. Ctrl indicates the probability of '1' appearing at the node,
The observation burden index is,
It is calculated according to the <Equation> below,
<Equation>

OP _Burden represents the observation burden index, |FaninCone| represents the number of failures that exist inside the logic cone connected to the input terminal of the gate into which the corresponding observation point (OP) is inserted, and Obs represents the number of failures of the corresponding node. Characterized in that it propagates to the output of the circuit and means the probability that the user can observe it,
How to determine the insertion node for self-testing of the scan chain. According to claim 1,
The step of determining the control point candidate comprises:
Determining at least one node belonging to the first threshold range in which the control burden index is predetermined as a control point candidate,
The step of determining the observation point candidate comprises:
Characterized in that the observation burden index determines at least one node belonging to a predetermined second threshold range as an observation point candidate,
How to determine the insertion node for self-testing of the scan chain. According to claim 1,
The control point-observation point pair candidate is,
including the control point candidate and the observation point candidate,
Two gates are connected between the control point candidate and the observation point candidate,
How to determine the insertion node for self-testing of the scan chain. 7. The method of claim 6,
The two gates are
characterized in that it consists of a first gate that is an AND gate that connects the node determined as the control point candidate to an input terminal, and a second gate that is an OR gate that connects the output of the first gate to an input terminal,
How to determine the insertion node for self-testing of the scan chain. According to claim 1,
The step of determining the observation point candidate comprises:
Determining the node providing the closest value to the control capability calculated according to the following <Equation> as the observation point candidate,
<Equation>

(for CP-1)

(for CP-0)
Ctrlreq represents a control capability value required to propagate failures related to the node of the corresponding control point (CP), B represents the number of '1's required to propagate failures related to the control point candidate node, and b is Indicates the number of '0's required to propagate a failure related to the control point candidate node, and |FaninCone| indicates the number of failures existing inside a logic cone connected to the input terminal of the corresponding control point (CP). , CP-1 indicates the type of control point for controlling as 1, and CP-0 indicates the type of control point for controlling as 0,
How to determine the insertion node for self-testing of the scan chain. A computer program stored in a computer-readable storage medium for executing the method of determining an insertion node for self-test of a scan chain according to any one of claims 1 to 8 in a computer. An insertion node determining device for self-testing of a scan chain, comprising:
a memory storing one or more programs for determining an insertion node for self-testing of the scan chain; and
one or more processors that perform an operation for determining an insertion node for self-test of a scan chain according to the one or more programs stored in the memory;
including,
The processor is
determining at least one control point candidate in consideration of a control burden index for each node with respect to a plurality of nodes included in the scan chain;
determining at least one observation point candidate different from the control point candidate in consideration of the observation burden index for each node with respect to a plurality of nodes included in the scan chain;
generating at least one control point-observation point pair candidate using the control point candidate and the observation point candidate; and
determining an insertion node for self-test of a scan chain into which the control point-observation point pair candidate is to be inserted;
Insertion node determination device for self-testing of scan chains. 11. The method of claim 10,
The step of determining the observation point candidate comprises:
When the control point candidate and the control point candidate are located at the input terminal of a fan-out free gate connected from a node different from the control point candidate, and at the same time, a node other than the control point candidate blocks a path through which a failure is propagated. Characterized in excluding nodes other than control point candidates from observation point candidates,
Insertion node determination device for self-testing of scan chains. 11. The method of claim 10,
The control point-observation point pair candidate is,
including the control point candidate and the observation point candidate,
Two gates are connected between the control point candidate and the observation point candidate,
Insertion node determination device for self-testing of scan chains. 11. The method of claim 10,
The control burden index is,
It is calculated based on the <Equation> below,
<Equation>

(for CP-1)

(for CP-0)
CP _Burden represents the control burden index, and |BlockedFaults| represents the number of failures in which propagation is blocked when the value of the node into which the corresponding control point (CP) is inserted is '0' or '1'. Ctrl indicates the probability of '1' appearing at the node,
The observation burden index is,
It is calculated according to the <Equation> below,
<Equation>

OP _Burden represents the observation burden index, |FaninCone| represents the number of failures that exist inside the logic cone connected to the input terminal of the gate into which the corresponding observation point (OP) is inserted, and Obs represents the number of failures in the corresponding node. Characterized in that it propagates to the output of the circuit and means the probability that the user can observe it,
Insertion node determination device for self-testing of scan chains.

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