KR20220142902A - An integrated circuit and an electronic device including the same - Google Patents

Abstract

An integrated circuit, according to an exemplary embodiment of the present disclosure, comprises: a power supply circuit configured to generate a supply voltage from at least one of first and second power supply voltages; and a system rod configured to receive and operate the supply voltage through an output node of the power supply circuit. The power supply circuit comprises: a first low drop-output (LDO) regulator configured to generate a first load current flowing from the first power supply voltage to the system rod through the output rod; and a second LOD regulator configured to selectively generate a second load current flowing from the second power supply voltage to the system load through the output node based on a difference between voltages of internal nodes of the first LDO regulator. According to the present invention, the second LDO regulator directly receives a signal required to generate a selective rod current from the first LDO regulator.

Description

AN INTEGRATED CIRCUIT AND AN ELECTRONIC DEVICE INCLUDING THE SAME

The technical idea of the present disclosure relates to an integrated circuit that performs a predetermined operation, and more particularly, to an integrated circuit including a power supply circuit for generating a supply voltage provided to a system load in the integrated circuit, and an electronic device including the same .

Recently, as one electronic device performs various operations, the range of current consumption of the electronic device is widened. For example, in the case of a display device, as the resolution and refresh rate of the display increase, the maximum value of the current consumption of the display driver integrated circuit continuously increases, and thus the range of the current consumption is widened. In addition, the current consumption of the display driving integrated circuit may change in real time according to various factors, such as characteristics of image data to be processed, and an operation mode of the display apparatus.

Accordingly, there is an increasing need for a method of preventing unnecessary current consumption by controlling the supply of current according to real-time changes in current consumption while covering the widened current consumption range.

The technical idea of the present disclosure is an integrated circuit that generates a supply voltage by using at least one of a plurality of power supply voltages according to a load current drawn by a system load included in the integrated circuit and provides the supply voltage to the system load, and the integrated circuit including the same To provide an electronic device that

An integrated circuit according to an exemplary embodiment of the present disclosure operates by receiving the supply voltage through a power supply circuit configured to generate a supply voltage from at least one of a first and a second supply voltage and an output node of the power supply circuit. a system load configured to a second LDO regulator configured to selectively generate a second load current flowing from the second supply voltage to the system load through the output node based on a difference between voltages of internal nodes of the first LDO regulator do it with

An integrated circuit according to an exemplary embodiment of the present disclosure operates by receiving the supply voltage from a power supply circuit and a power supply circuit configured to generate a supply voltage from at least one of a first and a second supply voltage, and a system load configured to draw a first load current from a supply circuit, the power supply circuit comprising: a first low drop-output (LDO) configured to generate a second load current flowing from the first supply voltage to the system load; ) a regulator and a second LDO regulator configured to generate a third load current flowing from the second supply voltage to the system load in response to a saturation state of the second load current with an increase in the first load current. characterized.

An electronic device according to an exemplary embodiment of the present disclosure includes a Display Driver Integrated Circuit (DDI) and a Power Management Integrated Circuit configured to provide the first and second power voltages to the DDI. Circuit; hereinafter, PMIC), wherein the DDI includes a first logic circuit configured to operate by receiving the first power supply voltage, a second logic circuit configured to operate by receiving the supply voltage, and the first and second power sources a power supply circuit configured to output the supply voltage from at least one of voltages, the power supply circuit comprising: a first LDO (Low) configured to output a first load current from the first supply voltage to the second logic circuit Drop-Output) regulator and internal nodes of the first LDO regulator to output a second load current from the second power supply voltage to the second logic circuit when a difference between voltages of the internal nodes is equal to or greater than a reference value It characterized in that it comprises a configured second LDO regulator.

An integrated circuit according to an exemplary embodiment of the present disclosure includes a first low drop-output (LDO) regulator configured to generate a first load current from a first power supply voltage, and selectively generate a second load current from a second power supply voltage a second LDO regulator configured to: and a system load configured to draw a third load current comprising at least one of the first and second load currents from an output node shared from the first and second LDO regulators; The first LDO regulator controls a first enable by comparing a reference voltage and a feedback voltage corresponding to a voltage of the output node and a first current generation circuit configured to generate the first load current by applying the first power supply voltage a first comparison circuit configured to generate a signal and provide the signal to the first current generation circuit, wherein the second LDO regulator comprises: a second current configured to be applied with the second supply voltage to generate the second load current; a generation circuit and a second comparison circuit coupled to internal nodes of the first comparison circuit and configured to compare voltages of the internal nodes to generate a second enable control signal and provide it to the second current generation circuit; It is characterized in that it is configured to do so.

The integrated circuit according to an exemplary embodiment of the present disclosure may provide a stable supply voltage to the system load using the first and second LDO regulators even in various operating regions of the system load, and the second LDO regulator is the first LDO regulator The circuit configuration can be relatively simplified by directly receiving the signal required for selective load current generation from the .

The second LDO regulator according to an exemplary embodiment of the present disclosure may efficiently consume power of the second LDO regulator by selectively enabling a plurality of auxiliary current generating circuits according to power consumption of a system load.

Effects that can be obtained in the exemplary embodiments of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned are common knowledge in the art to which exemplary embodiments of the present disclosure pertain from the following description. It can be clearly derived and understood by those who have That is, unintended effects of carrying out the exemplary embodiments of the present disclosure may also be derived by those of ordinary skill in the art from the exemplary embodiments of the present disclosure.

1 is a block diagram illustrating an integrated circuit according to an exemplary embodiment of the present disclosure.
2 is a flowchart illustrating a method of operating an integrated circuit according to an exemplary embodiment of the present disclosure.
3 is a circuit diagram illustrating a power supply circuit according to an exemplary embodiment of the present disclosure.
4A is a timing diagram illustrating the operation of the power supply circuit according to an exemplary embodiment of the present disclosure, and FIGS. 4B and 4C are circuit diagrams for explaining the operation of the power supply circuit according to an exemplary embodiment of the present disclosure; 4C is a timing diagram showing the operation of the power supply circuit.
5 is a circuit diagram illustrating a power supply circuit according to an exemplary embodiment of the present disclosure, and FIG. 6 is a timing diagram illustrating an operation of the power supply circuit of FIG. 5 .
7 is a graph illustrating a trend of a load current of a system load according to an exemplary embodiment of the present disclosure.
8A is a block diagram illustrating a second LDO regulator according to an exemplary embodiment of the present disclosure, and FIG. 8B is a graph for explaining an operation of the second LDO regulator of FIG. 8A according to an operating region of a system load; is a graph for explaining a supply voltage according to the operation of the second LDO regulator of FIG. 8A .
9 is a flowchart for explaining a specific operation method of the integrated circuit in step S120 of FIG. 2 .
10A is a circuit diagram illustrating a power supply circuit according to an exemplary embodiment of the present disclosure, and FIG. 10B is a graph for explaining an operation of the second LDO regulator of FIG. 10A according to an operating region of a system load.
11 is a circuit diagram illustrating a first LDO regulator according to an exemplary embodiment of the present disclosure.
12 is a circuit diagram illustrating a second LDO regulator according to an exemplary embodiment of the present disclosure.
13 is a block diagram illustrating a display driver integrated circuit according to an exemplary embodiment of the present disclosure.
14 is a block diagram illustrating an electronic device according to an exemplary embodiment of the present disclosure.

1 is a block diagram illustrating an integrated circuit 10 according to an exemplary embodiment of the present disclosure. In this specification, the integrated circuit 10 may be included in an electronic device (not shown) to perform a predetermined operation required by the electronic device. The integrated circuit 10 may be implemented as a single independent chip in an electronic device (not shown), or may be implemented in connection with other circuits in an electronic device (not shown). For example, the electronic device (not shown) includes a smart phone, a tablet personal computer (PC), a mobile phone, a video phone, an e-book reader, and a desktop PC ( desktop personal computer, laptop personal computer, netbook computer, personal digital assistant, PMP (portable multimedia player), MP3 player, mobile medical device, camera, or wearable device ( wearable devices (e.g., head-mounted-devices (HMDs) such as electronic glasses, electronic garments, electronic bracelets, electronic necklaces, electronic accessories, electronic tattoos, or smart watches). may include

According to some embodiments, the electronic device may be a smart home appliance having an image display function. Smart home appliances are, for example, televisions, digital video disk (DVD) players, audio, refrigerators, air conditioners, vacuum cleaners, ovens, microwave ovens, washing machines, air purifiers, set-top boxes, TV boxes (eg, For example, it may include at least one of Samsung HomeSync™, Apple TV™, or Google TV™), game consoles, an electronic dictionary, an electronic key, a camcorder, or an electronic picture frame.

According to some embodiments, the electronic device includes various medical devices (eg, magnetic resonance angiography (MRA), magnetic resonance imaging (MRI), computed tomography (CT), imagers, ultrasound machines, etc.), navigation devices, and GPS receivers. (global positioning system receiver), EDR (event data recorder), FDR (flight data recorder), automotive infotainment device, marine electronic equipment (eg, marine navigation system and gyro compass, etc.), avionics, It may include at least one of a security device, a head unit for a vehicle, an industrial or household robot, an automatic teller's machine (ATM) of a financial institution, or a point of sales (POS) of a store.

According to some embodiments, the electronic device is a piece of furniture or a building/structure including an image display function, an electronic board, an electronic signature receiving device, a projector, or It may include at least one of various measuring devices (eg, water, electricity, gas, or radio wave measuring devices). The electronic device according to exemplary embodiments of the present disclosure may be a combination of one or more of the various devices described above. Also, the electronic device may be a flexible display device.

Referring to FIG. 1 , the integrated circuit 10 may include a first terminal T1 , a second terminal T2 , a power supply circuit 20 , and a system load 30 . A first power voltage VDD1 may be applied to the first terminal T1 , and a second power voltage VDD2 may be applied to the second terminal T2 .

The power supply circuit 20 receives at least one of the first and second power voltages VDD1 and VDD2 through the first and second terminals T1 and T2 , and a supply voltage required for driving the system load 30 . can create The power supply circuit 20 may provide a supply voltage to the system load 30 through the output node N1 . In an exemplary embodiment, the first power voltage VDD1 and the second power voltage VDD2 are independent power voltages that are different from each other and may have the same or different magnitudes. In some embodiments, the first power voltage VDD1 may be generated from the second power voltage VDD2. In this specification, the voltage of the output node N1 may be understood to be the same as the supply voltage provided to the system load 30 .

Meanwhile, the system load 30 may operate in a plurality of operation regions according to the amount of power consumption. The operating region may be defined according to power consumption of the system load 30 . For example, the system load 30 may operate in a first operating region consuming relatively low power, or may operate in a second operating region consuming relatively high power. In some embodiments, the operating region may be defined by additionally considering a PVT (Process, Voltage, Temperature) condition of the system load 30 . The first load current drawn from the system load 30 from the output node N1 when performing an operation in the first operating region may be relatively small, and the first load current drawn from the output node N1 when performing an operation in the second operating region. The first load current drawn may be relatively large. The system load 30 may consume high power in a specific operating region, and at this time, a high first load current may be instantaneously drawn from the output node N1 . When the balance between the magnitude of the load current provided to the output node N1 from the power supply circuit 20 and the magnitude of the first load current drawn from the system load 30 is broken, the voltage of the output node N1 (ie, the system The supply voltage to the load 30) fluctuates, so that the system load 30 may not operate smoothly. To solve this problem, a power supply circuit 20 according to an exemplary embodiment of the present disclosure is described below.

The power supply circuit 20 may include a first low drop-output (LDO) regulator 21 and a second LDO regulator 22 . In an exemplary embodiment, the first LDO regulator 21 receives the first power supply voltage VDD1 through the first terminal T1 , and receives a system load from the first power supply voltage VDD1 through the output node N1 . A second load current flowing to (30) may be generated. The first LDO regulator 21 may generate a second load current that matches the power consumption of the system load 30 . For example, as the power consumption of the system load 30 increases, the first load current drawn from the output node N1 increases, and the first LDO regulator 21 responds to the increased first load current The increased second load current may be generated from the first power voltage VDD1 . When the magnitude of the first load current exceeds the threshold, the second load current generated by the first LDO regulator 21 reaches a saturation state, and after the saturation state, the magnitude of the first load current becomes the second load current may be larger than the size of In this case, the second LDO regulator 22 may generate a third load current for compensating for a difference between the continuously increasing first load current and the saturated second load current.

In an exemplary embodiment, the second LDO regulator 22 receives the second power supply voltage VDD2 through the second terminal T2 , and receives a system load from the second power supply voltage VDD2 through the output node N1 . A third load current flowing to (30) may be generated. In an exemplary embodiment, when the magnitude of the first load current of the system load 30 exceeds a threshold, that is, when the system load 30 performs an operation in a specific operating region, the first LDO regulator 21 By using the saturated second load current and the second LDO regulator 22 , a third load current may be generated and output to the system load 30 . In an exemplary embodiment, the level of the first power voltage VDD1 may be smaller than the level of the second power voltage VDD2 . In some embodiments, the level of the first power voltage VDD1 may be the same as the level of the second power voltage VDD2 .

In an exemplary embodiment, the second LDO regulator 22 is connected to the first and second internal nodes N1_INT and N2_INT of the first LDO regulator 21 to form the first and second internal nodes N1_INT and N2_INT. The third load current may be selectively generated based on the difference between the voltages. That is, the second LDO regulator 22 generates the third load current by recognizing the saturation state of the second load current of the first LDO regulator 21 through the voltages of the first and second internal nodes N1_INT and N2_INT. can start

In an exemplary embodiment, the voltages of the first and second internal nodes N1_INT and N2_INT are the supply voltage (or the output node N1 ) as the first load current drawn by the system load 30 increases beyond a threshold value. ) can change in response to a drop in voltage). Also, the voltage of the first internal node N1_INT may increase and the voltage of the second internal node N2_INT may decrease according to the drop of the supply voltage. In some embodiments, the voltage of the first internal node N1_INT may decrease and the voltage of the second internal node N2_INT may increase according to the drop of the supply voltage. In an exemplary embodiment, the first and second internal nodes N1_INT and N2_INT may output a difference between a reference voltage applied to the first LDO regulator 21 and a feedback voltage corresponding to the supply voltage, respectively.

The second LDO regulator 22 directly receives the voltages of the first and second internal nodes N1_INT and N2_INT indicating whether the supply voltage has dropped from the first LDO regulator 21, so as to detect a drop in the supply voltage. The configuration of the comparator circuit can be minimized.

In an exemplary embodiment, the second LDO regulator 22 may include a plurality of auxiliary current generation circuits (not shown) for respectively generating auxiliary currents included in the third load current. The second LDO regulator 22 may determine the number of enabled auxiliary current generating circuits according to the operating region of the system load 30 or the magnitude of the first load current of the system load 30 , and the enabled auxiliary current The generating circuit may generate an auxiliary current. The auxiliary current generating circuit may be referred to as an auxiliary current path, and a specific embodiment thereof will be described in FIG. 8A and the like.

The integrated circuit 10 according to an exemplary embodiment of the present disclosure may provide a stable supply voltage to the system load using the first and second LDO regulators 21 and 22 even in various operating regions of the system load 30 . In addition, the circuit configuration of the second LDO regulator 22 may be relatively simplified by directly receiving a signal required for selective load current generation from the first LDO regulator 21 .

2 is a flowchart illustrating a method of operating an integrated circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 2 , in operation S100 , the integrated circuit may supply a first load current to a system load using a first LDO regulator. Specifically, the first LDO regulator may supply a first load current to the system load through the output node, and the voltage of the output node may be a supply voltage and may be based on driving the system load. In step S110, the integrated circuit may detect whether a voltage drop at the output node occurs. In other words, in step S110, the integrated circuit may detect whether a drop in the supply voltage provided to the system load occurs. Specifically, the second LDO regulator of the integrated circuit may be connected to internal nodes of the first LDO regulator to determine whether a voltage drop of the output node occurs based on a difference between voltages of the internal nodes. As described above, the drop in the supply voltage occurs when the first load current supplied by the first LDO regulator reaches saturation due to a continuous or rapid increase in the third load current drawn by the system load from the output node, This may occur due to an imbalance between the saturated first load current and the increasing third load current. When step S110 is 'YES', the integrated circuit may additionally supply a second load current to the system load by using the second LDO regulator following step S120 to prevent a continuous drop of the supply voltage. The second LDO regulator shares an output node with the first LDO regulator, and may supply a second load current to the system load through the output node. The second LDO regulator may generate a second load current proportional to a difference between the third load current drawn by the system load and the saturated first load current. Through this, the second LDO regulator may provide the second load current in response to the drop of the supply voltage, thereby minimizing the drop of the supply voltage and ensuring stable operation of the system load. When step S120 is 'NO', when step S110 is 'NO', step S100 may be followed.

In some example embodiments, in operation S110 , the integrated circuit may detect whether a voltage drop of the output node is greater than or equal to a reference level. Specifically, the second LDO regulator of the integrated circuit may detect whether a difference between voltages of internal nodes of the first LDO regulator is equal to or greater than a reference value. Thereafter, in step S120 , the second LDO regulator may generate a second load current when a difference between voltages of internal nodes is equal to or greater than a reference value. Through this, the second LDO regulator sets the start time of the generation of the second load current by a predetermined delay from the time when the first load current reaches the saturation state, so that the ripple caused by the overlapping of the operations of the first LDO regulator and the second LDO regulator , an increase in noise can be avoided.

3 is a circuit diagram illustrating a power supply circuit 100 according to an exemplary embodiment of the present disclosure. In FIG. 3 , the load current source LCS may mean a load current drawn from a system load. On the other hand, the power supply circuit 100 shown in FIG. 3 is only an exemplary content for explaining the technical idea of the present disclosure, and the present disclosure is not limited thereto, and implementations of the power supply circuit 100 may vary. will be fully understood.

Referring to FIG. 3 , the power supply circuit 100 may include a first LDO regulator 110 and a second LDO regulator 120 . Also, in a non-exemplary embodiment, the power supply circuit 100 may further include a first capacitor C1 connected between the output node N1 and the ground for stable operation.

In an exemplary embodiment, the first LDO regulator 110 may include first to third resistors R1 to R3 , a first transistor TR1 , a first comparator 111 , and a second comparator 112 . have. In this specification, the first comparator 111 and the second comparator 112 may be defined as elements included in the first comparison circuit of the first LDO regulator 110 . Also, the first resistor R1 and the first transistor TR1 may be defined as elements included in the first current generation circuit configured to generate the first load current using the first power voltage VDD1 . The first transistor TR1 may be a p-channel metal-oxide-semiconductor field-effect transistor (p-channel MOSFET). In some embodiments, the first transistor TR1 may be a power transistor.

One end of the first resistor R1 may be connected to a terminal receiving the first power voltage VDD1 , and the other end may be connected to a source terminal of the first transistor TR1 . A drain terminal of the first transistor TR1 may be connected to the output node N1 . One end of the second resistor R2 may be connected to the output node N1 , and the other end may be connected to the feedback node N_FB. One end of the third resistor R3 may be connected to the feedback node N_FB, and the other end may be connected to the ground. The voltage of the feedback node N_FB may be determined by a voltage (or a supply voltage) of the output node N1 as a feedback voltage and a resistance value ratio between the second resistor R2 and the third resistor R3 .

An input terminal of the first comparator 111 may be connected to a terminal receiving the reference voltage VREF and a feedback node N_FB. The output terminal of the first comparator 111 may be connected to the input terminal of the second comparator 112 through the first and second internal nodes N1_INT and N2_INT. An output terminal of the second comparator 112 may be connected to a gate terminal of the first transistor TR1 .

The second LDO regulator 120 may include a fourth resistor R4 , a second transistor TR2 , and a third comparator 121 . In this specification, the third comparator 121 may be defined as an element included in the second comparison circuit of the second LDO regulator 120 . Also, the fourth resistor R4 and the second transistor TR2 may be defined as elements included in the second current generating circuit configured to generate the second load current using the second power voltage VDD2 . The second transistor TR2 may be a p-channel metal-oxide-semiconductor field-effect transistor (p-channel MOSFET). In some embodiments, the second transistor TR2 may be a power transistor.

One end of the fourth resistor R4 may be connected to a terminal receiving the second power voltage VDD2 , and the other end may be connected to a source terminal of the second transistor TR2 . A drain terminal of the second transistor TR2 may be connected to the output node N1 . An input terminal of the third comparator 121 may be connected to the first and second internal nodes N1_INT and N2_INT. The output terminal of the third comparator 121 may be connected to the gate terminal of the second transistor TR2 .

Hereinafter, the operation of the power supply circuit 100 of FIG. 3 in FIGS. 4A to 4B will be described.

4A is a timing diagram illustrating the operation of the power supply circuit 100 according to an exemplary embodiment of the present disclosure, and FIGS. 4B and 4C illustrate the operation of the power supply circuit 100 according to an exemplary embodiment of the present disclosure. It is a circuit diagram for explanation, and FIG. 4C is a timing diagram illustrating the operation of the power supply circuit 100 .

The power supply circuit 100 performs the operation shown in FIG. 4B in the interval between the first time t11 and the second time t21 and the third time t31 of FIG. 4A , and the second time In the section between (t21) and the third time (t31), the operation shown in FIG. 4C may be performed.

Referring to FIG. 4A , the load current LC represents a current drawn by the load current source LCS ( FIGS. 4B and 4C ) from the output node N1 , FIGS. 4B and 4C , and the first load current I1 . denotes the current generated by the first LDO regulator 110 ( FIGS. 4B and 4C ), and the second load current I2 denotes the current generated by the second LDO regulator 120 , FIGS. 4B and 4C , and supply The voltage SV may represent the voltage of the output node N1 ( FIGS. 4B and 4C ). The first and second reference currents I_RFE1 and I_REF2 may be a reference for defining the first and second operating regions OPR1 and OPR2 of the system load. The first saturation current I_SAT1 may represent the saturated first load current I1 , and the second saturation current I_SAT2 may represent the saturated second load current I2 . In addition, the target power supply voltage T_VDD may indicate a voltage having a target level of the supply voltage SV, and the minimum power supply voltage Min_VDD may indicate a voltage having a minimum voltage level at which a system load is operable.

In a section between the first time t11 and the second time t21 or a section after the third time t31, the system load may operate in the first operating region OPR1, and power consumption of the system load increases. The raw load current LC may increase. In response to the increased load current LC, the first load current I1 may also increase. Meanwhile, since the first load current I1 is before saturation, the second load current I2 may not be generated and the supply voltage SV may not drop.

Referring further to FIG. 4B , in the period between the first time t11 and the second time t21 or the third time t31 or later, the first comparator 111 is a reference voltage VREF and a feedback voltage ( VFB) may be received and output as first and second voltages V1 and V2 representing a comparison result, respectively. Since the supply voltage SV does not drop, the reference voltage VREF and the feedback voltage VFB may have the same magnitude, and the second comparator 112 responds to the first and second voltages V1 and V2. One gate voltage VG_MAIN may be generated and provided to the gate terminal of the first transistor TR1 . The first transistor TR1 may be turned on in response to the first gate voltage VG_MAIN, and may generate a first load current I1 from the first power voltage VDD1 and supply it to the output node N1 . . The first gate voltage VG_MAIN may decrease from the first level L1 to the second level L2 as the load current LC increases. Meanwhile, since the difference between the first and second voltages V1 and V2 does not occur before the first load current I1 is saturated, the second LDO regulator 120 may be in a disabled state.

Referring back to FIG. 4A , in the interval between the second time t21 and the third time t31 , the system load may operate in the second operating region OPR2 , and the load current due to an increase in power consumption of the system load (LC) may increase. Since the first load current I1 is saturated at the second time t21, a second load current I2 corresponding to the load current LC may be generated, and the drop of the supply voltage SV may be minimized. have.

Referring further to FIG. 4C , in the period between the second time t21 and the third time t31 , the second comparator 112 converts the first gate voltage VG_MAIN of the second level L2 to the first transistor ( It is provided to the gate terminal of TR1 , and the first transistor TR1 may be fully turned on in response to the first gate voltage VG_MAIN. The fully-on first transistor TR1 may generate a first load current I1 corresponding to the first saturation current I_SAT1 and supply it to the output node N1 . The supply voltage SV may drop instantaneously by the load current LC greater than the saturated first load current I1 , such that the feedback voltage VFB may be smaller than the reference voltage VREF. The first comparator 111 may receive the reference voltage VREF and the feedback voltage VFB and output them as first and second voltages V1 and V2 representing a comparison result, respectively. For example, the first voltage V1 is a voltage of the first internal node N1_INT and increases as the feedback voltage VFB becomes smaller than the reference voltage VREF, and the second voltage V2 is the second internal node N1_INT. As a voltage of N2_INT), it may decrease as the feedback voltage VFB becomes smaller than the reference voltage VREF. The third comparator 121 may compare the first and second voltages V1 and V2 to generate a second gate voltage VG_AUX based on the comparison result and provide it to the gate terminal of the second transistor TR2. . The second transistor TR2 may be turned on in response to the second gate voltage VG_AUX, and may generate a second load current I2 from the second power voltage VDD2 and supply it to the output node N1 . . In this way, the system load (not shown) may be supplied with the first and second load currents I1 and I2 through the output node N1 , and as a result, the drop of the supply voltage SV may be prevented. .

5 is a circuit diagram illustrating a power supply circuit 100' according to an exemplary embodiment of the present disclosure, and FIG. 6 is a timing diagram illustrating an operation of the power supply circuit 100' of FIG. As shown in FIG. 5 , the power supply circuit 100 ′ may include a first LDO regulator 110 and a second LDO regulator 120 ′. In FIG. 5 , content overlapping with the power supply circuit 100 of FIG. 3 will be omitted.

As described above, when the second LDO regulator 120 ′ generates the second load current as soon as the first load current of the first LDO regulator 110 reaches the saturation state, the first and second LDO regulators 110, 120'), ripple or noise may be overlapped due to the instantaneous overlap of operations, and unnecessary power consumption may be induced.

Referring to FIG. 5 , the second LDO regulator 120 ′ may further include an offset voltage source OS to prevent unnecessary power consumption. That is, the offset voltage source OS may delay the generation start timing of the second load current of the second LDO regulator 120 ′. Meanwhile, the second LDO regulator 120 ′ including the offset voltage source OS is only an exemplary embodiment and is not limited thereto, and a circuit implemented to perform the same operation as the offset voltage source OS is provided. It may be included in the second LDO regulator 120'. A specific embodiment thereof will be described later with reference to FIG. 11 .

In an exemplary embodiment, the third comparator 121 receives the second voltage obtained by adding the offset voltage of the offset voltage source OS to the first voltage of the first internal node N1_INT and the voltage of the second internal node N2_INT. can do. For example, when the first voltage is greater than the second voltage, the third comparator 121 may generate a second load current through the second transistor TR2 .

6 , in the interval between the first time t12 and the second time t22 , the system load operates in the first operating region OPR1 , and as power consumption increases, the load current LC is can increase The first load current I1 may increase in response to an increase in the load current LC, and may be saturated with the first saturation current I_SAT1 at a second time t22. After the second time t22 , the system load may operate in the second operation region OPR2 . The second LDO regulator 120 ′ may start generation of the second load current I2 at a third time t32 delayed by a delay corresponding to the offset voltage of the offset voltage source OS from the second time t22 . . The sum of the saturated first load current I1 and the additional second load current I2 can be balanced with the load current LC, so that the supply voltage SV is equal to the third time t32 and the fourth time t32. A predetermined size may be maintained in the interval between time t42. After the fourth time t42 , the second LDO regulator 120 ′ is disabled, and the system load operates again in the first operating region OPR1 , so that the supply voltage SV becomes the target power from the fifth time t52 . It may be restored to the voltage T_VDD.

7 is a graph illustrating a trend of a load current of a system load according to an exemplary embodiment of the present disclosure.

Referring to FIG. 7 , the system load may operate in any one of the first and second operation regions OPR1 and OPR2 . In the system load, the amount of power consumed may vary according to the number of simultaneously operating internal IPs among internal IPs (Intellectual Property). For example, as the number of simultaneously operated internal IPs increases, the power consumption of the system load may increase, and accordingly, the load current drawn by the system load may increase.

Most of the time, the system load may operate in the first operating region OPR1 , and the integrated circuit according to the exemplary embodiment may supply the first load current to the system load using only the first LDO regulator. In a limited time, the system load may operate in the second operating region OPR2 , and the integrated circuit according to an exemplary embodiment additionally uses the second LDO regulator together with the first LDO regulator to apply the first and second loads to the system load. Load current can be supplied.

The first and second operation regions OPR1 and OPR2 according to the exemplary embodiment of the present disclosure may be determined to enable efficient power consumption of the power management circuit in consideration of the operating frequency of the system load.

8A is a block diagram illustrating the second LDO regulator 220 according to an exemplary embodiment of the present disclosure, and FIG. 8B is a diagram illustrating the operation of the second LDO regulator 220 of FIG. 8A according to the operating region of the system load. , and FIG. 8C is a graph for explaining a supply voltage according to the operation of the second LDO regulator 220 of FIG. 8A .

Referring to FIG. 8A , the second LDO regulator 220 may include a comparison circuit 221 and first to nth auxiliary current generation circuits 222_1 to 222_n. The first to nth auxiliary current generation circuits 222_1 to 222_n are selectively enabled according to the magnitude of the load current LC of the system load ( FIG. 3 ) to generate the first to nth auxiliary currents I2_AUX1 to I2_AUXn, respectively. can do.

In an exemplary embodiment, the number of enabled auxiliary current generation circuits among the first to nth auxiliary current generation circuits 222_1 to 222_n may be determined according to the magnitude of the load current LC of the system load ( FIG. 3 ). For example, as the load current LC ( FIG. 3 ) of the system load increases, the number of enabled auxiliary current generating circuits may increase.

In an exemplary embodiment, the comparison circuit 221 is applied to the first voltage V1 received from the first internal node N1_INT ( FIG. 3 ) and the second voltage V2 of the second internal node N2_INT ( FIG. 3 ). The first enable control signal E_CS1 may be generated by comparing the voltage to which the first offset voltage VOS1 is added, and then provided to the first auxiliary current generating circuit 222_1 . The comparison circuit 221 compares the voltage obtained by adding the second offset voltage VOS2 to the first voltage V1 and the second voltage V2 to generate a second enable control signal E_CS2, and then a second auxiliary It may be provided to the current generating circuit 222_2 . In this way, the comparison circuit 221 compares the voltage obtained by adding the n-th offset voltage VOSn to the first voltage V1 and the second voltage V2 to generate the n-th enable control signal E_CSn. Thereafter, it may be provided to the n-th auxiliary current generation circuit 222_n.

In order to sequentially enable the first to nth auxiliary current generation circuits 222_1 to 222_n according to the increasing load current LC ( FIG. 3 ), the first to nth offset voltages VOS1 to VOSn have different sizes, respectively. can do. In an exemplary embodiment, a difference in magnitude between adjacent offset voltages in the first to nth offset voltages VOS1 to VOSn may be the same. In some embodiments, a difference in magnitude between adjacent offset voltages in the first to nth offset voltages VOS1 to VOSn may be different.

The second LDO regulator 220 may output the second load current I2 including the auxiliary current generated by the at least one enabled auxiliary current generating circuit to the output node N1 ( FIG. 3 ).

Referring further to FIG. 8B , the second operation region OPR2 of the system load may be subdivided into first to n-th sub operation regions OPR2_1 to OPR2_n. The second to nth reference currents I_REF2_1 to IREF2_n may represent currents serving as a reference to distinguish the first to nth sub-operation regions OPR2_1 to OPR2_n.

In an exemplary embodiment, the first auxiliary current generating circuit 222_1 may be enabled between a first time t13 and a second time t23 when the system load operates in the first sub operation region OPR2_1 . . The second auxiliary current generating circuit 222_2 may be additionally enabled between the second time t23 and the third time t33 when the system load operates in the second sub operation region OPR2_2 . In this way, the n-th auxiliary current generating circuit 222_n is additionally enabled between the fourth time t43 and the fifth time t53 when the system load operates in the n-th sub-operation region OPR2_n, so that all auxiliary The current generating circuits 222_1 to 222_n may be enabled. Thereafter, as the load current decreases, the first to nth auxiliary current generating circuits 222_1 to 222_n may be sequentially disabled.

Referring further to FIG. 8C , the supply voltage maintains the level of the target power voltage T_VDD when the system load operates in the first operating region OPR1 , and maintains the level of the target power voltage T_VDD when the system load operates in the second operating region OPR2 . , may begin to descend. When the supply voltage is in the first range R1 , the first auxiliary current generating circuit 222_1 is enabled to primarily prevent a drop in the supply voltage. When the supply voltage is continuously dropped to enter the second range R2 , the second auxiliary current generating circuit 222_2 is additionally enabled to prevent a drop in the supply voltage secondarily. Thereafter, when the supply voltage is continuously dropped to enter the n-th range Rn, the n-th auxiliary current generating circuit 222_n is additionally enabled to prevent the supply voltage from dropping in the n-th order.

The second LDO regulator 220 according to an exemplary embodiment of the present disclosure efficiently reduces power consumption of the second LDO regulator 220 by selectively enabling a plurality of auxiliary current generating circuits 222_1 to 222_n as needed. can be done with

9 is a flowchart for explaining a specific operation method of the integrated circuit in step S120 of FIG. 2 .

Referring to FIG. 9 , following step S110 in step S110 ( FIG. 2 ), the integrated circuit may enable at least one of a plurality of auxiliary current generating circuits based on a drop degree of a supply voltage. As an example, the number of auxiliary current generating circuits enabled in the integrated circuit may increase as the supply voltage drops from the target power voltage increases. In operation S122 , the integrated circuit may supply an auxiliary current to the system load through at least one auxiliary current generating circuit enabled.

10A is a circuit diagram illustrating a power supply circuit 300 according to an exemplary embodiment of the present disclosure, and FIG. 10B is a graph for explaining the operation of the second LDO regulator 320 of FIG. 10A according to an operating region of a system load to be. On the other hand, the power supply circuit 300 shown in FIG. 10A is only an exemplary content for explaining the technical idea of the present disclosure, and the present disclosure is not limited thereto, and implementations of the power supply circuit 300 may vary. will be fully understood. In addition, in FIG. 10A, content overlapping with FIG. 3 or 4C is omitted.

Referring to FIG. 10A , the second LDO regulator 320 includes a comparison circuit 321 , a first auxiliary current generation circuit 322_1 , a second auxiliary current generation circuit 322_2 , a first offset voltage source OS1 and a second An offset voltage source OS2 may be included. Although the second LDO regulator 320 including two auxiliary current generation circuits 322_1 and 322_2 is illustrated in FIG. 10A , more auxiliary current generation circuits may be included, like the second LDO regulator 220 of FIG. 8A . have.

In an exemplary embodiment, the first auxiliary current generating circuit 322_1 may include a fourth resistor R4 and a second transistor TR21. One end of the fourth resistor R4 may be connected to a terminal receiving the second power voltage VDD2 , and the other end may be connected to a source terminal of the second transistor TR21 . The drain terminal of the second transistor TR21 may be connected to the output node N1 , and the gate terminal may receive the second gate voltage VG_AUX1 from the comparison circuit 321 . The second gate voltage VG_AUX1 may be referred to as an enable control signal for the first auxiliary current generation circuit 322_1 .

In an exemplary embodiment, the second auxiliary current generating circuit 322_2 may include a fifth resistor R5 and a third transistor TR22. One end of the fifth resistor R5 may be connected to a terminal receiving the second power voltage VDD2 , and the other end may be connected to a source terminal of the third transistor TR22 . The drain terminal of the third transistor TR22 may be connected to the output node N1 , and the gate terminal may receive the third gate voltage VG_AUX2 from the comparison circuit 321 . The third gate voltage VG_AUX2 may be referred to as an enable control signal for the second auxiliary current generating circuit 322_2 .

In an exemplary embodiment, the current driving capability of the second transistor TR21 and the third transistor TR22 may be the same or different. For example, the ratio of the length to the width of the second transistor TR21 may be the same as or different from the ratio of the length to the width of the third transistor TR22 . For example, when the enable frequency of the first auxiliary current generation circuit 322_1 is greater than the enable frequency of the second auxiliary current generation circuit 322_2 , the current driving capability of the second transistor TR21 is increased by the third transistor TR22 ) can be implemented better. However, this is an exemplary embodiment, and the present invention is not limited thereto, and each of the transistors of the auxiliary current generating circuits may be implemented in various ways.

In an exemplary embodiment, the comparison circuit 321 may be configured by adding the offset voltage of the first offset voltage source OS1 to the first voltage V1 of the first internal node N1_INT and the voltage of the second internal node N2_INT. The second voltage V2_AUX1 and the third voltage V2_AUX2 obtained by adding the offset voltage of the second offset voltage source OS2 to the second voltage V2_AUX1 may be received.

In an exemplary embodiment, the comparison circuit 321 compares the first voltage V1 with the second voltage V2_AUX1 to generate a second gate voltage VG_AUX1 based on the comparison result, and then, after generating the second gate voltage VG_AUX1, the second transistor TR21 ) can be provided to the gate terminal of The comparison circuit 321 compares the first voltage V1 with the third voltage V2_AUX2 to generate a third gate voltage VG_AUX2 based on the comparison result, and then provides it to the gate terminal of the third transistor TR22 can do.

For example, when the first voltage V1 becomes greater than the second voltage V2_AUX1 , the comparison circuit 321 enables the first auxiliary current generation circuit 322_1 and generates the enabled first auxiliary current The circuit 322_1 may generate the first auxiliary current I2_AUX1 from the second power voltage VDD2 and supply it to the output node N1 . When the first voltage V1 becomes greater than the third voltage V2_AUX2, the comparison circuit 321 enables the second auxiliary current generation circuit 322_2, and the enabled second auxiliary current generation circuit 322_2 ) may generate a second auxiliary current I2_AUX2 from the second power voltage VDD2 and supply it to the output node N1 .

Referring further to FIG. 10B , the second operation region OPR2 of the system load may be subdivided into first and second sub operation regions OPR2_1 and OPR2_2 . The second and third reference currents IREF2_1 and IREF2_2 may represent currents serving as reference to distinguish the first and second sub-operation regions OPR2_1 and OPR2_2 .

In an exemplary embodiment, the first auxiliary current generating circuit 322_1 may be enabled between a first time t14 and a second time t24 when the system load operates in the first sub-operation region OPR2_1 . . The second auxiliary current generation circuit 222_2 may be additionally enabled between the second time t24 and the third time t34 when the system load operates in the second sub operation region OPR2_2 . Thereafter, the second auxiliary current generating circuit 322_2 may be disabled between a fourth time t44 and a fifth time t54 when the system load operates again in the first sub-operation region OPR2_1 . The first auxiliary current generating circuit 322_1 may be disabled after a fifth time t54 when the system load is again operated in the first operating region OPR1 .

11 is a circuit diagram illustrating the first LDO regulator 410 according to an exemplary embodiment of the present disclosure. The first LDO regulator 410 illustrated in FIG. 11 is only an exemplary embodiment, and is not limited thereto, and may be implemented in various embodiments capable of performing the operation of the first LDO regulator described above.

Referring to FIG. 11 , the first LDO regulator 410 includes first to fourteenth transistors TR11 to TR114, first to fourth resistors R11 to R14, a capacitor C11, and first and second current sources ( CS1, CS2). As described above, the first current source CS1 is a load current source, and the first current source CS1 may output a load current LC drawn from a system load (not shown) connected to the first LDO regulator 410 . . The first, second, fourth, sixth, seventh, tenth, twelfth and fourteenth transistors TR11, TR12, TR14, TR16, TR17 TR110, TR112, TR114 are p-channel transistors, and the remaining transistors (TR13, TR15, TR18, TR19, TR111, TR113) may be an n-channel transistor.

The source terminal of the first transistor TR11 is connected to the terminal receiving the first power voltage VDD1 , the drain terminal is connected to the output node N1 , and the gate terminal is connected to the gate terminal of the twelfth transistor TR112 . connected to receive the first gate voltage VG_MAIN. The first transistor TR11 may generate a first load current I_MAIN from the first power voltage VDD1 in response to the first gate voltage VG_MAIN. The voltage of the output node N1 may be supplied to a system load (not shown) as a supply voltage SV. The output node N1 may be the output node N1 described in FIG. 3 or the like.

One end of the first resistor R11 may be connected to the output node N1 , and the other end may be connected to one end of the second resistor R12 . The other end of the second resistor R12 may be connected to the ground. The first and second resistors R11 and R12 may generate a feedback voltage VFB from the supply voltage SV. One end of the capacitor C11 may be connected to the output node N1, and the other end may be connected to the ground.

The second transistor T12 and the fourth transistor T14 , the tenth transistor T10 and the fourteenth transistor TR114 , and the eleventh transistor TR111 and the thirteenth transistor TR113 may each form a current mirror. . The magnitude of the radiated current may be adjusted according to a ratio of sizes of the two transistors forming the current mirror. For example, the size of the transistor may be defined as a ratio of a length to a width of the transistor.

A source terminal of the fourteenth transistor TR114 is connected to a terminal to which the first power voltage VDD1 is received, a gate terminal receives the bias voltage VB1 , and a drain terminal of the sixth transistor TR16 and the seventh transistor is connected. It can be connected to the source terminal of (TR17). The fourteenth transistor TR114 generates a second bias current IB2 from the first power voltage VDD1 in response to the bias voltage VB1 and outputs the second bias current IB2 to the source terminals of the sixth and seventh transistors TR16 and TR17. can

A gate terminal of the sixth transistor TR16 may receive the reference voltage VREF, and a drain terminal of the sixth transistor TR16 may be connected to the second internal node N2_INT. The second internal node N2_INT may be the second internal node N2_INT described in FIG. 3 or the like. A gate terminal of the seventh transistor TR17 may receive the feedback voltage VFB, and a drain terminal of the seventh transistor TR17 may be connected to the first internal node N1_INT. The first internal node N1_INT may be the first internal node N1_INT described in FIG. 3 or the like. The first and second internal nodes N1_INT and N2_INT may be connected to a second LDO regulator 420 ( FIG. 12 ) to be described in FIG. 12 .

One end of the third resistor R13 may be connected to the second internal node N2_INT, and the other end may be connected to one end of the fourth resistor R14 and the gate terminals of the eighth and ninth transistors TR18 and TR19, respectively. . The other end of the fourth resistor R14 may be connected to the first internal node N2 . For example, the resistance value of the third resistor R13 and the resistance value of the fourth resistor R14 may be the same, and the third resistor R13 and the fourth resistor R14 have the resistance value of the first LDO regulator 410 . By increasing it, the gain of the first LDO regulator 410 may be improved. The drain terminal of the eighth transistor TR18 may be connected to the second internal node N2_INT, and the source terminal may be connected to the ground. The drain terminal of the ninth transistor TR19 may be connected to the second internal node N2_INT, and the source terminal may be connected to the ground.

For example, when the first reference voltage VREF and the feedback voltage VFB have the same magnitude, the first voltage V1 and the second voltage V2 may have the same magnitude. Thereafter, as the feedback voltage VFB becomes smaller than the first reference voltage VREF, the first voltage V1 may be greater than the second voltage V2. A second LDO regulator 420 to be described later may generate a second load current based on a difference between the first voltage V1 and the second voltage V2 .

The third resistor R13 , the fourth resistor R14 , the eighth transistor TR18 , and the ninth transistor TR19 may be included in the first common mode feedback (CMFB) circuit 1 ^st CMFB_CKT. That is, the eighth transistor TR18 and the ninth transistor TR19 may have a diode-connected NMOS structure.

Meanwhile, as the load current LC increases, the first load current I_MAIN increases, and as a result, the first gate voltage VG_MAIN decreases, so that the resistance value of the first transistor TR11 may decrease. Since a decrease in the resistance of the first transistor TR11 may cause a decrease in the amplification gain of the first LDO regulator 410 , an adaptive biasing circuit AB_CKT may be applied to prevent this.

The tenth transistor TR110 , the eleventh transistor TR111 , the twelfth transistor TR112 , the thirteenth transistor TR113 , and the second current source CS2 may be included in the adaptive biasing circuit AB_CKT. In an exemplary embodiment, the twelfth transistor TR112 may share the first gate voltage VG_MAIN with the first transistor TR11 . As the first gate voltage VG_MAIN provided to the twelfth transistor TR112 decreases, the additional current IEX by the current mirrors of the eleventh and thirteenth transistors TR111 and TR113 may increase. The tenth transistor TR110 may output the sum of the additional current IEX and the first bias current IB1 through the drain terminal. Since the fourteenth transistor TR114 shares the first bias voltage VB1 with the tenth transistor TR110 to form a current mirror, it drains the second bias current IB2 proportional to the summed current IB1+IEX. It can be output through the terminal. As the additional current IEX increases in response to the decreasing first gate voltage VG_MAIN, the second bias current IB2 may increase as a result, and the first LDO due to the increased second bias current IB2 The amplification gain of the regulator 410 may be maintained.

In an exemplary embodiment, the adaptive bias circuit AB_CKT may adjust the second bias current IB2 to stabilize the amplification gain of the first LDO regulator 410 . In some embodiments, the adaptive bias circuit AB_CKT may be omitted in the first LDO regulator 410 .

12 is a circuit diagram illustrating a second LDO regulator 420 according to an exemplary embodiment of the present disclosure. The second LDO regulator 420 shown in FIG. 12 is only an exemplary embodiment, and is not limited thereto, and may be implemented in various embodiments capable of performing the operation of the above-described second LDO regulator.

12 , the second LDO regulator 420 includes first to thirteenth transistors TR21 to TR213, first and second resistors R21 and R22, and first and second capacitors C21 and C22. may include The first, second, third, fifth, seventh, eighth, eleventh, and thirteenth transistors TR21, TR22, TR23, TR25, TR211, TR213 are p-channel transistors, and the remaining transistors TR24, TR26, TR29, TR210, TR212) may be n-channel transistors.

The source terminal of the first transistor TR21 may be connected to a terminal to which the second power voltage VDD2 is applied, the gate terminal may receive the second gate voltage VG_AUX1, and the drain terminal may be connected to the output node N1. have. The first transistor TR21 may generate the first auxiliary current I2_AUX1 in response to the second gate voltage VG_AUX1 . The first transistor TR21 may be included in the above-described first auxiliary current generation circuit.

The source terminal of the second transistor TR22 may be connected to a terminal to which the second power voltage VDD2 is applied, the gate terminal may receive the third gate voltage VG_AUX2, and the drain terminal may be connected to the output node N1. have. The second transistor TR22 may generate a second auxiliary current I2_AUX2 in response to the third gate voltage VG_AUX2. The second transistor TR22 may be included in the above-described second auxiliary current generation circuit. One end of the first and second capacitors C21 and C22 may be connected to gate terminals of the first and second transistors TR21 and TR22, respectively.

Each of the third transistor TR23 and the fifth transistor TR25 may form a current mirror with the eleventh transistor TR211. A source terminal of the third transistor TR25 and the fourth transistor TR26 may be connected to a terminal to which the second power voltage VDD2 is applied, respectively. The third transistor TR23 and the fourth transistor TR24 may share a node outputting the second gate voltage VG_AUX1 , and the first offset voltage of the first offset voltage source OS1 of FIG. 10A is considered. It may be implemented to generate 2 gate voltages VG_AUX1. The fifth transistor TR25 and the sixth transistor TR26 may share a node outputting the third gate voltage VG_AUX2 , and the first and second offset voltages of the second offset voltage source OS2 of FIG. 10A are It may be implemented to generate the considered third gate voltage VG_AUX2. For example, the size ratio between the eleventh transistor TR211 and the twelfth transistor TR212 is the size ratio between the third transistor TR23 and the fourth transistor TR24 and the fifth transistor TR25 and the sixth transistor TR26 ) may be different from each other in the size ratio of the liver. For example, when the size ratio between the eleventh transistor TR211 and the twelfth transistor TR212 is 2:1, the size ratio between the third transistor TR23 and the fourth transistor TR24 is 4:1, A size ratio between the fifth transistor TR25 and the sixth transistor TR26 may be 8:1. Through this, the level transition timings of the second gate voltage VG_AUX1 and the third gate voltage VG_AUX2 may be differently controlled, and the first and second auxiliary current generating circuits may have the second gate voltage VG_AUX1 and the third They may be sequentially enabled in response to each of the gate voltages VG_AUX2.

In this case, a separate offset voltage source may be omitted. In some embodiments, the size ratio between the third transistor TR23 and the fourth transistor TR24 and the size ratio between the fifth transistor TR25 and the sixth transistor TR26 may vary according to an offset voltage required for operation. have.

The third to sixth transistors TR23 to TR26 may be included in the dual output circuit DO_CKT, the third and fourth transistors TR23 and TR24 are defined as the first output circuit, and the fifth and sixth transistors ( TR25 and TR26) may be defined as a second output circuit. Also, the third and fifth transistors TR23 and TR25 may be referred to as pull-up transistors, and the fourth and sixth transistors TR24 and TR26 may be referred to as pull-down transistors.

A source terminal of the thirteenth transistor TR213 is connected to a terminal to which the second power voltage VDD2 is applied, a gate terminal receives the second bias voltage VB2 , and a drain terminal of the seventh and eighth transistors TR27 , TR28) can be connected to the source terminal. The thirteenth transistor 213 may output a third bias current IB3 in response to the second bias voltage VB2 .

The gate terminal of the seventh transistor TR27 may receive the first voltage V1 , and the gate terminal of the eighth transistor TR28 may receive the second voltage V2 . The first voltage V1 may correspond to the first voltage V1 of FIG. 11 , and the second voltage V2 may correspond to the second voltage V2 of FIG. 11 . A drain terminal of the seventh transistor TR27 may be connected to one end of the first resistor R21 , a drain terminal of the ninth transistor TR29 and a gate terminal of the twelfth transistor TR212 , respectively. The drain terminal of the eighth transistor TR28 is connected to one end of the second transistor R22, the drain terminal of the tenth transistor TR210, the gate terminal of the fourth transistor TR24, and the gate terminal of the sixth transistor TR26, respectively. can be connected The other end of the first resistor R21 may be connected to the other end of the second resistor R22 , the drain terminal of the ninth transistor TR29 , and the drain terminal of the tenth transistor TR210 , respectively. For example, the resistance value of the first resistor R21 and the resistance value of the second resistor R22 may be the same, and the first resistor R21 and the second resistor R22 have the resistance value of the second LDO regulator 420 . By increasing it, the gain of the second LDO regulator 420 may be improved. In an exemplary embodiment, a relationship of a ratio of a width to a length between the seventh transistor TR27 and the eighth transistor TR28 may be different.

The first resistor R21 , the second resistor R22 , the ninth transistor TR29 , and the tenth transistor TR210 may be included in the second common mode feedback (CMFB) circuit 2 ^nd CMFB_CKT. That is, the ninth transistor TR29 and the tenth transistor TR210 may have a diode-connected NMOS structure.

The second LDO regulator 420 may generate at least one of the first and second auxiliary currents I2_AUX1 and I2_AUX2 based on the difference between the first and second voltages V1 and V2. A detailed operation of the second LDO regulator 420 has been described above, and thus will be omitted below.

13 is a block diagram illustrating a display driver integrated circuit 1000 according to an exemplary embodiment of the present disclosure.

Referring to FIG. 13 , the display driver integrated circuit 1000 (hereinafter referred to as DDI) includes a first terminal T1 , a second terminal T2 , a third terminal T3 , a first logic circuit 1010 , It may include a first LDO regulator 1030 , a second LDO regulator 1040 , and a second logic circuit 1020 . The first terminal T1 may be connected to the power management integrated circuit (PMIC) 1100 and the first external resistor REXT1 to receive the first power voltage. The second terminal T2 may be connected to the PMIC 1100 through a second external resistor REXT2 to receive a second power voltage. The third terminal T3 may be connected to the external capacitor CEXT to promote stable operation of the first and second LDO regulators 1030 and 1040 .

The first power voltage received through the first terminal T1 may be less than or equal to the second power voltage received through the second terminal T2 . The DDI 1000 may receive different power supply voltages from the PMIC 1100 through independent terminals T1 and T2, respectively. The first logic circuit 1010 may directly receive the first power voltage through the first terminal T1 to perform a predetermined operation. The second logic circuit 1010 may receive a supply voltage from the first and second LDO regulators 1030 and 1040 to perform a predetermined operation. The first logic circuit 1010 may perform a different operation from the second logic circuit 1020 .

The first LDO regulator 1030 may be connected to the first terminal T1 to receive the first power voltage, generate a first load current from the first power voltage, and supply it to the second logic circuit 1020 . Meanwhile, as the power consumption of the second logic circuit 1020 increases, the load current drawn from the second logic circuit 1020 increases, so that the first load current may increase. When the first load current is saturated due to the limit of the first LDO regulator 1030 , the second LDO regulator 1040 according to exemplary embodiments of the present disclosure generates a second load current to generate a second load current to the second logic circuit 1020 . ) can be additionally supplied.

In an exemplary embodiment, the second LDO regulator 1040 is connected to the first and second internal nodes (N1_INT, N2_INT) of the first LDO regulator 1030, and the first and second internal nodes (N1_INT, N2_INT) When the difference between the voltages of is equal to or greater than the reference value, the second load current may be generated from the second power voltage received from the second terminal T2 and output to the second logic circuit 1020 . The various embodiments described in FIG. 1 and the like may be applied to the second LDO regulator 1040 , and specific details thereof have been described above, and thus will be omitted below.

The second logic circuit 1020 may operate by receiving a supply voltage generated from at least one of the first and second power voltages received from the first and second terminals T1 and T2 , and as a result, the second The power consumption range of the logic circuit 1020 may be widened to perform various operations.

14 is a block diagram illustrating an electronic device 2300 according to an exemplary embodiment of the present disclosure.

The electronic device 2300 may include, for example, all or a part of the integrated circuit 10 illustrated in FIG. 1 . Referring to FIG. 14 , the electronic device 2300 includes one or more application processors (AP) 2310 , a communication module 2320 , a subscriber identification module (SIM) card 2324 , a memory 2330 , and a sensor module. 2340, input device 2350, display module 2360, interface 2370, audio module 2380, camera module 2391, power management module 2395, battery 2396, indicator 2397 and A motor 2398 may be included.

The AP 2310 may control a plurality of hardware or software components connected to the AP 2310 by driving an operating system or an application program, and may perform various data processing and operations including multimedia data. The AP 2310 may be implemented as, for example, a system on chip (SoC). According to an exemplary embodiment, the AP 2310 may further include a graphic processing unit (GPU) (not shown).

The communication module 2320 may transmit/receive data in communication between the electronic device 2300 and other electronic devices connected through a network. According to an exemplary embodiment, the communication module 2320 includes a cellular module 2321, a Wifi module 2323, a BT module 2325, a GPS module 2327, an NFC module 2328, and a radio frequency (RF) module ( 2329) may be included.

The cellular module 2321 may provide a voice call, a video call, a text service, or an Internet service through a communication network (eg, LTE, LTE-A, CDMA, WCDMA, UMTS, WiBro, or GSM, etc.). Also, the cellular module 2321 may perform identification and authentication of an electronic device within a communication network using, for example, a subscriber identification module (eg, the SIM card 2324). According to an exemplary embodiment, the cellular module 2321 may perform at least some of the functions that the AP 2310 may provide. For example, the cellular module 2321 may perform at least a part of a multimedia control function.

The cellular module 2321 may include a communication processor (CP). In addition, the cellular module 2321 may be implemented as an SoC, for example. In FIG. 14 , components such as a cellular module 2321 (eg, a communication processor), a memory 2330 , or a power management module 2395 are illustrated as separate components from the AP 2310 , but in an exemplary embodiment Accordingly, the AP 2310 may be implemented to include at least some of the above-described components (eg, the cellular module 2321).

The AP 2310 or the cellular module 2321 (eg, a communication processor) may load and process a command or data received from at least one of a non-volatile memory or other components connected thereto to a volatile memory. Also, the AP 2310 or the cellular module 2321 may store data received from at least one of the other components or generated by at least one of the other components in a non-volatile memory.

Each of the Wifi module 2323, the BT module 2325, the GPS module 2327, or the NFC module 2328 may include, for example, a processor for processing data transmitted and received through a corresponding module. 23, the cellular module 2321, the Wifi module 2323, the BT module 2325, the GPS module 2327, or the NFC module 2328 are each shown as separate blocks, but according to an exemplary embodiment, the cellular module At least some (eg, two or more) of 2321, Wifi module 2323, BT module 2325, GPS module 2327, or NFC module 2328 are included in one integrated chip (IC) or IC package. can For example, at least some of the processors corresponding to each of the cellular module 2321, the Wifi module 2323, the BT module 2325, the GPS module 2327, or the NFC module 2328 (eg, the cellular module 2321) A communication processor corresponding to , and a Wifi processor corresponding to the Wifi module 2323) may be implemented as one SoC.

The RF module 2329 may transmit/receive data, for example, transmit/receive an RF signal. Although not shown, the RF module 2329 may include, for example, a transceiver, a power amp module (PAM), a frequency filter, or a low noise amplifier (LNA). In addition, the RF module 2329 may further include a component for transmitting and receiving electromagnetic waves in free space in wireless communication, for example, a conductor or a conducting wire. In FIG. 14 , the cellular module 2321 , the Wifi module 2323 , the BT module 2325 , the GPS module 2327 and the NFC module 2328 are shown to share one RF module 2329 with each other, but in an example According to an exemplary embodiment, at least one of the cellular module 2321, the Wifi module 2323, the BT module 2325, the GPS module 2327, or the NFC module 2328 transmits and receives the RF signal through a separate RF module. can be done

The SIM card 2324 may be a card including a subscriber identification module, and may be inserted into a slot formed at a specific location of the electronic device. The SIM card 2324 may include unique identification information (eg, integrated circuit card identifier (ICCID)) or subscriber information (eg, international mobile subscriber identity (IMSI)).

The memory 2330 may include an internal memory 2332 or an external memory 2334 . The built-in memory 2332 is, for example, a volatile memory (eg, dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), etc.) or non-volatile memory (eg, non-volatile memory). For example, at least one of OTPROM (one time programmable ROM), PROM (programmable ROM), EPROM (erasable and programmable ROM), EEPROM (electrically erasable and programmable ROM), mask ROM, flash ROM, NAND flash memory, NOR flash memory, etc.) may contain one.

The internal memory 2332 may be a solid state drive (SSD). External memory 2334 is a flash drive, for example, CF (compact flash), SD (secure digital), Micro-SD (micro secure digital), Mini-SD (mini secure digital), xD (extreme digital) or Memory It may further include a stick and the like. The external memory 2334 may be functionally connected to the electronic device 2300 through various interfaces. According to an exemplary embodiment, the electronic device 2300 may further include a storage device (or storage medium) such as a hard drive.

The sensor module 2340 may measure a physical quantity or sense an operating state of the electronic device 2300 to convert the measured or sensed information into an electrical signal. The sensor module 2340 includes, for example, a gesture sensor 2340A, a gyro sensor 2340B, a barometric pressure sensor 2340C, a magnetic sensor 2340D, an acceleration sensor 2340E, a grip sensor 2340F, and a proximity sensor ( 2340G), color sensor (2340H) (e.g. RGB (red, green, blue) sensor), biometric sensor (2340I), temperature/humidity sensor (2340J), illuminance sensor (2340K) or UV (ultra violet) sensor (2340M) ) may include at least one of. Additionally or alternatively, the sensor module 2340 may include, for example, an olfactory sensor (E-nose sensor, not shown), an electromyography sensor (not shown), an electroencephalogram sensor (EEG sensor, not shown), or an ECG sensor. (electrocardiogram sensor, not shown), an IR (infra red) sensor (not shown), an iris sensor (not shown), or a fingerprint sensor (not shown). The sensor module 2340 may further include a control circuit for controlling at least one or more sensors included therein.

The input device 2350 may include a touch panel 2352 , a (digital) pen sensor 2354 , a key 2356 , or an ultrasonic input device 2358 . have. The touch panel 2352 may recognize a touch input using, for example, at least one of a capacitive type, a pressure sensitive type, an infrared type, and an ultrasonic type. Also, the touch panel 2352 may further include a control circuit. In the case of capacitive, physical contact or proximity recognition is possible. The touch panel 2352 may further include a tactile layer. In this case, the touch panel 2352 may provide a tactile response to the user.

The (digital) pen sensor 2354 may be implemented, for example, using the same or similar method as receiving a user's touch input or a separate recognition sheet. Key 2356 may include, for example, a physical button, an optical key, or a keypad. The ultrasonic input device 2358 is a device that can check data by detecting sound waves from the electronic device 2300 to a microphone (eg, the microphone 2388) through an input tool that generates an ultrasonic signal. This is possible. According to an exemplary embodiment, the electronic device 2300 may receive a user input from an external device (eg, a computer or a server) connected thereto using the communication module 2320 .

The display module 2360 may include a display panel 2362 and a display driver integrated circuit 2363 (hereinafter referred to as DDI). The display panel 2362 may be, for example, a liquid-crystal display (LCD) or an active-matrix organic light-emitting diode (AM-OLED). The display panel 2362 may be implemented, for example, to be flexible, transparent, or wearable. The display panel 2362 may be composed of a touch panel 2352 and one module. The display panel 2362 may include a plurality of regions. Alternatively, there may be a plurality of display panels 2362 .

The display panel 2362 may be replaced with a hologram device or a projector. The holographic device may display a three-dimensional image in the air using interference of light. A projector can display an image by projecting light onto a screen. The screen may be located inside or outside the electronic device 2300 , for example.

The DDI 2363 may receive display data from the AP 2310 and drive the display panel 2362 based on the received display data. Meanwhile, the DDI 2363 according to an exemplary embodiment of the present disclosure may include first and second LDO regulators (not shown) to cover a wide power consumption range of a system load, and the second LDO regulator It may be connected to internal nodes of the first LDO regulator to generate a second load current to supplement the first load current of the first LDO regulator. The embodiments described in FIG. 1 and the like may be applied to the DDI 2363 , and detailed description thereof will be omitted.

The interface 2370 is, for example, a high-definition multimedia interface (HDMI) 2372, a universal serial bus (USB) 23704, an optical interface 2376, or a D-subminiature (D-sub) ( 2378) may be included. Additionally or alternatively, the interface 2370 includes, for example, a mobile high-definition link (MHL) interface, a secure digital (SD) card/multi-media card (MMC) interface, or an infrared data association (IrDA) standard interface. can do.

The audio module 2380 may interactively convert a sound and an electrical signal. The audio module 2380 may process sound information input or output through, for example, the speaker 2382 , the receiver 2384 , the earphone 2386 , or the microphone 2388 .

The camera module 2391 is a device capable of capturing still images and moving images, and according to an exemplary embodiment, one or more image sensors (eg, a front sensor or a rear sensor), a lens (not shown), an image signal processor (ISP, not shown) or a flash (not shown) (eg, LED or xenon lamp).

The power management module 2395 may manage power of the electronic device 2300 . Although not shown, the power management module 2395 may include, for example, a power management integrated circuit (PMIC), a charger integrated circuit (IC), or a battery or fuel gauge. In some embodiments, the power management module 2395 may include first and second LDO regulators to which the technical spirit of the present disclosure is applied by replacing the DDI 2363 , and providing a supply voltage to the DDI 2363 . In this regard, the technical spirit of the present disclosure may be applied to the power management module 2395 .

The PMIC may be mounted within an integrated circuit or SoC semiconductor, for example. The charging method can be divided into wired and wireless. The charger IC can charge the battery and prevent overvoltage or overcurrent from being drawn from the charger. According to an exemplary embodiment, the charging IC may include a charging IC for at least one of a wired charging method and a wireless charging method. As a wireless charging method, for example, there is a magnetic resonance method, a magnetic induction method, or an electromagnetic wave method, and an additional circuit for wireless charging, for example, a circuit such as a coil loop, a resonance circuit or a rectifier may be added. have.

The battery gauge may measure, for example, a remaining amount of the battery 2396 , voltage, current, or temperature during charging. The battery 2396 may store or generate electricity, and may supply power to the electronic device 2300 using the stored or generated electricity. The battery 2396 may include, for example, a rechargeable battery or a solar battery.

The indicator 2397 may display a specific state of the electronic device 2300 or a part thereof (eg, the AP 2310), for example, a booting state, a message state, a charging state, etc. The motor 2398 is an electrical signal Although not shown, the electronic device 2300 may include a processing device (eg, GPU) for supporting mobile TV. The processing device for supporting mobile TV may include, for example, , DMB (digital multimedia broadcasting), DVB (digital video broadcasting), or media data according to the media flow (media flow) can be processed.

Exemplary embodiments have been disclosed in the drawings and specification as described above. Although the embodiments have been described using specific terms in the present specification, these are used only for the purpose of explaining the technical spirit of the present disclosure and not used to limit the meaning or the scope of the present disclosure described in the claims. . Therefore, it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the true technical protection scope of the present disclosure should be defined by the technical spirit of the appended claims.

Claims (20)

a power supply circuit configured to generate a supply voltage from at least one of the first and second supply voltages; and
a system load configured to operate upon receiving the supply voltage through an output node of the power supply circuit;
The power supply circuit is
a first low drop-output (LDO) regulator configured to generate a first load current flowing from the first supply voltage to the system load through the output node; and
a second LDO regulator configured to selectively generate a second load current flowing from the second supply voltage to the system load through the output node based on a difference between voltages of internal nodes of the first LDO regulator characterized by an integrated circuit. According to claim 1,
The voltages of the internal nodes are
and the system load varies in response to a change in the supply voltage as a third load current drawn by the system load increases. According to claim 1,
The internal nodes are
and output a difference between a reference voltage respectively applied to the first LDO regulator and a feedback voltage corresponding to the supply voltage, respectively. According to claim 1,
The second LDO regulator,
and generate the second load current when a difference between voltages of the internal nodes is equal to or greater than a reference value. According to claim 1,
The second LDO regulator,
and a plurality of auxiliary current generating circuits configured to respectively generate an auxiliary current included in the second load current from the second power supply voltage. 6. The method of claim 5,
The second LDO regulator,
and enable at least one of the plurality of auxiliary current generating circuits based on a magnitude of a difference between voltages of the internal nodes. 7. The method of claim 6,
The second LDO regulator,
and the number of the auxiliary current generation circuits enabled increases as a difference between voltages of the internal nodes increases. According to claim 1,
The system load is
receiving the first load current from the first LDO regulator when operating in a first operating region;
and receive the second load current from the second LDO regulator together with the first load current when operating in a second region of operation. a power supply circuit configured to generate a supply voltage from at least one of the first and second supply voltages; and
a system load configured to operate on receiving the supply voltage from the power supply circuit and to draw a first load current from the power supply circuit;
The power supply circuit is
a first low drop-output (LDO) regulator configured to generate a second load current flowing from the first supply voltage to the system load; and
and a second LDO regulator configured to generate a third load current flowing from the second power supply voltage to the system load in response to a saturation state of the second load current according to the increase of the first load current. integrated circuit. 10. The method of claim 9,
The second LDO regulator,
and start generating the third load current after a predetermined interval from when the second load current reaches saturation. 10. The method of claim 9,
The second LDO regulator,
The integrated circuit of claim 1 , connected to internal nodes of the first LDO regulator and configured to generate the third load current based on a difference between voltages of the internal nodes. 12. The method of claim 11,
The internal nodes are
and output a difference between a reference voltage respectively applied to the first LDO regulator and a feedback voltage corresponding to the supply voltage, respectively. 13. The method of claim 12,
The magnitude of the voltages of the internal nodes is,
and the first load currents are equal to each other before saturation. 10. The method of claim 9,
The second LDO regulator,
and a plurality of auxiliary current generating circuits, each of which is sequentially enabled according to the magnitude of the first load current and configured to respectively generate an auxiliary current included in the third load current. 15. The method of claim 14,
The second LDO regulator,
output circuits configured to output enable control signals applied to the plurality of auxiliary current generating circuits;
Each of the output circuits,
a pull-up transistor and a pull-down transistor interconnected through a node to which the enable control signal is output;
The integrated circuit according to claim 1, wherein a ratio of a width to a length ratio between the pull-up transistor and the pull-down transistor is different. 16. The method of claim 15,
The integrated circuit according to claim 1, wherein a ratio relationship of a width to a length between the pull-up transistors of each of the output circuits is different. a first low drop-output (LDO) regulator configured to generate a first load current from the first power supply voltage;
a second LDO regulator configured to selectively generate a second load current from the second power supply voltage; and
a system load configured to draw a third load current comprising at least one of the first and second load currents from a shared output node from the first and second LDO regulators;
The first LDO regulator,
a first current generation circuit configured to apply the first power voltage to generate the first load current; and
a first comparison circuit configured to compare a feedback voltage corresponding to a voltage of the output node and a reference voltage to generate a first enable control signal and provide it to the first current generation circuit;
The second LDO regulator,
a second current generation circuit configured to apply the second power voltage to generate the second load current; and
configured to include a second comparison circuit coupled to internal nodes of the first comparison circuit and configured to compare voltages of the internal nodes to generate a second enable control signal and provide it to the second current generation circuit characterized by an integrated circuit. 18. The method of claim 17,
The internal nodes include first and second internal nodes,
The voltage of the first internal node corresponds to a positive comparison result between the feedback voltage and the reference voltage,
and the voltage of the second internal node corresponds to a negative comparison result between the feedback voltage and the reference voltage. 18. The method of claim 17,
The second current generation circuit,
a plurality of auxiliary current generating circuits configured to respectively generate an auxiliary current included in the second load current;
The second enable control signal is
and a plurality of third enable control signals provided to the plurality of auxiliary current generation circuits. 18. The method of claim 17,
and the number of the auxiliary current generating circuits enabled in response to the plurality of third enable control signals is determined based on a magnitude of a difference between voltages of the internal nodes.

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