KR20220141654A - An IC chip, a semiconductor package and a method of manufacturing IC chip - Google Patents

Abstract

According to exemplary embodiments, an integrated circuit device is provided. The device may include a noise blocking device. The integrated circuit may include: a substrate; and a plurality of metal oxide semiconductor field effect transistors (MOSFETs) formed on the substrate. An integrated circuit with improved energy efficiency can be provided.

Description

An IC chip, a semiconductor package and a method of manufacturing IC chip

The technical idea of the present invention relates to an integrated circuit (IC) device, a semiconductor package, and a method for manufacturing an IC device.

Over the past few decades, the discovery of technologies, materials and manufacturing processes has led to rapid advances in computing power and wireless communication technologies. This made high direct implementation of high-performance transistors possible, and the rate of integration doubled approximately every 18 months according to Moore's Law. Lightweight, compact, and power efficient systems are the permanent goals of the semiconductor manufacturing industry, and 3D integrated packaging is being proposed as an effective solution at this point in time when economic and physical process limits are reached.

The development of 3D integrated devices started with CMOS integrated devices presented in 1980, and has been developed through continuous research and development for 30 years. 3D integration technology includes, for example, integration of logic circuits and memory circuits, sensor packaging, and heterogeneous integration of MEMS and CMOS. The three-dimensional integration technology enables the achievement of high reliability, low power consumption, and low manufacturing cost as well as reduction of the form factor.

SUMMARY OF THE INVENTION An object to be solved by the technical idea of the present invention is to provide an integrated circuit (IC) device, a semiconductor package, and a method for manufacturing an IC device having improved energy efficiency.

The problems to be solved by the technical spirit of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to exemplary embodiments for solving the above problems, an integrated circuit (IC) device is provided. The device may include a substrate; a logic cell formed on the substrate, the logic cell comprising a plurality of metal oxide semiconductor field effect transistors (MOSFETs); first and second through silicon vias (TSVs) penetrating the substrate in a first direction perpendicular to an upper surface of the substrate; and a noise blocking element configured to be electrically connected to the first and second TSVs, wherein the noise blocking element includes: a first electrode; a second electrode formed on the first electrode; a third electrode formed on the second electrode; and a dielectric layer filling between the first electrode and the second electrode and between the second electrode and the third electrode.

According to exemplary embodiments, a semiconductor package is provided. The package may include an IC device; and a plurality of memory chips stacked on the IC device and controlled by the IC device, wherein the IC device includes: a substrate; a logic cell formed on the substrate, the logic cell comprising a plurality of MOSFETs; first and second TSVs penetrating the substrate in a first direction perpendicular to an upper surface of the substrate, wherein upper surfaces of the first and second TSVs are spaced apart from each other further than the upper surface of the substrate; and a noise blocking element configured to be electrically connected to the first and second TSVs, wherein the noise blocking element includes: a first electrode; a second electrode formed on the first electrode; a third electrode formed on the second electrode; and a dielectric layer filling between the first electrode and the second electrode and between the second electrode and the third electrode.

According to the technical idea of the present invention, an integrated circuit (IC) device with improved energy efficiency, a semiconductor package including the IC device, and a method of manufacturing an IC device are provided.

1 is a cross-sectional view illustrating an integrated circuit (IC) device according to example embodiments.
FIG. 2A is an enlarged partial cross-sectional view of a portion AA of FIG. 1 , and FIG. 2B is an enlarged partial cross-sectional view of a portion BB of FIG. 1 .
3A to 3H are cross-sectional views illustrating a method of manufacturing the IC device of FIG. 1 .
4 is a cross-sectional view illustrating a semiconductor package according to example embodiments.
5 is a plan view illustrating a semiconductor package according to some other exemplary embodiments.
6 is a cross-sectional view illustrating a semiconductor package according to other exemplary embodiments.
7 is a block diagram illustrating a system according to exemplary embodiments.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view illustrating an integrated circuit (IC) device 10 according to exemplary embodiments.

Referring to FIG. 1 , the IC device 100 may include a fin field effect transistor (FinFET) device. The FinFET device may constitute a logic cell. The logic cell may generate a control signal for controlling an external device of the IC device 100 . The logic cell may include a plurality of circuit elements such as transistors, resistors, and the like. The logic cell is, for example, AND, NAND, OR, NOR, XOR (exclusive OR), XNOR (exclusive NOR), INV (inverter), ADD (adder), BUF (buffer), DLY (delay), FIL ( filter), multiplexer (MXT/MXIT). OAI(OR/AND/INVERTER), AO(AND/OR), AOI(AND/OR/INVERTER), D flip-flop, reset flip-flop, master-slaver flip-flop, latch ) and the like, and the logic cells may constitute standard cells that perform desired logical functions such as counters and buffers.

The substrate 110 may include a semiconductor element such as germanium (Ge), or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). Alternatively, the substrate 110 may have a silicon on insulator (SOI) structure. For example, the substrate 110 may include a buried oxide layer (BOX). The substrate 110 may include a conductive region, for example, a well doped with an impurity or a structure doped with an impurity.

A device isolation layer 160 and an active region AC defined by the device isolation layer 160 may be formed on the substrate 110 . A plurality of fin-type active areas FA may protrude from the active area AC. The plurality of fin-type active regions FA may extend parallel to each other in the Y direction and may be spaced apart from each other in the X direction perpendicular to the Y direction.

The plurality of gate structures 131 may extend in the X direction crossing the plurality of fin-type active regions FA. A plurality of metal oxide semiconductor field effect transistors (MOSFETs) 130 including a plurality of gate structures 131 and source/drain regions 132 may be formed in the device layer DL along the plurality of gate structures 131 . have. Each of the plurality of MOSFETs 130 may have a three-dimensional structure in which channels are formed on the top surface and both sidewalls of the plurality of fin-type active regions FA.

Each of the plurality of gate structures 131 may include a gate insulating layer 131a, a gate line 131b, a gate insulating spacer 131c, and a gate insulating capping layer 131d.

The plurality of gate insulating layers 131a may include silicon oxide, a high-k material, or a combination thereof. The high-k material may include a material having a higher dielectric constant than silicon oxide. For example, the plurality of gate insulating layers 131a may have a dielectric constant of about 10 to 25. The high dielectric material may include a metal oxide or a metal oxynitride. For example, the high dielectric material includes a material selected from hafnium oxide, hafnium oxynitride, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, and combinations thereof. However, it is not limited to the bar illustrated above. An interface layer may be interposed between the fin-type active region FA and the gate insulating layer 131a. The interface layer may include oxide, nitride, or oxynitride.

The plurality of gate lines 131b may have a structure in which a metal nitride layer, a metal layer, a conductive capping layer, and a gap-fill metal layer are sequentially stacked. The metal nitride layer and the metal layer may include at least one metal selected from Ti, Ta, W, Ru, Nb, Mo, and Hf. The gap-fill metal layer may include a W layer or an Al layer. Each of the plurality of gate lines 131b may include a work function metal-containing layer. The work function metal-containing layer may include at least one metal selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. In some embodiments, the plurality of gate lines 131b may each have a stacked structure of TiAlC/TiN/W, a stacked structure of TiN/TaN/TiAlC/TiN/W, or a stacked structure of TiN/TaN/TiN/TiAlC/TiN/W. It may include a stacked structure, but is not limited thereto.

A gate insulating spacer 131c may be disposed on both sidewalls of each of the plurality of gate lines 131b. The gate insulating spacer 131c may cover both sidewalls of each of the plurality of gate lines 131b. The gate insulating spacer 131c may extend parallel to the gate line 131b along the second direction (Y direction) that is the lengthwise direction of the gate line 131b. The gate insulating spacer 131c may include silicon nitride, SiOCN, SiCN, or a combination thereof. In some embodiments, the plurality of gate insulating spacers 131c may include a material having a lower dielectric constant than silicon nitride, for example, SiOCN, SiCN, or a combination thereof.

A top surface of each of the plurality of gate lines 131b may be covered with a gate insulating capping layer 131d. The plurality of gate insulating capping layers 131d may include silicon nitride. The plurality of gate insulating capping layers 131d may vertically overlap the gate line 131b and the gate insulating spacer 131c, respectively, and extend in parallel to the gate line 131b.

The source/drain regions 132 may be disposed on the plurality of fin-type active regions FA. A pair of source/drain regions 132 may be formed on both sides of the plurality of gate lines 131b. The gate line 131b and the source/drain region 132 may be spaced apart from each other with the gate insulating layer 131a and the gate insulating spacer 131c interposed therebetween.

The source/drain region 132 is an impurity ion implantation region formed in a portion of the fin-type active region FA, a semiconductor epitaxial layer epitaxially grown from a plurality of recess regions formed in the fin-type active region FA, or a combination thereof. may include The plurality of source/drain regions 132 may include an epitaxially grown Si layer, an epitaxially grown SiC layer, or a plurality of epitaxially grown SiGe layers.

When the MOSFET 130 is an NMOS transistor, the plurality of source/drain regions 132 may include an epitaxially grown Si layer or an epitaxially grown SiC layer, and may include an N-type impurity. In the case of a PMOS transistor, the plurality of source/drain regions 132 may include an epitaxially grown SiGe layer and may include P-type impurities.

A portion of the plurality of source/drain regions 132 may be covered with the first insulating layer IL1 . The first insulating layer IL1 may include, but is not limited to, an insulating material such as silicon oxide or PSG (Phosphosilicate glass).

A plurality of source/drain contacts CA may be formed on the plurality of fin-type active areas FA. Each of the plurality of source/drain contacts CA may extend in a direction (eg, a Y direction) crossing the plurality of fin-type active areas FA. The plurality of source/drain contacts CA may contact the plurality of source/drain regions 132 .

A plurality of source/drain vias VA in contact with each of the plurality of source/drain contacts CA may be formed on each of the plurality of source/drain contacts CA.

A plurality of gate contacts CB may be formed on each of the plurality of gate structures 131 . The plurality of gate contacts CB may pass through the gate insulating capping layer 131d to be connected to any one of the gate lines 131b. The plurality of gate contacts CB may be positioned between a pair of source/drain contacts CA.

The second insulating layer IL2 may cover the first insulating layer IL1 and the gate insulating capping layer 131d. The second insulating layer IL2 may include silicon oxide. For example, the second insulating layer IL2 may include tetraethyl orthosilicate (TEOS) or an ultra low K (ULK) material having an ultra low dielectric constant K of about 2.2 to 2.4, but is limited thereto. it's not going to be The ULK material may include SiOC or SiCOH.

According to some embodiments, the plurality of source/drain contacts CA and the plurality of gate contacts CB may include titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or these. It may include a conductive barrier layer composed of a combination of and a conductive layer composed of Co, W, or a combination thereof. In some cases, a silicide layer may be disposed between the conductive barrier layer and the source/drain regions 132 . The silicide layer may include, for example, tungsten silicide (WSi), titanium silicide (TiSi), cobalt silicide (CoSi), or nickel silicide (NiSi).

Third to eleventh insulating layers IL3 to IL11 sequentially stacked on the second insulating layer IL2 may be formed. The third to eleventh insulating layers IL3 to IL3 may include a low-k material such as spin on dielectric (SOD).

In example embodiments, an etch stop layer made of a material such as SiC may be interposed between two adjacent layers of the first to eleventh insulating layers IL1 to IL12.

A via V1 may be formed in the third insulating layer IL3 , a metal layer M1 may be formed in the fourth insulating layer IL4 , and a metal layer M2 may be formed in the fifth insulating layer IL5 . The metal layer M3 may be formed in the sixth insulating layer IL6, the metal layer M4 may be formed in the seventh insulating layer IL7, and the metal layer M3 may be formed in the eighth insulating layer IL8. D5) may be formed, and a metal layer D6 may be formed in the ninth insulating layer IL9. A metal layer MY may be formed in the tenth insulating layer IL10 and the eleventh insulating layer IL11 . The metal layers M1, M2, M3, M4, D5, D6, and MY may be formed by a back end of line (BEOL) process and may be configured to be electrically connected to each other.

According to exemplary embodiments, titanium (Ti), tantalum ( Ta), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof, and a conductive barrier having a conformal shape may be interposed therebetween.

According to example embodiments, the conductive via V1 and the metal layer M1 in the third and fourth insulating layers IL3 and IL4 are formed through a separate process, and the fifth to eleventh insulating layers ( The metal layers M2, M3, M4, D5, D6, and MY in IL5 to IL11 are illustrated as being formed through a dual damascene process, but are not limited thereto. For example, conductive vias and conductive patterns formed by a separate process are formed on each of the third to eleventh insulating layers IL3 to IL11, or each of the third to eleventh insulating layers IL3 to IL11 is formed by a dual damascene process. A formed metal layer may be formed.

The metal layer MY may serve as a pad, and external connection terminals 181 , 182 , 183 , and 184 such as solder may be disposed on the metal layer MY. A power supply potential VDD may be applied to the connection terminal 181 , a signal SIG generated from the logic cell may be transmitted through the connection terminals 182 and 184 , and a ground potential may be applied to the connection terminal 183 . (VSS) may be applied.

A top surface of the eleventh insulating layer IL11 , a portion of the metal layer MY, and side surfaces of the external connection terminals 181 , 182 , 183 , and 184 may be covered by the passivation layer 122 . The protective layer 122 may include, for example, an insulating polymer.

The IC device 100 may further include through silicon vias (TSVs) 140 . Each of the TSVs 140 may extend in the Z direction to penetrate the substrate 110 . A lower surface of each of the TSVs 140 may be coplanar with the lower surface of the substrate 110 , and an upper surface of each of the TSVs 140 may be coplanar with the second insulating layer IL2 .

Each of the TSVs 140 may be formed between a Front End of Line (FEOL) process and a Back End of Line (BEOL) process. That is, each of the TSVs 140 may be formed by a via middle process. The TSVs 140 may further penetrate the first and second insulating layers IL1 and IL2, respectively. However, the present invention is not limited thereto, and the TSVs 140 may be formed before the FEOL process or after the BEOL process.

The TSV 140 includes a barrier layer 140B including titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), and the like, and tungsten (W), aluminum (Al), and copper (Cu). ) may include a conductive layer 140C including the like. Each of the barrier layers 140B may have a conformal shape, and the conductive layers 140C may fill the inside of the barrier layers 140B.

Additional insulating layers 150 may be interposed between the TSV 140 and the substrate 110 and between the TSV 140 and the first and second insulating layers IL1 and IL2 . Each of the insulating layers 150 may have a conformal shape.

A noise blocking element 170 may be disposed between the tenth insulating layer IL10 and the eleventh insulating layer IL11 . The noise blocking device 170 includes first to third electrodes 171 , 173 , and 175 sequentially stacked and a dielectric layer 177 interposed between the first to third electrodes 171 , 173 and 175 . can do. The noise blocking element 170 may be a capacitor. The first to third electrodes may include a conductive material such as a metal or a doped semiconductor.

The dielectric layer 177 may include a high-k material. The high-k material may include a material having a higher dielectric constant than silicon oxide. For example, the plurality of gate dielectric layers 177 may have a dielectric constant of about 10-25. The high dielectric material may include a metal oxide or a metal oxynitride. The dielectric layer 177 may insulate the first to third electrodes 171 , 173 , and 175 from each other and provide high capacitance to the noise blocking device 170 .

Hereinafter, the structure of the noise blocking device 170 will be described in more detail with reference to FIGS. 2A and 2B .

FIG. 2A is an enlarged partial cross-sectional view of a portion AA of FIG. 1 , and FIG. 2B is an enlarged partial cross-sectional view of a portion BB of FIG. 1 .

1 to 2B , the first electrode 171 may contact the tenth insulating layer IL10. The first electrode 171 may be in contact with the metal layer MY to which the power voltage VDD is applied. Accordingly, the first electrode 171 may be configured to be electrically connected to the TSV 140 to which the power voltage VDD is applied. The first electrode 171 may be horizontally spaced apart from the metal layer MY to which the signal SIG is applied and the metal layer MY to which the ground voltage VSS is applied. The first electrode 171 may be insulated from the metal layer MY to which the signal SIG is applied and the metal layer MY to which the ground voltage VSS is applied.

A portion of the dielectric layer 177 may be interposed between the first electrode 171 and the second electrode 173 . A portion of the dielectric layer 177 may be interposed between the second electrode 173 and the third electrode 175 . A portion of the dielectric layer 177 may be in contact with the tenth insulating layer IL1 .

The second electrode 173 may be in contact with the metal layer MY to which the ground voltage VSS is applied. Accordingly, the second electrode 173 may be configured to be electrically connected to the TSV 140 to which the ground voltage VSS is applied. The second electrode 173 may be horizontally spaced apart from the metal layer MY to which the signal SIG is applied and the metal layer MY to which the power voltage VDD is applied. The first electrode 171 may be insulated from the metal layer MY to which the signal SIG is applied and the metal layer MY to which the power voltage VDD is applied.

The second electrode 173 includes a first portion 173a, a second portion 173b spaced apart from the substrate 110 further than the first portion 173a, and the first portion 173a and the second portion ( It may include a step portion 173S connecting the 173b. The first portion 173a may be horizontally spaced apart from the first electrode 171 . The first portion 173a may not vertically overlap the first electrode 171 . The second portion 173b may vertically overlap the first electrode 171 .

The third electrode 175 may be in contact with the metal layer MY to which the power voltage VDD is applied. Accordingly, the third electrode 175 may be configured to be electrically connected to the TSV 140 to which the power voltage VDD is applied. The third electrode 175 may be horizontally spaced apart from the metal layer MY to which the signal SIG is applied and the metal layer MY to which the ground voltage VSS is applied. The third electrode 175 may be insulated from the metal layer MY to which the signal SIG is applied and the metal layer MY to which the ground voltage VSS is applied.

The third electrode 175 includes a first portion 175a, a second portion 175b spaced apart from the substrate 110 further than the first portion 175a, and the first portion 175a and the second portion ( It may include a step portion (175S) for connecting 175b). The first portion 175a may be horizontally spaced apart from the second electrode 173 . The first portion 175a may not vertically overlap the second electrode 173 . The second portion 175b may vertically overlap the second electrode 173 .

1 to 2B , the noise blocking element 170 in contact with the uppermost metal layer MY is provided, but the technical spirit of the present invention is not limited thereto. The IC device according to example embodiments may include a noise blocking device in contact with any one of the metal layers M2, M3, M4, D5, and D6 adjacent to the substrate 110 rather than the uppermost metal layer MY. .

According to other exemplary embodiments, a ground potential VSS may be applied to the first and third electrodes 173 and 175 , and a power potential VDD may be applied to the second electrode 174 . According to other exemplary embodiments, the noise blocking device may include four or more layers of electrodes.

According to exemplary embodiments, the power supply potential VDD and the reference potential VSS can be stably maintained in spite of external noise by the noise blocking device 170 , thereby improving the energy efficiency of the IC device 100 . and the reliability of the operation of the IC device 100 may be improved.

Referring back to FIG. 1 , the TSV 140 to which the power voltage VDD is applied and the pad 191 may contact, and the TSV 140 to which the ground voltage VSS is applied and the pad 191 may be in contact. . The lower surface of the substrate 110 on which the pads 191 and 192 are not formed may be covered by the protective layer 121 . The passivation layer 121 may include the same material as the passivation layer 122 . Connection terminals 185 and 186 may be formed on each of the pads 191 and 192 .

3A to 3H are cross-sectional views for explaining a method of manufacturing the IC device 100 of FIG. 1 .

Referring to FIG. 3A , a logic cell including a plurality of MOSFETs 130 may be formed on a substrate 110 by performing a FEOL process, and TSVs 140 may be formed through a via middle process. . Subsequently, by performing a part of the BEOL process, after forming the third to tenth insulating layers IL3 to IL10, the via V1, and the metal layers M1, M2, M3, M4, D5, D6, and My , the first electrode material layer 171L including the same material as the first electrode 171 (refer to FIG. 1 ) may be provided.

3A and 3B , the first electrode material layer 171L may be etched through a patterning process including an exposure process and an etching process to form a first electrode pattern 171P.

Referring to FIG. 3C , the dielectric material layer 177a may be formed by providing a dielectric material using various deposition processes such as chemical vapor deposition, atomic deposition, and physical vapor deposition. The dielectric material layer 177a may have a conformal shape and may insulate the first electrode pattern 171P from subsequently formed electrode layers by covering the first electrode pattern 171P.

Referring to FIG. 3D , the second electrode pattern 173P may be formed through a patterning process through a process similar to that of the first electrode pattern 171P. By patterning the second electrode pattern 173P not to at least partially overlap the first electrode pattern 171P, different potentials are applied to the first electrode 171 and the second electrode 173 as shown in FIG. 1 . can do.

Referring to FIG. 3E , the dielectric material layer 177b may be formed by conformally providing the dielectric material using various deposition processes such as chemical vapor deposition, atomic deposition, and physical vapor deposition. The dielectric material layer 177b may insulate the second electrode pattern 173P from subsequently formed electrode layers by covering the second electrode pattern 173P.

Referring to FIG. 3F , the third electrode pattern 175P may be formed through a deposition and patterning process similar to the formation of the first and second electrodes 173 and 175 .

Referring to FIG. 3G , an eleventh insulating layer IL11 may be formed. The eleventh insulating layer IL11 may be provided through, for example, a spin coating process.

Referring to FIG. 3H , a plurality of holes H1 , H2 , and H3 for forming a metal layer MY (refer to FIG. 1 ) by performing a via etching process and a trench etching process of the dual damascene process on the eleventh insulating layer IL11 . , H4) can be formed. The first to third electrodes 171 , 173 , 175 and the dielectric layer 177 having the shapes shown in FIG. 1 may be formed by forming the plurality of holes H1 , H2 , H3 , and H4 .

The hole H1 may expose the top surface of the metal layer MY and the side surfaces of the first and third electrodes 171 and 175 , and the holes H2 and H4 may expose the top surface of the metal layer MY. , the hole H3 may expose an upper surface of the metal layer MY and a side surface of the second electrode 173 .

Referring back to FIG. 1 , the metal layer MY may be provided through a BEOL process, and then the protective layer 122 and the connection terminals 181 , 182 , 183 , and 184 may be formed. In addition, the pads 191 and 192 and the connection terminals 185 and 186 may be provided to each of the TSVs 140 through a rear bumping process.

4 is a cross-sectional view illustrating a semiconductor package 40 according to example embodiments.

Referring to FIG. 4 , the semiconductor package 40 may include an IC device 400 and a chip stack CS formed on the IC device.

The IC device 400 may be the IC device 100 described with reference to FIGS. 1 to 2B .

The chip stack CS may include first to fourth semiconductor chips 411 , 412 , 413 , and 414 sequentially stacked. In FIG. 4 , four semiconductor chips 411 , 412 , 413 , and 414 are stacked, but the number of stacked semiconductor chips may be variously changed according to embodiments. For example, 2 to 32 or more semiconductor chips may be stacked.

In example embodiments, the first to fourth semiconductor chips 411 , 412 , 413 , and 414 may be memory semiconductor chips. The memory semiconductor chip is, for example, a volatile memory semiconductor chip such as dynamic random access memory (DRAM) or static random access memory (SRAM), phase-change random access memory (PRAM), magnetic random access memory (MRAM), It may be a non-volatile memory semiconductor chip such as Ferroelectric Random Access Memory (FeRAM) or Resistive Random Access Memory (ReRAM). According to some embodiments, each of the first to fourth semiconductor chips 411 , 412 , 413 , and 414 may be a DRAM semiconductor chip for configuring a high bandwidth memory (HBM).

However, the present invention is not limited thereto, and the first to fourth semiconductor chips 411 , 412 , 413 , and 414 may include various microelectronic devices, for example, MOSFETs such as complementary metal-insulator-semiconductor transistors (CMOS transistors). (metal-oxide-semiconductor field effect transistor), system LSI (large scale integration), flash memory, DRAM, SRAM, EEPROM, PRAM, MRAM, or RERAM, image sensor such as CIS (CMOS imaging sensor), MEMS (micro- electro-mechanical systems), active and passive components, etc.

The first to third semiconductor chips 411 , 412 , and 413 may include the TSV 421 , and the fourth semiconductor chip 414 may not include the TSV 421 . However, the present invention is not limited thereto, and each of the first to fourth semiconductor chips 411 , 412 , 413 , and 414 may include the TSV 421 .

In example embodiments, the first to third semiconductor chips 411 , 412 , and 413 may include upper and lower pads 422 and 423 , and the fourth semiconductor chip 414 may include lower pads. (423) only. Solders 424 may be provided between the upper pad 422 of the lower one of the first to fourth semiconductor chips 411 , 412 , 413 , and 414 and the lower pad 423 of the upper one.

Insulating layers 430 may be interposed between the first to fourth semiconductor chips 411 , 412 , 413 , and 414 . The upper pads 422 , the lower pads 423 , and the solders 424 may be covered and protected by the insulating layers 430 . Each of the insulating layers 430 may include an underfill material such as an insulating polymer or an epoxy resin.

The molding layer 440 may cover and protect the chip stack CS, and may include an epoxy mold compound (EMC) or the like.

According to some embodiments, the semiconductor package 40 may be a hybrid package. The first to fourth semiconductor chips 411 , 412 , 413 , and 414 may be a memory device or a DRAM device for implementing a hybrid memory cube (HMC).

According to some embodiments, by stacking the first to fourth semiconductor chips 411 , 412 , 413 , and 414 that is a memory chip and the IC device 400 that is a logic chip together, localized calculation and arithmetic processing are possible, deep learning It is advantageous for the implementation of the technology. Calculations in deep learning may be performed by a central processing unit such as a field programmable gate array (FPGA), a GPU, and some CPUs, but as shown in FIG. 12 , the logic layer inside the semiconductor package 40 , that is, the IC device 400 ), it is possible to increase the processing throughput per watt at a high memory bandwidth, thereby reducing energy consumption.

5 is a plan view illustrating a semiconductor package 50 according to some other exemplary embodiments.

Referring to FIG. 5 , the semiconductor package 50 may include a chip stack 510 , an interposer 520 , a package substrate 530 , and an IC device 540 .

The chip stack 510 is similar to the chip stack CS of FIG. 4 , but a memory chip disposed in a lowermost layer for forming a mold may have an increased cross-sectional area.

The IC device 540 may be a logic chip for controlling the operation of the chip stack CS′. The IC device 540 may be the IC device 100 described with reference to FIG. 1 .

The IC device 540 and the chip stack CS′ may be mounted on the interposer 520 . A connection terminal 527 such as solder may be provided between the IC device 540 and the interposer 520 and between the chip stack CS′ and the interposer 520 . The connection terminal 527 may provide an electrical connection between the chip stack CS′ and the interposer 520 and an electrical connection between the IC device 540 and the interposer 520 .

The interposer 520 may include a base B made of a semiconductor material, and upper and lower surfaces of pads 521 and 523 respectively formed on the upper and lower surfaces of the base B. The base B may be formed from, for example, a silicon wafer. In addition, an internal wiring 525 may be formed inside the base B.

The package substrate 530 may be, for example, a printed circuit board. When the package substrate 530 is a printed circuit board, the package substrate 530 may include a substrate base, and upper and lower pads respectively formed on the upper and lower surfaces. The upper and lower pads may be portions exposed by a solder resist layer among circuit wirings patterned after coating a copper foil on the upper and lower surfaces of the substrate base.

The substrate base may include at least one material selected from a phenol resin, an epoxy resin, and a polyimide.

Connection terminals 529 such as solder may be provided between the package substrate 530 and the interposer 520 . The connection terminals 529 may provide an electrical connection between the package substrate 530 and the interposer 520 .

An external connection terminal 535 may be attached to a lower surface of the package substrate 530 . The external connection terminal 535 may be, for example, a solder ball or a bump. The external connection terminal 535 may electrically connect the semiconductor package 50 and an external device.

6 is a cross-sectional view illustrating a semiconductor package 60 according to other exemplary embodiments.

In example embodiments, the semiconductor package 60 may be a TSV-based 3D complementary metal-oxide-semiconductor (CMOS) image sensor package.

The semiconductor package 60 may include first and second chips 610 and 620 formed on the IC device 630 . The first chip 610 may be an image sensor chip in which a plurality of pixels are formed. The first chip 610 may include a plurality of microlenses formed thereon.

The second chip 620 may be, for example, a memory chip in which a memory device such as a DRAM is formed.

A TSV 615 may be formed inside the first chip 610 , and a TSV 625 connected to the TSV 615 may be formed inside the second chip 620 . The first chip 610 , the second chip 620 , and the IC device may communicate with each other through the TSVs 615 and 625 .

The second chip 620 may serve as a buffer for image data recorded at a very high speed before being output to a general image signal processor at a normal speed, and enables high-speed shooting without distortion by storing a large amount of frame data.

The IC device 630 may be the IC device 100 described with reference to FIG. 1 . The IC device 630 may control operations of the first and second chips 610 and 620 . For example, the IC device 630 provides control signals such as a driving signal, a transmission signal, a reset signal, and a read signal to the pixels included in the first chip 610 , or correlated double sampling (CDS) and auto gain control (AGC). ), or operates as an A/D converter (Analog to Digital Converter).

7 is a block diagram illustrating a system 1200 in accordance with example embodiments.

Referring to FIG. 7 , a system 1200 includes a controller 1210 , an input/output device 1220 , a storage device 1230 , and an interface 1240 . According to some embodiments, the system 1200 includes at least one of the IC device 100 of FIG. 1 , the semiconductor package 40 of FIG. 4 , the semiconductor package 50 of FIG. 5 , and the semiconductor package 60 of FIG. 6 . may include, or be implemented by.

The system 1200 may be a mobile system or a system that transmits or receives information. In some embodiments, the mobile system is a PDA, portable computer, web tablet, wireless phone, mobile phone, digital music player, or memory card. (memory card).

The controller 1210 is for controlling an executable program in the system 1200 and may include a microprocessor, a digital signal processor, a microcontroller, or a similar device.

The input/output device 1220 may input or output data of the system 1200 . The system 1200 may be connected to an external device, for example, a personal computer or a network, using the input/output device 1220 , and may exchange data with the external device. The input/output device 1220 may be, for example, a keypad, a keyboard, or a display.

The storage device 1230 may store codes and/or data for the operation of the controller 1210 or data processed by the controller 1210 .

The interface 1240 may be a data transmission path between the system 1200 and another external device. The controller 1210 , the input/output device 1220 , the storage device 1230 , and the interface 1240 may communicate with each other via the bus 1250 . The system 1200 may be included in a mobile phone, an MP3 player, a navigation system, a portable multimedia player (PMP), a solid state disk (SSD), or household appliances. can

As described above, embodiments of the present invention have been described with reference to the accompanying drawings, but it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

Claims (10)

Board;
a logic cell formed on the substrate, the logic cell comprising a plurality of metal oxide semiconductor field effect transistors (MOSFETs);
first and second through silicon vias (TSVs) penetrating the substrate in a first direction perpendicular to an upper surface of the substrate; and
and a noise blocking element configured to be electrically connected to the first and second TSVs,
The noise blocking element is
a first electrode;
a second electrode formed on the first electrode;
a third electrode formed on the second electrode; and
and a dielectric layer filling between the first electrode and the second electrode and between the second electrode and the third electrode. According to claim 1,
The first and third electrodes are configured to be electrically connected to the first TSV,
The second electrode is configured to be electrically connected to the second TSV. 3. The method of claim 2,
A power supply potential is applied to the first TSV and a ground potential is applied to the second TSV. According to claim 1,
The second electrode is
first part;
a second portion spaced apart from the substrate further than the first portion; and
and a step portion connecting the first portion and the second portion. 5. The method of claim 4,
The first portion is horizontally spaced apart from the first electrode, and
and the second portion vertically overlaps the first electrode. According to claim 1,
The third electrode is
first part;
a second portion spaced apart from the substrate further than the first portion; and
and a step portion connecting the first portion and the second portion. 7. The method of claim 6,
The first portion is horizontally spaced apart from the second electrode, and
and the second portion vertically overlaps the second electrode. According to claim 1,
The logic cell generates a control signal for controlling an external device,
The IC device, characterized in that the control signal is not applied to the noise blocking device. IC devices; and
a plurality of memory chips stacked on the IC device and controlled by the IC device,
The IC device is
Board;
a logic cell formed on the substrate, the logic cell comprising a plurality of MOSFETs;
first and second TSVs penetrating the substrate in a first direction perpendicular to a top surface of the substrate, wherein top surfaces of the first and second TSVs are farther apart than the top surface of the substrate; and
and a noise blocking element configured to be electrically connected to the first and second TSVs,
The noise blocking element is
a first electrode;
a second electrode formed on the first electrode;
a third electrode formed on the second electrode; and
and a dielectric layer filling between the first electrode and the second electrode and between the second electrode and the third electrode. 10. The method of claim 9,
the logic cell generates a control signal for controlling the plurality of memory chips;
The control signal is not applied to the noise blocking element, and
A power supply potential is applied to the first TSV and a ground potential is applied to the second TSV.

Images