KR20220140389A - A semiconductor device and method of forming the same - Google Patents

Abstract

The present invention provides a semiconductor device with improved electrical characteristics. The semiconductor device comprises: an integrated circuit on a substrate; an interlayer insulation film on the substrate; a contact connected to the integrated circuit through the interlayer insulation film; a wire layer arranged on the interlayer insulation film, and having a wire connected to the contact; a first protective film arranged on the wire layer; a first pad and a second pad arranged on the first protective film; and a penetration electrode connected to the first pad through the substrate, the interlayer insulation film, the wire layer, and the first protective film. The first pad includes a first had unit positioned on the first protective film, and a protruding unit extended from the first head unit into the first protective film, and surrounding the side of the penetration electrode in the first protective film. The second pad can be connected to the integrated circuit through the contact and the wire.

Description

A semiconductor device and its manufacturing method

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device having a through electrode and a manufacturing method thereof.

As the size and design rules of semiconductor devices are gradually reduced, the scale down of transistors is required. As the size of the transistors is reduced, the operating characteristics of the semiconductor device may be deteriorated. Accordingly, various methods for forming semiconductor devices with superior performance while overcoming limitations due to high integration of semiconductor devices are being studied.

In order to electrically connect a semiconductor device to another semiconductor device or a printed circuit board, a through electrode penetrating the substrate has been proposed. The through-electrode can be used for three-dimensional mounting and can realize a faster transmission speed compared to conventional solder balls or solder bumps. Therefore, it is necessary to form an electrically reliable through electrode.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device with improved electrical characteristics and a method for manufacturing the same.

Another object to be solved by the present invention is to provide a semiconductor device with improved structural stability and a method for manufacturing the same.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

A semiconductor device according to embodiments of the present invention for solving the above technical problems includes an integrated circuit formed on a substrate, an interlayer insulating film on the substrate, a contact connected to the integrated circuit through the interlayer insulating film, and the interlayer insulating film a wiring layer disposed on and having a wiring connected to the contact, a first passivation layer disposed on the wiring layer, first and second pads disposed on the first passivation layer, and the substrate, the interlayer insulating layer, and the It may include a through electrode connected to the first pad through the wiring layer and the first passivation layer. The first pad includes a first head portion positioned on the first passivation layer, and a protrusion extending from the first head portion into the first passivation layer and enclosing a side surface of the through electrode in the first passivation layer. can do. The second pad may be connected to the integrated circuit through the wiring and the contact.

A semiconductor device according to embodiments of the present invention for solving the above technical problems includes a substrate having an integrated circuit and a contact electrically connected to the integrated circuit, an interlayer insulating film covering the integrated circuit and the contact on the substrate, and the interlayer A passivation layer on an insulating layer, a first pad and a second pad spaced apart from each other in the passivation layer, a wiring pattern connecting the contact and the second pad between the interlayer insulating layer and the passivation layer, and spaced apart from the contact and the wiring pattern and a through electrode connected to the first pad through the substrate and the interlayer insulating layer, and a third pad connected to the through electrode on a lower surface of the substrate. A portion of the first pad may cover a side surface of the through electrode. The uppermost end of the wiring pattern may be positioned at a level lower than the uppermost end of the through electrode.

A method of manufacturing a semiconductor device according to embodiments of the present invention for solving the above technical problems includes forming an interlayer insulating layer covering an integrated circuit and a substrate provided with a contact electrically connected to the integrated circuit, on the interlayer insulating layer forming stacked wiring layers, forming a lower protective film on the wiring layers, forming a through electrode penetrating a part of the substrate, the interlayer insulating film, the wiring layers and the lower protective film, the lower protective film and the lower protective film forming an upper passivation layer on the through electrode, performing an etching process on the upper passivation layer to form a first opening exposing the through electrode and a second opening exposing a wiring pattern of the wiring layers; and filling the first opening and the second opening with a conductive material to form a first pad connected to the through electrode and a second pad connected to the wiring pattern of the wiring layers.

In the semiconductor device according to the embodiments of the present invention, the through electrode may pass through the substrate, the interlayer insulating layer, and the wiring layers to be directly connected to the upper pad corresponding to the pad of the semiconductor device. Accordingly, the electrical resistance between the upper pad and the through electrode may be small. In addition, the upper pad is provided to be in contact with both the side surfaces of the through electrode in addition to the upper surface of the through electrode, so that the contact resistance between the upper pad and the through electrode may be small. That is, a semiconductor device having improved electrical characteristics may be provided.

In addition, since connection wires are not provided between the upper pad and the through electrode, and electrical connection toward the upper pad is provided using only one through electrode having a large width in the semiconductor device, the semiconductor device can be resistant to external impact, Structural stability of the semiconductor device may be improved.

1 is a plan view illustrating a semiconductor device according to embodiments of the present invention.
2 is a cross-sectional view illustrating a semiconductor device according to embodiments of the present invention.
3 and 4 are enlarged views illustrating an enlarged area A of FIG. 2 .
5 is a plan view schematically illustrating a semiconductor device according to embodiments of the present invention.
FIG. 6 is an enlarged plan view of the first and second regions of FIG. 5 .
7 is a cross-sectional view illustrating a semiconductor device according to embodiments of the present invention.
8 is a cross-sectional view illustrating a semiconductor package including a semiconductor device according to embodiments of the present invention.
9 is a cross-sectional view illustrating a semiconductor module including a semiconductor device according to embodiments of the present invention.
10 to 20 are cross-sectional views for explaining a method of manufacturing a semiconductor device according to embodiments of the present invention.

A semiconductor device according to the concept of the present invention will be described with reference to the drawings.

1 is a plan view illustrating a semiconductor device according to embodiments of the present invention. FIG. 2 is a cross-sectional view for explaining a semiconductor device according to embodiments of the present invention, and corresponds to a cross-section taken along line A-A' of FIG. 1 . 3 and 4 are enlarged views illustrating an enlarged area A of FIG. 2 .

1 and 2 , a substrate 100 may be provided. The substrate 100 may have an upper surface 100a and a lower surface 100b opposite to the upper surface 100a. The upper surface 100a of the substrate 100 may be an active surface, and the lower surface 100b of the substrate 100 may be an inactive surface. The substrate 100 may be a semiconductor substrate including silicon (Si), germanium (Ge), silicon-germanium (Si-Ge), or the like, or a compound semiconductor substrate. For example, the substrate 100 may be a silicon substrate. The substrate 100 may have a first region RG1 and a second region RG2 positioned in the first direction D1 from the first region RG1 . The first region RG1 may correspond to a region in which the integrated circuit 102 to be described later is provided, and the second region RG2 may correspond to a region for vertical connection of semiconductor devices. 1 and 2 , another first region RG1 may be disposed in the first direction D1 of the second region RG2 . However, the present invention is not limited thereto, and the first region RG1 may be provided only on one side of the second region RG2 or may be provided at various locations around the first region RG1 . Hereinafter, for convenience of description, components of the semiconductor device will be described with reference to one first region RG1 . When a plurality of first regions RG1 are provided, the description of one first region RG1 may be equally applied to the remaining first region RG1 or the remaining first regions RG1. .

An integrated circuit 102 may be provided on the top surface 100a of the substrate 100 . The integrated circuit 102 may be positioned on the first region RG1 of the substrate 100 . The integrated circuit 102 may include memory circuitry, logic circuitry, or a combination thereof. Although FIG. 2 illustrates that the integrated circuit 102 is a planar transistor as an example, the present invention is not limited thereto. The integrated circuit 102 may include a gate all around (GAA) type transistor or a vertical type transistor. Also, unlike shown, the integrated circuit 102 may include a combination of a plurality of transistors. The integrated circuit 102 may include various passive components, such as resistors or capacitors, along with the transistors.

An interlayer insulating layer 110 may be provided on the substrate 100 . The interlayer insulating layer 110 may cover the components of the integrated circuit 102 on the upper surface 100a of the substrate 100 . That is, the integrated circuit 102 may be buried by the interlayer insulating layer 110 . The interlayer insulating layer 110 may include a silicon oxide layer (SiO) or a silicon nitride layer (SiN). For example, the interlayer insulating layer 110 may include a tetraethyl ortho silicate oxide layer (Tetra Ethyl Ortho Silicate Oxide, TEOS Oxide).

At least one contact 104 may be provided in the interlayer insulating layer 110 . The contact 104 may be located on the first region RG1 . The contact 104 may vertically penetrate the interlayer insulating layer 110 to contact the upper surface 100a of the substrate 100 , and may be electrically connected to the substrate 100 or the integrated circuit 102 . For example, if integrated circuit 102 includes a transistor, contact 104 may be coupled to a source or drain of the transistor. The contact 104 may include a metal such as copper (Cu), tungsten (W), aluminum (Al), or a combination thereof. Although the contact 104 is illustrated as having a single pillar shape in FIG. 2 , the present invention is not limited thereto. The contact 104 may include a plurality of sub-contacts positioned at different levels and wirings connecting the plurality of sub-contacts between the plurality of sub-contacts.

At least one wiring layer RL1 , RL2 , and LR3 may be provided on the interlayer insulating layer 110 . The wiring layers RL1 , RL2 , and LR3 may be sequentially stacked on the upper surface of the interlayer insulating layer 110 . In FIG. 2 , it is illustrated as including three wiring layers RL1 , RL2 , and LR3 , but the present invention is not limited thereto. One or two wiring layers may be provided, or a plurality of four or more wiring layers may be provided according to the degree of integration or wiring density in the semiconductor device. Hereinafter, the description will be continued based on the embodiment of FIG. 2 . Each of the wiring layers RL1 , RL2 , and LR3 may include a capping layer 142 , 144 , 146 , an intermetallic insulating layer 152 , 154 , 156 , and wiring patterns 162 , 164 , and 166 .

The first wiring layer RL1 may include a first capping layer 142 , a first intermetallic insulating layer 152 , and a first wiring pattern 162 .

A first capping layer 142 may be provided on the interlayer insulating layer 110 . The first capping layer 142 may cover the top surface of the interlayer insulating layer 110 and the top surface of the contact 104 . The first capping layer 142 may include a silicon nitride layer (SiN). Alternatively, the first capping layer 142 may include an insulator having a low dielectric constant capable of blocking diffusion of metal components constituting the contact 104 . For example, the insulator having the low dielectric constant may include silicon carbonitride (SiCN) or the like.

A first intermetallic insulating layer 152 may be provided on the first capping layer 142 . The first intermetallic insulating layer 152 may cover an upper surface of the first capping layer 142 . The first intermetallic insulating layer 152 may include a silicon oxide layer (SiO) or a silicon nitride layer (SiN). For example, the first intermetallic insulating layer 152 may include a tetraethyl orthosilicate oxide layer (TEOS oxide).

A first wiring pattern 162 may be provided in the first intermetallic insulating layer 152 . The first wiring pattern 162 may be positioned on the first region RG1 of the substrate 100 . The first wiring pattern 162 may penetrate the first intermetallic insulating layer 152 and the first capping layer 142 to make contact with the contact 104 and the internal wiring pattern 112 . The first wiring pattern 162 may include an intermetallic compound such as a metal such as copper (Cu), tungsten (W), or aluminum (Al), or a combination thereof.

The first wiring pattern 162 may have a damascene structure. For example, the first wiring pattern 162 may include a first conductive pattern CP constituting a horizontal redistribution in the first intermetallic insulating layer 152 on the first region RG1 , and a first intermetallic insulating layer 152 . 152 and a first wiring via VI vertically penetrating through the first capping layer 142 and connected to the lower surface of the first conductive pattern CP. The upper surface of the first conductive pattern CP may be exposed on the upper surface of the first intermetallic insulating layer 152 . The upper surface of the first conductive pattern CP and the upper surface of the first intermetallic insulating layer 152 may be coplanar. The first wiring via VI may pass through the first intermetallic insulating layer 152 and the first capping layer 142 to connect the first conductive pattern CP and the contact 104 . The first conductive pattern CP may be connected to the first wiring via VI on the first wiring via VI, and the first conductive pattern CP and the first wiring via VI may form an integral body. A width of the first conductive pattern CP may be greater than a width of the first interconnection via VI. That is, the first conductive pattern CP and the first wiring via VI may have a T-shaped cross-section.

A first seed/barrier pattern may be provided between the first wiring pattern 162 and the first intermetallic insulating layer 152 . The first seed/barrier pattern may surround side surfaces and lower surfaces of the first wiring pattern 162 . That is, the first seed/barrier pattern may cover the side and lower surfaces of the first conductive pattern CP and the side and lower surfaces of the first interconnection via VI. The first seed/barrier pattern serves as a seed layer for forming the first wiring pattern 162 during a semiconductor device manufacturing process, or a component between the first wiring pattern 162 and the first intermetallic insulating layer 152 . It can serve as a barrier film to prevent diffusion. The first seed/barrier pattern may be a multilayer film including only one of the seed layer and the barrier layer, or a multilayer layer including both the seed layer and the barrier layer. The seed layer may include gold (Au), silver (Ag), nickel (Ni), tungsten (W), or the like. The barrier layer may include a metal nitride layer or a multilayer of a metal layer and a metal nitride layer. The metal nitride layer may include at least one of a titanium nitride layer (TiN), a tantalum nitride layer (TaN), a tungsten nitride layer (WN), a nickel nitride layer (NiN), a cobalt nitride layer (CoN), and a platinum nitride layer (PtN). The first seed/barrier pattern may not be provided as necessary.

The second wiring layer RL2 may have a configuration similar to that of the first wiring layer RL1 . For example, the second wiring layer RL2 may include a second capping layer 144 , a second intermetallic insulating layer 154 , and a second wiring pattern 164 .

A second capping layer 144 may be provided on the first intermetallic insulating layer 152 of the first wiring layer RL1 . The second capping layer 144 may cover the top surface of the first intermetallic insulating layer 152 and the top surface of the first wiring pattern 162 . The second capping layer 144 may include a silicon nitride layer (SiN). Alternatively, the second capping layer 144 may include an insulator having a low dielectric constant capable of blocking diffusion of a metal component constituting the first wiring pattern 162 .

A second intermetallic insulating layer 154 may be provided on the second capping layer 144 . The second intermetallic insulating layer 154 may cover the upper surface of the second capping layer 144 . The second intermetallic insulating layer 154 may include a silicon oxide layer (SiO) or a silicon nitride layer (SiN). For example, the second intermetallic insulating layer 154 may include a tetraethyl orthosilicate oxide layer (TEOS oxide).

A second wiring pattern 164 may be provided in the second intermetallic insulating layer 154 . The second wiring pattern 164 may be positioned on the first region RG1 of the substrate 100 . The second wiring pattern 164 may penetrate the second intermetallic insulating layer 154 and the second capping layer 144 to contact the first wiring pattern 162 . The second wiring pattern 164 may include an intermetallic compound such as a metal such as copper (Cu), tungsten (W), or aluminum (Al), or a combination thereof.

The second wiring pattern 164 may have a damascene structure. For example, the second wiring pattern 164 includes a second conductive pattern constituting a horizontal redistribution in the second intermetallic insulating layer 154 on the first region RG1 , and a second intermetallic insulating layer 154 and The second wiring via may vertically penetrate through the second capping layer 144 and be connected to the lower surface of the second conductive pattern. The upper surface of the second conductive pattern may be exposed on the upper surface of the second intermetallic insulating layer 154 . The upper surface of the second conductive pattern and the upper surface of the second intermetallic insulating layer 154 may be coplanar. The second wiring via may pass through the second intermetallic insulating layer 154 and the second capping layer 144 to connect the second conductive pattern and the first conductive pattern CP.

A second seed/barrier pattern may be provided between the second wiring pattern 164 and the second intermetallic insulating layer 154 . The second seed/barrier pattern may surround side surfaces and lower surfaces of the second wiring pattern 164 . The second seed/barrier pattern may be a multilayer film including only one of the seed layer and the barrier layer, or a multilayer layer including both the seed layer and the barrier layer. The second seed/barrier pattern may not be provided as necessary.

The third wiring layer RL3 may have a configuration similar to that of the first wiring layer RL1 and the second wiring layer RL2 . For example, the third wiring layer RL3 may include a third capping layer 146 , a third intermetallic insulating layer 156 , and a third wiring pattern 166 .

A third capping layer 146 may be provided on the second intermetallic insulating layer 154 of the second wiring layer RL2 . The third capping layer 146 may cover the top surface of the second intermetallic insulating layer 154 and the top surface of the second wiring pattern 164 . The third capping layer 146 may include a silicon nitride layer (SiN). Alternatively, the third capping layer 146 may include an insulator having a low dielectric constant capable of blocking diffusion of a metal component constituting the second wiring pattern 164 .

A third intermetallic insulating layer 156 may be provided on the third capping layer 146 . The third intermetallic insulating layer 156 may cover an upper surface of the third capping layer 146 . The third intermetallic insulating layer 156 may include a silicon oxide layer (SiO) or a silicon nitride layer (SiN). For example, the third intermetallic insulating layer 156 may include a tetraethyl orthosilicate oxide layer (TEOS oxide).

A third wiring pattern 166 may be provided in the third intermetallic insulating layer 156 . The third wiring pattern 166 may be positioned on the first region RG1 of the substrate 100 . The third wiring pattern 166 may penetrate the third intermetallic insulating layer 156 and the third capping layer 146 to contact the second wiring pattern 164 . The third wiring pattern 166 may include a metal such as copper (Cu), tungsten (W), aluminum (Al), or a combination thereof.

The third wiring pattern 166 may have a damascene structure. For example, the third wiring pattern 166 may include a third conductive pattern and a third intermetallic insulating layer 156 and a third conductive pattern constituting a horizontal redistribution in the third intermetallic insulating layer 156 on the first region RG1 . The third wiring via may vertically penetrate through the capping layer 146 and be connected to the lower surface of the third conductive pattern. The upper surface of the third conductive pattern may be exposed on the upper surface of the third intermetallic insulating layer 156 . The upper surface of the third conductive pattern and the upper surface of the third intermetallic insulating layer 156 may be coplanar. The third wiring via may pass through the third intermetallic insulating layer 156 and the third capping layer 146 to connect the third conductive pattern and the second conductive pattern.

A third seed/barrier pattern may be provided between the third wiring pattern 166 and the third intermetallic insulating layer 156 . The third seed/barrier pattern may surround side surfaces and lower surfaces of the third wiring pattern 166 . The third seed/barrier pattern may be a multilayer film including only one of the seed layer and the barrier layer, or a multilayer layer including both the seed layer and the barrier layer. The third seed/barrier pattern may not be provided as needed.

A fourth capping layer 148 may be provided on the third wiring layer RL3 . The fourth capping layer 148 may cover the top surface of the third intermetallic insulating layer 156 and the top surface of the third wiring pattern 166 . The fourth capping layer 148 may include a silicon nitride layer (SiN). Alternatively, the fourth capping layer 148 may include an insulator having a low dielectric constant capable of blocking diffusion of a metal component constituting the third wiring pattern 166 . For example, the insulator having the low dielectric constant may include silicon carbonitride (SiCN) or the like.

A first upper passivation layer 172 may be provided on the fourth capping layer 148 . The first upper passivation layer 172 may cover the upper surface of the fourth capping layer 148 . The first upper passivation layer 172 may include an insulator such as a silicon oxide layer (SiO), a silicon nitride layer (SiN), or a polymer. For example, the first upper passivation layer 172 may include a tetraethyl orthosilicate oxide layer (TEOS oxide).

The through electrode 130 may be provided in the substrate 100 , the interlayer insulating layer 110 , the first to third wiring layers RL1 , RL2 , and LR3 , and the first upper passivation layer 172 . The through electrode 130 may be positioned on the second region RG2 of the substrate 100 . The through electrode 130 may vertically penetrate the substrate 100 , the interlayer insulating layer 110 , the first to third wiring layers RL1 , RL2 , and LR3 , and the first upper passivation layer 172 . The through electrode 130 may have a vertically extending column shape. In this case, the through electrode 130 may be spaced apart from the integrated circuit 102 , the contact 104 , and the first to third wiring patterns 162 , 164 , and 166 by a predetermined distance. The lower surface of the through electrode 130 may be exposed on the lower surface 100b of the substrate 100 . The upper surface 130a of the through electrode 130 may be exposed on the upper surface 172a of the first upper passivation layer 172 . In this case, the upper surface of the through electrode 130 may be positioned at the same level as the upper surface 172a of the first upper passivation layer 172 from the substrate 100 . The upper surface 130a of the through electrode 130 may be coplanar with the upper surface 172a of the first upper passivation layer 172 . The upper surface 130a of the through electrode 130 may be positioned at a level higher than the upper surface of the third wiring pattern 166 . The through electrode 130 may include at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), and cobalt (Co).

The through electrode 130 may have a barrier layer 134 on an outer wall of the through electrode 130 . The barrier layer 134 may surround the conductive portion 132 of the through electrode 130 . Here, the conductive portion 132 of the through electrode 130 refers to a metal portion of the through electrode 130 surrounded by the barrier layer 134 . That is, the barrier layer 134 may cover the outer wall of the conductive portion 132 of the through electrode 130 . The barrier layer 134 may prevent a component (eg, copper (Cu)) of the conductive portion 132 of the through electrode 130 from diffusing into the substrate 100 or the integrated circuit 102 . The barrier layer 134 may include a metal nitride layer or a multilayer of a metal layer and a metal nitride layer. The metal nitride layer may include at least one of a titanium nitride layer (TiN), a tantalum nitride layer (TaN), a tungsten nitride layer (WN), a nickel nitride layer (NiN), a cobalt nitride layer (CoN), and a platinum nitride layer (PtN). The barrier layer 134 may not be provided as necessary.

Although not shown, between the through electrode 130 and the first upper passivation layer 172 , between the through electrode 130 and the first to third wiring layers RL1 , RL2 , and RL3 , and between the through electrode 130 and the interlayer A seed layer may be provided between the insulating layer 110 and between the through electrode 130 and the substrate 100 . The seed layer may include gold (Au) or nickel (Ni). The seed layer may not be provided as needed.

Between the through electrode 130 and the first upper passivation layer 172 , between the through electrode 130 and the first to third wiring layers RL1 , RL2 , and RL3 , and between the through electrode 130 and the interlayer insulating layer 110 . The through-electrode insulating layer 120 may be interposed between the electrodes and between the through-electrode 130 and the substrate 100 . The through electrode insulating layer 120 may surround the outer wall of the through electrode 130 . In this case, the through electrode insulating layer 120 may expose a portion of the outer wall of the through electrode 130 . For example, the upper surface of the through electrode insulating layer 120 may be located at a level lower than the upper surface 130a of the through electrode 130 , and the upper outer surface of the through electrode insulating layer 120 is the through electrode insulating layer 120 . ) may not be covered by The through electrode insulating layer 120 may separate the through electrode 130 from the substrate 100 , the interlayer insulating layer 110 , the first to third wiring layers RL1 , RL2 , and RL3 , and the first upper protective layer 172 . have. The through electrode insulating layer 120 may not be provided as necessary.

A second upper passivation layer 174 may be provided on the first upper passivation layer 172 . The second upper passivation layer 174 may cover the upper surface 172a of the first upper passivation layer 172 . The second upper passivation layer 174 may include the same material as the material constituting the first upper passivation layer 172 . The second upper passivation layer 174 may include an insulator such as a silicon oxide layer (SiO), a silicon nitride layer (SiN), or a polymer.

A first upper pad 182 and a second upper pad 184 may be provided on the second upper passivation layer 174 . The first upper pad 182 and the second upper pad 184 may be buried in the second upper passivation layer 174 on the first upper passivation layer 172 . The first upper pad 182 and the second upper pad 184 may be exposed on the upper surface of the second upper passivation layer 174 . The first upper pad 182 and the second upper pad 184 may correspond to pads of a semiconductor device to which upper terminals 192 to be described later are connected.

The first upper pad 182 may be disposed in the second upper passivation layer 174 on the first region RG1 . The first upper pad 182 is exposed on the upper surface of the second upper passivation layer 174 , passes through the first upper passivation layer 172 and the fourth capping layer 148 , and is electrically connected to the third wiring pattern 166 . can be connected to The first upper pad 182 may be connected to the integrated circuit 102 through the first to third wiring patterns 162 , 164 , and 166 and the contact 104 . 2 and 3 , the first upper pad 182 is illustrated as having a pad shape, but the present invention is not limited thereto. The first upper pad 182 may include a metal material such as copper (Cu).

The first upper pad 182 may have a damascene structure. For example, the first upper pad 182 passes through the first head unit HP1 positioned on the first upper passivation layer 172 and the first upper passivation layer 172 to be connected to the first head unit HP1 . It may include a via part VP. The first head part HP1 and the via part VP may be provided integrally. That is, the first head portion HP1 and the via portion VP may be portions of the first upper pad 182 . In this specification, for convenience of description, the configuration of the first head part HP1 and the via part VP will be separately referred to.

The first head unit HP1 may be provided in the second upper passivation layer 174 on the first upper passivation layer 172 . In a plan view, the first head unit HP1 may be surrounded by the second upper passivation layer 174 . A portion of the first head part HP1 may be buried in the first upper passivation layer 172 . For example, the lower surface of the first head unit HP1 may be located at a level lower than the upper surface of the first upper passivation layer 172 from the substrate 100 . Here, the upper surface of the first upper passivation layer 172 may be defined as a surface exposed from one side of the first upper pad 182 or the second upper pad 184 among the surfaces of the first upper passivation layer 172 . . The upper surface of the first head part HP1 may be exposed on the upper surface of the second upper passivation layer 174 . The upper surface of the first head part HP1 and the upper surface of the second upper passivation layer 174 may be coplanar. The width of the first head part HP1 may be uniform regardless of the distance from the substrate 100 .

The via part VP may vertically penetrate the first upper passivation layer 172 and the fourth capping layer 148 to connect the first head part HP1 and the third wiring pattern 166 . The first head part HP1 may be connected to the via part VP on the via part VP, and may be integrally formed with the first head part HP1 and the via part VP. The width of the via part VP may be smaller than the width of the first head part HP1 . That is, the first head part HP1 and the via part VP may have a T-shaped cross section. The width of the through electrode 130 may be 20 to 100 times the width of the via portion VP. If necessary, as shown in FIGS. 2 and 3 , a plurality of via parts VP may be provided. The uppermost end of the via portion VP may be positioned at a level lower than the upper surface 172a of the first upper passivation layer 172 . The width of the via portion VP may be uniform regardless of the distance from the substrate 100 . However, the present invention is not limited thereto, and the width of the via portion VP may not be uniform according to a distance from the substrate 100 .

A first seed layer 183 may be provided between the first upper pad 182 and the first upper passivation layer 172 and between the first upper pad 182 and the second upper passivation layer 174 . The first seed layer 183 may surround side surfaces and lower surfaces of the first upper pad 182 . That is, the first seed layer 183 may cover the side and lower surfaces of the first head part HP1 and the side and lower surfaces of the via part VP. The first seed layer 183 may include gold (Au), silver (Ag), nickel (Ni), tungsten (W), or the like. Although not shown, the first barrier along with the first seed layer 183 is between the first upper pad 182 and the first upper passivation layer 172 and between the first upper pad 182 and the second upper passivation layer 174 . A membrane may be provided. The first barrier layer may include a metal nitride layer or a multilayer of a metal layer and a metal nitride layer. The metal nitride layer may include at least one of a titanium nitride layer (TiN), a tantalum nitride layer (TaN), a tungsten nitride layer (WN), a nickel nitride layer (NiN), a cobalt nitride layer (CoN), and a platinum nitride layer (PtN).

The second upper pad 184 may be disposed in the second upper passivation layer 174 on the second region RG2 . The second upper pad 184 may be exposed on the upper surface of the second upper passivation layer 174 and may be electrically connected to the through electrode 130 . That is, the second upper pad 184 may be positioned on the through electrode 130 and may be in contact with the through electrode 130 . 2 and 3 , the second upper pad 184 is illustrated as having a pad shape, but the present invention is not limited thereto. The second upper pad 184 may include a metal material such as copper (Cu).

The second upper pad 184 may have a damascene structure. For example, the second upper pad 184 may include a second head portion HP2 positioned on the first upper passivation layer 172 and a protrusion PP extending into the first upper passivation layer 172 . . The second head part HP2 and the protrusion part PP may be provided integrally. That is, the second head portion HP2 and the protrusion portion PP may be portions of the second upper pad 184 . In this specification, for convenience of description, the configuration of the second head part HP2 and the protrusion part PP will be referred to separately.

The second head part HP2 may be provided in the second upper passivation layer 174 on the through electrode 130 . In a plan view, the second head unit HP2 may be surrounded by the second upper passivation layer 174 . A lower surface of the second head unit HP2 may be in contact with an upper surface of the through electrode 130 . The lower surface of the second head unit HP2 may be positioned at the same level as the upper surface 172a of the first upper passivation layer 172 and the upper surface of the through electrode 130 from the substrate 100 . A planar shape of the second head part HP2 may be larger than a planar shape of the through electrode 130 . For example, the width of the second head part HP2 may be greater than the width of the through electrode 130 . In a plan view, the through electrode 130 may be disposed below the central portion of the second head unit HP2 . That is, the through electrode 130 is positioned below the second head part HP2 , but may be spaced apart from the side surface of the second head part HP2 . The upper surface of the second head unit HP2 may be exposed on the upper surface of the second upper passivation layer 174 . The upper surface of the second head unit HP2 and the upper surface of the second upper passivation layer 174 may be coplanar. The width of the second head part HP2 may be uniform regardless of the distance from the substrate 100 .

The protrusion PP may extend from the lower surface of the second head part HP2 into the first upper passivation layer 172 . The protrusion PP may not completely vertically penetrate the first upper passivation layer 172 . That is, the lower surface of the protrusion PP may be located in the first upper passivation layer 172 . The lower surface of the protrusion PP may be positioned at a higher level from the substrate 100 than the lower surface of the first upper passivation layer 172 and the lower surface of the via portion VP of the first upper pad 182 . In this case, the lower surface of the protrusion PP may be positioned at the same level as the lower surface of the first head portion HP1 of the first upper pad 182 and the substrate 100 .

The protrusion PP may extend along a side surface of the through electrode 130 . For example, in a plan view, the protrusion PP may surround the through electrode 130 . In other words, the protrusion PP may cover an upper side surface of the through electrode 130 in the first upper passivation layer 172 . The planar shape of the protrusion PP may have a closed curve shape surrounding the through electrode 130 . For example, when the planar shape of the through electrode 130 is circular, the planar shape of the protrusion PP may be a circular ring shape, or when the planar shape of the through electrode 130 is rectangular, the protrusion PP. The planar shape of may be a quadrangular ring shape. The width of the protrusion PP may be uniform regardless of the distance from the substrate 100 . Here, the width of the protrusion PP means a distance from the inner surface of the protrusion PP to the outer surface of the protrusion PP. An outer surface of the protrusion PP may be coplanar with an outer surface of the second head portion HP2 .

The protrusion PP may be in contact with a side surface of the through electrode 130 . Specifically, the upper surface of the through electrode insulating film 120 may be lower than the upper surface of the through electrode 130 from the substrate 100 , and the upper outer surface of the through electrode 130 is exposed from the through electrode insulating film 120 . can be In other words, the through electrode 130 may protrude on the upper surface of the through electrode insulating layer 120 . The upper surface of the through-electrode insulating layer 120 may be positioned at the same level as the lower surface of the first head unit HP1 and the substrate 100 . A lower surface of the protrusion PP may be in contact with the upper surface of the through-electrode insulating layer 120 . The protrusion PP may surround the upper portion of the exposed through electrode 130 , and may contact the outer surface of the upper portion of the exposed through electrode 130 . The distance from the outer surface of the through electrode 130 to the outer surface of the protrusion PP may be uniform regardless of the distance from the substrate 100 .

According to embodiments of the present invention, the through electrode 130 penetrates through all of the substrate 100 , the interlayer insulating layer 110 , and the wiring layers RL1 , RL2 , and RL3 to the second upper pad corresponding to the pad of the semiconductor device. It can be directly connected to (184). Accordingly, the electrical resistance between the second upper pad 184 and the through electrode 130 may be small. In addition, the second upper pad 184 is provided to contact both the outer surface of the through electrode 130 in addition to the upper surface of the through electrode 130 , and accordingly, the second upper pad 184 and the through electrode 130 . The contact resistance between them may be small. That is, a semiconductor device having improved electrical characteristics may be provided.

In addition, connection wires are not provided between the second upper pad 184 and the through electrode 130 , and the electrical connection toward the second upper pad 184 in the semiconductor device uses only one of the through electrodes 130 having a large width. As it is provided by using, complicated wires for electrical connection between the second upper pad 184 and the through electrode 130 are not required, so that it can be strong against external impact. In addition, since the through electrode 130 having a large width vertically penetrates the wiring layers RL1 , RL2 and RL3 , the through electrode 130 is subjected to external stress and strain in the wiring of the wiring layers RL1 , RL2 , and RL3 . can be prevented from proceeding. That is, the semiconductor device may be resistant to external impact, and structural stability of the semiconductor device may be improved.

between the second upper pad 184 and the first upper passivation layer 172 , between the second upper pad 184 and the second upper passivation layer 174 , and between the second upper pad 184 and the through electrode 130 . Two seed layers 185 may be provided. The second seed layer 185 may surround side surfaces and lower surfaces of the second upper pad 184 . That is, the second seed layer 185 may cover the side and lower surfaces of the second head unit HP2 and the side and lower surfaces of the protrusion PP. The second seed layer 185 may include gold (Au), silver (Ag), nickel (Ni), tungsten (W), or the like. Although not shown, between the second upper pad 184 and the first upper passivation layer 172 , between the second upper pad 184 and the second upper passivation layer 174 , and between the second upper pad 184 and the through electrode 130 . ), a second barrier layer may be provided together with the second seed layer 185 between them. The second barrier layer may include a metal nitride layer or a multilayer of a metal layer and a metal nitride layer. The metal nitride layer may include at least one of a titanium nitride layer (TiN), a tantalum nitride layer (TaN), a tungsten nitride layer (WN), a nickel nitride layer (NiN), a cobalt nitride layer (CoN), and a platinum nitride layer (PtN).

According to other embodiments, as shown in FIG. 4 , the width of the first head part HP1 of the first upper pad 182 and the width of the second head part HP2 of the second upper pad 184 are Silver may decrease toward the substrate 100 . In this case, the width of the protrusion PP may also decrease toward the substrate 100 . In other words, the distance from the outer surface of the through electrode 130 to the outer surface of the protrusion PP may decrease toward the substrate 100 . The outer surface of the protrusion PP may be coplanar with the outer surface of the second head portion HP2 . That is, the outer surface of the protrusion PP and the outer surface of the second head part HP2 may form a single inclined surface inclined with respect to the upper surface of the first upper passivation layer 172 . Hereinafter, the description will be continued based on the embodiment of FIGS. 1 to 3 .

Upper terminals 192 may be provided on the first upper pad 182 and the second upper pad 184 . The upper terminals 192 may be connection terminals for connecting a semiconductor device to an external device. For example, the upper terminals 192 may be solder balls.

A lower passivation layer 176 may be provided under the substrate 100 . The lower passivation layer 176 may cover the lower surface 100b of the substrate 100 . In this case, the lower passivation layer 176 may expose the lower surface of the through electrode 130 . For example, the through electrode 130 includes the first upper protective layer 172 , the first to third wiring layers RL1 , RL2 , and RL3 , the interlayer insulating layer 110 , the substrate 100 , and the lower protective layer 176 . It can penetrate vertically.

A lower pad 186 may be provided under the lower passivation layer 176 . The lower pad 186 may cover the lower surface of the through electrode 130 on the lower surface of the lower passivation layer 176 . The lower pad 186 may be electrically connected to the through electrode 130 . Although the lower pad 186 is illustrated in FIG. 2 as having a pad shape, the present invention is not limited thereto. The lower pad 186 may be in the form of a solder ball connected to the through electrode 130 .

5 is a plan view schematically illustrating a semiconductor device according to embodiments of the present invention.

Referring to FIG. 5 , a logic chip may be provided. The logic chip may include first regions RG1 on the substrate 100 . For example, the first regions RG1 may be logic cell regions. The first regions RG1 may be two-dimensionally arranged on the substrate 100 . Each of the first regions RG1 may be a region in which logic cells constituting a logic circuit are disposed. The first regions RG1 illustrated in FIG. 5 may exemplify one logic cell.

The logic chip may further include a second region RG2 adjacent to the first regions RG1 . The second region RG2 may be a connection region. The first regions RG1 may be disposed on one side of the second region RG2 or may surround the periphery of the second region RG2 . At least one through electrode 130 may be provided in the second region RG2 .

FIG. 6 is an enlarged plan view of the first and second regions of FIG. 5 . 7 is a cross-sectional view for explaining a semiconductor device according to embodiments of the present invention, and corresponds to a cross-section taken along line B-B' of FIG. 6 .

6 and 7 , the substrate 100 may include active regions AR. For example, each of the active regions AR may be a P-MOSFET region or an N-MOSFET region. The substrate 100 may be a semiconductor substrate such as silicon (Si), germanium (Ge), silicon-germanium (Si-Ge), or a compound semiconductor substrate. For example, the substrate 100 may be a silicon substrate.

Active regions AR may be defined on the substrate 100 . The active regions AR may be spaced apart from each other in the second direction D2 . Each of the active regions AR may extend in the first direction D1 .

Active patterns AP may be provided on each of the active areas AR. The active patterns AP may extend parallel to each other in the first direction D1 . The active patterns AP are a part of the substrate 100 , and may be portions that vertically protrude upward from the substrate 100 . The active patterns AP adjacent to each other may be spaced apart from each other by a trench TR positioned therebetween.

The device isolation layer ST may fill between the active regions AR and between the active patterns AP. For example, the trench TR separating the adjacent active patterns AP may be filled by the device isolation layer ST. The device isolation layer ST may include a silicon oxide layer (SiO). Upper portions of the active patterns AP may protrude vertically onto the device isolation layer ST. Each of upper portions of the active patterns AP may have a fin shape. The device isolation layer ST may not cover upper portions of the active patterns AP. The device isolation layer ST may cover lower sidewalls of the active patterns AP.

Source/drain patterns SD may be provided on upper portions of the active patterns AP. The source/drain patterns SD may be impurity regions of the first conductivity type. For example, the first conductivity type may be a p-type. A channel pattern may be interposed between the pair of source/drain patterns SD. The source/drain patterns SD may be epitaxial patterns formed by a selective epitaxial growth process. For example, upper surfaces of the source/drain patterns SD may be coplanar with upper surfaces of the channel patterns. As another example, upper surfaces of the source/drain patterns SD may be higher than upper surfaces of the channel patterns.

Gate electrodes GE crossing the active patterns AP and extending in the second direction D2 may be provided. The gate electrodes GE may be arranged in the first direction D1 at a constant pitch. The gate electrodes GE may vertically overlap the channel patterns. Each of the gate electrodes GE may surround an upper surface and both sidewalls of each of the channel patterns.

A pair of gate spacers GS may be disposed on both sidewalls of each of the gate electrodes GE. The gate spacers GS may extend in the second direction D2 along the gate electrodes GE. Top surfaces of the gate spacers GS may be higher than top surfaces of the gate electrodes GE. Top surfaces of the gate spacers GS may be coplanar with the top surface of the first interlayer insulating layer 114 to be described later. The gate spacers GS may include at least one of carbonitride (SiCN), silicon carbonoxynitride (SiCON), and silicon nitride (SiN).

A gate capping pattern GP may be provided on each of the gate electrodes GE. The gate capping pattern GP may extend in the second direction D2 along the gate electrode GE. The gate capping pattern GP may include a material having etch selectivity with respect to first and second interlayer insulating layers 114 and 116 to be described later. Specifically, the gate capping patterns GP may include at least one of silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon carbon dioxide nitride (SiCON), and silicon nitride (SiN).

A gate insulating layer GI may be interposed between the gate electrode GE and the active pattern AP. The gate insulating layer GI may extend along the lower surface of the gate electrode GE positioned on the gate insulating layer GI. The gate insulating layer GI may cover the upper surface of the device isolation layer ST under the gate electrode GE. The gate insulating layer GI may include a high-k material having a higher dielectric constant than that of the silicon oxide layer. For example, the high dielectric constant material is hafnium oxide (HfO ₂ ), hafnium zirconium oxide (HfZrO ₂ ), zirconium oxide (ZrO ₂ ), zirconium silicon oxide (ZrSiO ₄ ), tantalum oxide (TaO) or titanium oxide (TiO) may include

A first interlayer insulating layer 114 may be provided on the substrate 100 . The first interlayer insulating layer 114 may cover the gate spacers GS and the source/drain patterns SD. A top surface of the first interlayer insulating layer 114 may be substantially coplanar with top surfaces of the gate capping patterns GP and top surfaces of the gate spacers GS. A second interlayer insulating layer 116 covering the gate capping patterns GP may be provided on the first interlayer insulating layer 114 . A third interlayer insulating layer 118 may be provided on the second interlayer insulating layer 116 . The first to third interlayer insulating layers 114 , 116 , and 118 may include a silicon oxide layer. The first to third interlayer insulating layers 114 , 116 , and 118 may constitute one interlayer insulating layer 110 .

Active contacts AC may be provided through the first and second interlayer insulating layers 114 and 116 to be electrically connected to the source/drain patterns SD, respectively. Each of the active contacts AC may be provided between a pair of gate electrodes GE. The active contact AC may be a self-aligned contact. In other words, the active contact AC may be formed in self-alignment using the gate capping pattern GP and the gate spacer GS. For example, the active contact AC may cover at least a portion of a sidewall of the gate spacer GS. Although not shown, the active contact AC may cover a portion of the upper surface of the gate capping pattern GP.

The active contact AC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. The barrier pattern BM may cover sidewalls and a lower surface of the conductive pattern FM. The conductive pattern FM may include at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), and cobalt (Co). The barrier pattern BM may include a metal nitride layer or a metal layer/metal nitride layer. The metal layer may include at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), and platinum (Pt). The metal nitride layer may include at least one of a titanium nitride layer (TiN), a tantalum nitride layer (TaN), a tungsten nitride layer (WN), a nickel nitride layer (NiN), a cobalt nitride layer (CoN), and a platinum nitride layer (PtN).

A silicide pattern SC may be interposed between the active contact AC and the source/drain pattern SD. The active contact AC may be electrically connected to the source/drain pattern SD through the silicide pattern SC. The silicide pattern SC may include metal-silicide. For example, the silicide pattern SC is titanium-silicide (Ti silicide), tantalum-silicide (Ta silicide), tungsten-silicide (W silicide), nickel-silicide (Ni silicide), and cobalt-silicide (Co silicide). may include at least one of

Connection patterns CNP may be provided in the third interlayer insulating layer 118 . The connection patterns CNP may be provided on the active contacts AC. The connection patterns CNP may be connected to the active contacts AC. Although not shown, each of the connection patterns CNP may include a conductive pattern and a barrier pattern. The conductive pattern may include the same or different metal from the conductive pattern FM of the active contacts AC.

At least one wiring layer RL1 , RL2 , and RL3 may be provided on the interlayer insulating layer 110 . The wiring layers RL1 , RL2 , and RL3 may be sequentially stacked on the upper surface of the interlayer insulating layer 110 .

The first wiring layer RL1 may include a first capping layer 142 , a first intermetallic insulating layer 152 , and a first wiring pattern 162 .

A first capping layer 142 may be provided on the interlayer insulating layer 110 . The first capping layer 142 may cover the upper surface of the interlayer insulating layer 110 , the upper surface of the connection patterns CNP, the upper surface of the internal wiring pattern 112 , and the upper surface of the through electrode 130 .

A first intermetallic insulating layer 152 may be provided on the first capping layer 142 . The first intermetallic insulating layer 152 may cover an upper surface of the first capping layer 142 .

A first wiring pattern 162 may be provided in the first intermetallic insulating layer 152 . The first wiring pattern 162 may penetrate the first intermetallic insulating layer 152 and the first capping layer 142 to contact the connection patterns CNP.

The second wiring layer RL2 may have a configuration similar to that of the first wiring layer RL1 . The second wiring layer RL2 may include a second capping layer 144 , a second intermetallic insulating layer 154 , and a second wiring pattern 164 .

A second capping layer 144 may be provided on the first intermetallic insulating layer 152 of the first wiring layer RL1 . The second capping layer 144 may cover the top surface of the first intermetallic insulating layer 152 and the top surface of the first wiring pattern 162 .

A second intermetallic insulating layer 154 may be provided on the second capping layer 144 . The second intermetallic insulating layer 154 may cover the upper surface of the second capping layer 144 .

A second wiring pattern 164 may be provided in the second intermetallic insulating layer 154 . The second wiring pattern 164 may penetrate the second intermetallic insulating layer 154 and the second capping layer 144 to contact the first wiring pattern 162 .

The third wiring layer RL3 may have a configuration similar to that of the first wiring layer RL1 and the second wiring layer RL2 . The third wiring layer RL3 may include a third capping layer 146 , a third intermetallic insulating layer 156 , and a third wiring pattern 166 .

A third capping layer 146 may be provided on the second intermetallic insulating layer 154 of the second wiring layer RL2 . The third capping layer 146 may cover the top surface of the second intermetallic insulating layer 154 and the top surface of the second wiring pattern 164 .

A third intermetallic insulating layer 156 may be provided on the third capping layer 146 . The third intermetallic insulating layer 156 may cover an upper surface of the third capping layer 146 .

A third wiring pattern 166 may be provided in the third intermetallic insulating layer 156 . The third wiring pattern 166 may penetrate the third intermetallic insulating layer 156 and the third capping layer 146 to contact the second wiring pattern 164 .

A fourth capping layer 148 may be provided on the second wiring layer RL2 . The fourth capping layer 148 may cover the top surface of the third intermetallic insulating layer 156 and the top surface of the third wiring pattern 166 .

A first upper passivation layer 172 may be provided on the fourth capping layer 148 . The first upper passivation layer 172 may cover the upper surface of the fourth capping layer 148 .

The through electrode 130 may be provided in the substrate 100 , the interlayer insulating layer 110 , the first to third wiring layers RL1 , RL2 , and LR3 , and the first upper passivation layer 172 . The through electrode 130 may be positioned on the second region RG2 of the substrate 100 . The through electrode 130 may vertically penetrate the substrate 100 , the device isolation layer ST, the interlayer insulating layer 110 , the first to third wiring layers RL1 , RL2 , and LR3 , and the first upper protective layer 172 . can The through electrode 130 may have a vertically extending column shape. The lower surface of the through electrode 130 may be exposed on the lower surface of the substrate 100 . The upper surface 130a of the through electrode 130 may be exposed on the upper surface 172a of the first upper passivation layer 172 .

The through electrode 130 may have a barrier layer 134 on an outer wall of the through electrode 130 . The barrier layer 134 may surround the conductive portion 132 of the through electrode 130 . That is, the barrier layer 134 may surround the outer wall of the through electrode 130 .

The through electrode insulating layer 120 may be interposed between the through electrode 130 and the interlayer insulating layer 110 and between the through electrode 130 and the substrate 100 . In the substrate 100 , the interlayer insulating layer 110 , the first to third wiring layers RL1 , RL2 , and RL3 , and the first upper passivation layer 172 , the through electrode insulating layer 120 forms an outer wall of the barrier layer 134 . can be wrapped

A second upper passivation layer 174 may be provided on the first upper passivation layer 172 . The second upper passivation layer 174 may cover the upper surface 172a of the first upper passivation layer 172 .

A first upper pad 182 and a second upper pad 184 may be provided on the second upper passivation layer 174 . The first upper pad 182 and the second upper pad 184 may be buried in the second upper passivation layer 174 on the first upper passivation layer 172 .

The first upper pad 182 may be disposed in the second upper passivation layer 174 on the first region RG1 . The first upper pad 182 is exposed on the upper surface of the second upper passivation layer 174 , passes through the first upper passivation layer 172 and the fourth capping layer 148 , and is electrically connected to the third wiring pattern 166 . can be connected to The first upper pad 182 includes a first head portion HP1 positioned on the first upper protective layer 172 and a via portion connected to the first head portion HP1 through the first upper protective layer 172 . (VP) may be included.

The second upper pad 184 may be disposed in the second upper passivation layer 174 on the second region RG2 . The second upper pad 184 may be exposed on the upper surface of the second upper passivation layer 174 and may be electrically connected to the through electrode 130 . The second upper pad 184 may include a second head portion HP2 positioned on the first upper passivation layer 172 and a protrusion PP extending into the first upper passivation layer 172 . The protrusion PP may be in contact with an upper side surface of the exposed through electrode 130 .

Upper terminals 192 may be provided on the first upper pad 182 and the second upper pad 184 . The upper terminals 192 may be connection terminals for connecting a semiconductor device to an external device. For example, the upper terminals 192 may be solder balls.

A lower passivation layer 176 may be provided under the substrate 100 . The lower passivation layer 176 may cover the lower surface 100b of the substrate 100 , and the lower passivation layer 176 may expose the lower surface of the through electrode 130 .

A lower pad 186 may be provided under the lower passivation layer 176 . The lower pad 186 may be electrically connected to the through electrode 130 on the lower surface of the lower passivation layer 176 .

8 is a cross-sectional view illustrating a semiconductor package including a semiconductor device according to embodiments of the present invention.

Referring to FIG. 8 , the semiconductor package 10 includes a package substrate 210 such as a printed circuit board (PCB) to which an external terminal 212 is attached, and an application processor mounted on the package substrate 210 ( 230 : Application Processor), a memory chip 250 stacked on the application processor 230 , and a mold layer 260 covering the application processor 230 and the memory chip 250 . The semiconductor package 10 may be used in a mobile product such as, for example, a mobile phone or a tablet computer.

The application processor 230 may be electrically connected to the package substrate 210 through the solder balls 220 disposed on the package substrate 210 . The memory chip 250 may be electrically connected to the application processor 230 through the solder balls 240 disposed on the application processor 230 . The application processor 230 may be mounted on the package substrate 210 with the active surface facing the package substrate 210 or the active surface facing the memory chip 250 . The memory chip 250 may be stacked on the application processor 230 with its active surface facing the application processor 230 . The application processor 230 may include a through electrode 235 . For example, the application processor 230 may have the same or similar structure to the semiconductor device of FIGS. 1 to 7 . The description of the semiconductor device of FIGS. 1 to 7 may be similarly applied to the application processor 230 .

9 is a cross-sectional view illustrating a semiconductor module including a semiconductor device according to embodiments of the present invention.

Referring to FIG. 9 , the semiconductor module 20 includes a package substrate 310 such as a printed circuit board (PCB) to which an external terminal 312 is attached, a chip stack 360 mounted on the package substrate 310 , and graphics. It may be, for example, a memory module including a processing unit 350 (GPU) and a mold layer 370 covering the chip stack 360 and the graphic processing unit 350 . The semiconductor module 20 may further include an interposer 330 provided on the package substrate 310 .

The graphic processing unit 350 and the chip stack 360 may be electrically connected to the interposer 330 through a solder ball 340 disposed on the interposer 330 . The interposer 330 may include a through electrode 335 , and may be electrically connected to the package substrate 310 through a solder ball 320 disposed on the package substrate 310 .

The chip stack 360 may include a plurality of stacked high-band memory chips 361 , 362 , 363 , and 364 . The memory chips 361 , 362 , 363 , and 364 may be electrically connected to each other through solder balls 367 . At least one of the memory chips 361 , 362 , 363 , and 364 may include a through electrode 365 . For example, each of the first memory chip 361 , the second memory chip 362 , and the third memory chip 363 may include at least one through electrode 365 . The fourth memory chip 364 may not include a through electrode. As another example, the fourth memory chip 364 may include a through electrode 365 . At least the first to third memory chips 361 , 362 , and 363 of the memory chips 361 , 362 , 363 , and 364 may have the same or similar structure to the semiconductor device of FIGS. 1 to 7 . The description of the semiconductor device of FIGS. 1 to 7 may be similarly applied to the first to third memory chips 361 , 362 , and 363 .

10 to 20 are cross-sectional views for explaining a method of manufacturing a semiconductor device according to embodiments of the present invention.

Referring to FIG. 10 , a substrate 100 having an upper surface 100a and a lower surface 100b facing the upper surface 100a may be provided. The substrate 100 may include a semiconductor substrate such as silicon (Si).

The interlayer insulating layer 110 including the integrated circuit 102 may be formed on the upper surface 100a of the substrate 100 . The integrated circuit 102 may include memory circuitry, logic circuitry, or a combination thereof. The interlayer insulating layer 110 may be formed of a silicon oxide layer (SiO) or a silicon nitride layer (SiN). For example, the insulating interlayer 110 may include a tetraethyl orthosilicate oxide (TEOS oxide) formed by chemical vapor deposition (CVD). At least one electrical contact 104 vertically penetrating the interlayer insulating layer 110 may be formed by patterning the interlayer insulating layer 110 and depositing a conductor. The contacts 104 may contact the substrate 100 and may be electrically connected to the substrate 100 or the integrated circuit 102 .

Referring to FIG. 11 , a first capping layer 142 covering the interlayer insulating layer 110 may be formed. The first capping layer 142 may cover the interlayer insulating layer 110 and the contact 104 . For example, the first capping layer 142 may include a silicon nitride layer (SiN) formed by chemical vapor deposition (CVD). Alternatively, the first capping layer 142 may include an insulator (eg, silicon carbonitride (SiCN), etc.) having a low dielectric constant capable of preventing diffusion of metal components constituting the contact 104 .

A first intermetallic insulating layer 152 may be formed on the first capping layer 142 . The first intermetallic insulating layer 152 may include a tetraethylorthosilicate oxide layer (TEOS oxide) formed by chemical vapor deposition (CVD) in the same manner as or similarly to the interlayer insulating layer 110 .

A first wiring pattern 162 connected to the contact 104 may be formed in the first intermetallic insulating layer 152 . The first wiring pattern 162 may include a metal such as copper (Cu), tungsten (W), aluminum (Al), or a combination thereof. For example, the first wiring pattern 162 may include copper formed by a damascene process. For example, the first wiring pattern 162 includes a first conductive pattern CP constituting a horizontal redistribution in the first intermetallic insulating layer 152 , a first intermetallic insulating layer 152 , and a first capping layer ( ). The first interconnection via VI may vertically penetrate through 142 and be connected to the lower surface of the first conductive pattern CP. For example, the first wiring pattern 162 may be formed by, for example, a dual damascene process.

As described above, the first wiring layer RL1 including the first capping layer 142 , the first intermetallic insulating layer 152 and the first wiring pattern 162 may be formed.

A second wiring layer RL2 and a third wiring layer RL3 may be sequentially formed on the first wiring layer RL1 . A method of forming the second wiring layer RL2 and the third wiring layer RL3 may be substantially the same as or similar to a method of forming the first wiring layer RL1 . For example, the second wiring layer RL2 is formed by sequentially forming the second capping layer 144 , the second intermetallic insulating layer 154 , and the second wiring pattern 164 on the first intermetallic insulating layer 152 . A third wiring layer RL3 is formed by sequentially forming a third capping layer 146 , a third intermetallic insulating layer 156 , and a third wiring pattern 166 on the second intermetallic insulating layer 154 . can be The second capping layer 144 and the third capping layer 146 may be formed in the same or similar manner as the first capping layer 142 . For example, the second capping layer 144 and the third capping layer 146 may include a silicon nitride layer (SiN) formed by chemical vapor deposition (CVD). The second intermetallic insulating layer 154 and the third intermetallic insulating layer 156 may be formed in the same or similar manner as the first intermetallic insulating layer 152 . For example, the second intermetallic insulating layer 154 and the third intermetallic insulating layer 156 may include a tetraethylorthosilicate oxide layer (TEOS oxide) formed by chemical vapor deposition (CVD). The second wiring pattern 164 and the third wiring pattern 166 may be formed in the same or similar manner as the first wiring pattern 162 . For example, the second wiring pattern 164 and the third wiring pattern 166 may include copper formed by a damascene process.

As described above, the second wiring layer RL2 including the second capping layer 144 , the second intermetallic insulating layer 154 , and the second wiring pattern 164 , the third capping layer 146 , and the third intermetallic insulating layer A third wiring layer RL3 including 156 and a third wiring pattern 166 may be formed.

A fourth capping layer 148 may be formed on the third wiring layer RL3 . The fourth capping layer 148 may be formed in the same or similar manner as the first capping layer 142 . For example, the fourth capping layer 148 may include a silicon nitride layer (SiN) formed by chemical vapor deposition (CVD).

Referring to FIG. 12 , a first upper passivation layer 172 may be formed on the fourth capping layer 148 . For example, the first upper passivation layer 172 may be formed by depositing an insulator such as a silicon oxide layer (SiO), a silicon nitride layer (SiN), or a polymer on the fourth capping layer 148 .

A polishing stop layer 171 may be formed on the first upper passivation layer 172 . The polishing stop layer 171 may be formed of a material different from that of the first upper passivation layer 172 . For example, the polishing stop layer 171 may include a silicon nitride layer (SiN) formed by chemical vapor deposition (CVD).

A via hole vertically penetrating the polishing stop layer 171 , the first upper passivation layer 172 , the first to third wiring layers RL1 , RL2 , and RL3 , the interlayer insulating layer 110 , and the substrate 100 through a photo and etching process (101) may be formed. The via hole 101 may completely penetrate the polishing stop layer 117 , the first upper passivation layer 172 , the first to third wiring layers RL1 , RL2 , and RL3 , and the interlayer insulating layer 110 . The via hole 101 may partially penetrate the substrate 100 and may not reach the lower surface 100b of the substrate 100 .

Referring to FIG. 13 , an insulating layer 122 covering an inner wall of the via hole 101 and an upper surface of the polishing stop layer 111 may be formed. The insulating layer 122 may be formed by depositing a high-aspect-ration process (HARP) oxide layer using sub-atmosheric chemical vapor deposition (SACVD).

The via hole 101 may be filled by forming a conductive layer 136 on the substrate 100 . The conductive layer 136 may be formed by depositing or plating polysilicon (poly Si), copper (Cu), tungsten (W), aluminum (Al), or the like.

When the conductive layer 136 is formed of copper (Cu) or a conductor including copper, a metal layer 138 capable of blocking diffusion of the copper (Cu) element may be further formed on the insulating layer 122 . The metal layer 138 may be formed of titanium (Ti), titanium nitride (TiN), chromium (Cr), tantalum (Ta), tantalum nitride (TaN), nickel (Ni), tungsten (W), tungsten nitride (WN), or A metal including a combination thereof may be deposited to form a shape extending along the insulating layer 122 .

Referring to FIG. 14 , the conductive layer 136 may be planarized using a chemical mechanical polishing (CMP) process. The chemical mechanical polishing process may proceed until the polishing stop layer 171 is removed. In the planarization process, the insulating layer 122 and the metal layer 138 may be polished together with the conductive layer 136 . Through the planarization process, the conductive layer 136 may be formed as the conductive portion 132 of the through-electrode 130 having a pillar shape, for example, filled in the via hole 101 , and the insulating layer 122 may be formed of the through-electrode 130 . It may be formed of the through-electrode insulating layer 120 having a cup shape surrounding the outer wall and the lower surface. When the metal layer 138 is further formed, the metal layer 138 is formed such that the component (eg, copper (Cu)) of the conductive part 132 of the through electrode 130 is formed on the substrate 100 by the planarization process. Alternatively, it may be formed as a barrier layer 134 that prevents diffusion into the integrated circuit 102 . An upper surface of the first upper passivation layer 172 may be exposed by the planarization process. The upper surface of the first upper passivation layer 172 may be coplanar with the upper surface of the through electrode 130 .

Alternatively, the planarization process may be performed until the polishing stop layer 171 is exposed. In this case, the polishing stop layer 171 may be selectively removed after the planarization process. For example, by an etching process using an etchant capable of selectively removing the polishing stop layer 171 , the polishing stop layer 171 may be removed from the substrate 100 . By removing the polishing stop layer 171 , the upper surface of the first upper passivation layer 172 and the through electrode 130 may be exposed. In some embodiments, the through electrode 130 may protrude on the upper surface of the first upper passivation layer 172 .

According to other embodiments, the polishing stop layer 171 may not be provided. In this case, the upper surface of the through electrode 130 may be coplanar with the upper surface of the first upper passivation layer 172 .

Referring to FIG. 15 , a second upper passivation layer 174 may be formed on the first upper passivation layer 172 . The second upper passivation layer 174 may be formed through a process substantially the same as or similar to the process of forming the first upper passivation layer 172 . For example, the second upper passivation layer 174 may be formed by depositing an insulator such as a silicon oxide layer (SiO), a silicon nitride layer (SiN), or a polymer on the first upper passivation layer 172 . The second upper passivation layer 174 may be formed of the same material as the material constituting the first upper passivation layer 172 . The second upper passivation layer 174 may cover the first upper passivation layer 172 and the through electrode 130 .

Referring to FIG. 16 , an etching process may be performed on the second upper passivation layer 174 to form first holes H1 . The first holes H1 pass through the second upper passivation layer 174 , the first upper passivation layer 172 , and the fourth capping layer 148 to pass through the upper surface of the third wiring pattern 166 of the third wiring layer RL3 . can be exposed. In a plan view, the first holes H1 may be disposed on one side of the through electrode 130 .

Referring to FIG. 17 , a sacrificial layer 178 may be formed on the second upper passivation layer 174 . The sacrificial layer 178 may cover the upper surface of the second upper passivation layer 174 and may fill the inside of the first holes H1 .

A mask pattern MP may be formed on the sacrificial layer 178 . The pattern of the mask pattern MP may expose a top surface of the sacrificial layer 178 through the first holes H1 and expose the top surface of the sacrificial layer 178 on the through electrode 130 .

Referring to FIG. 18 , an etching process using the mask pattern MP as an etching mask may be performed on the sacrificial layer 178 to form a second hole H2 and a third hole H3 . The second hole H2 may be formed on the first holes H1 , and the third hole H3 may be formed on the through electrode 130 . The second hole H2 and the third hole H3 may be formed to completely penetrate the sacrificial layer 178 and the second upper passivation layer 174 . A portion of the first upper passivation layer 172 may be removed together by the etching process. That is, the second hole H2 and the third hole H3 may be formed to extend into the first upper passivation layer 172 . The bottom surface H3a of the second hole H2 and the third hole H3 may be lower than the top surface 172a of the first upper passivation layer 172 . The first holes H1 may be exposed on the bottom surface of the second hole H2 . The through electrode 130 may protrude onto the bottom surface H3a of the third hole H3. During the etching process, the through electrode insulating layer 120 may be etched together. Accordingly, the upper surface of the through electrode insulating layer 120 may form a coplanar surface with the bottom surface H3a of the third hole H3. An upper outer surface of the through electrode 130 may be exposed in the third hole H3 .

Referring to FIG. 19 , the mask pattern MP and the sacrificial layer 178 may be removed to expose an upper surface of the second upper passivation layer 174 . The sacrificial layer 178 in the first holes H1 may be removed, so that the first holes H1 and the second hole H2 may be connected to each other. The first holes H1 define a region in which a via portion VP of a first upper pad 182 to be described later is formed, and the second hole H2 is a first head of a first upper pad 182 to be described later. A region in which the portion HP1 is formed may be defined. A space located on one side of the through electrode 130 in the third hole H3 defines a region in which a protrusion PP of a second upper pad 184 to be described later is formed, and a through electrode in the third hole H3. A space positioned at a level higher than 130 may define a region in which the second head portion HP2 of the second upper pad 184, which will be described later, is formed.

A seed layer 188 may be formed on the second upper passivation layer 174 . The seed layer 188 may be formed to conformally cover the top surface of the second upper passivation layer 174 , the inside of the second hole H2 , and the inside of the third hole H3 . In particular, the seed layer 188 may contact the upper surface of the through electrode 130 and the exposed outer surface of the through electrode 130 in the third hole H3 .

A conductive layer 189 may be formed on the seed layer 188 . The conductive layer 189 may cover the upper surface of the second upper passivation layer 174 and may fill the inside of the second hole H2 and the inside of the third hole H3 .

Referring to FIG. 20 , the conductive layer 189 may be planarized using a planarization process such as a chemical mechanical polishing (CMP) process. The planarization polishing process may be performed until the upper surface of the upper passivation layer 174 is exposed. In the planarization process, the seed layer 188 may be polished together with the conductive layer 189 . By the planarization process, the conductive layer 189 is formed by the first upper pad 182 filling the first hole H1 and the second hole H2 and the second upper pad 184 filling the third hole H3. ), and the seed film 188 surrounds the outer wall and lower surface of the first seed film 183 and the second upper pad 184 surrounding the outer wall and lower surface of the first upper pad 182 . may be formed as the second seed layer 185 .

The through electrode 130 may protrude by recessing the substrate 100 . For example, etching using an etchant or slurry capable of selectively removing a material (eg, silicon (Si)) constituting the substrate 100 , chemical mechanical polishing (CMP), grinding, or a method thereof In combination, the lower surface 100b of the substrate 100 may be recessed. The recess process may be performed until the through electrode 130 is exposed on the lower surface 100b of the substrate 100 . For example, a chemical mechanical polishing (CMP) process is performed on the lower surface 100b of the substrate 100 so that the through electrode 130 is not exposed on the lower surface 100b of the substrate 100 , and then the substrate The lower surface 100b of the substrate 100 may be dry etched so that the through electrode 130 is exposed on the lower surface 100b of (100).

A lower passivation layer 176 covering the lower surface 100b of the substrate 100 may be formed. For example, the lower passivation layer 176 may be formed by depositing an insulator such as a silicon oxide layer (SiO), a silicon nitride layer (SiN), or a polymer.

A planarization process may be performed on the lower passivation layer 176 . The through electrode 130 may be exposed by the planarization process. During the planarization process, the through electrode insulating layer 120 and the barrier layer 134 of the through electrode 130 may be etched together. Accordingly, the conductive portion 132 and the barrier layer 134 of the through electrode 130 may be exposed on the lower surface of the lower passivation layer 176 .

Referring back to FIG. 1 , a lower pad 186 electrically connected to the through electrode 130 may be formed on the lower passivation layer 176 . For example, the lower pad 186 may be formed of copper (Cu). Unlike that shown in FIG. 1 , the lower pad 186 may have a solder ball shape.

As described above, the semiconductor device described with reference to FIGS. 1 to 3 may be manufactured.

In the above, embodiments of the present invention have been described with reference to the accompanying drawings, but those of ordinary skill in the art to which the present invention pertains can practice the present invention in other specific forms without changing its technical spirit or essential features. You will understand that there is Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

100: substrate 104: contact
110: interlayer insulating film 120: through electrode insulating film
130: through electrodes 142, 144, 146, 148: capping film
152, 154, 156: intermetallic insulating film 162, 164, 166: wiring pattern
172, 174: upper passivation layer 182, 184: upper pad
192: upper terminal

Claims (10)

an integrated circuit formed on a substrate;
an interlayer insulating film on the substrate;
a contact connected to the integrated circuit through the interlayer insulating layer;
a wiring layer disposed on the interlayer insulating layer and having a wiring connected to the contact;
a first passivation layer disposed on the wiring layer;
a first pad and a second pad disposed on the first passivation layer; and
a penetrating electrode connected to the first pad through the substrate, the interlayer insulating film, the wiring layer, and the first protective film;
The first pad comprises:
a first head portion positioned on the first passivation layer; and
a protrusion extending into the first passivation layer from the first head part and enclosing a side surface of the through electrode in the first passivation layer;
The second pad is a semiconductor device connected to the integrated circuit through the wiring and the contact.
The method of claim 1,
The second pad comprises:
a second head portion positioned on the first passivation layer; and
It has a via part extending from the second head part and penetrating the first protective film,
A lower surface of the via portion is positioned at a level lower than a lower surface of the protrusion from the substrate. 3. The method of claim 2,
The width of the through electrode is 20 to 100 times the width of the via portion. The method of claim 1,
The upper surface of the through electrode is positioned at the same level as the upper surface of the first passivation layer from the substrate. The method of claim 1,
The protrusion has a closed curve shape surrounding the through electrode in a plan view,
The protrusion is a semiconductor device in contact with a side surface of the through electrode.

a substrate having an integrated circuit and contacts electrically coupled to the integrated circuit;
an interlayer insulating layer covering the integrated circuit and the contact on the substrate;
a protective film on the interlayer insulating film;
a first pad and a second pad spaced apart from each other in the passivation layer;
a wiring pattern connecting the contact and the second pad between the interlayer insulating layer and the passivation layer;
a through electrode disposed to be spaced apart from the contact and the wiring pattern and connected to the first pad through the substrate and the interlayer insulating layer; and
a third pad connected to the through electrode on the lower surface of the substrate;
A portion of the first pad covers a side surface of the through electrode,
The uppermost end of the wiring pattern is positioned at a level lower than the uppermost end of the through electrode.
7. The method of claim 6,
The first pad comprises:
a first head part buried in an upper portion of the passivation layer; and
and a protrusion extending from the first head part toward a lower surface of the passivation layer and surrounding a side surface of the through electrode;
The second pad comprises:
a second head part embedded in an upper portion of the passivation layer; and
A semiconductor device having a via portion extending from the second head portion toward a lower surface of the passivation layer and penetrating the passivation layer. 8. The method of claim 7,
The lower surface of the via part is located at a level lower than the lower surface of the protrusion part from the substrate,
The lower surface of the protrusion is positioned at the same level as the lower surface of the second head portion from the substrate. 7. The method of claim 6,
The protective film is:
capping film;
a first upper passivation layer on the capping layer; and
a second upper passivation layer on the first upper passivation layer;
A height of an upper surface of the through electrode from the substrate is substantially equal to a height of an upper surface of the first upper passivation layer.

forming an interlayer insulating film covering an integrated circuit and a substrate provided with a contact electrically connected to the integrated circuit;
forming wiring layers stacked on the interlayer insulating film;
forming a lower passivation layer on the wiring layers;
forming a through electrode penetrating a portion of the substrate, the interlayer insulating layer, the wiring layers, and a lower protective layer;
forming an upper passivation layer on the lower passivation layer and the through electrode;
performing an etching process on the upper passivation layer to form a first opening exposing the through electrode and a second opening exposing a wiring pattern of the wiring layers; and
and filling the first opening and the second opening with a conductive material to form a first pad connected to the through electrode and a second pad connected to the wiring pattern of the wiring layers.

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