KR20220139278A - MINIATURIZED GaAs-BASED BANDPASS FILTER AND RADIO FREQUENCY DEVICE EQUIPMENT - Google Patents

Abstract

The present invention relates to an integrated circuit including a quad flat no-lead (QFN) package miniaturized GaAs-based bandpass filter, a manufacturing method thereof, and a radio frequency (RF) device including the QFN package miniaturized GaAs-based bandpass filter. One embodiment of the present invention provides a manufacturing method of a bandpass filter (BPF), which comprises: a washing step of washing a substrate consisting of a compound including at least one of materials from Group III to Group V with a washing solution including alcohol; a first passivation layer generation step of generating a passivation layer; and a step of applying at least one of a photoresistor coating (PR coating) step, an exposure step, and an etching step.

Description

RF device comprising a small GaAs-based bandpass filter

The present invention relates to an RF device comprising a small GaAs-based bandpass filter. Specifically, the present invention relates to an integrated circuit including a QFN package small GaAs-based bandpass filter and a method for manufacturing the same, and to an RF device including a QFN package small GaAs-based bandpass filter.

In a situation in which wireless communication systems and/or communication fields are increasingly developed, radio frequency (RF) and/or microwaves such as balancers, mixers, and power splitters Related passive devices have played various important roles. Also, among various types of microwave filters, as an important block of RF and/or microwave integrated circuits and systems, a band-pass filter (BPF) has been extensively studied. In addition, various and stringent requirements such as low cost, small size, and high performance have been required for the BPF in relation to a wireless communication system and/or communication field.

Meanwhile, Korean Patent Laid-Open No. 10-2010-0067003 relates to a semiconductor device having a balanced band-pass filter implemented as an LC resonator.

The document describes a band-pass filter comprising a plurality of LC resonators each comprising first and second balanced ports and first and second unbalanced ports, wherein the LC resonators are connected to the first balanced port. a first inductor comprising a first end terminal and a second end terminal connected to the second balance port; a first capacitor connected between a first end terminal and a second end terminal of the first inductor; a second inductor having a first portion of a second inductor parallel to a first portion adjacent the second inductor of the first inductor, wherein a first end terminal of the second inductor is connected to the first unbalanced port, and a second end terminal of a second inductor is connected to the second unbalanced port; a second capacitor connected between a first end terminal and a second end terminal of the second inductor; a first portion of a third inductor parallel to a second portion adjacent to the third inductor of the first inductor, a second portion of the third inductor parallel to a second portion adjacent to the third inductor of the second inductor, and a first end a third inductor including a terminal and a second end terminal; and a third capacitor connected between a first end terminal and a second end terminal of the third inductor, wherein the third inductor is disposed adjacent to the first and second inductors to provide first, second and second inductors. Disclosed is a band-pass filter characterized in that it induces electronic coupling between three inductors.

Accordingly, the present invention intends to propose an integrated circuit including an enhanced QFN package small GaAs-based bandpass filter and a method for manufacturing the same, and an RF device including a QFN package small GaAs-based bandpass filter.

Laid-Open Patent Publication No. 10-2010-0067003

It is an object of the present invention to provide an integrated circuit including a QFN package small GaAs-based bandpass filter, a manufacturing method thereof, and an RF device including a QFN package small GaAs-based bandpass filter.

The technical problems to be achieved in the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those of ordinary skill in the art to which the present invention belongs from the description below. will be able

In one embodiment of the present invention, a substrate made of a compound containing at least one of a group III material to a group V material: a cleaning step of cleaning with a cleaning solution containing an alcohol material; creating a first passivation layer to create a passivation layer; And PR coating (photoresistor coating) step; exposure step; and an etching step; By applying at least one of the above, a manufacturing method of manufacturing a bandpass filter (BPF) is proposed.

The cleaning solution may be characterized in that the alcohol material includes an acetone solution, and the compound includes gallium arsenide (GaAs).

The first passivation layer generating step may be characterized in that the SiNx passivation layer having a thickness of 150 nm to 250 nm is generated.

The manufacturing method may include depositing a seed metal layer on the substrate; The seed metal layer may include titanium (Ti) having a thickness of 15 nm to 25 nm and gold (Au) having a thickness of 70 nm to 90 nm.

The manufacturing method includes a first PR coating step of generating a first positive photoresistor (PR) based on spin coating; and a first mask exposure step of exposing using a first mask; may further include.

The manufacturing method may include: a first metal plating step of forming a first metal layer using an electroplating technique; It further includes, wherein the first metal layer may be composed of copper (Cu) having a thickness of 4 μm to 5 μm and gold (Au) having a thickness of 0.4 μm to 0.6 μm.

The manufacturing method includes: a first strip-off step of stripping off the positive PR using an acetone solution; may further include.

The manufacturing method includes a second PR coating step of generating a second positive PR; a second exposure step of exposing using a second mask; a seed metal etching step of etching a portion of the seed metal layer using inductively coupled plasma (ICP); and a second strip-off step of stripping off the second positive PR using an acetone solution. may further include.

The manufacturing method, a third PR coating step of generating a third positive PR; a third exposure step of exposing using a third mask; and a second metal plating step of forming a second metal layer using an electroplating technique; may further include.

The manufacturing method, a fourth PR coating step of generating a negative PR (negative photoresistor); a fourth exposure step of exposing using a fourth mask; a third metal plating step of forming a third metal layer using an electroplating technique; and a third strip-off step of stripping off the negative PR using an acetone solution; may further include.

The manufacturing method includes a second passivation layer generation step of depositing a SiNx passivation layer having a thickness of 250 nm to 350 nm using a plasma-enhanced chemical vapor deposition (PECVD) technique; a fifth PR coating step to produce a fourth positive PR; and a fifth exposure step of exposing using a fifth mask; may further include.

The manufacturing method includes a passivation layer etching step using an SF6 and O2 based ICP (Inductively Coupled Plasma) dry etching technique; a fourth strip-off step of stripping off the fourth positive PR; and a wire bonding step of performing at least one of polishing, dicing, and wire-bonding processes; may further include.

An embodiment of the present invention provides an integrated circuit including a bandpass filter (BPF), comprising: a substrate made of a compound including at least one of a group III material to a group V material; for the substrate: cleaned with a cleaning solution comprising an alcohol material, a passivation layer is formed, during a photoresistor coating (PR) process, an exposure process, and an etching process By applying at least one, an integrated circuit is proposed, characterized in that the bandpass filter is manufactured.

The cleaning solution may be characterized in that the alcohol material includes an acetone solution, and the compound includes gallium arsenide (GaAs).

The integrated circuit may include a SiNx passivation layer having a thickness of 150 nm to 250 nm; and a seed metal layer comprising titanium (Ti) having a thickness of 15 nm to 25 nm and gold (Au) having a thickness of 70 nm to 90 nm; may further include.

The integrated circuit may include: a first metal layer made of copper (Cu) having a thickness of 4 μm to 5 μm and gold (Au) having a thickness of 0.4 μm to 0.6 μm; may further include.

One embodiment of the present invention is a communication module including a radio frequency (RF) integrated circuit; and a control module for controlling the communication module; wherein the RF integrated circuit comprises a bandpass filter (BPF), for the substrate: washed with a cleaning solution comprising an alcohol substance, a passivation layer is created, and a PR coating ( The RF integrated circuit may be manufactured by applying at least one of a photoresistor coating process, an exposure process, and an etching process.

The cleaning solution may be characterized in that the alcohol material includes an acetone solution, and the compound includes gallium arsenide (GaAs).

The RF integrated circuit may include a SiNx passivation layer having a thickness of 150 nm to 250 nm; and a seed metal layer comprising titanium (Ti) having a thickness of 15 nm to 25 nm and gold (Au) having a thickness of 70 nm to 90 nm; may further include.

The RF integrated circuit may include: a first metal layer made of copper (Cu) having a thickness of 4 μm to 5 μm and gold (Au) having a thickness of 0.4 μm to 0.6 μm; may further include.

An embodiment of the present invention can provide an improved (enhanced) QFN package integrated circuit including a small GaAs-based bandpass filter and a method for manufacturing the same, and an RF device including a QFN package small GaAs-based bandpass filter. have.

The bandpass filter according to an embodiment of the present invention provides technical advantages in that it is characterized by a relatively small chip size, a wide fractional bandwidth, and excellent insertion and return losses.

The effects obtainable in the present invention are not limited to the above-mentioned effects, and other effects not mentioned may be clearly understood by those of ordinary skill in the art from the following description. will be.

Other aspects, features and benefits as described above of certain preferred embodiments of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings.
1 is a diagram illustrating a circuit implementing a bandpass filter according to an embodiment of the present invention.
2A and 2B are diagrams illustrating a bandpass filter according to an embodiment of the present invention.
3 is a diagram illustrating a π-type circuit model according to an embodiment of the present invention.
4 is a diagram illustrating an equivalent circuit model of a bandpass filter according to an embodiment of the present invention.
5 is a diagram illustrating a frequency-dependent simulation result of the capacitance of a central capacitor optimized according to an embodiment of the present invention.
6 is a diagram illustrating a frequency-dependent simulation result of an inductance of a central capacitor optimized according to an embodiment of the present invention.
7 is a diagram illustrating a frequency-dependent simulation result of a resistance of a central capacitor optimized according to an embodiment of the present invention.
8 to 10 are views illustrating a manufacturing process of a bandpass filter according to an embodiment of the present invention.
11 to 14 are flowcharts illustrating a manufacturing method according to an embodiment of the present invention.
15 is a diagram illustrating a measurement setup according to an embodiment of the present invention.
16 is a diagram illustrating simulation and measurement results of an IPD-based bandpass filter according to an embodiment of the present invention.
17 is a block diagram illustrating an RF device including a bandpass filter according to an embodiment of the present invention.
It should be noted that throughout the drawings, like reference numerals are used to denote the same or similar elements, features, and structures.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In describing the embodiments, descriptions of technical contents that are well known in the technical field to which the present invention pertains and are not directly related to the present invention will be omitted. This is to more clearly convey the gist of the present invention by omitting unnecessary description.

For the same reason, some components are exaggerated, omitted, or schematically illustrated in the accompanying drawings. In addition, the size of each component does not fully reflect the actual size. In each figure, the same or corresponding elements are assigned the same reference numerals.

Advantages and features of the present invention, and a method of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the art to which the present invention pertains. It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout.

At this time, it will be understood that each block of the flowchart diagrams and combinations of the flowchart diagrams may be performed by computer program instructions. These computer program instructions may be embodied in a processor of a general purpose computer, special purpose computer, or other programmable data processing equipment, such that the instructions performed by the processor of the computer or other programmable data processing equipment are not described in the flowchart block(s). It creates a means to perform functions. These computer program instructions may also be stored in a computer-usable or computer-readable memory that may direct a computer or other programmable data processing equipment to implement a function in a particular manner, and thus the computer-usable or computer-readable memory. It is also possible for the instructions stored in the flowchart block(s) to produce an article of manufacture containing instruction means for performing the function described in the flowchart block(s). The computer program instructions may also be mounted on a computer or other programmable data processing equipment, such that a series of operational steps are performed on the computer or other programmable data processing equipment to create a computer-executed process to create a computer or other programmable data processing equipment. It is also possible that instructions for performing the processing equipment provide steps for performing the functions described in the flowchart block(s).

Additionally, each block may represent a module, segment, or portion of code that includes one or more executable instructions for executing specified logical function(s). It should also be noted that in some alternative implementations it is also possible for the functions recited in the blocks to occur out of order. For example, it is possible that two blocks shown in succession are actually performed substantially simultaneously, or that the blocks are sometimes performed in the reverse order according to the corresponding function.

In this case, the term '~ unit' used in this embodiment means software or hardware components such as field-programmable gate array (FPGA) or ASIC (Application Specific Integrated Circuit), and '~ unit' refers to what role carry out the However, '-part' is not limited to software or hardware. '~unit' may be configured to reside on an addressable storage medium or may be configured to refresh one or more processors. Thus, as an example, '~' denotes components such as software components, object-oriented software components, class components, and task components, and processes, functions, properties, and procedures. , subroutines, segments of program code, drivers, firmware, microcode, circuitry, data, databases, data structures, tables, arrays, and variables. The functions provided in the components and '~ units' may be combined into a smaller number of components and '~ units' or further separated into additional components and '~ units'. In addition, components and '~ units' may be implemented to play one or more CPUs in a device or secure multimedia card.

In describing embodiments of the present invention in detail, an example of a specific system will be mainly targeted, but the main subject matter to be claimed in this specification is to extend the scope disclosed herein to other communication systems and services having a similar technical background. It can be applied within a range that does not deviate significantly, and this will be possible at the discretion of a person with technical knowledge skilled in the art.

Low-temperature co-fired ceramics (LTCC), monolithic microwave integrated circuits (MMICs), and high-temperature superconductors (HTSs) facilitating the development of BPF designs and implementations , micro-electromechanical systems (MEMS), and research related to micro-manufacturing techniques exist.

The LTCC consists of a mix of various passive components such as strip lines, filters, antennas, and resonators. LTCC has several advantages in terms of BPF manufacturing and/or processing processes, in terms of a low cost process, and in terms of the high electrical conductivity of the working metal and low conductor losses. However, the LTCC has a disadvantage that the size of the ceramic and the processed plate may be reduced after firing. In addition, a heat sink after heating is required for a module that requires heat dissipation.

Integrated circuits such as MMICs, based on III-V materials such as gallium arsenide (GaAs), have higher functional capability, improved system stability, weight/size/price, etc. It can be applied to devices operating in this reduced millimeter-wave band.

Here, gallium arsenide (GaAs) may mean a multi-element compound containing gallium (Ga) and arsenic (As). Gallium arsenide has 6 times faster electron movement speed than single elements such as germanium (Ge) or silicon (Si), so the operation speed can be increased 6 times. Semi-insulating substrates can be easily made, various other compound semiconductors can be formed, and power consumption is low and suitable for integrated circuits (ICs). In particular, it can be widely applied in semiconductor fields such as application-specific semiconductors (ASICs) because devices with complex structures that can exhibit various properties can be manufactured.

A major disadvantage of MMIC-based devices is that they perform poorly compared to devices using discrete components. The micro strip BPF based on HTS has a very low surface resistance, which shows a significant advantage in terms of low insertion loss compared to the conventional micro strip BPF, which can be advantageous for a compact and miniaturized design. Here, the microstrip may be a microwave transmission line composed of a single strip conductor supported in parallel to the ground plane. However, the high cost and complexity of the low temperature operating environment may limit the wide application of HTS. MEMS is attractive for the manufacture of electronic equipment due to the advantages of batch production of small structures ranging in size from micrometer (μm) to millimeter (mm). A distinguishing feature of MEMS is that it can reduce cost, size and weight by seamlessly integrating mechanical components and electronics on a single wafer. Nevertheless, the reliability and dynamic range of the power handling capability can greatly shorten the lifespan of MEMS-based devices.

IPD (Integrated Passive Device) is a developed technology that has been widely used over the past few decades, providing a balance between system packaging and module solutions, allowing integration of other functions to improve overall system performance. IPD provides advantages and/or advantages over standard discrete systems, such as simplified models, reduced size and improved performance due to reduced parasitic effects. Here, the parasitic effect may mean an undesirable function and influence of a passive or active element that occurs in a part of a circuit as a result of manufacturing an integrated circuit (IC), regardless of an original design intention. In addition, the Q-factor used to evaluate device performance is low in the case of a lumped device, but can be improved by the IPD technique related to the present invention.

Since GaAs substrates have excellent characteristics of high peak power and high repetition frequency of near-infrared rays, they can be seen as important semiconductor materials, and are used in various applications such as medical, information storage, communication, military, laser and/or sensing. can be

In one embodiment of the present invention, a quad flat no-lead (QFN) package BPF comprising an external entangled metal track, a central dendritic capacitor and four air bridge structures using IPD processing technology on a GaAs substrate is proposed.

The QFN packaging technology according to an embodiment of the present invention can be used to protect the device from moisture and ensure excellent thermal and electrical performance. In addition, the package device according to an embodiment of the present invention may be mounted on a printed circuit board (PCB) through gold wire-bonding for final measurement and evaluation.

1 is a diagram illustrating a circuit implementing a bandpass filter according to an embodiment of the present invention.

1 may relate to design and circuit analysis according to an embodiment of the present invention.

Reference numeral 110 of FIG. 1 denotes a 3D image (3D view) according to an example of a QFN package bandpass filter (BPF) mounted on a printed circuit board (PCB) board.

Reference numeral 120 in FIG. 1 denotes an enlarged view of a bandpass filter (BPF) according to an embodiment of the present invention, and reference numeral 130 denotes a side view of the bandpass filter (BPF) according to an embodiment of the present invention.

Referring to FIG. 1 , a dendritic capacitor is positioned at the center of an octagonal external spiral inductor, for example, and is composed of three multilayer conductor layers. Each of the metal layers 140 , 150 , and 160 may be formed of, for example, an alloy (metal alloy) in which a composition ratio of copper (Cu) and gold (Au) is 9 to 1.

The metal layer may include at least one of a lead layer 140 , a text layer 150 , and a bonding layer 160 . On the other hand, the lead layer 140, the text layer 150, and the bonding layer 160 are i) red-accumulated/deposited in the order as shown in FIG. 1 or ii) stacked/deposited in another order. deposited or iii) only some layers of which are deposited/deposited.

Also, the bonding layer 160 may be referred to as a first metal layer, for example, and may be generated or deposited/deposited by Step 6 of FIG. 8 .

Also, the text layer 150 may be referred to as, for example, a second metal layer, and may be generated or deposited/deposited by Step 15 of FIG. 9 .

In addition, the lead layer 140 may be referred to as, for example, a third metal layer, and may be generated or deposited/deposited by Step 18 of FIG. 10 .

Also, the resonance frequency f ₀ of the LC circuit may be calculated based on Equation 1 below.

[Equation 1]

Here, L and C may be the total inductance and capacitance of the entire device, respectively. After considering the parasitic effect under high-frequency excitation, a lumped model according to an embodiment of the present invention is a non-overlapping part of a metal line, a coupling capacitor between metals, a SiN _x passivation layer ( passivation layer) and a parasitic effect induced by the GaAs substrate, and/or a central capacitor.

In order to more accurately evaluate the equivalent circuit, one embodiment of the present invention is that an analytical model for performance evaluation of a bandpass filter (BPF) may be based on a segmentation method, a mutual inductance method, and a simulated S-parameter (scattering parameter). have. Here, the S-parameter is a circuit result value widely used in RF and may mean a ratio of an input voltage to an output voltage on the frequency axis.

Segment Box Internal Model

2A and 2B are diagrams illustrating a bandpass filter according to an embodiment of the present invention.

Referring to FIG. 2A , a bandpass filter (BPF) 200 according to an embodiment of the present invention includes a first metal track 210 , a second metal track 220 , and/or a central metal element 230 . can do. Also, the bandpass filter 200 may include a first air bridge 240 , a second air bridge 250 , a third air bridge 260 , and/or a fourth air bridge 270 .

For example, the thickness, height, and/or component of the first metal track 210 and the second metal track 220 may be the same or different.

2B shows the number of segment boxes of a bandpass filter according to an embodiment of the present invention.

Referring to FIG. 2B , a metal track (eg, an entangled spiral metal track) according to an embodiment of the present invention is to be divided into 10 segments (see (1) to (10) in FIG. 2B ) by four air bridges. can

3 is a diagram illustrating a π-type circuit model according to an embodiment of the present invention.

For example, FIG. 3 may represent an example of an equivalent circuit model of the metal track shown in FIG. 2 .

* Each segment (Seg i) of FIG. 3 may be analyzed using a ð-type lumped model. Also in FIG. 3 , R _T represents the series resistance of the segment, Lt represents the series inductance of the segment, C _SiNx represents the capacitance connected to SiN _x , C _SUB represents the capacitance related to GaAs, and G _SUB represents GaAs represents the conductance associated with

4 is a diagram illustrating an equivalent circuit model of a bandpass filter according to an embodiment of the present invention.

Meanwhile, the series inductance and series resistance can be determined by the structure of the metal track and the low frequency resistance. Since the current in a spiral inductor has a superposition effect under high-frequency excitation, the current distribution in the track may be uneven. Therefore, the inductance and resistance of each segment can be related to an instantaneous frequency.

To this end, W _eff representing a frequency-dependent effective linewidth is used to model an equivalent circuit and may be calculated based on Equations 2 and 3 below.

[Equation 2]

[Equation 3]

where w represents the physical metal line width, i represents the number of turns of the coil, and c ₁ and c ₂ may represent resistance and inductance, respectively, and parameters matching the measurement results. The resistance of each metal line (R-line) for the evaluation of signal loss may be calculated based on Equation 4 below.

[Equation 4]

Here, ρ represents the resistivity (Ω·cm) of the metal, and l and t _m may represent the length and thickness of the metal line, respectively. The inductance of each segment may include a self-inductance of the metal line and a mutual inductance with another metal segment. According to W _eff , frequency-dependent self-inductance may be calculated based on Equation 5 below.

[Equation 5]

Since the metal tracks of each segment are almost parallel to each other, the mutual inductance can be expressed as Equation 6 below.

[Equation 6]

Here, d may represent the distance between the wire center positions. It should be emphasized that the mutual inductance is positive if the two metal tracks have the same current direction and the metal tracks with opposite current carrying directions have negative mutual inductance. Accordingly, the total inductance associated with the length l and the desired metal track length can be calculated through Equations 4 and 5 described above.

Segment Box External Model

Because of the compact structure of the outer spiral inductor, the capacitance effect needs to be considered. C _{i_j} represents the coupling capacitance between adjacent metal tracks, and i and j represent the number of segments indicated in FIG. 2 . Here, the coupling capacitance may be calculated by Equation 7 below.

[Equation 7]

Here, ε ₀ represents the vacuum permittivity, and Q and V represent the normalized charge and the potential between the center positions of the two ends, respectively. In addition, the capacitive effect of the four air bridge structures cannot be ignored due to the air gap between the lead layer and the bonding layer, which is expressed as C _ABi and can be calculated based on Equation 8 below.

[Equation 8]

Based on the length calculated in the above-described " segment box internal model ", two types of capacitors may be determined together with Equations 7 and 8 above.

Embedded Capacitor

An embodiment of the present invention considers an inductive effect and an ohmic loss, and a central buried dendritic capacitor including three components: a capacitor C _C , a resistor R _C , and an inductor L _C . A model of (center dendritic embedded capacitor) is proposed.

However, the complex structure of the central capacitor causes difficulties in calculating the above parameters. Therefore, by introducing the simulated S-parameter and Y-parameter, capacitance, inductance, and resistance may be calculated based on Equations 9 to 11 below.

[Equation 9]

[Equation 10]

[Equation 11]

In addition, the capacitance of the central capacitor can be adjusted or reset according to design goals by optimizing its size.

5 to 7 each show an example of a frequency-dependent simulation result of an optimized central capacitor's capacitance, inductance, and resistance.

Parasitic Effects Associated with the Substrate

Accurately achieving design goals requires considering the effect of the parasitic effects of the substrate and passivation layer on capacitance and inductance.

Accordingly, an embodiment of the present invention provides a capacitance associated with the passivation layer (C _SiNx and C _{SiNx_AB} ), a conductor associated with a substrate (C _SUB and C _{SUB_AB} ), and a capacitor associated with the substrate (C _SUB and C _{SUB_AB} ) consider Since the resistance of the GaAs substrate is greater than 10 Ω·cm, the loss due to the eddy current is negligible.

C _SiNx may be calculated based on Equation 12 below.

[Equation 12]

C _{SUB_AB} may be calculated based on Equation 13 below.

[Equation 13]

C _{SUB_AB} may be calculated based on Equation 14 below.

[Equation 14]

C _SiNx may be calculated based on Equation 15 below.

[Equation 15]

C _SUB may be calculated based on Equation 16 below.

[Equation 16]

C _SUB may be calculated based on Equation 17 below.

[Equation 17]

Here, the parameter with the subscript SUB_AB indicates a parameter related to the air-bridge area, and can be considered frequency-independent because of its short length.

Also, in Equations 14 to 16, t _SiNx and t _GaAs represent the thicknesses of the passivation layer and the substrate, respectively, and ε ₀ , ε _SiNx and ε _GaAs represent the free space, the permittivity of the passivation layer and the substrate, respectively.

Therefore, an embodiment of the present invention introduces a new function F(W _eff ,t) for ε _eff (f), which is effective linewidth, metal thickness and frequency-dependent permittivity. Thus, we propose a method for calculating C _SiNx , C _SUB and G _SUB .

Manufacturing Process

8 to 10 are views illustrating a manufacturing process of a band pass filter (BPF) according to an embodiment of the present invention.

*IPDs (GaAs-based) according to one embodiment of the present invention are fabricated using standard wafer fabrication techniques using thin-film and photolithography processes, and individual passive electronic devices can be integrated or designed on the chip.

The band pass filter (BPF) according to an embodiment of the present invention may be developed through 25 steps and 5 masks, and the manufacturing process and/or manufacturing process are shown in FIGS. 10 can be explained.

Referring to FIG. 8 , in the manufacturing process of the band-pass filter according to an embodiment of the present invention, a 6-inch-long GaAs wafer is washed with a cleaning solution using a lift-off machine to have a flat surface. It includes the step of manufacturing (Step 1: wafer cleaning).

The cleaning solution is an acetone solution, and/or an alcoholic substance (eg, methanol, ethanol, isopropanol, normalbutanol, isobutanol, etc.), and/or an alkaline detergent composition, and/or an aqueous hydroxide solution (eg, an aqueous hydroxide solution of quaternary ammonium, etc.). ), and/or a water-based cleaning solution may be further included. Here, the alkaline detergent composition may include an aqueous metal ion-free base, a nonionic surfactant, and a component in an amount sufficient to reduce or adjust the pH of the detergent solution to 8 to 10.

Then, the manufacturing process includes forming a SiN _x passivation layer (ie, creating a passivation layer) of 150 nm to 250 nm thick (preferably 200 nm thick) (Step 2: SiN _x Passivation).

In Step 2, a plasma-enhanced chemical vapor deposition (PECVD) technique that improves adhesion between the metal layer and the GaAs wafer may be applied.

Then, in the manufacturing process, a seed metal layer of titanium (Ti)/gold (Au) having a thickness of 20/80 nm is deposited (on the top of the substrate) by thin film deposition (sputtering). step (ie, depositing a seed metal layer) (Step 3: seed metal deposition).

For example, a first seed metal layer made of gold (Au) is deposited to a thickness of 70 nm to 90 nm (preferably 80 nm), and then, a second seed metal layer made of titanium (Ti) is deposited on the first seed metal layer. It can be deposited to a thickness of 15 nm to 25 nm (preferably 20 nm).

Then, the manufacturing process includes a step in which a positive photoresistor (photoresist) is generated by spin coating and exposed/exposed using a first mask (mask 1) (Step 4: PR coating & exposure (Step 4: PR coating & exposure) mask 1)/Step 5: 1 ^st exposure result).

The manufacturing process then includes forming a first metal layer using an electroplating technique (ie, a first metal plating step) (Step 6: 1 ^st metal plating).

The first metal layer may be made of copper (Cu) having a thickness of 4 μm to 5 μm and gold (Au) having a thickness of 0.4 μm to 0.6 μm. For example, copper (Cu) having a thickness of 4 μm to 5 μm may be deposited on top of gold (Au) having a thickness of 0.4 μm to 0.6 μm.

For example, the first metal layer may be composed of copper (Cu)/gold (Au) having a thickness of 4.5/0.5 μm.

Immediately thereafter, the manufacturing process includes a step (ie, the first strip off step) of stripping off the PR (eg, the positive PR) using an acetone solution (Step 7: strip off PR) .

Then, referring to FIG. 9 , the manufacturing process includes a step of re-coating a positive PR and exposing/exposing it with a second mask (mask 2) (Step 8: PR coating & exposure (mask 2)/Step) 9: 2 ^nd exposure result), which is used to protect the first metal layer from the next etching process.

The fabrication process then includes a step (ie, seed metal etching step) in which the obsolete portion of the seed metal layer is etched by SF ₆ /Ar plasma using Inductively Coupled Plasma (ICP). 10: etch seed metal/Step 11: 1 ^st etch result/Step 12: strip off PR).

Then, the manufacturing process includes the positive PR being re-coated and exposed/exposed using a third mask to prepare for deposition of a second metal layer (Step 13: PR coating & exposure) (mask 3)/Step 14: ^3rd exposure result).

*Then, the manufacturing process includes a step in which a second metal layer based on copper (Cu)/gold (Au) with a thickness of 1.8 μm is created using electroplating technology (Step 15: 2 ^nd metal plating).

Then, the manufacturing process includes a step of creating or defining a pattern of a third metal layer by coating a negative PR rather than a positive PR and exposing/exposing it with a fourth mask (Step 16: PR) coating & exposure (mask 4)).

Then, referring to FIG. 10 , the manufacturing process includes a step (ie, a third metal plating step) in which a third metal layer is electroplated using copper (Cu)/gold (Au) having a thickness of 4.5/0.5 μm. and (Step 17: 4 ^th exposure result/Step 18: 3 ^rd metal plating), which is the same as the first metal layer.

Then, the manufacturing process is an air-bridge structure is formed, the PR is removed using an acetone solution and wet etching technique, and at the same time, an intertwined coil and a central capacitor and a step in which another general three-metal layer structure (eg, a structure in which three metal layers are deposited/deposited) is created (ie, a third strip-off step) such as Step 19: strip off PR).

The fabrication process then includes a feature in which a 250 nm to 350 nm (especially 300 nm) thick SiN _x passivation layer is deposited via PECVD, thereby protecting the device from moisture and oxidation (i.e. , a second passivation layer generation step) (Step 20: SiN _x passivation plating).

Then, in order to connect the contacts for a more convenient performance test, the above fabrication process is carried out after the positive PR is coated to etch the passivation layer through an ICP dry etching process using SF ₆ /O ₂ (ie, the fifth PR coating step), and exposure/exposure with a fifth mask (mask 5) (ie, fifth exposure step) (Step 21: PR coating & exposure (mask 5)/Step 22: exposure result/Step 23: etch passivation).

Then, the manufacturing process may include stripping the positive PR (Step 24: strip off PR).

Finally, the manufacturing process is a step in which polishing, dicing and wire-bonding processes are used to mount a bandpass filter (BPF) device on a printed circuit board (PCB). Including (Step 25: wire bonding), it is possible to measure the RF performance of the manufactured device through this.

11 to 14 are flowcharts illustrating a manufacturing method according to an embodiment of the present invention.

As described above, the manufacturing method of the bandpass filter (BPF) of the present invention according to an embodiment of the present invention is performed on a substrate made of a compound including at least one of a group III material to a group V material. : a washing step of washing with a washing solution containing an alcohol substance; creating a first passivation layer to create a passivation layer; And PR coating (photoresistor coating) step; exposure step; and an etching step; By applying at least one of the following, it may be a manufacturing method of manufacturing a bandpass filter (BPF).

The cleaning solution may be characterized in that the alcohol material includes an acetone solution, and the compound includes gallium arsenide (GaAs).

The first passivation layer generating step may be characterized in that the SiNx passivation layer having a thickness of 150 nm to 250 nm is generated.

The manufacturing method may include depositing a seed metal layer on the substrate; The seed metal layer may include titanium (Ti) having a thickness of 15 nm to 25 nm and gold (Au) having a thickness of 70 nm to 90 nm.

The manufacturing method includes a first PR coating step of generating a first positive photoresistor (PR) based on spin coating; and a first mask exposure step of exposing using a first mask; may further include.

The manufacturing method may include: a first metal plating step of forming a first metal layer using an electroplating technique; It further includes, wherein the first metal layer may be composed of copper (Cu) having a thickness of 4 μm to 5 μm and gold (Au) having a thickness of 0.4 μm to 0.6 μm.

The manufacturing method includes: a first strip-off step of stripping off the positive PR using an acetone solution; may further include.

The manufacturing method includes a second PR coating step of generating a second positive PR; a second exposure step of exposing using a second mask; a seed metal etching step of etching a portion of the seed metal layer using inductively coupled plasma (ICP); and a second strip-off step of stripping off the second positive PR using an acetone solution. may further include.

The manufacturing method, a third PR coating step of generating a third positive PR; a third exposure step of exposing using a third mask; and a second metal plating step of forming a second metal layer using an electroplating technique; may further include.

The manufacturing method, a fourth PR coating step of generating a negative PR (negative photoresistor); a fourth exposure step of exposing using a fourth mask; a third metal plating step of forming a third metal layer using an electroplating technique; and a third strip-off step of stripping off the negative PR using an acetone solution; may further include.

The manufacturing method includes a second passivation layer generation step of depositing a SiNx passivation layer having a thickness of 250 nm to 350 nm using a plasma-enhanced chemical vapor deposition (PECVD) technique; a fifth PR coating step to produce a fourth positive PR; and a fifth exposure step of exposing using a fifth mask; may further include.

The manufacturing method includes a passivation layer etching step using an SF6 and O2 based ICP (Inductively Coupled Plasma) dry etching technique; a fourth strip-off step of stripping off the fourth positive PR; and a wire bonding step of performing at least one of polishing, dicing, and wire-bonding processes; may further include.

Table 1 below shows a list of manufacturing techniques used in IPD's (Integrated Passive Devices) process.

[Table 1]

15 is a diagram illustrating a measurement setup according to an embodiment of the present invention.

For example, FIG. 15 is an enlarged view of various components of an S-parameter measurement setting of an IPD-based bandpass filter (BPF) according to an embodiment of the present invention. Reference numeral 1510 denotes a measurement setting, reference numeral 1520 denotes a bandpass filter (BPF) installed in an aluminum cube, reference numeral 1530 denotes a plan view of the entire PCB, and reference numeral 1540 denotes a plan view of a package chip on the PCB; Reference numeral 1550 denotes a plan view of the SEM figure, and reference numerals 1560 and 1570 denote expanded air-bridge regions and cross sections of three metal layers.

The BPF according to an embodiment of the present invention may be fabricated on a GaAs substrate having a thickness of 200.1 μm, a dielectric constant of 12.85 and a loss tangent of 0.006, and may be packaged using QFN technology. QFN packaging technology can be used to protect the device from moisture and ensure good thermal and electrical performance. S-parameters are used to describe the electrical performance of a linear electrical network when subjected to various steady-state stimuli with electrical signals. Especially at high frequencies, it can be essential to describe a given network as waves instead of voltages or currents. Transmission and reflection parameters can be measured and/or recorded using an Agilent 8510C vector network analyzer (VNA).

16 is a diagram illustrating simulation and measurement results of an IPD-based bandpass filter (BPF) according to an embodiment of the present invention.

In the case of FIG. 16 , the measured center frequency is 2.21 GHz, the 3 dB pass band is 1.61 GHz to 3.20 GHz, and the fractional bandwidth may be 72.53%. Here, the ratio of the pass bandwidth (frequency band until the output is lowered by 6dB from the center frequency) B with respect to the center frequency f ₀ , that is, γ=B/f ₀ , can be referred to as a specific bandwidth. Also, the transmit frequency is located to the right of the passband, the measured frequency is 6.38 GHz and the magnitude may be 30.55 dB.

Table 2 below shows the performance difference between another bandpass filter (eg, Refs. 36 to 40 in Table 2) and a bandpass filter according to an embodiment of the present invention (Ref. This work in Table 2).

[Table 2]

As shown in Table 2, it is shown that the bandpass filter according to an embodiment of the present invention provides a technical effect in that it is characterized by a relatively small chip size, a wide fractional bandwidth, and excellent insertion and return losses.

In addition, an embodiment of the present invention proposes a micro-scale bandpass filter (BPF) composed of two twisted spiral inductors and a central embedded capacitor using GaAs-based IPD technology. The equivalent circuit model takes into account capacitive and inductive parasitic effects.

In addition, an embodiment of the present invention proposes a three-layer IPD manufacturing process by a thin film and photolithography process including 25 steps as shown in FIGS. 8 to 10 .

In addition, the band pass filter (BPF) manufactured according to an embodiment of the present invention is characterized by a miniaturized overall size of 0.8Х0.8 mm ² .

In addition, the performance and measurement results of the bandpass filter manufactured according to an embodiment of the present invention show excellent results such as a low insertion loss of 0.38 dB and an ultrawide 3-dB FBW of 72.53%.

17 is a block diagram illustrating an RF device including a bandpass filter according to an embodiment of the present invention.

The radio frequency (RF) device 1700 of FIG. 17 may include the bandpass filter described/manufactured with reference to FIGS. 1 to 16 of the present invention. For example, the communication module 1720 of the RF device 1700 may include the bandpass filter described/manufactured with reference to FIGS. 1 to 16 of the present invention. For example, the communication module 1720 may include an electronic component and/or an electronic device to which a bandpass filter is attached/included as shown in reference numerals 1520 to 1540 of FIG. 15 .

Also, the RF device 1700 may include a control module 1710 , a communication module 1720 , an input module 1730 , and/or an output module 1740 .

The control module 1710 may directly/indirectly control the RF device 1700 to implement an operation/step/step according to an embodiment of the present invention. Also, the control module 1710 may include at least one processor, and the processor may include at least one central processing unit (CPU) and/or at least one graphics processing device (GPU).

The communication module 1720 may transmit/receive various data, signals, and information to and from an external device and/or an external server. In addition, the communication module 1720 may include a wireless communication module (eg, a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module (eg, a local area network (LAN) communication module; or a power line communication module). In addition, the communication module 1720 may be configured for a first network (eg, a short-range communication network such as Bluetooth, WiFi direct, or infrared data association (IrDA)) or a second network (eg, a cellular network, the Internet, or a computer network (eg, LAN or It can communicate with an external electronic device through a telecommunication network such as WAN). These various types of communication modules may be integrated into one component (eg, a single chip) or may be implemented as a plurality of components (eg, multiple chips) separate from each other.

The input module 1730 transmits commands or data to be used in components of the RF device 1700 (eg, the control module 1710, etc.) to the outside of the RF device 1700 (eg, a user (eg, a first user, a second user). user, etc.), the administrator of the RF device 1700, etc.). In addition, the input module 1730 may include a touch recognition capable display installed in the RF device 1700 , a touch pad, a button type recognition module, a voice recognition sensor, a microphone, a mouse, or a keyboard. Here, the touch recognition capable display, the touch pad, and the button-type recognition module may recognize a touch through the user's body (eg, a finger) through a pressure-sensitive and/or capacitive method.

The output module 1740 is generated by the control module 1710 of the RF device 1700 or acquired through the communication module 1720 (eg, a voice signal), information, data, images, and/or various objects ( It is a module that displays objects), etc. For example, the output module 1740 may include a display, a screen, a displaying unit, a speaker, and/or a light emitting device (eg, an LED lamp).

In addition, the RF device 1700 may further include a storage module, and stores data such as a basic program, an application program, and setting information for the operation of the RF device 1700 . In addition, the storage module is a flash memory type (Flash Memory Type), a hard disk type (Hard Disk Type), a multimedia card micro type (Multimedia Card Micro Type), a card type memory (eg, SD or XD memory, etc.), Magnetic Memory, Magnetic Disk, Optical Disk, Random Access Memory (RAM), Static Random Access Memory (SRAM), Read-Only Memory, ROM, Programmable Read-Only Memory (PROM), Electrically Erasable Programmable Read (EEPROM) -Only Memory) may include at least one storage medium.

Also, the storage module may include personal information of a user who uses the RF device 1700 . Here, the personal information may include a name, an identifier (ID), a password, a resident registration number, a street address, a phone number, a mobile phone number, and/or an email address. In addition, the control module 1710 may perform various operations using various programs, contents, data, etc. stored in the storage module.

Embodiments of the present invention disclosed in the present specification and drawings are merely provided for specific examples in order to easily explain the technical contents of the present invention and help the understanding of the present invention, and are not intended to limit the scope of the present invention. That is, it will be apparent to those of ordinary skill in the art to which the present invention pertains that other modifications can be implemented based on the technical spirit of the present invention. In addition, each of the above embodiments may be operated in combination with each other as needed. For example, all embodiments of the present invention may be implemented by the RF device 1700 in parts in combination with each other.

In addition, the method for controlling the RF device 1700 according to the present invention may be implemented in the form of program instructions that can be executed through various computer means and recorded in a computer-readable medium.

As such, various embodiments of the present invention may be embodied as computer readable code on a computer readable recording medium in a particular aspect. A computer readable recording medium is any data storage device capable of storing data that can be read by a computer system. Examples of computer readable recording media include read only memory (ROM), random access memory (RAM), and compact disk-read only memory (CD-ROM). ), magnetic tapes, floppy disks, optical data storage devices, and carrier waves (such as data transmission over the Internet). The computer readable recording medium may also be distributed over network-connected computer systems, so that the computer readable code is stored and executed in a distributed manner. In addition, functional programs, codes, and code segments for achieving various embodiments of the present invention may be easily interpreted by programmers skilled in the field to which the present invention is applied.

In addition, it will be appreciated that the apparatus and method according to various embodiments of the present invention can be realized in the form of hardware, software, or a combination of hardware and software. Such software may contain, for example, a volatile or non-volatile storage device such as a ROM, or a memory such as, for example, RAM, a memory chip, device or integrated circuit, whether erasable or rewritable, or For example, the storage medium may be stored in an optically or magnetically recordable storage medium such as a compact disk (CD), DVD, magnetic disk or magnetic tape, and at the same time, a machine (eg, computer) readable storage medium. The method according to various embodiments of the present invention may be implemented by a computer or a mobile terminal including a control unit (control module 1710) and a memory, such memory including instructions for implementing embodiments of the present invention It will be appreciated that this is an example of a machine-readable storage medium suitable for storing a program or programs.

Accordingly, the present invention includes a program including code for implementing the apparatus or method described in the claims of the present specification, and a machine (computer, etc.) readable storage medium storing such a program. Further, such a program may be transmitted electronically over any medium, such as a communication signal transmitted over a wired or wireless connection, and the present invention suitably includes the equivalent thereof.

The embodiments of the present invention disclosed in the present specification and drawings are merely provided for specific examples to easily explain the technical contents of the present invention and help the understanding of the present invention, and are not intended to limit the scope of the present invention. In addition, the embodiments according to the present invention described above are merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent ranges of embodiments are possible therefrom. Accordingly, the true technical protection scope of the present invention should be defined by the following claims.

Claims (1)

For a substrate made of a compound containing gallium arsenide (GaAs):
a washing step of washing with a washing solution containing an alcohol substance and an acetone solution;
creating a first passivation layer to create a SiN _x passivation layer having a thickness of 150 nm to 250 nm;
depositing a seed metal layer comprising titanium (Ti) having a thickness of 15 nm to 25 nm and gold (Au) having a thickness of 70 nm to 90 nm on the substrate;
a first PR coating step of generating a first positive photoresistor (PR) based on spin coating;
a first mask exposure step of exposing using a first mask;
a first metal plating step of forming a first metal layer comprising copper (Cu) having a thickness of 4 μm to 5 μm and gold (Au) having a thickness of 0.4 μm to 0.6 μm using an electroplating technique;
a first strip-off step of stripping off the positive PR using an acetone solution;
a second PR coating step to produce a second positive PR;
a second exposure step of exposing using a second mask;
a seed metal etching step of etching a portion of the seed metal layer using inductively coupled plasma (ICP);
a second strip-off step of stripping off the second positive PR using an acetone solution;
a third PR coating step to produce a third positive PR;
a third exposure step of exposing using a third mask;
a second metal plating step of forming a second metal layer using an electroplating technique;
a fourth PR coating step to create a negative photoresistor;
a fourth exposure step of exposing using a fourth mask;
a third metal plating step of forming a third metal layer using an electroplating technique;
a third strip-off step of stripping off the negative PR using an acetone solution;
A second passivation layer generation step of depositing a SiN _x passivation layer having a thickness of 250 nm to 350 nm using a PECVD (Plasma-Enhanced Chemical Vapor Deposition) technique;
a fifth PR coating step to produce a fourth positive PR;
a fifth exposure step of exposing using a fifth mask;
Passivation layer etching step using SF ₆ and O ₂ based ICP (Inductively Coupled Plasma) dry etching technique;
a fourth strip-off step of stripping off the fourth positive PR; and
By applying a wire bonding step of performing at least one of polishing, dicing and wire-bonding processes,
To manufacture a bandpass filter (BPF; bandpass filter) having an area of 0.64mm ² ,
manufacturing method.

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