KR20220136869A - Printed circuit board and electronic component package including the same - Google Patents

Abstract

The present disclosure is to provide a printed circuit board advantageous in reducing overall thickness and product miniaturization, and an electronic component package including the same. The printed circuit board according to the present disclosure includes: a first insulating layer; a first cavity which is formed on one surface of the first insulating layer; a plurality of protrusion parts which are disposed in the first cavity to be spaced apart from each other; and a first wiring layer which is embedded in one surface of the first insulating layer.

Description

Printed circuit board and electronic component package including the same {PRINTED CIRCUIT BOARD AND ELECTRONIC COMPONENT PACKAGE INCLUDING THE SAME}

The present disclosure relates to a printed circuit board and an electronic component package including the same.

Recently, the number of I/O (Input/Output) of the AP (Application Processor) and the memory is gradually increasing due to the high functionalization of electronic devices, and the miniaturization of the PKG (Package) is continuously required. APs are continuously being developed in the form of SOC (System On Chip), and recently, the size and thickness of electronic components are increasing as the function of NPU (Neural Processing Unit) and 5G modem is expanded. Therefore, in order to reduce the size and thickness of the PKG, a cavity or groove method for inserting electronic components such as AP in the board is required.

As electronic devices in the IT (Information Technology) field, including mobile phones, have become lighter, thinner and smaller, a technology for reducing the thickness of a package including electronic components such as AP and IC (Integrated Circuit) is required in response to the technological demands. Printed circuit boards of various structures connected to electronic components and technologies related to packages on which electronic components are mounted are being developed.

One of several objects of the present disclosure is to provide a printed circuit board advantageous for reducing the overall thickness and miniaturization of a product, and an electronic component package including the same.

A printed circuit board according to an example includes a first insulating layer; a first cavity formed on one surface of the first insulating layer; a plurality of protrusions spaced apart from each other in the first cavity; and a first wiring layer buried in one surface of the first insulating layer. may include.

Alternatively, an electronic component package according to an example includes: a first printed circuit board including an insulating layer, a first cavity formed on one surface of the insulating layer, and a plurality of protrusions spaced apart from each other in the first cavity; a second printed circuit board disposed on one side of the first printed circuit board and having the first printed circuit board mounted on one surface; and an electronic component mounted on one surface of the second printed circuit board. Including, one surface of the insulating layer of the first printed circuit board may be in contact with the electronic component.

As one of the various effects of the present disclosure, it is possible to provide a printed circuit board and an electronic component package including the same, which are advantageous in reducing the overall thickness and reducing the size of the product.

1 is a block diagram schematically showing an example of an electronic device system.
2 is a perspective view schematically illustrating an example of an electronic device.
3 is a cross-sectional view schematically illustrating an example of a printed circuit board.
4 is a plan view schematically illustrating one surface of the printed circuit board of FIG. 3 .
5 is a cross-sectional view schematically illustrating another example of a printed circuit board.
6 is a cross-sectional view schematically illustrating another example of a printed circuit board.
7 is a cross-sectional view schematically illustrating another example of a printed circuit board.
8 is a cross-sectional view schematically illustrating another example of a printed circuit board.
9 to 14 are cross-sectional views schematically illustrating an example of manufacturing the printed circuit board of FIG. 3 .
15 is a cross-sectional view schematically illustrating an example of an electronic component package.
16 is a cross-sectional view schematically illustrating another example of an electronic component package.
17 is a cross-sectional view schematically illustrating another example of an electronic component package.
18 is a cross-sectional view schematically illustrating another example of an electronic component package.
19 is a cross-sectional view schematically illustrating another example of an electronic component package.

Hereinafter, the present disclosure will be described with reference to the accompanying drawings. The shapes and sizes of elements in the drawings may be exaggerated or reduced for clearer description.

1 is a block diagram schematically showing an example of an electronic device system.

Referring to the drawings, the electronic device 1000 accommodates the main board 1010 . A chip-related component 1020 , a network-related component 1030 , and other components 1040 are physically and/or electrically connected to the main board 1010 . These are also combined with other electronic components to be described later to form various signal lines 1090 .

The chip-related component 1020 includes a memory chip such as a volatile memory (eg, DRAM), a non-volatile memory (eg, ROM), and a flash memory; application processor chips such as a central processor (eg, CPU), a graphics processor (eg, GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller; Logic chips such as analog-to-digital converters and application-specific ICs (ASICs) are included. However, the present invention is not limited thereto, and in addition to these chips, other types of chip-related components may be included. Also, these chip related parts may be combined with each other. The chip-related component 1020 may be in the form of a package including the above-described chip.

The network-related components 1030 include Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM. , GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G and any other wireless and wired protocols designated thereafter, including, but not limited to, many other wireless or wired protocols. Any of the standards or protocols may be included. Also, the network-related component 1030 may be combined with the chip-related component 1020 and provided in the form of a package.

Other components 1040 include a high-frequency inductor, a ferrite inductor, a power inductor, ferrite beads, low temperature co-firing ceramics (LTCC), an electro magnetic interference (EMI) filter, a multi-layer ceramic condenser (MLCC), and the like. . However, the present invention is not limited thereto, and in addition to this, a passive element in the form of a chip component used for various other purposes may be included. In addition, the other component 1040 may be provided in the form of a package in combination with the chip-related component 1020 and/or the network-related component 1030 .

Depending on the type of the electronic device 1000 , the electronic device 1000 may include other electronic components that may or may not be physically and/or electrically connected to the main board 1010 . Examples of other electronic components include a camera module 1050 , an antenna module 1060 , a display 1070 , and a battery 1080 . However, the present invention is not limited thereto, and an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (eg, a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), etc. may be In addition to this, it goes without saying that other electronic components used for various purposes may be included depending on the type of the electronic device 1000 .

The electronic device 1000 includes a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, and a computer ( computer), monitor, tablet, laptop, netbook, television, video game, smart watch, automotive, and the like. However, the present invention is not limited thereto, and may be any other electronic device that processes data in addition to these.

2 is a perspective view schematically illustrating an example of an electronic device.

Referring to the drawings, the electronic device may be, for example, a smartphone 1100 . A motherboard 1110 is accommodated inside the smartphone 1100 , and various electronic components 1120 are physically and/or electrically connected to the motherboard 1110 . In addition, a camera module 1130 and/or a speaker 1140 are accommodated therein. Some of the electronic components 1120 may be the aforementioned chip-related components, for example, the printed circuit board 1121, but is not limited thereto. The printed circuit board 1121 may have an electronic component embedded in the multilayer printed circuit board, but is not limited thereto. On the other hand, the electronic device is not necessarily limited to the smartphone 1100, and of course, it may be other electronic devices as described above.

3 is a cross-sectional view schematically illustrating an example of a printed circuit board.

Referring to the drawings, a printed circuit board 100A according to an example includes a first insulating layer 111 having a first cavity C1 formed therein, a plurality of protrusions P formed in the first cavity C1, and a first insulating layer. The first wiring layer 121 buried on one side of the 111 , the second wiring layer 122 disposed on the other surface of the first insulating layer 111 , and the second wiring layer 122 passing through at least a portion of the first insulating layer 111 The first via layer 131 electrically connecting the first and second wiring layers 121 and 122 , and a second insulation disposed on the other surface of the first insulating layer 111 to cover at least a portion of the second wiring layer 122 . The layer 112, the third wiring layer 123 disposed on the second insulating layer 112, penetrates at least a portion of the second insulating layer 112, and electrically connects the second and third wiring layers 122 and 123 and solder resist layers 141 and 142 disposed on one surface of the connecting second via layer 132 and the first insulating layer 111 and the other surface of the second insulating layer 112 .

For example, the printed circuit board 100A according to an example may be an interposer board that is later connected to an electronic component. In the case of the printed circuit board 100A according to an example, the first cavity C1 is formed on one surface of the first insulating layer 111, and a plurality of protrusions P are disposed in the first cavity C1. can In this case, when bonding the printed circuit board 100A and the electronic component later, the electronic component can be more easily arranged, and stable bonding is possible without damage to the electronic component.

On the other hand, the first cavity C1 and the plurality of protrusions P of the printed circuit board 100A according to an example facilitate bonding between the electronic component and the printed circuit board 100A as described above, and provide a stable bonding structure. An encapsulant may be filled in the first cavity C1 to maintain the suture material. In this case, the first cavity C1 and the plurality of protrusions P may be formed through plating and removal of the second region M2 of the metal layer M as in a manufacturing process to be described later, and a separate processing process There is no need, and since the first wiring layer 121 may be formed during the manufacturing process, the process can be simplified and cost can be reduced.

On the other hand, the first cavity C1 and the plurality of protrusions P of the printed circuit board 100A according to an example may be formed by plating and removing the second region M2 of the metal layer M as in a manufacturing process to be described later. can be formed. High roughness may be formed on the surface of the second region M2 through roughening, and the inner wall of the first cavity C1 formed by the removal of the second metal layer M2 may also have high roughness. have.

Meanwhile, the first wiring layer 121 of the printed circuit board 100A according to an example may be formed by plating the first region M1 of the metal layer M as in a manufacturing process to be described later. During the manufacturing process, a high roughness may be formed on the surface of the first region M1 through a roughening process, so that the first wiring layer 121 may have surfaces having different roughness. Specifically, the surface of the first wiring layer 121 in contact with the first insulating layer 111 may have a relatively low illuminance compared to the surface exposed from the first insulating layer 111 of the first wiring layer 121 .

Hereinafter, the components of the printed circuit board 100A according to an example will be described in more detail with reference to the drawings.

The insulating layer 110 may include first and second insulating layers 111 and 112 . The insulating layer 110 may further improve the rigidity of the printed circuit board 100A according to a specific material. A first cavity C1 may be formed on one surface of the insulating layer 110 , and a plurality of protrusions P may be formed in the first cavity C1 . The first cavity C1 may be a closed space in which all four sides are closed, but a discontinuous portion, for example, an externally open portion, may exist in some areas as needed. If necessary, a plurality of first cavities C1 may exist. The plurality of protrusions P formed in the first cavity C1 may be disposed to be spaced apart from each other. An encapsulant 400 to be described later may be filled in the inside of the first cavity C1 . That is, the encapsulant 400 may be disposed between the plurality of protrusions P inside the first cavity C1 .

An insulating material may be used as the material of the insulating layer 110 , and a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyimide may be used as the insulating material. In addition, those containing inorganic fillers such as silica and reinforcing materials such as glass fibers may be used in these resins. For example, a prepreg may be used, but is not limited thereto, and a material that does not include a reinforcing material such as glass fiber, for example, Ajinomoto-Build up Film (ABF), etc. may be used. . If necessary, a photosensitive insulating material such as PID (Photo Image-able Dielectric) may be used. Referring to FIG. 3 , the current insulating layer 110 is illustrated to include the first and second insulating layers 111 and 112 , but the insulating layer 110 may include more layers than shown. , may include fewer layers.

4 is a plan view schematically illustrating one surface of the printed circuit board of FIG. 3 .

The plurality of protrusions P may be formed to be spaced apart from each other in the first cavity C1 . The plurality of protrusions P may be formed on the lower surface of the first cavity C1 , and may be formed to protrude toward the inside of the first cavity C1 from the lower surface of the first cavity C1 . The height of the plurality of protrusions P may be substantially the same as the height of the first cavity C1, whereby one surface of the first insulating layer 111 of the plurality of protrusions P is coplanar. can The plurality of protrusions P may function to support a configuration to be disposed later in the first cavity C1 or on one surface of the first insulating layer 111 , for example, electronic components. That is, when the plurality of protrusions P are disposed to protrude from the lower surface of the first cavity C1 , when an electronic component to be described later is disposed on one surface of the first insulating layer 111 , the lower surface of the first cavity C1 and the It may be spaced apart as much as the height of the protrusion P, and the encapsulant 400 may be filled in the spaced space to secure adhesion of the electronic component. In addition, there is no need for steps such as distance measurement and equipment setting for separating the electronic component from the lower surface of the first cavity C1, and the printed circuit board is placed on the electronic component until the electronic component comes into contact with the plurality of protrusions P. Since it is sufficient to arrange, the process can be further simplified.

The first cavity C1 and the plurality of protrusions P may be formed by removing the second region M2 of the metal layer M, not by laser processing or mechanical processing, and thus the first cavity C1 A high roughness may be formed on the inner wall and the lower surface and the surfaces of the plurality of protrusions P through roughening treatment during a manufacturing process to be described later. For example, the inner wall and lower surface of the first cavity C1 and the surface of the plurality of protrusions P may have a greater roughness than the surface of the first wiring layer 121 exposed from one surface of the first insulating layer 111 . have. As high roughness is formed on the inner wall of the first cavity C1, when the encapsulant 400 to be described later is disposed in the first cavity C1, the adhesion between the encapsulant 400 and the first cavity C1 is increased. can be improved

The plurality of wiring layers 120 may include first to third wiring layers 121 , 122 , and 123 , configured to transmit a signal of the printed circuit board 100A, on or between the insulating layer 110 . can be placed in

The first wiring layer 121 may be buried in one surface of the first insulating layer 111 , and at least a portion thereof may be exposed to the outside of the first insulating layer 111 . The surface of the first wiring layer 121 may have a rather high roughness by roughening the surface during a manufacturing process to be described later. For example, a surface of the first wiring layer 121 in contact with the first insulating layer 111 may have a higher illuminance than a surface of the first wiring layer 121 exposed to the outside from the first insulating layer 111 . have. As described above, as the surface of the first wiring layer 121 in contact with the first insulating layer 111 has high roughness, adhesion between the first wiring layer 121 and the first insulating layer 111 may be improved. Referring to FIG. 3 , the first wiring layer 121 may be exposed from one surface of the first insulating layer 111 toward the outside, and due to the characteristics of the etching process, the exposed surface of the first wiring layer 121 is Compared to one surface of the first insulating layer 111 , the printed circuit board 100A may have a recessed structure by a predetermined distance. Although not shown, a surface treatment layer including at least one of nickel (Ni) and gold (Au) is disposed on a surface of the first wiring layer 121 exposed from one surface of the first insulating layer 111 or OSP ( An organic layer through surface treatment such as Organic Solderability Preservative may be disposed to protect the surface of the first wiring layer 121 from oxidation.

The second wiring layer 122 may be disposed on the other surface of the first insulating layer 111 , and may have a structure buried into the second insulating layer 112 from one surface of the second insulating layer 112 . The third wiring layer 123 may be disposed on the other surface of the second insulating layer 112 .

A metal material may be used as a material of the first to third wiring layers 121 , 122 , and 123 , and as the metal material, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold ( Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof may be used. The first to third wiring layers 121 , 122 , and 123 may perform various functions according to a design design. For example, it may include a ground pattern, a power pattern, a signal pattern, and the like. Each of these patterns may have a line, plane, or pad shape. The first wiring layer 121 may be formed by a plating process such as AP (Additive Process), SAP (Semi AP), MSAP (Modified SAP), TT (Tenting), and the like, and as a result, each of the seed layer and the electroless plating layer; An electrolytic plating layer formed based on such a seed layer may be included. When the insulating layer 110 is provided in the form of Resin Coated Copper (RCC), the first to third wiring layers 121 , 122 , and 123 may further include a metal foil such as a copper foil, and if necessary, on the surface of the metal foil A primer resin may be present. In the case of the wiring layer exposed to the outermost layer among the plurality of wiring layers 120 , it may function as a connection pad for connection with other substrates or components. For example, the first and third wiring layers 121 and 123 exposed from the outermost layer of the printed circuit board 100A of FIG. 3 may be connected to an electrical connection metal to be described later and function as a connection pad.

Referring to FIG. 3 , only the first to third wiring layers 121 , 122 , and 123 are currently illustrated. However, a greater number of wiring layers may be disposed than illustrated or fewer wiring layers may be disposed. .

The plurality of via layers 130 may include first and second via layers 131 and 132 . The plurality of via layers 130 pass through the first insulating layer 111 and form a first via layer 131 and a second insulating layer 112 that electrically connect the first and second wiring layers 121 and 121 to each other. A second via layer 131 penetrating through and electrically connecting the second and third wiring layers 122 and 123 may be included. A metal material may be used as a material of the first and second via layers 131 and 132 , and the metal material includes copper (Cu), aluminum (Al), silver (Ag), tin (Sn), and gold (Au). ), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof may be used. The first and second via layers 131 and 132 may include signal vias, ground vias, power vias, and the like according to design design. Each of the vias of the first and second via layers 131 and 132 may have a via hole completely filled with a metal material, or a metal material may be formed along a wall surface of the via hole. The first and second via layers 131 and 132 may also be formed by a plating process, for example, AP, SAP, MSAP, TT, etc., and are formed based on the seed layer that is the electroless plating layer and the seed layer. It may include an electrolytic plating layer. Each of the vias of the first and second via layers 131 and 132 may have a tapered shape in which the width of the upper surface is greater than the width of the lower surface.

Meanwhile, although only the first and second via layers 131 and 132 are illustrated in FIG. 3 , more or fewer via layers may be disposed as needed.

The first and second passivation layers 141 and 142 may protect internal components from external physical and chemical damage. The first and second passivation layers 141 and 142 may have a plurality of first and second openings, respectively. The plurality of first openings may expose at least a portion of the first wiring layer 121 and at least a portion of the first insulating layer 111 , respectively. Each of the plurality of second openings may expose at least a portion of the third wiring layer 123 . An insulating material may be used as the material of the first and second passivation layers 141 and 142. In this case, as the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or these resins are mixed with an inorganic filler. A material such as, but not limited to, ABF may be used.

5 is a cross-sectional view schematically illustrating another example of a printed circuit board.

In the printed circuit board 100B according to another example of FIG. 5 , as compared with the printed circuit board 100A according to the above-described example, the fourth wiring layer 124 includes the first insulating layer 111 and the first wiring layer 121 . ) is placed on In this case, a fourth wiring layer 124 may be disposed on the exposed surface of the first wiring layer 121 , and the first wiring layer 121 may be covered by the first insulating layer 111 and the fourth wiring layer 124 . can

Also, at least a portion of the fourth wiring layer 124 may be exposed through the first opening of the first passivation layer 141 . The fourth wiring layer 124 exposed through the first opening may function as a connection pad.

The fourth wiring layer 124 may include a metal material used as a material of the first to third wiring layers 121 , 122 , and 123 , and may be disposed through a process such as AP, SAP, MSAP, or TT. The fourth wiring layer 124 may be in contact with the first wiring layer 121 and may have a wider width than the first wiring layer 121 . That is, when viewed from the stacking direction of the printed circuit board 100B, the cross-section of the fourth wiring layer 124 may be disposed to include the cross-section of the first wiring layer 121 . Due to this, the connection pad may have a larger area, so that electrical connection with other components may be easier.

On the other hand, as described above, on the surface where the first wiring layer 121 and the first insulating layer 111 are in contact with each other, a high illuminance is formed through the roughening process, so that the first insulating layer 111 of the first wiring layer 121 is ), the surface of the first wiring layer 121 in contact with the fourth wiring layer 124 may have a greater illuminance than the surface in contact with the first wiring layer 121 .

A description of other configurations will be omitted, since the description of the printed circuit board 100A according to the above-described example may be equally applied.

6 is a cross-sectional view schematically illustrating another example of a printed circuit board.

7 is a cross-sectional view schematically illustrating another example of a printed circuit board.

The printed circuit boards 100C and 100D according to another example of FIGS. 6 and 7 are compared with the printed circuit boards 100A and 100B according to the above-described examples and other examples, respectively, the second cavity C2 is the first It is additionally formed on one surface of the insulating layer 111 . In this case, the first cavity C1 may be formed on the lower surface of the second cavity C2 .

Referring to the printed circuit board 100C according to another example of FIG. 6 , the second cavity C2 may be manufactured through a process described below, and in particular, not formed by laser processing or mechanical processing, but a metal layer ( Since it may be formed by removing the second region M2 of M), the roughness formed on the surface of the second region M2 may be maintained on the lower surface and inner wall of the second cavity C2 . As the lower surface and inner wall of the second cavity (C2) maintain high roughness in this way, high adhesion with the configuration in contact with the lower surface and inner wall of the second cavity (C2) such as the encapsulant 400 can be secured later.

The first cavity C1 may be formed on the lower surface of the second cavity C2 , and as described above, the plurality of protrusions P may be formed to be spaced apart from each other in the first cavity C1 . The lower surface and inner wall of the first cavity C1 and the surfaces of the plurality of protrusions P may also maintain high roughness similarly to the lower surface and inner wall of the second cavity C2 .

Referring to FIG. 7 , a printed circuit board 100D according to another example in which the second cavity C2 is formed and the above-described fourth wiring layer 124 is additionally disposed is disclosed.

A description of other configurations will be omitted, since the description of the printed circuit board 100A according to the above-described example may be equally applied.

8 is a cross-sectional view schematically illustrating another example of a printed circuit board.

The printed circuit board 100E according to another example of FIG. 8 has a structure in which a groove portion R is additionally formed on the side surface of the second cavity C2, compared with the printed circuit board 100D according to the other example described above. start

A groove portion R may be formed on a side surface of the second cavity C2 , and the groove portion R is also formed in the second region M2 of the metal layer M like the first and second cavities C1 and C2 described above. Since it may be formed through removal, high roughness may be formed on the lower surface and inner wall of the groove portion R, thereby securing adhesion with the encapsulant 400 .

Meanwhile, as the groove portion R is formed on the side surface of the second cavity C2 , the side surface of the second cavity C2 may have a step difference. As the second cavity (C2) has a step in this way, a configuration arranged in the second cavity (C2) later, for example, a bonding area with the encapsulant 400 is increased, and due to the anchor effect of the step structure Adhesion between the second cavity C2 and the components inside the second cavity C2 may be improved.

9 to 14 are cross-sectional views schematically illustrating an example of manufacturing the printed circuit board of FIG. 3 .

Referring to FIG. 9 , a carrier 700 is prepared, and the carrier 700 may include a core 710 and first and second copper foils 711 and 712 .

Referring to FIG. 10 , a metal layer M may be disposed on the second copper foil 712 , and the metal layer M may be divided into first and second regions M1 and M2 through patterning. In this case, the first region M1 may have a shape of a wiring layer surrounding the second region M2 .

Thereafter, high roughness may be formed on the surface of the patterned metal layer M through a roughening treatment such as black oxide. In this case, not only the first and second regions M1 and M2 , but also the surface of the second copper foil 712 exposed through patterning of the metal layer M may have high roughness formed on the surface through roughening treatment.

11 and 12 , a first insulating layer 111 may be stacked on the metal layer M, and a second wiring layer 122 and a first via layer 131 may be disposed. Thereafter, a second insulating layer 112 covering the second wiring layer 122 may be stacked, and a third wiring layer 123 and a second via layer 123 may be disposed.

Referring to FIG. 13 , the first and second copper foils 711 and 712 may be separated from each other, and a portion of the carrier 700 may be removed.

Thereafter, the exposed second copper foil 712 may be first removed by etching. As the second copper foil 712 is etched, the first wiring layer 121 may be completed. At this time, due to the effect of the etching process of the second copper foil 712 , a small amount of the lower surface of the first wiring layer 121 is also removed. Accordingly, the lower surface of the first wiring layer 121 may have a recessed structure by a predetermined distance compared to the one surface of the first insulating layer 111 .

Next, as shown in FIG. 14 , after a mask is disposed on the first wiring layer 121 , the second region M2 of the metal layer M may be removed through additional etching. Thereafter, the mask is separated, and a first cavity C1 may be formed on one surface of the first insulating layer 111 through removal of the second region M2 , and a first cavity C1 may be formed on a lower surface of the first cavity C1 . A plurality of protrusions P formed to protrude from the lower surface of (C1) may be disposed. The same roughness as the surface of the second region M2 of the metal layer M may be formed on the inner wall and lower surface of the first cavity C1 and the surfaces of the plurality of protrusions P.

Thereafter, the printed circuit board of FIG. 3 may be manufactured by disposing the first and second passivation layers 141 and 142 .

15 is a cross-sectional view schematically illustrating an example of an electronic component package.

The electronic component package 600A according to the example of FIG. 15 may include the printed circuit board 100A according to the above-described example. In the following description of the electronic component package 600A, the first printed circuit board 100A refers to the printed circuit board 100A according to the above-described example.

The description of the first printed circuit board 100A may be equally applied to the description of the printed circuit board 100A according to the above-described example.

The electronic component package 600A according to an example of FIG. 15 is a first printed circuit board 100A, a second printed circuit board 200 connected to the first printed circuit board 100A, and a second printed circuit board 200 The first electrical connection metal 510 electrically connecting the electronic component 300 mounted on the second printed circuit board 200 and the electronic component 300 . A second electrical connection metal 520 electrically connecting the first and second printed circuit boards 100A and 200 , a plurality of protrusions P disposed in the first cavity C1 , the first and second printed circuits The encapsulant 400 is disposed between the substrates 100A and 200 to fill the first cavity C1 and covers at least a portion of the electronic component 300 .

The second printed circuit board 200 is a printed circuit board on which the electronic component 300 is mounted, and includes a build-up insulating layer 210 , a build-up wiring layer 220 , a build-up via layer 230 and a third passivation layer. (240).

The build-up wiring layer 220 may be disposed on at least one of the outside or the inside of the build-up insulating layer 210 , and the build-up via layer 230 penetrates at least a portion of the build-up insulating layer 210 , and mutually passes through each other. The buildup wiring layers 220 disposed on different layers may be electrically connected. The third passivation layer 240 is disposed on the outer layer of the build-up insulating layer 210 and may have an opening exposing a portion of the build-up wiring layer 220 .

An insulating material may be used as a material of the build-up insulating layer 210 , and a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyimide may be used as the insulating material. In addition, those containing inorganic fillers such as silica and reinforcing materials such as glass fibers may be used in these resins. For example, a prepreg may be used, but is not limited thereto, and a material that does not include a reinforcing material such as glass fiber, for example, ABF, etc. may be used. If necessary, a photosensitive insulating material such as PID may be used. The build-up insulating layer 210 may include more or fewer layers than shown in FIG. 15 .

A metal material may be used as the material of the build-up wiring layer 220 , and the metal material includes copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni). , lead (Pb), titanium (Ti), or an alloy thereof may be used. The build-up wiring layer 220 may perform various functions according to a design design. For example, it may include a ground pattern, a power pattern, a signal pattern, and the like. Each of these patterns may have a line, plane, or pad shape. The build-up wiring layer 220 may be formed by a plating process such as AP, SAP, MSAP, TT, and the like, and as a result, each may include a seed layer that is an electroless plating layer and an electrolytic plating layer formed based on the seed layer. . When the build-up insulating layer 210 is provided in the form of RCC, the build-up wiring layer 220 may further include a metal foil such as copper foil, and a primer resin may be present on the surface of the metal foil if necessary. In the case of the wiring layer exposed to the outermost layer of the build-up wiring layer 220 , it may function as a connection pad for connection with other substrates or components. For example, the buildup wiring layer 220 exposed from the outermost layer of the second printed circuit board 200 of FIG. 15 is connected to first and second electrical connection metals 510 and 520 to be described later and functions as a connection pad. can do.

The buildup wiring layer 220 may have more or fewer layers than shown in FIG. 15 .

A metal material may be used as the material of the build-up via layer 230 , and the metal material includes copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), and nickel (Ni). ), lead (Pb), titanium (Ti), or an alloy thereof may be used. The build-up via layer 230 may include signal vias, ground vias, power vias, and the like according to a design design. Each of the vias of the build-up via layer 230 may have a via hole completely filled with a metal material, or a metal material may be formed along a wall surface of the via hole. The build-up via layer 230 may also be formed by a plating process, for example, AP, SAP, MSAP, TT, etc., and includes a seed layer that is an electroless plating layer and an electrolytic plating layer formed based on the seed layer. can do. Each via of the buildup via layer 230 may have a tapered shape in which the width of the upper surface is greater than the width of the lower surface.

The build-up via layer 230 may have more or fewer layers than shown in FIG. 15 as needed.

The electronic component 300 may be an integrated circuit (IC) die in which hundreds to millions of devices are integrated in one chip. For example, the electronic component 300 includes a central processor (eg, CPU), a graphics processor (eg, GPU), a field programmable gate array (FPGA), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, etc. It may be a processor chip, specifically, an application processor (AP), but is not limited thereto, and other memories such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), flash memory, etc. Alternatively, it may be an analog-to-digital converter, or logic such as an ASIC (application-specific IC). If necessary, the electronic component 300 may be a chip-type passive component, for example, a chip-type capacitor such as a multi-layer ceramic capacitor (MLCC), a chip-type inductor such as a PI (power inductor), and the like. . The electronic component 300 may be disposed so that the side on which the connection pad (not shown) is disposed faces downward, and the opposite side thereof faces upward. The connection pad of the electronic component 300 may include a metal material such as copper (Cu) or aluminum (Al), and may be connected to the first electrical connection metal 510 . The electronic component 300 may be covered by the encapsulant 400 without a separate adhesive film, and as a result, the back and side surfaces may be in physical contact with the encapsulant 400 .

According to the electronic component package 600A according to an example, the electronic component 300 may be in contact with one surface of the first insulating layer 111 of the first printed circuit board 100A. At least a portion of the first insulating layer 111 may be exposed from the first passivation layer 141 through the first opening, so that the electronic component 300 is in contact with the exposed one surface of the first insulating layer 111 . can be placed. Also, a first cavity C1 may be formed between the region where the electronic component 300 and the first insulating layer 111 contact each other. In this way, when the first insulating layer 111 and the electronic component 400 come into contact with each other, when the first printed circuit board 100A is stacked on the second printed circuit board 200, a separate distance is measured or a fine control process is performed. this will no longer be necessary

Specifically, when an electronic component is placed in a conventional separate accommodation space or cavity, a predetermined separation distance must be secured between the electronic component and the accommodation space in order to secure a space in which the encapsulant is to be disposed between the electronic component and the accommodation space. , a fine substrate arrangement process is required to secure the separation distance. Accordingly, defects in fixing of electronic components, failure of damage to electronic components, etc. may occur due to a failure in adjusting the distance between the substrates and the like.

On the other hand, according to the electronic component package 600A according to an example, the first cavity C1 is previously formed on one surface of the first insulating layer 111 , and a plurality of protrusions protruding from the lower surface of the first cavity C1 . (P) is formed, and as the plurality of protrusions P separate the electronic component 300 by a predetermined distance from the lower surface of the first cavity C1, a space that can be filled with the encapsulant 400 can be sufficiently secured and , so that the encapsulant 400 can be filled in the first cavity C1 even when the first insulating layer 111 and the electronic component 300 come into contact with each other. That is, the encapsulant 400 may fill between the plurality of protrusions P or between the plurality of protrusions P and the inner wall of the first cavity C1 . Therefore, there is no need to secure the separation distance between the electronic component 300 and the first insulating layer 111, and accordingly, equipment and processes used for measuring the separation distance and maintaining the separation state can be omitted, thereby simplifying the process. and the manufacturing cost can be reduced.

On the other hand, when the first printed circuit board 100A is stacked on the electronic component 300, the plurality of protrusions P perform a support function between the electronic component 300 and the first printed circuit board 100A. , the plurality of protrusions P may be in contact with the upper surface of the electronic component 300 .

The encapsulant 400 is disposed on one surface of the first insulating layer 111 , and at least a portion of one surface of the first insulating layer 111 , the upper surface of the second printed circuit board 200 , and the outer surface of the electronic component 300 . can cover Also, the encapsulant 400 may fill at least a portion of the first cavity C1 , and as a result, may cover at least a portion of the upper surface of the electronic component 300 . For example, the encapsulant 400 may physically contact at least a portion of each of the upper surface, the lower surface, and the side surface of the electronic component 300 . Since the encapsulant 400 has fluidity in the state before curing, it may flow along the outer surface of the electronic component 300 and the surface of the first insulating layer 111 . At this time, the first cavity C1 is the first insulating layer As it is formed in the layer 111 , the encapsulant 400 may fill the inside of the first cavity C1 , and accordingly, the first insulating layer 111 of the electronic component 300 and the first printed circuit board 100A. ) to ensure adhesion between As the encapsulant 400 fills the first cavity C1 and comes into contact with at least a portion of the upper surface of the electronic component 300 , the electronic component 300 may be more stably fixed.

In addition, as described above, a large roughness is formed on the inner wall and lower surface of the first cavity C1 on one surface of the first insulating layer 111 and the surface of the plurality of protrusions P through roughening treatment, the encapsulant ( Since sufficient adhesion between the 400 ) and the first insulating layer 111 can be secured, a more stable package structure can be completed.

An insulating material may be used as the material of the encapsulant 400 , and a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyimide may be used as the insulating material. In addition, those in which inorganic fillers, such as silica, are contained in these resins can also be used. For example, Ajinomoto Build-up Film (ABF) may be used as a material of the encapsulant 400 . ABF may be provided in the form of resin coated copper (RCC), but is not limited thereto. If necessary, a photosensitive material such as PIE (Photo Image-able Dielectric) may be used. In addition, the encapsulant 400 may be a known EMC (Epoxy Molding Compound), but is not limited thereto.

The first and second electrically connecting metals 510 and 520 are disposed in at least a portion of the opening of the third passivation layer 240 . The first and second electrical connection metals 510 and 520 may physically and/or electrically connect the second printed circuit board 200 to the outside. For example, the first electrical connection metal 510 may electrically connect the exposed buildup wiring layer 220 and the electronic component 300 , and the second electrical connection metal 520 may include the exposed buildup wiring layer 220 . ) and the first wiring layer 121 may be electrically connected. Each of the first and second electrical connection metals 510 and 520 may be formed of tin (Sn) or an alloy containing tin (Sn), for example, solder, but is not limited thereto. Each of the first and second electrical connection metals 510 and 520 may be a land, a ball, a pin, or a metal post in the form of a column.

In the electronic component package 600A according to an example, the second electrically connecting metal 520 may have a larger volume than the first electrically connecting metal 510 . On the other hand, since the electronic component 300 is in contact with one surface of the first insulating layer 111, the thickness of the second electrical connection metal 520 in the stacking direction of the electronic component package 600A is the electronic component ( 300) and the thickness of the first electrically connecting metal 510 may be substantially the same as the sum of the thicknesses.

Here, the meaning of being substantially the same is not completely identical in numerical terms, and it is meant to comprehensively include even the meaning of equivalents including errors in the process.

In the description of the electronic component package 600A, the description of the printed circuit board 100A according to the above-described example may be equally applied to the first printed circuit board 100A.

16 is a cross-sectional view schematically illustrating another example of an electronic component package.

The electronic component package 600B according to another example of FIG. 16 has a different structure of the first printed circuit board 100B than the electronic component package 600A according to the above-described example.

Referring to FIG. 16 , the first printed circuit board 100B mounted on the second printed circuit board 200 of the electronic component package 600B according to another example is a printed circuit board 100B according to another example described above. ) can be

Accordingly, a fourth wiring layer 124 having a width wider than that of the first wiring layer 121 may be additionally disposed on the first wiring layer 121 .

As the fourth wiring layer 124 is disposed, in the case of the electronic component package 600B according to another example, the volume of the second electrically connecting metal 520 may be relatively small. Since the second electrical connection metal 520 can be made smaller, the electronic component package 600B according to another example can implement a finer structure in terms of mounting. In addition, in the electronic component package 600B according to another example, since the volume of the second electrical connection metal 520 is reduced, between the second electrical connection metal 520 or the second electrical connection metal 520 and the first electrical connection It is advantageous in that a short circuit between the metals 510 can be prevented.

In addition, with respect to the overlapping configuration, since the description of the electronic component package 600A according to the above-described example and the printed circuit board 100B according to another example may be equally applied, it will be omitted.

17 is a cross-sectional view schematically illustrating another example of an electronic component package.

The electronic component package 600C according to another example of FIG. 17 has a different structure from the electronic component package 600A according to the above-described example, the first printed circuit board 100C.

Referring to FIG. 17 , the first printed circuit board 100C mounted on the second printed circuit board 200 of the electronic component package 600C according to another example is a printed circuit board 100C according to another example described above. ) can be

Accordingly, the second cavity C2 may be formed on one surface of the first insulating layer 111 of the first printed circuit board 100C, and the first cavity C1 is formed on the lower surface of the second cavity C2. may have been

Referring to FIG. 17 , the width of the second cavity C2 may be greater than that of the electronic component 300 , and accordingly, the electronic component 300 and the first printed circuit board 100C are formed by the second printed circuit board 200 . When mounted on the upper surface, at least a portion of the electronic component 300 may be disposed inside the second cavity C2 . Also, the width of the second cavity C2 may be greater than the width of the first cavity C1 . The upper surface of the electronic component 300 disposed in the second cavity C2 may be in contact with the lower surface of the second cavity C2 and may be in contact with the plurality of protrusions P disposed in the first cavity C1 . In addition, since the width of the second cavity C2 is greater than that of the electronic component 300 , when the encapsulant 400 fills the inside of the second cavity C2 , the encapsulant 400 is disposed on the upper surface of the electronic component 300 . and at least a portion of the side surface. As described above, since the encapsulant 400 may cover at least a portion of each of the top and side surfaces of the electronic component 300 , stable bonding and fixing of the electronic component 300 are possible. In addition, since a plurality of protrusions P are formed in the first cavity C1 to secure a space for the encapsulant 400 to be disposed, the distance between the lower surface of the second cavity C2 and the electronic component 300 . It is advantageous in that there is an effect of improving the yield and reducing the cost since the process and cost for securing the product are not consumed.

On the other hand, the inner wall and lower surface of the second cavity C2 also have high illuminance through roughening, similar to the above-described first cavity C1 . Accordingly, high adhesion between the encapsulant 400 and the first insulating layer 111 may be secured.

With respect to other overlapping configurations, the description of the electronic component package 600A according to the above-described example and the printed circuit board 100C according to another example may be equally applied, and thus will be omitted.

18 is a cross-sectional view schematically illustrating another example of an electronic component package.

The electronic component package 600D according to another example of FIG. 18 has a different structure from the electronic component package 600C according to the other example described above, the first printed circuit board 100D.

Referring to FIG. 18 , the first printed circuit board 100D mounted on the second printed circuit board 200 of the electronic component package 600D according to another example is a printed circuit board 100D according to another example described above. ) can be

Accordingly, the first printed circuit board 100D of the electronic component package 600D according to another example of FIG. 18 may further include a fourth wiring layer 124 disposed on the first wiring layer 121 , A second cavity C2 may be formed on one surface of the first insulating layer 111 .

For the electronic component package 600D according to another example of FIG. 18 , the description of the printed circuit board 100D according to the above-described other example and the electronic component packages 600B and 600C according to another example may be equally applied. .

19 is a cross-sectional view schematically illustrating another example of an electronic component package.

The electronic component package 600E according to another example of FIG. 19 has a different structure from the electronic component package 600D according to the other example described above in the structure of the first printed circuit board 100E.

Referring to FIG. 19 , the first printed circuit board 100E mounted on the second printed circuit board 200 of the electronic component package 600E according to another example is a printed circuit board 100E according to another example described above. ) can be

Accordingly, a groove portion R may be formed on the side surface of the second cavity C2 formed in the first insulating layer 111 of the first printed circuit board 100E, and accordingly, the second cavity C2 is formed on the side surface. may have a difference.

As the side of the second cavity C2 has a step difference, the encapsulant 400 may be filled in the groove portion R as well, and the encapsulant 400 and the first insulating layer ( 111), the adhesion between the two can be further improved.

On the other hand, the inner wall and the lower surface of the groove portion R also have high roughness through roughening, similar to the above-described first cavity C1 and second cavity C2 . Accordingly, high adhesion between the encapsulant 400 and the first insulating layer 111 may be secured.

With respect to other overlapping configurations, the description of the printed circuit board 100E according to the above-described other example and the electronic component package 600D according to another example may be equally applied, and thus will be omitted.

In the present disclosure, expressions of side, side, etc. are used to mean a plane in the left/right direction or in that direction based on the drawing for convenience, and expressions of upper side, upper side, upper surface, etc. It was used to mean the face in the direction, and the lower side, lower side, lower side, etc. were used to mean the face in the downward direction or that direction for convenience. In addition, being located on the side, upper, upper, lower, or lower side means that the target component not only directly contacts the reference component in the corresponding direction, but also includes a case where the target component is positioned in the corresponding direction but does not directly contact was used as However, this is a definition of the direction for convenience of explanation, and the scope of the claims is not particularly limited by the description of this direction, and the concept of upper/lower may be changed at any time.

The meaning of connected in the present disclosure is a concept including not only directly connected, but also indirectly connected through an adhesive layer or the like. In addition, the meaning of being electrically connected is a concept that includes both a physically connected case and a non-connected case. In addition, expressions such as first, second, etc. are used to distinguish one component from another, and do not limit the order and/or importance of the corresponding components. In some cases, without departing from the scope of rights, the first component may be referred to as the second component, and similarly, the second component may be referred to as the first component.

The expression “an example” used in the present disclosure does not mean the same embodiment, and is provided to emphasize and explain different unique features. However, the examples presented above are not excluded from being implemented in combination with features of other examples. For example, even if a matter described in one specific example is not described in another example, it may be understood as a description related to another example unless a description contradicts or contradicts the matter in another example.

The terminology used in the present disclosure is used to describe an example only, and is not intended to limit the present disclosure. In this case, the singular expression includes the plural expression unless the context clearly indicates otherwise.

100A, 100B, 100C, 100D, 100E: Printed circuit board
111, 112: insulating layer
121, 122, 123, 124: first to fourth wiring layers
131 and 132: first and second via layers
C: cavity
R1, R2: first and second grooves
141, 142: first and second passivation layers
600A, 600B, 600C, 600D, 600E: Electronic component package
200: second printed circuit board
300: electronic component
400: suture material
510, 520: first and second electrical connection metal
700: carrier

Claims (16)

a first insulating layer;
a first cavity formed on one surface of the first insulating layer;
a plurality of protrusions spaced apart from each other in the first cavity; and
a first wiring layer buried in one surface of the first insulating layer; Including, a printed circuit board.
The method of claim 1,
a second cavity formed on one surface of the first insulating layer; further comprising,
The first cavity is formed on a lower surface of the second cavity.
3. The method of claim 2,
The printed circuit board further comprising a groove formed on a side surface of the second cavity.
3. The method of claim 2,
a second wiring layer disposed on the other surface of the first insulating layer;
a first via layer passing through at least a portion of the first insulating layer and connecting the first and second wiring layers;
a second insulating layer disposed on the other surface of the first insulating layer and having the second wiring layer embedded therein;
a third wiring layer disposed on the other surface of the second insulating layer; and
a second via layer passing through at least a portion of the second insulating layer and connecting the second and third wiring layers; Further comprising a, printed circuit board.
5. The method of claim 4,
a fourth wiring layer disposed on one surface of the first insulating layer; further comprising,
and the fourth wiring layer covers at least a portion of the first wiring layer.
6. The method of claim 5,
a solder resist layer disposed on one surface of the first insulating layer and the other surface of the second insulating layer; Further comprising a, printed circuit board.
The method of claim 1,
The first wiring layer is exposed from one surface of the first insulating layer,
A surface of the first wiring layer in contact with the first insulating layer has relatively greater roughness than a surface exposed from the first insulating layer of the first wiring layer.
a first printed circuit board including an insulating layer, a first cavity formed on one surface of the insulating layer, and a plurality of protrusions spaced apart from each other in the first cavity;
a second printed circuit board disposed on one side of the first printed circuit board and having the first printed circuit board mounted on one surface; and
an electronic component mounted on one surface of the second printed circuit board; includes,
One surface of the insulating layer of the first printed circuit board is in contact with the electronic component, an electronic component package.
9. The method of claim 8,
The plurality of protrusions are in contact with one surface of the electronic component, the electronic component package.
9. The method of claim 8,
an encapsulant disposed between the first and second printed circuit boards to cover at least a portion of the electronic component; Further comprising, an electronic component package.
11. The method of claim 10,
The encapsulant fills at least a portion of the first cavity.
12. The method of claim 11,
a second cavity formed on one surface of the insulating layer; further comprising,
The first cavity is formed on a lower surface of the second cavity,
and the encapsulant fills at least a portion of the second cavity.
12. The method of claim 11,
The first printed circuit board,
a first wiring layer buried in one surface of the insulating layer; and
and a second wiring layer disposed on the first wiring layer and protruding from one surface of the insulating layer.
12. The method of claim 11,
a first electrical connection metal disposed between the second printed circuit board and the electronic component; and
a second electrical connection metal disposed between the first and second printed circuit boards; Further comprising, an electronic component package.
14. The method of claim 13,
a surface of the first wiring layer in contact with the insulating layer,
The electronic component package, wherein the illuminance is greater than that of a surface of the first wiring layer in contact with the second wiring layer.
13. The method of claim 12.
Further comprising a groove formed on the side of the second cavity,
The encapsulant further fills the groove portion, the electronic component package.

Images