KR20220136824A - Current mode logic circuit and PAM4 driving circuit including the same - Google Patents

Abstract

A current mode logic circuit according to an embodiment comprises: a first circuit which includes a first transistor connected to an input voltage, and a second transistor connected to an inverting input voltage; a second circuit which includes a third transistor connected to a cascode input voltage, and a fourth transistor connected to a cascode inverting input voltage; and a fifth transistor which has one end connected to the first transistor and the third transistor, and the other end connected to the second transistor and the fourth transistor.

Description

Current mode logic circuit and PAM4 driving circuit including the same

The present invention relates to a current mode logic circuit and a PAM4 driving circuit including the same, and more particularly, by changing the direction of the current flowing inside the current mode logic circuit to reduce the magnitude of the voltage applied to the input transistor, The present invention relates to a technology capable of stably driving a current mode logic circuit and a PAM 4 driving circuit including the same.

A current mode logic circuit is a type of semiconductor logic device, and refers to a non-saturation type high-speed logic circuit constructed using differentially connected current switches.

High-speed operation signal processing circuits are implemented using a technique called Current Mode Logic (CML). Generally, they are configured in the form of using a resistive element as a load in a differential amplifier, so NMOS (N-channel metal oxide semiconductor ) or PMOS (N-channel metal oxide semiconductor) devices have the advantage of achieving higher operating speed than the complementary metal-oxide semiconductor (CMOS) method in which a pair is connected.

In addition, the current mode logic circuit has an advantage in terms of noise because it can be transmitted as a differential signal. Accordingly, most of the current mode logic is used in gigaband integrated circuits constituting devices requiring high-speed operation to support a 10-Gbps Gigabit Capable Passive Optical Network (GPON).

The output voltage level of the current mode logic circuit is variable according to the voltage applied to the drain node of the differential transistor. Accordingly, when it is desired to increase the output voltage of the current mode logic circuit, the magnitude of the voltage applied to the drain node of the differential transistor is generally increased.

However, if the level of the voltage applied to the drain node of the transistor is continuously increased in order to increase the level of the output voltage, the transistor device may break out of the voltage range at which the transistor device can operate normally. It is common to design the level of the input voltage applied to the transistor within a range in which the transistor does not destroy the device.

However, as the technology advances, the size of the transistor becomes smaller and, accordingly, the durability of the device becomes weaker, so the size of the voltage that can be applied to the drain node continues to decrease. There is a problem in that the level of the output voltage of the logic circuit is decreased.

That is, in the past, a high voltage of about 1.8V could be applied to the drain node of the transistor, so it was relatively easy to obtain a high output voltage. Currently, in order to operate the device stably, a voltage of 0.8V or less is applied to the drain node of the transistor. , there is a problem in that the output voltage of the current mode logic circuit is lowered accordingly.

Korean Patent Laid-Open Patent Publication 10-2006-0043278 A (Differential Current Mode Phase Frequency Detector Circuit)

Accordingly, the current mode logic circuit and the PAM4 driving circuit according to an embodiment are inventions designed to solve the above-described problems, and the current mode logic circuit stably without destroying the transistor element even when the input voltage is increased in the current mode logic circuit. The purpose is to implement a circuit that can drive

More specifically, by changing the direction and magnitude of the current flowing inside the current mode logic circuit, the magnitude of the voltage applied between the drain and the gate of the input transistor is reduced, so that the input transistor is not destroyed by the high voltage and more stably An object of the present invention is to provide a circuit that can be driven.

A current mode logic circuit according to an embodiment includes a first circuit including a first transistor connected to an input voltage and a second transistor connected to an inverted input voltage; a second circuit including a third transistor connected to the cascode input voltage and a fourth transistor connected to the cascode inversion input voltage; and a fifth transistor having one end connected to the first transistor and the third transistor and the other end connected to the second transistor and the fourth transistor.

Since the fifth transistor is connected to an external voltage, the magnitude of the voltage applied to the gate of the fifth transistor may be varied.

The direction of the current flowing through the fifth transistor may be changed according to ON/OFF of the input voltage and the inverted input voltage.

When the input voltage is OFF and the inverted input voltage is ON, the direction of the current flowing through the fifth transistor may flow from the third transistor to the fifth transistor.

When the input voltage is OFF, the voltage applied between the drain and the gate of the first transistor may be reduced by conducting a current flowing through the third transistor to the fifth transistor.

When the input voltage is ON and the inverted input voltage is OFF, the direction of the current flowing through the fifth transistor may flow from the fourth transistor to the fifth transistor.

When the input voltage is ON, the voltage applied to the drain and gate of the second transistor may be reduced by conducting a current flowing through the fourth circuit to the fifth transistor.

A current mode logic circuit according to another embodiment includes a first circuit including a first transistor connected to an input voltage and a second transistor connected to an inverted input voltage and a third transistor connected to a cascode input voltage and a cascode inversion input a second circuit including a fourth transistor connected to a voltage, wherein the first circuit is connected between the first transistor and the third transistor to control the magnitude of the voltage applied to the first transistor A first slave circuit may be included, and the second circuit may include a second slave circuit connected between the second transistor and the fourth transistor to control a level of a voltage applied to the second transistor. .

The first slave circuit includes a first current source connected to a ground and a ground;

The second dependent circuit may include a second current source connected to the ground and the ground.

In the first current source, the input voltage is OFF, the current flows when the inverted input voltage is ON, the current does not flow when the input voltage is ON and the inverted input voltage is OFF, the second current source is , a current may flow when the input voltage is ON and the inverted input voltage is OFF, and no current flows when the input voltage is OFF and the inverted input voltage is ON.

A PAM 4 driving circuit according to an embodiment includes: a first circuit including a first transistor connected to a first input voltage and a third transistor connected to a first cascode input voltage; a second circuit including a second transistor connected to the first inverted input voltage and a fourth transistor connected to the first cascode inverted input voltage; and a first load having one end connected to the first circuit and the other end connected to the second circuit; and a third circuit including a sixth transistor connected to the second input voltage and an eighth transistor connected to the second cascode input voltage; a fourth circuit including a seventh transistor connected to a second inverted input voltage and a ninth transistor connected to a second cascode inverted input voltage; and a second current mode logic circuit including a second load having one end connected to the third circuit and the other end connected to the fourth circuit.

The direction of the current flowing through the first load and the second load may be changed according to ON/OFF of the input voltages and the inverted input voltages.

The first load includes the second transistor, the third transistor, and a fifth transistor connected to a first external voltage, and the second load includes the seventh transistor and the eighth transistor and a second external voltage. It may include a tenth transistor connected to.

The first load includes a first resistor connected to the second transistor and the third transistor, and the second load is connected to the seventh transistor and the eighth transistor, and is 2 less than the first resistor. A second resistor having a double resistance value may be included.

The first load includes a 1-1 resistor connected to the first transistor and the third transistor, a 1-2 resistance connected to the second transistor and the fourth transistor, and the 1-1 resistor and the a first capacitor connected between a 1-2th resistor, and the second load includes: a 2-1th resistor connected to the sixth and eighth transistors; the seventh transistor; and the ninth transistor; A 2-2 resistor connected thereto and a second capacitor connected between the 2-1 th resistor and the 2-2 resistor may be included.

In the current mode logic circuit and the PAM4 driving circuit including the same according to an embodiment, the voltage applied to the input transistor is lowered unlike the prior art even when the driving voltage of the circuit is increased, so that the input transistor can be stably driven. The durability of the logic circuit can be increased, and there is an advantage that it can be implemented in a small area without additional power consumption.

Accordingly, there is an effect of reducing the influence of noise and interference by improving the output signal and signal to noise ratio (SNR) of the current mode logic circuit.

1 is a circuit diagram showing the structure of a current mode logic circuit according to the prior art.
FIG. 2 is a diagram illustrating equations of an input voltage and an inverted input voltage input to a current mode logic circuit and equations of an output voltage and an inverted output voltage output from the current mode logic circuit according to the prior art.
3 is a diagram for explaining a gate-oxide destruction phenomenon of a transistor.
4 is a circuit diagram illustrating a structure of a current mode logic circuit according to an exemplary embodiment.
5 is a diagram illustrating a direction of a current flowing when an input voltage is 0 in a current mode logic circuit according to an exemplary embodiment.
6 is a diagram illustrating a direction of a current flowing when an inverted input voltage is 0 in a current mode logic circuit according to an exemplary embodiment.
7 is a diagram illustrating experimental results on voltage levels in a current mode logic circuit according to an embodiment and a current mode logic circuit according to the related art.
8 is a circuit diagram illustrating a structure of a current mode logic circuit according to another embodiment.
9 is a circuit diagram illustrating a structure of a PAM4 driving circuit according to an exemplary embodiment.
10 is a circuit diagram illustrating a structure of a PAM4 driving circuit according to another embodiment.
11 is a circuit diagram illustrating a structure of a PAM4 driving circuit according to another embodiment.
12 is a diagram illustrating experimental results of a PAM4 driving circuit according to a prior art of a PAM4 driving circuit according to an embodiment.
13 is a circuit diagram illustrating a structure of a PAM16 driving circuit according to an exemplary embodiment.
14 is a circuit diagram illustrating a structure in which resistors may be disposed in a PAM16 driving circuit according to an exemplary embodiment.

The configuration shown in the embodiments and drawings described in this specification is only a preferred example of the disclosed invention, and there may be various modifications that can replace the embodiments and drawings of the present specification at the time of filing of the present application.

Throughout this specification, when a part is "connected" to another part, it includes not only a case in which it is directly connected, but also a case in which it is indirectly connected, and the indirect connection refers to being connected through a wireless communication network. include

In addition, the terms used herein are used to describe the embodiments, and are not intended to limit and/or limit the disclosed invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present specification, terms such as “comprise” or “have” are intended to designate that a feature, number, step, operation, component, part, or combination thereof described in the specification exists, but one or more other features It does not preclude the possibility of the presence or addition of numbers, steps, operations, components, parts, or combinations thereof.

In addition, terms including an ordinal number such as "first", "second", etc. used herein may be used to describe various elements, but the elements are not limited by the terms, and the terms are It is used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component.

In addition, terms such as "~ part", "~ group", "~ block", "~ member", and "~ module" may mean a unit for processing at least one function or operation. For example, the terms may mean at least one process processed by at least one hardware such as a field-programmable gate array (FPGA) / application specific integrated circuit (ASIC), at least one software stored in a memory, or a processor. have.

The signs attached to each step are used to identify each step, and these signs do not indicate the order between the steps, and each step is performed differently from the stated order unless the context clearly indicates a specific order. can be

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram illustrating a structure of a current mode logic circuit according to the prior art, and FIG. 2 is an input voltage input to a current mode logic circuit according to the prior art and an inverted input voltage equation and an output voltage output from the current mode logic circuit It is a diagram showing the expression of the over-inverted output voltage, and FIG. 3 is a diagram for explaining the gate-oxide destruction phenomenon of the transistor.

1 to 3, in a current mode logic circuit according to the prior art, the driving voltage is Vtt(V), and the input voltage Vip and the inverted input voltage Vin are input as Vd(V) and 0(V). If so, the output voltage (Vop) and the inverted voltage output (Von) of the current mode logic circuit are output as (Vtt -Itx*Rt) (V) and Vtt(V). Conversely, if the input voltage and inverting input voltage are input as 0(V) and Vd(V), the output voltage (Vop) and inverting voltage output (Von) of the current mode logic circuit are Vtt(V) and (Vtt -Itx* Rt) is output as (V).

The reason that the output voltage of the circuit is not in the range of 0 ~ Vtt (V) is that the first transistor T1 and the second transistor T2, which are differential transistors, must operate in a convergence region due to the characteristics of the current mode logic circuit. Since the current source (Itx) must be driven at the same time, a constant voltage is required, so the output voltage and inverting output voltage of the current mode circuit are not 0 ~ Vtt (V), but a smaller range (Vtt -Itx*Rt) ~ Vtt (V) ) is output.

In a current mode logic circuit, the output width (swing) may be defined as the difference between the output voltage and the inverted output voltage. That is, a difference between a value having a high level of the output voltage and a value having a low level of the output voltage may be defined as the width of the output. Accordingly, the width of the output in the current mode logic circuit as shown in FIG. 1 becomes Itx*Rt.

Due to the characteristics of the current mode logic circuit, the output width becomes smaller than that of the CMOS circuit, which causes a lot of difficulty in driving the current mode logic circuit at high speed while maintaining a high voltage in an environment with large noise or interference. Therefore, when the width of the output in the current mode logic circuit is to be increased, the width of the output of the circuit is increased by increasing the magnitude of the driving voltage Vtt.

However, since general transistors have a fixed voltage range that can operate normally without stress, inadvertently increasing the voltage of the driving power source to widen the output width in a current mode logic circuit may result in overloading the transistor. As a result, there may be a problem that the device is destroyed.

Specifically, as shown in FIG. 3 , in the case of an NMOS transistor, if the voltage (Vdg) between the drain and the gate of the transistor is higher than a predetermined voltage, the device cannot withstand the voltage and the gate-oxide is destroyed. (gate-oxide breakdown) phenomenon occurs.

Therefore, in general, in manufacturing a circuit, the bias voltage applied to the transistor should be controlled not to exceed a certain level so as not to destroy the device. Then, the voltage (Vdg) between the drain and the gate of the input transistors becomes larger, which soon exceeds the limiting operating voltage range (Vbreak) that the device can withstand, so the gate-oxide breakdown phenomenon described above may occur .

Accordingly, the current mode logic circuit 10 according to an embodiment is an invention designed to solve all of these problems, and the drain and gate of the input transistor without changing the widths of the driving voltage and the output voltage in the current mode logic circuit. It is an invention designed to provide a current mode logic circuit that can be stably driven without destroying a transistor by reducing the voltage applied therebetween, and a high-order PAM driving circuit including the same. Hereinafter, various embodiments of the present invention will be described with reference to the drawings.

4 is a circuit diagram illustrating a structure of a current mode logic circuit according to an exemplary embodiment.

Referring to FIG. 4 , the current mode logic circuit 10 according to an embodiment is connected to a first trim resistor Rt1 and a second trim resistor Rt2 connected to a supply voltage Vtt, and an input voltage Vip. The first transistor T1 to be used, the second transistor T2 connected to the inverted input voltage Vin, the first transistor T1 and the second transistor T2 and the third connected in a cascode manner, respectively A transistor T3 and a fourth transistor T4, one end connected to the first transistor T1 and the third transistor T3, and the other end connected to the second transistor T2 and the fourth transistor T4 Five transistors T5 may be included.

The first trimmed resistor Rt1, the first transistor T1, and the second transistor T2 are combined to form a first circuit, and the second trimmed resistor Rt2, the third transistor T3, and the fourth transistor T4 are connected. Together, it may be referred to as a second circuit.

The third transistor T3 and the fourth transistor T4 are disposed between the first trim resistor R1 and the first transistor T1 as shown in FIG. 4 , and the fourth transistor T4 has the second trim It may be disposed between the resistor R2 and the second transistor T2.

In addition, although not shown in the drawing, the current mode logic circuit 10 is a control unit (not shown) capable of adjusting all kinds of voltages (input voltage, inverted input voltage, cascode input voltage) input to the current mode logic circuit 10 . ), and in the drawings of this specification, for convenience of explanation, all input voltages are applied from the left side of the current mode logic circuit 10 , and all inverted input voltages are applied from the right side of the current mode logic circuit 10 . Although shown as being, the embodiment of the present invention is not limited thereto, and the positions of the input voltage and the inverted input voltage may be switched.

In addition, the transistor described in the drawings is not limited to a specific transistor, and according to the principle of the present invention, a transistor suitable for the flow of current, for example, NMOS, PMOS, CMOS, etc. may be disposed in the circuit.

In the current mode logic circuit 10 according to an embodiment, when the circuit is configured as shown in FIG. 4 , the first transistor T1 and the second transistor T2 corresponding to the input transistor have a third transistor ( Since T3) and the fourth transistor T4 are connected in a cascode manner, the magnitude of the voltage applied to the first transistor T1 and the second transistor T2 may be reduced. That is, the third transistor T3 and the fourth transistor T4 may serve to protect the first transistor T1 and the second transistor T2 by the amount of the reduced voltage.

When the current mode logic circuit 10 is implemented without the fifth transistor T5 as shown in FIG. 4 , the voltage 0 (V) as the input voltage to the first transistor T1 and the second transistor T2 Vd (for example, 1.0V) is input as an inverted input voltage to , and Vca (for example, 1.2V) is input as a cascode input voltage and a cascode inverted input voltage to the third transistor T3 and the fourth transistor T4. , the voltage between the drain and gate of the third transistor T3 becomes Vtt-Vca (V), not Vtt (V). Accordingly, since a spare voltage is generated as much as Vca (V) voltage, the driving voltage can be further increased by Vca (V), thereby increasing the stability of the first transistor T1 corresponding to the input transistor.

In the present invention, the cascode input voltage (Vcasp) and the cascode inversion input voltage (Vcasn) are described on the premise that the same voltage Vcas is input, but the cascode input voltage and the cascode inversion input voltage are each other over time. It can also be turned ON/OFF differently.

However, when the current mode circuit is implemented without the fifth transistor T5, when the input voltage continuously enters the current mode logic circuit 10 over time, the characteristics of the input transistors T1 and T2 The drain-gate voltage converges to the magnitude of the cascode input voltage (for example, when the cascode input voltage is 1.2V, the drain-gate voltage of the input transistor converges to 1V), which is an operation that the input transistor can tolerate There is a problem in that a voltage exceeding the range may be input and the device may be destroyed.

However, as shown in FIG. 5, the current mode logic circuit 10 is between the first circuit and the second circuit, specifically, one end is connected to the first transistor T1 and the third transistor T3, and the other end is connected to the first transistor T1 and the third transistor T3. When a fifth transistor T5 that is connected to the second transistor T2 and the fourth transistor T4 and receives a gate voltage from the external voltage Vb is included, flowing through the first circuit or the second circuit A portion of the current may be conducted to the second circuit or the first circuit, so that the magnitude of the voltage applied to the first transistor T1 and the second transistor T2 may be reduced.

Looking at this in detail with reference to FIGS. 5 and 6 , FIG. 5 is a view showing the direction of a current flowing when the input voltage is 0 in the current mode logic circuit according to the embodiment, and FIG. 6 is the current mode according to the embodiment. It is a diagram showing the direction of the current flowing when the inverted input voltage is 0 in the logic circuit.

As shown in FIG. 5, when the input voltage is 0 (V) and a voltage of a certain magnitude is applied to the cascode input voltage, the contact X1 of the first circuit has a higher voltage than the contact X2 of the second circuit, Current can flow from the first circuit to the second circuit through the fifth transistor T5. That is, since the current flows from the first circuit to the second circuit, the voltage between the drain and the gate of the first transistor T1 to which no input voltage is applied can be lowered by that much, so that the first transistor T1 corresponding to the input transistor There is a stabilizing effect of

In this way, when the inverted input voltage is 0 (V) and a voltage of a certain magnitude is applied to the cascode input voltage and the inverted input voltage, the contact X2 of the second circuit has a voltage higher than that of the contact X1 of the first circuit. Since it is formed high, the current can flow from the second circuit to the first circuit through the fifth transistor T5. That is, since the current flows from the second circuit to the first circuit, the voltage between the drain and the gate of the third transistor T3 to which the input voltage is not applied can be lowered by that much, so that the second transistor T2 corresponding to the input transistor There is a stabilizing effect of

Accordingly, the fifth transistor T5 may be included as long as it is a transistor capable of serving as a switch capable of changing the flow of current while flowing current, and may include, for example, NMOS, PMOS, or CMOS.

7 is a view showing experimental results for voltage magnitudes in a current mode logic circuit according to an embodiment and a current mode logic circuit according to the prior art. Specifically, FIG. A diagram showing the magnitude of the voltage applied to the first transistor T1 in this case, and the magnitude of the voltage applied to the first transistor T1 in the case in which the fifth transistor is included as an experimental result in FIG. 8B. to be.

As shown in FIG. 7, when the fifth transistor is not included, the voltage V2 between the drain and the gate applied to the first transistor corresponds to 986.5 mV. However, when the fifth transistor is included, the current is Since it can flow from the first circuit to the second circuit, the magnitude of the drain-gate voltage V1 applied to the first transistor is lowered to 904.8Mv. That is, when a portion of the current flows through the fifth transistor T5 by including the fifth transistor, the level of the voltage between the drain and the gate of the input transistor T1 to which the input voltage is not applied can be lowered, thereby reducing the stability of the input transistor. There is an effect that can increase the

8 is a circuit diagram illustrating a structure of a current mode logic circuit according to another embodiment.

Referring to FIG. 8 , a current mode logic circuit 10 according to another embodiment is connected to a first trim resistor Rt1 and a second trim resistor Rt2 connected to a supply voltage Vtt, and an input voltage Vip. The first transistor T1 to be used, the second transistor T2 connected to the inverted input voltage Vin, the first transistor T1 and the second transistor T2 and the third connected in a cascode manner, respectively A first dependent circuit Z1 connected to a transistor T3 and a fourth transistor T4, a first transistor T1 and a second transistor T2, and a third transistor T3 and a fourth transistor T4 and It may include a connected second dependent circuit (Z2).

The first and second dependent circuits Z1 and Z2 of the current mode logic circuit 10 according to FIG. 8 have a first transistor T1 and a second transistor when the input voltage is 0V or the inverted input voltage is 0V. It means a circuit for lowering the voltage between the drain and gate of (T2). In FIG. 8, the components of the first slave circuit Z1 are limited to the first current source Ib1 and the components of the second slave circuit Z2 are limited to the second current source Ib2, but the embodiment of the present invention is not The present invention is not limited thereto, and if it is a component capable of lowering the voltage between the drain and gate of the first transistor T1 and the second transistor T2, it is included in the first and second dependent circuits Z1 and Z2. can

The first current Ib1 and the second current source Ib2 may be respectively connected to the ground as shown in FIG. 8 , and the first current source Ib1 has an input voltage of OFF and a current when the inverted input voltage is ON. flows, the input voltage is ON, and can be controlled so that no current flows when the inverted input voltage is OFF, and the second current source (Ib2) also flows when the input voltage is ON and the inverted input voltage is OFF , when the input voltage is OFF and the inverted input voltage is ON, it can be controlled so that no current flows.

When the input voltage is OFF and the inverted input voltage is ON, since some current flows from the third transistor T3 to the first slave circuit Z1 by the first current source Ib1, compared to the case where no current flows Since the voltage between the drain and gate of the first transistor T1 is lowered, the first transistor T1 may be driven more stably without being destroyed.

In addition, when the input voltage is ON and the inverted input voltage is OFF, the current does not flow because a part of the current flows from the fourth transistor T4 to the second slave circuit Z2 by the second current source Ib2. Since the voltage between the drain and gate of the third transistor T3 is lower than in the case of the third transistor T3 , the third transistor T3 may be driven more stably without being destroyed.

9 to 11 are diagrams illustrating various embodiments of implementing a PAM driving circuit using a current mode circuit according to the present invention.

PAM (Pulse Amplitude Modulation) driving circuit refers to a pulse amplitude modulation circuit, and PAM driving circuit is generally driven by connecting current mode logic circuits in parallel step by step, and when two are connected in parallel, PAM4 driving circuit When three are connected in parallel, it is referred to as a PAM8 driving circuit, and when four are connected in parallel, it is referred to as a PAM16 driving circuit.

Referring to FIG. 9 , the PAM4 driving circuit 100 according to an embodiment may include a first current mode logic circuit 11 and a second current mode logic circuit 12 , and a first current mode logic circuit ( 11) is a first trim resistor Rt1 and a second trim resistor Rt2 connected to the supply voltage Vtt, a first transistor M1 connected to the first input voltage Vip1, a first inverted input voltage ( Vin) connected to the second transistor M2, the first transistor M1, and the second transistor M2 and the third transistor M3 and the fourth transistor M4 connected in a cascode manner, respectively, and One end is connected to the first transistor (M1) and the third transistor (M3), the other end is connected to the second transistor (M2) and the fourth transistor (M4), the gate input voltage from the first external voltage (Vb1) It may include a fifth transistor M5 that receives an input, where the fifth transistor may be referred to as a first load.

The second current mode logic circuit 12 includes a sixth transistor M6 connected to the second input voltage Vip2, a seventh transistor M7 connected to the second inverted input voltage Vin, and a sixth transistor M6 ) and the seventh transistor M7 and the eighth transistors M8 and the ninth transistor M9 connected in a cascode manner, respectively, and one end connected to the sixth transistor M6 and the seventh transistor M7 and a tenth transistor M10 having the other end connected to the eighth transistor M8 and the ninth transistor M9 and receiving a gate input voltage from the second external voltage Vb2, where the tenth The transistor may be referred to as a second load.

When the PAM4 driving circuit is implemented by connecting the current mode logic circuits in parallel as shown in FIG. 9 , the operating principle of each current mode circuit 11 and 12 is the same as described in the previous drawings, so the input transistor There is an advantage of stably driving the PAM4 driving circuit without destroying the device because the magnitude of the voltage applied to the device is small.

In the case of the PAM 4 driving circuit according to FIG. 10, the basic components of the current mode circuit are the same as those of the current mode logic circuit in FIG. 9, but as shown in FIG. ) is changed to the first resistor R1, and in the second current mode circuit 12, a second resistor R2 having a resistance value twice that of the first resistor R1 is changed. When the PAM 4 driving circuit is implemented with the structure shown in FIG. 10 , as in FIG. 9 , some current flows through the first resistor R1 and the second resistor R2 , so that in each current mode logic circuit 10 There is an effect that can lower the magnitude of the gate-drain voltage of the input transistor. Here, the first resistor R1 may be referred to as a first load, and the second resistor R2 may be referred to as a second load.

In the case of the PAM 4 driving circuit according to FIG. 11, the basic components of the current mode circuit are the same as those of the current mode logic circuit in FIG. 9, but as shown in FIG. ) is changed to the first load composed of the first resistor R1-1, the second resistor R1-2, and the first capacitor C1, and in the second current mode circuit 12, the third resistor R2- 1), there is a difference in the change to the second load composed of the fourth resistor (R2-2) and the second capacitor (C2).

When the PAM 4 driving circuit is implemented with the structure shown in FIG. 11, in addition to the effect described above, since a capacitor is connected between each resistor, a filter effect that can prevent signals from other circuits from entering through the resistor also exist

12 is a view showing experimental results of a PAM4 driving circuit according to a prior art of a PAM4 driving circuit according to an embodiment. When the circuit is implemented, it is a diagram showing the output waveform, and FIG. 12 (b) is the output waveform when the PAM4 driving circuit including the first load and the second load is implemented according to the present invention. 13 is an experimental result comparing only the magnitude of the voltage between the gate and the drain applied to the input transistor of the PAM4 driving circuit according to the prior art and the PAM4 driving circuit according to the present invention.

In addition, the lowermost graph in FIG. 12 is the output waveform of the current mode circuit, the upper graph is the voltage waveform with time applied to the input transistor, and the purple line in FIG. 13 is the voltage applied to the input transistor according to the present invention. is a line showing the magnitude of , and the green line is a line showing the magnitude of the voltage applied to the input transistor according to the prior art.

12 and 13, according to the prior art, the highest voltage of the input transistor outputs a value similar to 1V several times, but in the present invention, the highest voltage of the input transistor does not exceed 1V. It can be seen that the input transistors can be driven more stably in the PAM 4 driving circuit according to the prior art than in the PAM 4 driving circuit according to the related art.

14 is a circuit diagram illustrating a structure of a PAM16 driving circuit according to an exemplary embodiment.

Referring to FIG. 14 , the PAM4 driving circuit 100 according to an embodiment includes a first current mode logic circuit 11 , a second current mode logic circuit 12 , a third current mode logic circuit 13 , and a fourth A current mode logic circuit 14 may be included, and the current mode logic circuits may be connected in parallel while sharing an output voltage as shown in the figure.

Specifically, the first current mode logic circuit 11 includes a first trim resistor Rt1 and a second trim resistor Rt2 connected to the supply voltage Vtt, and a first transistor connected to the first input voltage Vip1 ( M1), the second transistor M2 connected to the first inverting input voltage Vin1, the first transistor M1, and the second transistor M2 and the third transistor M3 connected in a cascode manner, respectively ) and the fourth transistor M4 and the 1-1 resistor R1-1 connected to the first transistor M1 and the third transistor M3, the second transistor M2 and the fourth transistor M4 and It may include a 1-2-th resistor R1-2 connected thereto, and the 1-1-th resistor R1-1 and the 1-2-th resistor R1-2 may be connected in series.

The second current mode logic circuit 12 includes a sixth transistor M6 connected to the second input voltage Vip2, a seventh transistor M7 connected to the second inverted input voltage Vin2, and a sixth transistor M6 ) and the seventh transistor M7 and the eighth transistors M8 and the ninth transistor M9 connected in a cascode manner, respectively, and the sixth transistor M6 and the eighth transistor M8 connected to each other. It may include a 2-1 resistor R2-1, a 2-2 resistor R2-2 connected to the seventh transistor M7 and the ninth transistor M9, and a 2-1 resistor R2- 1) and the second-second resistor R2-2 may be connected in series.

The third current mode logic circuit 13 includes an eleventh transistor M11 connected to the third input voltage Vip3, a twelfth transistor M12 connected to the third inverted input voltage Vin3, and an eleventh transistor M11 ) and a thirteenth transistor (M13) and a fourteenth transistor (M14) respectively connected to the cascode method with the twelfth transistor (M12), and a thirteenth transistor (M11) and a thirteenth transistor (M13) connected to the eleventh transistor (M11) and the thirteenth transistor (M13) It may include a 3-1 resistor R3-1, a 3-2 resistor R3-2 connected to the twelfth transistor T12, and the 14 th transistor M14, and a 3-1 resistor R3- 1) and the 3-2 resistor R3-2 may be connected in series.

The fourth current mode logic circuit 14 includes a sixteenth transistor T16 connected to the fourth input voltage Vip4, a seventeenth transistor M17 connected to the fourth inverted input voltage Vin4, and a sixteenth transistor M16 ) and the 18th transistor (M18) and the 19th transistor (M19) respectively connected to the 18th transistor (M18) in a cascode method, and the 16th transistor (M16) and the 18th transistor (M18) connected to the A 4-1 resistor R4-1, a 17th transistor M17, and a 4-2th resistor R4-2 connected to the 19th transistor M19 may be included, and the 4-1th resistor R4- 1) and the 4-2th resistor R4-2 may be connected in series.

When the PAM16 driving circuit is implemented by connecting the current mode logic circuits in parallel as in FIG. 14 , the operation principle of each of the current mode circuits 11 , 12 , 13 , and 14 operates the same as described in the previous figure. Therefore, there is an advantage of stably driving the PAM16 driving circuit without destroying the device because the voltage applied to the input transistors is small.

So far, the current mode logic circuit 10 and the PAM4 driving circuit 100 including the current mode logic circuit 10 according to an embodiment have been described in detail through the drawings.

In the current mode logic circuit and the PAM4 driving circuit including the same according to an embodiment, the voltage applied to the input transistor is lowered unlike the prior art even when the driving voltage of the circuit is increased, so that the input transistor can be stably driven. The durability of the logic circuit can be increased, and there is an advantage that it can be implemented in a small area without additional power consumption.

Accordingly, there is an effect of reducing the influence of noise and interference by improving the output signal and signal to noise ratio (SNR) of the current mode logic circuit.

The device described above may be implemented as a hardware component, a software component, and/or a combination of the hardware component and the software component. For example, devices and components described in the embodiments may include, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA), It may be implemented using one or more general purpose or special purpose computers, such as a programmable logic unit (PLU), microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. The processing device may also access, store, manipulate, process, and generate data in response to execution of the software. For convenience of understanding, although one processing device is sometimes described as being used, one of ordinary skill in the art will recognize that the processing device includes a plurality of processing elements and/or a plurality of types of processing elements. It can be seen that may include For example, the processing device may include a plurality of processors or one processor and one controller. Other processing configurations are also possible, such as parallel processors.

The software may comprise a computer program, code, instructions, or a combination of one or more thereof, which configures a processing device to operate as desired or is independently or collectively processed You can command the device. The software and/or data may be any kind of machine, component, physical device, virtual equipment, computer storage medium or device, to be interpreted by or to provide instructions or data to the processing device. may be embodied in The software may be distributed over networked computer systems and stored or executed in a distributed manner. Software and data may be stored in one or more computer-readable recording media.

The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, etc. alone or in combination. The program instructions recorded on the medium may be specially designed and configured for the embodiment, or may be known and available to those skilled in the art of computer software. Examples of the computer-readable recording medium include magnetic media such as hard disks, floppy disks and magnetic tapes, optical media such as CD-ROMs and DRs, and magnetic such as floppy disks. - includes magneto-optical media, and hardware devices specially configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. Examples of program instructions include not only machine language codes such as those generated by a compiler, but also high-level language codes that can be executed by a computer using an interpreter or the like.

As described above, although the embodiments have been described with reference to the limited embodiments and drawings, various modifications and variations are possible by those skilled in the art from the above description. For example, the described techniques are performed in a different order than the described method, and/or the described components of the system, structure, apparatus, circuit, etc. are combined or combined in a different form than the described method, or other components Or substituted or substituted by equivalents may achieve an appropriate result. Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

10: current mode logic circuit 11: first current mode logic circuit
12: second current mode logic circuit 13: third current mode logic circuit
14: third current mode logic circuit T1: first transistor
T2: second transistor T3: third transistor
T4: fourth transistor T5: fifth transistor
T6: sixth transistor Ib1: first current source
Ib2: second current source Vin: input voltage
Vip: Inverting input voltage Von: Output voltage
Vop: inverted output voltage Vcasp: cascode input voltage
Vcasn: second cascode inverted input voltage
Vtt: drive voltage

Claims (15)

a first circuit including a first transistor connected to an input voltage and a second transistor connected to an inverted input voltage;
a second circuit including a third transistor connected to the cascode input voltage and a fourth transistor connected to the cascode inversion input voltage; and
and a fifth transistor having one end connected to the first transistor and the third transistor and the other end connected to the second transistor and the fourth transistor. According to claim 1,
The fifth transistor is connected to an external voltage, so that the magnitude of the voltage applied to the gate of the fifth transistor is variable, a current mode logic circuit, According to claim 1,
The direction of the current flowing through the fifth transistor is,
Current mode logic circuit, characterized in that it changes according to ON/OFF of the input voltage and the inverted input voltage, 4. The method of claim 3,
The direction of the current flowing through the fifth transistor is,
A current mode logic circuit, characterized in that when the input voltage is OFF and the inverted input voltage is ON, a direction of a current flows from the third transistor to the fifth transistor. 5. The method of claim 4,
When the input voltage is OFF,
A current mode logic circuit, characterized in that the voltage applied between the drain and the gate of the first transistor is reduced by conducting a current flowing through the third transistor to the fifth transistor. 4. The method of claim 3,
The direction of the current flowing through the fifth transistor is,
The current mode logic circuit, characterized in that when the input voltage is ON and the inverted input voltage is OFF, a direction of a current flows from the fourth transistor to the fifth transistor. 7. The method of claim 6,
When the input voltage is ON,
The current mode logic circuit, characterized in that the voltage applied to the drain and gate of the second transistor is reduced by conducting a current flowing through the fourth circuit to the fifth transistor. a first circuit including a first transistor connected to an input voltage and a second transistor connected to an inverted input voltage; and
A second circuit including; a third transistor connected to the cascode input voltage and a fourth transistor connected to the cascode inversion input voltage;
The first circuit is
and a first slave circuit connected between the first transistor and the third transistor to control the magnitude of the voltage applied to the first transistor,
The second circuit is
and a second slave circuit connected between the second transistor and the fourth transistor to control the magnitude of the voltage applied to the second transistor. 9. The method of claim 8,
The first slave circuit includes a first current source connected to a ground and a ground;
The second slave circuit comprises a second current source connected to a ground and a ground. 10. The method of claim 9,
In the first current source, when the input voltage is OFF, when the inverted input voltage is ON, a current flows, when the input voltage is ON, and when the inverted input voltage is OFF, no current flows;
The second current source, characterized in that the input voltage is ON, the current flows when the inverted input voltage is OFF, the input voltage is OFF, and the current does not flow when the inverted input voltage is ON, mode logic circuit. a first circuit including a first transistor connected to a first input voltage and a third transistor connected to a first cascode input voltage;
a second circuit including a second transistor connected to the first inverted input voltage and a fourth transistor connected to the first cascode inverted input voltage; and
a first current mode logic circuit including a first load having one end connected to the first circuit and the other end connected to the second circuit; and
a third circuit including a sixth transistor connected to a second input voltage and an eighth transistor connected to a second cascode input voltage;
a fourth circuit including a seventh transistor connected to a second inverted input voltage and a ninth transistor connected to a second cascode inverted input voltage; and
and a second current mode logic circuit including a second load having one end connected to the third circuit and the other end connected to the fourth circuit. 12. The method of claim 11
The direction of the current flowing through the first load and the second load is,
PAM 4 driving circuit, characterized in that it changes according to ON/OFF of the input voltages and the inverted input voltages. 12. The method of claim 11
The first load includes the second transistor, the third transistor, and a fifth transistor connected to a first external voltage,
The second load includes the seventh transistor, the eighth transistor, and a tenth transistor connected to a second external voltage. 12. The method of claim 11
The first load includes a first resistor connected to the second transistor and the third transistor,
and the second load includes a second resistor connected to the seventh transistor and the eighth transistor and having a resistance value twice that of the first resistor. 12. The method of claim 11,
The first load,
A 1-1 resistor connected to the first transistor and the third transistor, a 1-2 resistance connected to the second transistor and the fourth transistor, and between the 1-1 resistor and the 1-2 resistor a first capacitor connected to
The second load,
A 2-1 th resistor connected to the sixth and eighth transistors, a 2-2 th resistor connected to the seventh transistor and the ninth transistor, and between the 2-1 th resistor and the 2-2 resistor PAM4 driving circuit, characterized in that it comprises a second capacitor connected to.

Images