KR20220133005A - Artificial Neuromorphic Device and Methode of operating the same - Google Patents

Abstract

Disclosed are an artificial neural network element for transcribing the weight information having a volatile characteristic into the weight information having a non-volatile characteristic, and an operating method of the artificial neural network element. The volatile weight information having a volatile characteristic in a learning part is compared in an inference control part and transcribed as the non-volatile weight information in the information storage part. A program operation is performed in the information storage part for transcribing of the weight information. Therefore, the present invention is capable of having an advantage of being able to update the weight information.

Description

Artificial Neuromorphic Device and Methode of operating the same

The present invention relates to a neural network device, and more particularly, to an artificial neural network device for transferring volatile weight data to non-volatile weight data, and an operating method thereof.

An artificial neural network that mimics the behavior of the human cranial nerves is a key technology for realizing artificial intelligence. The artificial neural network is composed of a neuron that collects and processes electrical signals from multiple paths and a synaptic network that adjusts the size of a signal transmitted between two neurons according to a stored value. A circuit that has devices that simulate and execute these neurons and synapses, respectively, and directly implements neural network operations in hardware through electrical connections between these devices, is called a neuromorphic chip. It is an architecture that is differentiated from machines. The artificial neural network stores the characteristic of the pattern of the data as a characteristic value called a weight in a plurality of synapses that form an arrangement through supervised learning of a large amount of data. An inference operation for determining the characteristics of newly input data is performed by the stored synaptic weights. Therefore, in order to perform an inference work to determine the characteristics of data through the neuromorphic chip, a learning operation must be performed in advance to obtain appropriate synaptic weight values.

In practical applications, the application method of the neuromorphic chip can be divided into two types. First, the learning motion uses artificial neural network S/W such as TensorFlow running on the existing von Neumann computer to obtain synaptic weights, stores them in the synapses of the neuromorphic chip, and executes the inference motion with the neuromorphic chip. way to do it In this case, since the neuromorphic chip only needs to execute the operation of inferring by storing the weight in the synapses, the configuration of the chip is simplified, the conditions required for the synaptic device are relaxed, and the implementation possibility is increased. On the other hand, since on-chip learning is impossible, immediate and individual, that is, in-situ weight update in the field is not possible, which greatly reduces utilization.

Second, the learning operation as well as the inference operation is directly executed from the neuromorphic chip on-chip. In this case, immediate and individual weight learning in the field is possible for each neuromorphic chip, greatly expanding the utility of the chip. While the learning operation is being executed, the synapse weight must be continuously updated with a new value, so the synapse of a neuromorphic chip capable of on-chip learning should be able to repeat writing and erasing without limiting the number of times, and it should be a device with a fast writing and erasing speed. . In addition, since an inference operation must also be performed through the same synaptic arrangement, the learned synaptic weights must be stored for a long time. However, it is not easy to implement a highly reliable synaptic device having these conditions.

Currently, research on using a capacitor as a synaptic device is being attempted as a way to implement a neuromorphic chip capable of on-chip learning. A capacitor is a device that has no limit on the number of writes and erases among semiconductor memory devices commercialized so far, and also has a very fast write and erase speed. The detailed configuration of the capacitor synaptic device and circuit can be implemented in various forms, but in general, the weight is stored as an amount of charge or voltage charged to the capacitor, and the capacitor voltage is output to the neuron in the form of a current of a read transistor. However, since the amount of charge stored in the capacitor is attenuated by the leakage current of the switching element, the learned weight cannot be stored for a long time. Various methods have been tried to solve this problem, and one of them is to maintain a synaptic weight set by continuously and repeatedly performing a learning operation similar to the refresh operation of DRAM.

The content presented in the present specification relates to an on-chip neuromorphic chip employing a capacitor element as the synapse, and is intended to solve the problem of gradually losing the weight stored in the capacitor element due to leakage current.

A first technical object of the present invention is to provide an artificial neural network device capable of transferring weight information having a volatile characteristic into weight information having a non-volatile characteristic.

In addition, a second technical problem to be achieved by the present invention is to provide a method of operating an artificial neural network device for achieving the first technical problem.

The present invention for achieving the above-described first technical problem, a learning unit for acquiring weight information and storing it as a volatile weighted voltage; and an inference unit selectively connected to the learning unit, receiving the weighting current supplied by the learning unit, and storing the weighted current as non-volatile data.

The first technical problem of the present invention is, a learning unit for acquiring weight information and storing it as a volatile weight voltage; a temporary storage unit for storing a temporary storage voltage corresponding to a weighting current generated by the weighting voltage of the learning unit; and an inference unit selectively connected to the temporary storage unit, receiving the weight current supplied by the temporary storage unit, and storing it as non-volatile data.

The present invention for achieving the second technical problem described above includes the steps of performing a current comparison operation with respect to a weighting current corresponding to volatile weighting information; and determining a program operation for a non-volatile memory in which the weight current is transferred into non-volatile weight information based on the current comparison operation.

According to the present invention described above, the volatile weight information obtained in the learning unit is stored as non-volatile weight information in the information storage unit. The transcription of the stored information consists of a comparison operation of weighted currents and a program determination operation using the inference control unit. Through this, a program operation is performed on the information storage unit formed of the non-volatile memory, and the threshold voltage is changed. By changing the threshold voltage, nonvolatile weight information is transferred to the information storage unit.

In the present invention, there is provided a neural network element separated into a learning unit in which a weight is obtained by performing a learning operation and an inference unit capable of storing weight information obtained in the learning unit even when power is removed. The weight information is stored as non-volatile data, and after the transcription or inference operation is completed, the learning unit has the advantage of starting a new learning operation to update the weight information.

1 is a block diagram of an artificial neural network device according to a first embodiment of the present invention.
2 is a circuit diagram for implementing the artificial neural network device of FIG. 1 according to the first embodiment of the present invention.
3 is a timing diagram for explaining the operation of the artificial neural network element of FIG. 2 according to the first embodiment of the present invention.
4 is a block diagram of an artificial neural network device according to a second embodiment of the present invention.
5 is a circuit diagram of an artificial neural network device according to a second embodiment of the present invention.
6 is a timing diagram for explaining the operation of the artificial neural network device according to the second embodiment of the present invention.
7 is a circuit diagram illustrating an artificial neural network device according to a third embodiment of the present invention.

Since the present invention can have various changes and can have various forms, specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention. In describing each figure, like reference numerals have been used for like elements.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related art, and should not be interpreted in an ideal or excessively formal meaning unless explicitly defined in the present application. does not

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

first embodiment

1 is a block diagram of an artificial neural network device according to a first embodiment of the present invention.

Referring to FIG. 1 , the artificial neural network device includes a learning unit 100 and an inference unit 200 .

The learning unit 100 is connected to the learning column line VBL and the learning row line VWL, and stores the obtained weight information in the form of a voltage. However, the learning unit 100 has a dynamic storage characteristic in which the stored weight information disappears with the lapse of time when the learning operation is stopped. Weight information stored in the form of voltage is transmitted to the reasoning unit 200 . The weight information transmitted to the reasoning unit is converted into a current form.

The reasoning unit 200 is connected to the learning unit 100 through the first node N1 , and has an inference control unit 210 and an information storage unit 220 . The reasoning unit 200 may be selectively connected to the learning unit 100 , and the learning unit 100 receives weight information converted in the form of current. The weight information stored in the learning unit 100 is converted into a form of current, and the reasoning unit 200 is stored as weight information having non-volatile characteristics through the comparison operation of the current. That is, the weight information learned and stored in the learning unit 100 has dynamic or volatile characteristics, and the weight information in the inference unit 200 is stored in the form of a threshold voltage of a flash memory cell or a resistance value of a memristor, and the weight is read. can also be converted into current for However, the weight information stored in the reasoning unit 200 has a non-volatile characteristic in which the information is semi-permanently maintained.

The inference control unit 210 constituting the reasoning unit 200 may be selectively connected to the learning unit 100 and the information storage unit 220 , and the information storage unit 220 may also be selectively connected to the learning unit 100 and the reasoning unit 220 . It may be connected to the control unit 210 . It is a known fact that the selective connection of the above-described components can be achieved through various means. For example, a switch or a transistor may be used for selective connection, and selective connection may be implemented through means such as an activation signal and a deactivation signal. However, in the present invention, selective connection of components will be described through a switch. This needs to be interpreted as a means used for convenience of understanding.

The inference control unit 210 supplies a current to the information storage unit 220 according to the magnitude of the current flowing through the learning unit 100 and the information storage unit 220, respectively, or a part of the current supplied from the learning unit 100 get delivered

For convenience of explanation, weight information is reflected, the current flowing from the learning unit 100 is referred to as the weight current iw, the current flowing into the information storage unit 220 is the synaptic current is, and the inference control unit 210 flows through the The current is referred to as the inference control current ia. According to Kirchhoff's law, ia is the difference between iw and is. The inference control unit detects the inference control current ia and transfers the weight current iw to the information storage unit 220 in such a way that the synaptic current is is changed so that the inference control current ia converges to zero.

For example, if the synaptic current is flowing into the information storage unit 220 is greater than the weighting current iw, the inference control current ia flows in the direction from the inference control unit 210 . The reasoning control unit 210 detects the speculation control current ia and adjusts the weight stored in the nonvolatile memory cell of the information storage unit 220 in a direction to reduce the synaptic current is of the information storage unit 220 . That is, when the nonvolatile memory cell is a flash memory cell, the threshold voltage of the cell transistor is increased to decrease the current.

The transfer operation of the weighting current iw is performed until the synaptic current is generated in the information storage unit 220 is equal to the weighting current iw or less than the weighting current iw. The transfer of the weight current iw in the information storage unit 220 is described as a program operation. The program operation should be understood as an operation of changing a channel resistance or a threshold voltage of a nonvolatile memory constituting the information storage unit 220 . That is, the current flowing through the nonvolatile memory decreases by performing the program operation in a situation where the same voltage is applied to the gate terminal.

If the threshold voltage of the memory cell of the information storage unit 220 continues to rise, the synaptic current is sufficiently decreases, and accordingly, the current reasoning control current ia does not flow from the reasoning controller 210 to the node N1. The program operation of the storage unit 220 does not occur, and it is determined that the weight of the learning unit 100 is transferred to the information storage unit 220 so that the weight current iw and the synaptic current is flowing through the information storage unit 220 are equal. , the transfer of weights is complete.

Whether a program operation is performed is determined by the program control signal CSO, which is an output of the inference control unit 210 . The column line to which the information storage unit 220 is connected may include a pair of a column source line SSL of the reasoning unit 200 and a column bit line SBL. The voltage levels of the column source line SSL and the column bit line SBL are adjusted depending on the program control signal CSO. According to an embodiment, the program control signal CSO may be directly connected to the column source line SSL and the column bit line SBL, and a separate control for controlling the voltage levels of the column source line SSL and the column bit line SBL by the program control signal CSO signal Means may be provided.

An inference low line SWL is connected to the information storage unit 220 , and a read voltage Vread or a programming voltage Vpp may be supplied through the inference low line SWL. The synaptic current is flowing through the memory cell of the information storage unit 220 depends on a voltage value applied to the inferred low line SWL. When a predetermined Vread is applied to the information storage unit 220 through the inference low line SWL, the synaptic current is is determined by the threshold voltage of the memory cell and the applied read voltage Vread.

If the synaptic current is generated by the predetermined read voltage Vread applied to the inferred low line SWL of the information storage unit 220 is greater than the weight current iw supplied from the learning unit 100, inferred to balance the current in the node N1 The speculation control current ia is drawn from the control unit 210 to the node N1. The reasoning controller 210 detects a direction in which the speculation control current ia is drawn and generates a program control signal CSO. In addition, the program control signal CSO controls the voltages of the column bit line SBL and the column source line SSL so that a program operation for increasing the threshold voltage occurs in the information storage unit 220 in a subsequent program operation step. In the program operation step, the program voltage Vpp may be applied to the speculation low line SWL. When a program operation is performed in the information storage unit 220 , the threshold voltage or channel resistance of the information storage unit 220 increases, so that the amount of current generated by the read voltage Vread later decreases.

The above-described operation is performed until the synaptic current is flowing through the information storage unit 220 is equal to or smaller than the weight current iw. That is, under the condition that the synaptic current is is less than the weighting current iw, the reasoning control current ia flows in the direction flowing into the reasoning controller 210 . The reasoning controller 210 detects the direction of the speculation control current ia and outputs a program control signal CSO corresponding to the direction of the speculation control current ia. In a subsequent program operation step, the program control signal CSO controls the voltages of the column bit line SBL and the column source line SSL, and the information storage unit 220 uses the controlled voltages of the column bit line SBL and the column source line SSL as a threshold in the information storage unit 220 . The program phenomenon that raises the voltage does not occur.

In the present invention, the inference control current ia is not a fixed value at a specific level, and when the read voltage Vread is applied from the information storage unit 220 , the synaptic current is generated from the information storage unit 220 and the weighting current iw refers to the difference.

In addition, it is preferable that the maximum value of the synaptic current is generated by the information storage unit 220 by the read voltage Vread is greater than or equal to the maximum value of the weighting current iw supplied by the learning unit 100 .

Through the above-described process, the volatile weight information of the dynamic characteristics stored in the learning unit 100 is stored as non-volatile weight information of the inference unit 200 by matching the weighting current iw and the synaptic current is.

In addition, the weight information stored in the form of capacitor voltage in the learning unit 100 is converted into the form of threshold voltage or channel resistance of the memory cell of the inference unit 200 through the above-described process. The learning unit 100 has a dynamic and volatile memory characteristic such as a capacitor for a repetitive and high-speed learning operation. Also, the information storage unit 220 of the reasoning unit 200 has a characteristic of a non-volatile memory to store weight information of the learning unit 100 . Therefore, the learned weight information may be maintained as a value recorded in the synaptic device regardless of the stored data refresh operation or power condition.

2 is a circuit diagram for implementing the artificial neural network device of FIG. 1 according to the first embodiment of the present invention.

Referring to FIG. 2 , the learning unit 100 includes a weight information forming unit 110 and a weight information controlling unit 120 . The weight information forming unit 110 stores the weighting voltage Vw through learning, and determines the magnitude of the weighting current iw corresponding to the weighting voltage Vw. In addition, the weight information control unit 120 connected between the weight information forming unit 110 and the first node N1 sets the weighting current iw to the first of the learning column line VBL depending on the row selection voltage VL applied through the learning row line VWL. output to node N1.

The weight information forming unit 110 includes a first capacitor CL and a first transistor Q1 , and the weight information control unit has a second transistor Q2 .

The first capacitor CL and the first transistor Q1 are connected to the positive reference voltage VBDD, and the other terminal of the first capacitor CL is connected to the gate terminal of the first transistor Q1. In addition, the second transistor Q2 is connected between the first node N1 and the first transistor Q1, the learning row line VWL is connected to the gate terminal, and the row selection voltage VL is applied.

For convenience of description, the learning operation of the weight will be described as controlling two current sources Iup and Idw using two switches SWup and SWdw. That is, the value of the weight stored in the form of voltage across the first capacitor CL is continuously updated through propagation and reverse propagation of the learning operation, and the switches SWup and SWdw are used. As an example, when it is necessary to increase the weight by Δw as a result of learning, the Vw value may be increased by turning on the SWdw switch for a time proportional to Δw.

The row selection voltage VL may form a weighting current iw flowing through the first node N1 depending on the on/off state of the second transistor Q2. For example, when the row selection voltage VL is at a high level, the second transistor Q2 is turned off, and no current is supplied to the first node N1. Also, when the row selection voltage VL is at a low level, the second transistor Q2 is turned on. In addition, the weighting current iw is generated depending on the weighting voltage Vw, which is the voltage difference between the source and the gate of the first transistor Q1. The generated weight current iw is transferred to the first node N1 through the second transistor Q2.

The reasoning unit 200 may be electrically connected to the learning unit 100 through a switch or the like.

The reasoning control unit 210 constituting the reasoning unit 200 includes a current detector 211 and a comparator 212 . The current detector 211 may use various types of current sense amplifiers, but in this specification, a current integrator type current sensor will be described as an example. In the case of a current integrator, it can be configured with an operational amplifier and a feedback capacitor CA. A comparison reference voltage VB may be applied to the positive input terminals of the current detector 211 and the comparator 212 . When SW2 is turned on, the learning column line VBL voltage is also maintained as the comparison reference voltage VB by feedback of the operational amplifier. The VBL voltage determines the drain voltages of Q1 and Q2 current read transistors of the learning weight cell, and the column bit line SBL corresponds to the drain of the transistor Q3 of the reasoning unit 200 . During the transfer operation of the weighting current iw, the VBL and SBL voltages are maintained as the comparison reference voltage VB by the operational amplifier feedback. A reset switch SWr may be provided in parallel with the feedback capacitor CA for the reset operation of the current detector 211 .

The operation of the current detector 211 in terms of current is interpreted as follows.

If the speculation control current ia flows from the input terminal of the current detector 211 toward the first node N1 , the speculation control current ia must be supplied from the feedback capacitor CA and the third node N3 that is the output terminal of the current 211 . Also, due to the virtual short circuit of the amplifier, the negative input terminal has the same DC voltage value as the comparison reference voltage VB. Accordingly, under the above condition, the third node N3 , which is the output terminal of the current detector 211 , has a voltage higher than the comparison reference voltage VB, and the comparator 212 forms the low-level program control signal CSO.

If the inference control current ia flows from the first node N1 to the input terminal of the current detector 211, the voltage of the third node N3 as a result of current integration has a lower value than the comparison reference voltage VB, and the comparator 212 ) outputs the high level program control signal CSO.

The information storage unit 220 is composed of a non-volatile memory device having dynamic characteristics. Non-volatile memory devices that can be used include ReRAM, MRAM, or flash memory cells. ReRAM has a characteristic that a conductive filament is generated by performing a program operation and a threshold voltage is reduced. In addition, the flash memory is characterized in that electrons are trapped by performing a program operation, and a threshold voltage is increased by the trapped electrons.

In the present embodiment, for convenience of description, it will be described that the information storage unit 220 is configured as an n-type flash memory Q3. However, if the resistance of the channel is changed or the threshold voltage is changed through the program voltage Vpp applied to the speculation low line SWL, which is the gate terminal, and has non-volatile characteristics, any form may be used.

One terminal of the source/drain of the flash memory cell Q3 is connected to the second node N2 of the column bit line SBL, and the other terminal is connected to the column source line SSL. Also, the gate terminal of the flash memory cell Q3 is connected to the speculative row line SWL. A program voltage Vpp or a read voltage Vread may be applied to the reasoning low line SWL, and in the case of a series cell arrangement, a pass voltage Vpass may be applied.

The program voltage Vpp has a voltage level capable of injecting electrons from the channel region into the charge storage layer in the flash memory cell. In addition, the read voltage Vread has a lower value than the program voltage Vpp, and a program operation does not occur due to the application of the read voltage Vread. Also, the read voltage Vread has a specific value, and the amount of current flowing through the flash memory cell Q3 decreases as the program operation proceeds. In addition, when the erase operation is performed on the flash memory Q3 and the electron trap does not occur, the current of the flash memory Q3 according to the read voltage Vread becomes the maximum value imax. In addition, the maximum current imax is preferably set to be greater than the maximum current of the weighting current iw that can be generated by the learning unit 100 .

An example of a circuit operation process for weight transfer will be described with reference to FIG. 2 . First, a current comparison step of comparing and sensing the weight current iw of the learning unit 100 and the synaptic current is flowing through the memory cell of the inference unit 200 is performed. In the current comparison step, when SW2 is connected while SWr is connected and the feedback of the operational amplifier is maintained, the voltage of the learning column line VBL is maintained as the comparison reference voltage VB. SW1 is connected so that the learning column line VBL and the column bit line SSL line are connected. When Q2 is turned on by the learning low line VWL, a weighting current iw proportional to the learning weight flows into the first node N1. In addition, the read voltage Vread is applied to the inference low line SWL connected to Q3, and the synaptic current is current flows from the first node N1 to Q3. Accordingly, in order to balance the current in the first node N1 , the reasoning control current ia, which is a current corresponding to the difference between is and iw, starts to flow from the reasoning controller 210 to the first node N1. After that, SWr is opened, and from this point on, the speculation control current ia current flows through the capacitor CA, not through SWr, and the amount of charge obtained by integrating the speculation control current ia is accumulated in the capacitor CA. In the circuit operation for weight transfer, the connection of the switches and the voltage application order of the row lines may be various examples other than the above description.

Also, in FIG. 2, it is described that the first switch SW1 connects the common connection point X and the second node N2, and the second switch SW2 connects the common connection point X and the inference control unit 210 input node N4. The common connection point X may be connected to any two of the first node N1, the second node N2, and the inference control unit 210 input node N4, respectively.

In the operation of the current comparison step, a bias voltage higher than the comparison reference voltage VB may be applied to VBDD of the learning unit 100, and an appropriate bias voltage lower than the comparison reference voltage VB may be applied to the column source line SSL. The bias applied to the column source line SSL line may be a negative power supply voltage VSS (in the present invention, a negative reference voltage should be understood to refer to a power supply voltage having a lower value than the positive reference voltage VDD or the like). During the circuit operation of the current comparison step, the PMOS transistor Q1 of the learning unit 100 may be in a linear region or a saturation region, and the flash cell Q3 of the inference unit 200 may also be in a linear region or a saturation region.

In a state in which the switch SWr is connected, the voltages of the third node N3 and the fourth node N4 become VB by the virtual short feedback. After SWr is open, if the synaptic current is flowing through the flash memory cell Q3 has a value greater than the weight current iw of the learning unit 100, in order to satisfy the Kirchhoff current law at the common connection point X, The inference control current ia flows from the third node N3 through CA to the common connection point X through the fourth node N4. The speculation control current ia flowing for a predetermined time is accumulated as the charge amount of the capacitor CA, and the voltage of the third node N3 increases in proportion to the charge amount of the capacitor CA to become higher than the initial value VB.

When the appropriate time for accumulating the inference control current ia has elapsed, the comparator 212 is activated by the Ecomp signal, and the comparison reference voltage VB is compared with the voltage of the third node N3, which is the output of the current detector 211, and the result is obtained. It is output as the program control signal CSO. As in the above-described case, when the output of the current detector 211 is higher than the comparison reference voltage VB, the program control signal CSO outputs the voltage value VSS.

Following the current comparison step in which the inference control unit 210 compares and detects the weight current iw of the learning unit 100 and the memory cell current is of the inference unit 200 , the threshold of the memory cell is based on the result of comparing the two currents. A program step for adjusting the voltage is executed. When the synaptic current is is greater than the weight current iw, the program control signal CSO outputs VSS (negative power supply voltage) as described above. The column source line SSL and the column bit line SBL are connected to the program control signal CSO through a switch (not shown), or are controlled by the program control signal CSO such that the VSS voltage is applied. During this phase, SW1 remains open.

In the programming step, the program voltage Vpp is applied to the speculation low line SWL. When the SSL/SBL voltage corresponding to the source/drain of the flash memory cell Q3 is VSS and the SWL voltage corresponding to the gate is Vpp, in the Q3 cell, channel electrons are tunneled to the charge storage layer by the high gate-source voltage. The injected program phenomenon occurs. As electrons are injected into the charge storage layer, the threshold voltage of the memory cell Q3 increases. Since the threshold voltage of the memory cell subjected to the program operation is higher than before the execution of the program, the magnitude of the synaptic current is flowing while the Vread voltage is applied is reduced compared to before the execution of the program. As the number of executions of the program operation increases, the magnitude of the synaptic current is continuously decreases.

When the synaptic current is flowing through the flash memory cell Q3 in the current comparison step has a value smaller than the weight current iw of the learning unit 100, the inference control current ia flows from the common connection point X to the fourth node N4 and flows through the capacitor CA flows to the third node N3. The speculation control current ia flowing for a predetermined time is accumulated as the amount of charge of the capacitor CA, and the voltage of the third node N3 falls in proportion to the amount of charge of the capacitor CA to be lower than the comparison reference voltage VB, which is an initial value. When an appropriate time for accumulating the inference control current ia elapses, the comparator 212 is activated by the Ecomp signal, compares the comparison reference voltage VB with the voltage of the third node N3, and outputs the result as the program control signal CSO.

As in the above-described case, when the voltage of the third node N3 that is the output of the current detector 211 is lower than the comparison reference voltage VB, the program control signal CSO outputs a VDD (positive power supply voltage) voltage value. Following the current comparison step, a program step is executed. When the synaptic current is is less than the weight current iw, the program control signal CSO outputs VDD as described above, and the column source line SSL and the column bit line SBL are connected to the program control signal CSO through a switch (not shown). connected or controlled by the program control signal CSO so that the VDD voltage is applied. During this phase, SW1 remains open.

In the programming step, the program voltage Vpp is applied to the speculation low line SWL. When VDD is applied to the SSL/SBL corresponding to the source/drain of the flash memory cell Q3, even if a high programming voltage Vpp is applied to the gate, the gate-source voltage is significantly lowered in the Q3 cell, so that the tunneling phenomenon is sufficiently suppressed to prevent the programming phenomenon. doesn't happen Therefore, there is no change in the threshold voltage of the Q3 cell even after the programming step.

3 is a timing diagram for explaining the operation of the artificial neural network element of FIG. 2 according to the first embodiment of the present invention.

The artificial neural network element shown in FIG. 2 may have three operating states: a learning mode, a weighted transcription mode, and an inference mode.

The learning mode is an operation state in which the neural network composed of the arrangement of the learning unit 100 obtains an optimized weight arrangement stored in the capacitor CL through propagation and backpropagation operations. In the operation of the above mode, weights are continuously updated by learning. The weight update operation is performed while the capacitor CL is charged or discharged in an amount proportional to the pulse time period to which the switch SWup or SWdw is connected. Accordingly, the sign of the weight change amount Δw of the learning unit 100 that is updated by selecting one of the switches may be determined, and the magnitude of the Δw may be adjusted by the length of the pulse time period to which the switch is connected. During the learning mode operation, SW1 is opened and the reasoning unit 200 is separated from the learning unit 100 . However, depending on the system design, since the inference control unit 210 can also be used as a current sensor of the learning unit 100, SW2 may be connected during the learning mode.

In the weight transfer mode, an operation of duplicating the synaptic weight obtained by the learning unit 100 to the information storage unit 220 which is a non-volatile synaptic cell of the inference unit 200 is executed.

The weight transfer operation mode is a current comparison step of comparing the weight current iw of the learning unit 100 and the synaptic current is of the information storage unit 220 corresponding to the synaptic memory cell of the inference unit 200, the current comparison result It is divided into program steps for adjusting the current level of the information storage unit 220 based on the background. In the weight transfer operation mode, the current comparison step and the programming step are alternately repeated to bring the synaptic current is as close to the weight current iw as possible.

The reasoning mode is a state in which the neural network calculation operation is performed by the reasoning unit using the weight transferred to the nonvolatile memory cell. In the reasoning mode, the learning unit 100 and the reasoning unit 200 are electrically separated.

Referring to FIG. 3 , in the weight transfer mode, the current comparison sensing step and the program step are repeated in an operation unit.

The waveforms in FIG. 3 are applied in conjunction with the system clock. It is obvious to those skilled in the art that the waveforms for driving the artificial neural network element are applied in conjunction with the system clock, so a detailed description thereof will be omitted.

2 and 3 , during the learning mode operation, the first switch SW1 is turned off, so that the learning unit 100 and the information storage unit 220 corresponding to the inference unit synapse arrangement are electrically separated. The unit synapse of the learning unit 100 outputs the accumulated current amount corresponding to the product of the weight stored as the CL voltage and the input value corresponding to the width of the learning row line VWL pulse to the learning column line VBL line.

In the learning column line VBL, the output currents of synapses connected to each row are summed, and a multiply-and-accumulation operation corresponding to the basic propagation operation in the neural network is executed. In addition, the learning unit 100 also executes a backpropagation operation necessary for a learning operation through an additional auxiliary circuit connection.

Through the propagation and backpropagation operations, the weight of the learning unit 100 is determined as the update amount Δw. The weight update amount Δw determines the sign of the weight change amount Δw of the learning unit 100 that is updated by selecting one of the switches SWup and SWdw, and the magnitude of the Δw can be adjusted by the length of the pulse time period to which the switch is connected. . In order to perform propagation, backpropagation, and weight update of the learning unit 100, an appropriate arrangement and peripheral circuit configuration not shown in FIG. 2 are required.

However, as long as the synaptic weight of the learning unit 100 is stored as a capacitor voltage and output as a current value, the content presented in this specification is not limited to the specific configuration of the arrangement and peripheral circuits.

Referring to the timing diagram of FIG. 3 , the learning mode is stopped and the weight transfer mode is started. The weight transfer mode first starts with a current comparison step. In the current comparison step, the learning column line VBL and the column bit line SBL are connected by SW1.

As the low-level voltage that turns on Q2 to the training row line VWL and the voltage Vread are applied to the inference low line SWL, respectively, a weighting current iw flows into the training column line VBL, and the inference unit synaptic cell current is is from the column bit line SBL. flows to the information storage unit 220 . According to the magnitude of the two currents, the inference control current ia corresponding to the difference flows into or out of the inference control unit 210 .

The reasoning control current ia is accumulated as an amount of charge of the capacitor CA, and the voltage of the third node N3 deviates from the comparison reference voltage VB depending on the amount of charge of the capacitor CA. That is, the voltage of the third node N3 has a value higher or lower than the comparison reference voltage VB depending on the direction of the inference control current ia by the integration operation of the current detector 211 .

When the synaptic current is is greater than the weighting current iw, the voltage of the third node N3 has a voltage higher than the comparison reference voltage VB, and when the synaptic current is is smaller than the weighting current iw, the voltage of the third node N3 is It has a lower value than the comparison reference voltage VB. When the inference control current ia is sufficiently accumulated in the capacitor CA, the comparator 212 is activated, and the result of comparing the voltage of the third node N3 with the comparison reference voltage VB is converted to VDD or VSS through the program control signal CSO. is output

Referring to the timing diagram of FIG. 3 , the current comparison phase ends and the program phase begins.

In the program stage, SW1 is opened to electrically separate the reasoning unit 200 from the learning unit 100, and the voltages of the column lines SSL and SBL are connected to the program control signal CSO as a switch or controlled by the program control signal CSO. . A program voltage Vpp that may cause tunneling to Q3 is applied to the speculative low line SWL. However, as described above, whether or not a program phenomenon occurs in the corresponding Q3 cell is determined by the column source line SSL and column bit line SBL voltages controlled by the program control signal CSO voltage.

In this way, the current comparison step and the program step are paired and executed as a bundle operation (program package). The program package operation is repeated a sufficient number of times until the initial synaptic current is gradually decreases and initially becomes lower than the weight current iw. When the synaptic current is is less than the weight current iw, the magnitude of the synaptic current is no longer decreased by the program package operation.

When the amount of change (program step) of the synaptic current is due to the unit program package operation is sufficiently reduced, the magnitudes of the two currents are sufficiently close when the current is is lower than the weight current iw for the first time. Under the above conditions, it is determined that the weight transfer has been made from the learning unit 100 to the information storage unit 220 of the inference unit 200 .

Although only one synapse row and column is illustrated in FIG. 2 , the learning unit 100 and the inference unit 200 both have a plurality of synaptic rows and columns to form a synapse arrangement. Preferably, the program package operation is simultaneously executed in all or a plurality of columns in units of individual rows, and when weight transfer is performed in cells of all rows constituting the arrangement of the reasoning unit 200, the learning unit 100 sends the inference unit ( 200) is complete.

second embodiment

4 is a block diagram of an artificial neural network device according to a second embodiment of the present invention.

Referring to FIG. 4 , the artificial neural network device includes a learning unit 300 , a temporary storage unit 400 , and an inference unit 500 .

The learning unit 300 is connected to the first node N1 of the learning column line VBL, and receives the row selection voltage VL through the learning row line VWL. In addition, the learning unit 300 stores the obtained weight information in the form of voltage. However, the weight information stored in the learning unit 300 has a dynamic storage characteristic.

Also in the second embodiment, the weight transfer operation is an operation of transferring the synaptic weight of the learning unit 300 to the synaptic weight of the inference unit 500 . When the current output by the synaptic cell of the learning unit 300 to the learning column line VBL and the current output by the synaptic cell of the inference unit 500 to the column bit line SBL are equal, the synaptic weight of the learning unit 300 is determined by the inference unit (500) It is determined that the synapse is transcribed. In the second embodiment, the weight transfer operation is performed in two steps. The second step is a temporary storage step of first copying the synaptic weight of the learning unit 300 to the temporary storage unit 400 , and then applying the weight copied to the temporary storage unit 400 to the non-volatile synaptic cell of the inference unit 500 . The transfer consists of a weight transfer step.

The temporary storage unit 400 is a memory device capable of rapidly executing a write operation of analog data having a continuous value, and may be a capacitor for storing data in the same amount of charge as the synaptic cell of the learning unit 300 . Since the weight is stored as a capacitor element, it may have a dynamic storage characteristic due to charge loss over time like the synaptic cell of the learning unit 300 , but a larger capacitance value than the synaptic cell of the learning unit 300 . By having it, it is possible to store data for a longer time than the synaptic cell of the learning unit 300 .

When the learning row line VWL is activated in the temporary storage step, the first weight current iw of the synaptic cell of the learning unit 300 flows in from the learning column line VBL, and the synaptic current is and the inference control current ia are controlled to be 0. , the capacitor voltage of the temporary storage unit 400 is automatically adjusted so that the second weighting current ic output from the temporary storage unit 400 is equal to the first weighting current iw.

When the second weighting current ic and the first weighting current iw reach the same state, a switch of the temporary storage unit 400 is opened to fix the capacitor voltage value. The fixed capacitor voltage corresponds to the weight copied to the temporary storage unit 400 .

In the weight transfer step, the magnitude of the two currents is compared and sensed so that the synaptic current is of the reasoning unit 500 becomes equal to the second weighted current ic of the temporary storage unit 400, and the memory cell of the information storage unit 520 is stored. This is the programming step.

That is, in the first embodiment, the magnitude of the two currents is compared and detected so that the synaptic current is of the inference unit 200 is equal to the first weight current iw of the learning unit 100 , and the information storage unit of the inference unit 200 . It is the same process as the operation of programming 220 , except that the learning unit 100 is replaced with the temporary storage unit 400 . In more detail, as in the first embodiment, the weight transfer step includes a current comparison step of comparing the synaptic current is and the second weight current ic and a program step of adjusting the threshold voltage of the synaptic memory cell of the information storage unit 520 . is composed

In the weight transfer step, the learning unit 300 is electrically separated from the reasoning unit 500 , and the temporary storage unit 400 , the reasoning control unit 510 , and the information storage unit 520 are activated to operate.

When the weights are copied to the temporary storage unit 400 , the learning unit 300 is electrically separated to perform a separate independent learning operation during the weight transfer operation.

While the learning unit 300 and the information storage unit 520 form a neural network array having a plurality of rows and columns, the temporary storage unit 400 has one weight storage cell for each column, and thus only one row is configured as a whole. do.

The temporary storage step and the weight transfer step are performed as a bundle for each row of the neural network array. In the learning unit 300 , synaptic weights constituting one row of the neural network are stored in the temporary storage unit 400 , and the stored weights in the temporary storage unit 400 are transferred to synaptic cells constituting a row of the corresponding reasoning unit 500 . do. After the transfer operation on the learning unit 300 connected to the row line is completed, the transfer operation on the next row line may be performed. However, the cell weight connected to the row line in the learning unit 300 is transferred as the cell weight in the information storage unit 520 of the corresponding row line, but the temporary storage unit 400 used in the transfer operation process stores all the row lines. can share When the transcription operation is completed for all row lines, all synaptic weights of the learning unit 300 are transferred to the information storage unit 520 of the inference unit 500 .

5 is a circuit diagram of an artificial neural network device according to a second embodiment of the present invention.

Referring to FIG. 5 , the learning unit 300 includes a weight information forming unit 310 and a weighting information control unit 320 .

The weight information forming unit 310 stores the weight voltage Vw through learning and generates a first weight current iw corresponding to the weight voltage Vw.

In addition, the weight information control unit 320 connected between the weight information forming unit 310 and the first node N1 of the learning column line VBL generates a first weighting current iw depending on the row selection voltage VL applied through the learning row line VWL. It flows in from the first node N1 of the learning column line VBL.

The weight information forming unit 310 includes a first capacitor CL and a second transistor Q2 , and the weight information control unit 320 includes a first transistor Q1 . The first transistor Q1 is connected to the first node N1, and the transfer control voltage row selection voltage VL is applied to the gate terminal. Also, the second transistor Q2 is connected between the first transistor Q1 and the VBSS terminal. A first capacitor CL is connected between the gate terminal of the second transistor Q2 and the VBSS terminal.

For convenience of description, the learning operation of the weight will be described as controlling two current sources Iup and Idw using two switches SWup and SWdw. The weight through the learning operation is stored in the form of a weight voltage Vw across the first capacitor CL.

The temporary storage unit 400 is connected between the positive power voltage VBDD and the second node N2 , and is selectively connected to the learning unit 300 through the first switch SW1 . The temporary storage unit 400 includes a third transistor Q3 and a second capacitor CT. The third transistor Q3 is connected between the positive power supply voltage VBDD and the second node N2, and the gate terminal is connected to the other terminal of the second capacitor CT. One terminal of the second capacitor CT is connected to the positive power supply voltage VBDD. Also, a second switch SW2 is disposed between the gate terminal and the drain terminal of the third transistor Q3.

The temporary storage operation of the weight information stored in the learning unit 300 is started when the transfer control voltage low selection voltage VL is at a high level, the first switch SW1 is turned on, and the second switch SW2 is turned on. Also, the third switch SW3 and the fourth switch SW4 are turned off to perform the temporary storage operation. The first weighting current iw corresponding to the weighting voltage Vw stored in the first capacitor CL flows along a path formed by the third transistor Q3, the second node N2, the first node N1, the first transistor Q1, and the second transistor Q2. The voltage of the second node N2 connected to the first node N1 is adjusted until the first weight current iw flowing through Q2 and the second weight current ic of the temporary storage unit 400 flowing through Q3 become the same, and the second weight When the current ic reaches the same magnitude as the first weight current iw, the voltages of the N1 and N2 nodes and the Q3 gate terminals, which are the same voltages, are kept constant. Thereafter, by opening SW2, the voltage Vtmp outputting the second weighting current ic equal to the first weighting current iw is stored in the capacitor CT. This completes the operation of the temporary storage step. When the temporary storage operation is completed, SW1 is opened to electrically disconnect the learning unit 300 .

The weight transfer step executed following the temporary storage step includes the current comparison step described above in the first embodiment so that the synaptic current is of the information storage unit 520 has the same magnitude as the second weight current ic of the temporary storage unit 400 . The program package operation of the program stage is repeatedly performed.

That is, in the current comparison step, VSS is applied to the column source line SSL and Vread voltage is applied to the inferred row line SWL, so that a synaptic current is flows from the column bit line SBL to the Q4 cell. A current corresponding to the difference between the second weighted current ic and the synaptic current is is accumulated in the current detector 511 and Ecmp is activated at an appropriate time to control the program according to the comparison result between the synaptic current is and the second weighted current ic A VDD or VSS voltage is output through the signal CSO.

When the synaptic current is is larger than the second weighting current ic, VSS is output to the program control signal CSO, and in the subsequent program step, the program control signal CSO signal is directly connected or used as a control signal to form a column source line SSL and a column A voltage VSS is applied to the bit line SBL. In the programming phase, when the high voltage Vpp is applied to the inferred row line SWL and the VSS voltage is applied to the column source line SSL and the column bit line SBL, a programming phenomenon due to tunneling occurs to increase the threshold voltage of the synaptic cell.

As described above in the first embodiment, the above-described program package operation is repeated so that the synaptic current is is lower than the second weight current ic. When the synaptic current is less than the second weighting current ic, the program control signal CSO output becomes VDD, and the column source line SSL and the column bit line SBL are controlled to be VDD. The phenomenon is suppressed and the threshold voltage of the cell is maintained as it is.

When the weights of the learning unit 300 for all the row lines are stored in the information storage unit 520 through the temporary storage unit 400, it is determined that the weight transfer mode of the second embodiment is completed.

In the second embodiment, since the capacitor CT has a larger capacitance value than that of the capacitor CL, the area required for the unit element is increased. However, since the capacitor CL of the temporary storage unit 400 is arranged at each intersection of a plurality of row lines and column lines, while only one capacitor CT exists in one column line, even if it has a large capacity as a unit device, the overall The required area burden is reduced.

6 is a timing diagram for explaining the operation of the artificial neural network device according to the second embodiment of the present invention.

Referring to FIG. 6 , the artificial neural network device of this embodiment consists of a weight temporary storage step and a weight transfer step, and the weight transfer step includes a current comparison step and a programming step in detail.

5 and 6 , a high level voltage is applied to the learning low line VWL selected in the temporary storage step, and the first switch SW1 and the second switch SW2 are connected. Further, the third switch SW3 and the fourth switch SW4 are turned off.

Under the above condition, the first transistor Q1 is turned on, and a first weighting current iw corresponding to the weighting voltage Vw stored in the first capacitor CL is generated. The learning column line VBL line has no bias intentionally applied from the outside, and the initial voltage may be any value, but for convenience of description, it is assumed that the VBDD voltage is initialized. It is assumed that the gate voltage of Q3 connected to the N2 node by the connected second switch SW2 is also initialized to VBDD.

In the above condition, since the voltage between the source and gate of Q3 is 0, Q3 is turned off, so the net current of the learning column line VBL line is the first weighting current iw flowing from the first node N1 to the weight information control unit 320 . . As a current flows from the learning column line VBL line to the learning unit 300 , the learning column line VBL line voltage decreases, and the gate voltage of Q3 connected to the learning column line VBL also decreases accordingly. As the gate voltage of transistor Q3 falls, the Vtmp voltage increases and thus the second weight current ic also increases. The transition continues until the magnitude of the second weighting current ic becomes equal to the first weighting current iw and the net current of the learning column line VBL becomes zero.

After a sufficient time elapses, Vtmp at which the magnitude of the second weighting current ic becomes equal to the first weighting current iw is stored in the capacitor CT, and the SW2 switch is opened so that the weight of the learning unit 300 is transferred to the temporary storage unit 400 ), the operation of being copied to the capacitor CT is completed. After SW1 is opened, the learning unit 300 is electrically separated.

After the temporary storage phase is completed, the weight transfer phase begins. The weight transfer step is more specifically composed of a current comparison step and a programming step, wherein switches SW3 and SW4 are connected in the current comparison step. The voltage Vread is applied to the reasoning row line SWL, which is the row line of the synaptic cell of the reasoning unit 500, to draw the synaptic current is from the column bit line SBL.

Initially, the switch SWr is connected and virtually shorts the learning column line VBL voltage to the comparison reference voltage VB through the feedback of the operational amplifier. The connected switch SWr opens and the current comparison operation starts. The speculation control current ia corresponding to the difference between the second weight current ic flowing into the column bit line SBL and the synaptic current is flowing from the column bit line SBL flows into or flows out into the speculation control unit 510 . The reasoning control current ia accumulated in the capacitor CA for a certain time increases or decreases the voltage of the fourth node N4 than the comparison reference voltage VB depending on the direction.

When a time sufficient for current accumulation has elapsed, the comparator 512 is activated through the Ecmp signal to generate a program control signal CSO output, and the current comparison operation is completed. When the synaptic current is is larger than the second weighting current ic, VSS is output to the program control signal CSO, and in the opposite case, VDD is outputted.

In the subsequent programming step, a voltage of VSS or VDD is applied to or connected to the program control signal CSO to the column source line SSL and the column bit line SBL, and a high voltage Vpp is applied to the selected inference row line SWL line.

When the synaptic current is greater than the second weight current ic as a result of the current comparison step, VSS is applied to the column source line SSL and the column bit line SBL, and when the inferred row line SWL voltage corresponding to the gate is Vpp, cell Q4 In this case, a programming phenomenon occurs in which channel electrons are injected into the charge storage layer by tunneling due to a high gate-source voltage. As electrons are injected into the charge storage layer, the threshold voltage of the memory cell Q4 increases. Since the threshold voltage of the memory cell subjected to the program operation is higher than before the execution of the program, the magnitude of the synaptic current is flowing while the Vread voltage is applied is reduced compared to before the execution of the program. As the number of executions of the program operation increases, the magnitude of the synaptic current is continuously decreases.

When the current comparison step and the programming step are repeated and the synaptic current is gradually decreased to be less than the second weight current ic, the program control signal CSO outputs the VDD voltage as a result of the current comparison operation, and in the subsequent programming step, the column A voltage VDD is applied to the source line SSL and the column bit line SBL. In the above condition, even if Vpp is applied to the inferred low line SWL line, the gate-source voltage of the Q4 cell is significantly reduced, so that tunneling is suppressed in the Q4 cell, and thus the threshold voltage is maintained without increasing, and thus the synaptic current is also not decreased. is maintained without

As described above, by repeatedly performing the bundling operation of the current comparison and programming steps a plurality of times, the synaptic current is of Q4 may be adjusted to have a value sufficiently close to the second weight current ic.

third embodiment

7 is a circuit diagram illustrating an artificial neural network device according to a third embodiment of the present invention.

Referring to FIG. 7 , except that the information storage unit 620 is formed of string-type flash memories QF1, QF2, QF3, and QF4, other configurations are the same as those of the first and second embodiments. However, in FIG. 7 , weight information obtained in time series by one learner may be sequentially stored in string-type flash memories QF1, QF2, QF3, and QF4.

In order to explain the operation of FIG. 7 , the first mode and the second mode subsequent thereto are exemplified. Weight information obtained by the learning unit in each mode is stored in the information storage unit 620 .

First, in the first mode, a weighting current iw1 is supplied from the learning unit. The weight current iw1 is stored in the form of a threshold voltage of the flash memory selected by the information storage unit 620 . For example, when the third flash memory QF3 is selected, the passing voltage Vpass is applied to the speculation row lines SWL1, SWL2, and SWL4 that are gate terminals of the unselected flash memories, and the read voltage Vread is applied to the speculation row line SWL3 of the selected flash memory. do. The passing voltage Vpass is a value between the read voltage Vread and the program voltage Vpp, and through the application of the passing voltage Vpass, the corresponding flash memory acts only as a switch.

Accordingly, the weight current comparison operation and the program determination operation are performed through the third flash memory QF3 selected in the first mode. Through this, the weighting current iw1 is transferred in the first mode. When the transfer is completed, the second mode proceeds.

In the second mode, the above-described learning unit learns new weight information, and supplies it to the information storage unit 620 as a new weight current. At this time, other flash memories are selected from among the plurality of flash memories QF1, QF2, QF3, and QF4 except for the third flash memory QF3 in which the weight is stored in the first mode. The selection operation of the flash memory is an operation of applying the read voltage Vread to the speculation row line SWL of the selected flash memory. At this time, the passing voltage Vpass is applied to the gate terminals of the remaining flash memories that are not selected.

Through the above-described operation, the plurality of flash memories QF1, QF2, QF3, and QF4 constituting the string may each constitute an individual reasoning unit synapse row. That is, a plurality of synaptic rows may be implemented in one string in which cells are serially connected, thereby reducing the chip area.

In the present invention, the volatile weight information obtained by the learning unit is stored as non-volatile weight information in the information storage unit. The transcription of the stored information consists of a comparison operation of weighted currents and a program determination operation using the inference control unit. Through this, a program operation is performed on the information storage unit formed of the non-volatile memory, and the threshold voltage is changed. By changing the threshold voltage, nonvolatile weight information is transferred to the information storage unit.

In the present invention, there is provided a neural network element separated into a learning unit in which a weight is obtained by performing a learning operation and an inference unit capable of storing weight information obtained in the learning unit even when power is removed. The weight information is stored as non-volatile data, and after the transcription or inference operation is completed, the learning unit has the advantage of starting a new learning operation to update the weight information.

100, 300: learning unit 200, 500: reasoning unit
210, 510: inference control unit 220, 520: information storage unit
400: temporary storage

Claims (22)

a learning unit that acquires weight information through learning; and
and an inference unit selectively connected to the learning unit and configured to receive and store the weight information obtained by the learning unit. According to claim 1,
the learning unit
storing the weight information as a capacitor voltage of dynamic characteristics;
The reasoning part
The artificial neural network device, characterized in that the weight is stored in a non-volatile memory device. 3. The method of claim 2,
An artificial neural network device, characterized in that the weight of the reasoning unit is adjusted so that the weighted current output by the learning unit and the synaptic current output by the corresponding inference unit are the same. According to claim 1, wherein the learning unit
a weight information forming unit for storing the capacitor voltage through learning; and
a weight information control unit connected between the weight information forming unit and the learning column line, forming a weight current depending on a control voltage applied through the learning row line, and transmitting the weight current to the learning column line; Characterized by an artificial neural network device. The method of claim 1, wherein the inference unit
an inference control unit selectively connected to the learning unit, performing a current comparison operation with respect to the weighted current, and performing a program determination operation; and
an information storage unit selectively connected to the reasoning control unit, the threshold voltage is changed by a program operation, and forming a synaptic current according to the read voltage applied through the speculation row line;
The inference control unit compares the current according to the read voltage with the weighted current and outputs a program control signal. The artificial neural network device according to claim 5, wherein when the reasoning control current flows into the information storage unit, the information storage unit performs a program operation according to the program control signal. The artificial neural network device of claim 6 , wherein the programming operation is repeated until a point in time when magnitudes of the current according to the weight current and the read voltage are inverted. The method of claim 5, wherein the inference control unit
a current sensor selectively connected to the learning unit or the information storage unit; and
An artificial neural network device connected to the current sensor and comprising a comparator for outputting the program control signal. The artificial neural network device according to claim 5, wherein the information storage unit comprises a flash memory cell. The artificial neural network device according to claim 5, wherein the information storage unit has a plurality of flash memory cells connected in a string form. a learning unit that acquires weight information and stores it as a volatile weighted voltage;
a temporary storage unit for storing a temporary storage voltage corresponding to a weighting current generated by the weighting voltage of the learning unit; and
and an inference unit selectively connected to the temporary storage unit, receiving the weight current supplied by the temporary storage unit, and storing the weighted current as non-volatile data. The method of claim 11, wherein the learning unit
a weight information forming unit for storing the weighted voltage through learning; and
and a weight information controller connected between the weight information forming unit and the learning column line and configured to form a weighting current depending on a control voltage applied through the learning row line. The artificial neural network device according to claim 12, wherein a capacitance for storing the temporary storage voltage in the temporary storage unit is greater than a capacitance for storing the weight voltage in the learning unit. The method of claim 11, wherein the inference unit
an inference control unit selectively connected to the temporary storage unit, performing a current comparison operation with respect to the weighted current, and performing a program determination operation; and
an information storage unit selectively connected to the reasoning control unit, the threshold voltage is changed by a program operation, and forming a synaptic current according to the read voltage applied through the speculation row line;
The inference controller compares the synaptic current according to the read voltage with the weighted current and outputs a program control signal. 15. The artificial neural network device of claim 14, wherein the information storage unit comprises a flash memory. 15. The artificial neural network device of claim 14, wherein the information storage unit comprises a plurality of flash memory cells connected in series to form a string. performing a current comparison operation with respect to a weighting current corresponding to the volatile weighting information; and
and determining, based on the current comparison operation, a program operation for a non-volatile memory in which the weight current is transcribed into non-volatile weight information. The artificial neural network device of claim 17, wherein the current comparison operation compares the synaptic current of the non-volatile memory with respect to the weight current and the read voltage, and an inference control current is generated according to the current comparison result. how it works. 19. The method of claim 18, wherein when the weight current is smaller than the synaptic current as a result of the current comparison, a program operation on the non-volatile memory is performed. The method of claim 18 , wherein, as a result of comparing the currents, when the magnitudes of the weight current and the synaptic current are inverted by a program operation, the program operation on the non-volatile memory is stopped. 21. The method of claim 20, wherein it is determined that the transfer of the weight current is completed in the non-volatile memory by stopping the program operation. 18. The method of claim 17, wherein prior to the current comparison operation,
and temporarily storing the weighting information as weighting information having different volatility by using a weighting current corresponding to the volatile weighting information.

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