KR20220131715A - Quantum-dot cellular automata vedic multiplier using cell interaction - Google Patents

Abstract

The present invention relates to a QCA Vedic multiplier. For 2-bit binary numbers A and B, a QCA Vedic multiplier according to the present invention includes: a first combinational logic cell that inputs A0, which is the least significant bit (LSB) of A, and B0, which is the least significant bit (LSB) of B, and outputs the 0^th bit value, which is the least significant bit of the final result value, by performing an AND gate function; a second combinational logic cell that performs an AND gate function when A1 and B0, which are the most significant bits (MSB) of A, are input; a third combinational logic cell that performs an AND gate function when B1, which is the most significant bit of A0 and B, is input; a fourth combinational logic cell to which A1 and B1 are input and to perform an AND gate function; a fifth combinational logic cell in which the output signal of the second combinational logic cell and the output signal of the third combinational logic cell are input, wherein the fifth combinational logic cell performs a half-adder function to output the first bit value of the final result value as the first carry and sum value; and a sixth combinational logic cell in which the output signal of the fourth combinational logic cell and the first carry are input, and the half-adder function is performed to output the second bit value of the final result value as the sum value and the third bit value of the final result value as the carry signal. According to the present invention, it is possible to provide a QCA multiplier having a structure capable of fast arithmetic processing by reducing the complexity of time and space using the Vedic mathematical algorithm.

Description

Quantum-dot cellular automata vedic multiplier using cell interaction

The present invention relates to a half adder using a QCA XOR gate based on cell interaction and a Quantum-dot Cellular Automata (QCA) multiplier based on a Vedic mathematical algorithm.

The present invention is derived from the research results conducted with the support of the National Research Foundation with the funding of the government (Ministry of Science and Technology Information and Communication) (task number: 2021R1A2C1013122).

Quantum-dot Cellular Automata (QCA), replacing complementary metal oxide semiconductor (CMOS) technology, is being considered as the future nanotechnology for high-performance integrated circuits. QCA has the potential advantage of implementing nanoscale circuits with high-speed operation, making it more attractive due to its low-power consumption capabilities. The performance of a QCA device is determined not only by the magnitude of the current or the associated voltage, but also by the composition of the charge according to the arrangement of the constituent cells.

According to the QCA physical fabrication method, four implementation types have been proposed: metallic dot, semiconductor, molecular and magnetic QCA. If material production can be handled efficiently, the next practical issue for QCA circuits is operating temperature. This temperature is considered very low, and the QCA circuit should be optimized for room temperature operation. Recently, successful fabrication of QCA cells using the nano-damascene process has been achieved, potentially enabling room-temperature operation of QCA-based circuits.

Meanwhile, a multiplier is a hardware circuit for the purpose of multiplying two binary values in a digital circuit, and is one of the important constituent circuits in a digital signal processing and communication system. A method of using the QCA technique for such a multiplier has been extensively studied.

However, in addition to the method generally used as a multiplication method, ancient Indian Vedic mathematics can be used. Vedic mathematics provides a way to solve a set of mathematical problems based on 16 sutras.

Therefore, it is necessary to consider a method of implementing a QCA multiplier having a structure that can minimize energy loss while reducing time and space complexity by using a Vedic mathematical algorithm.

Accordingly, an object of the present invention is to provide a QCA multiplier having a structure with high energy efficiency and reducing complexity in time and space by using a Vedic mathematical algorithm.

QCA Vedic multiplier according to the present invention for achieving the above object, for 2-bit binary numbers A and B, A0, which is the least significant bit (LSB) of A, and B0, which is the least significant bit (LSB) of B, are input, AND A first combinational logic cell that performs a gate function and outputs a 0th bit value that is the least significant bit of the final result value. When A1 and B0, which are the most significant bits (MSB) of A, are input, a second AND gate function is performed When the combinational logic cell, A0 and B1, which is the most significant bit of B, is input, a third combinational logic cell performing an AND gate function, the A1 and B1 are input, and a fourth combinational logic cell performing an AND gate function , the output signal of the second combinational logic cell and the output signal of the third combinational logic cell are input, performing a half adder function to output the first bit value of the final result value as the sum value with the carry C1; The combinational logic cell, the output signal of the fourth combinational logic cell, and the C1 are input, performing a half adder function, outputting the second bit value of the final result as a sum value, and the final result as a carry signal and a sixth combinational logic cell that outputs the third bit value of the value.

The first to fourth combinational logic cells may be formed of combinational logic cells in which one of the inputs of the 3-input QCA majority vote gate is fixed to a value corresponding to logic bit 0.

In addition, the QCA Vedic multiplier according to the present invention for achieving the above object, for 4-bit binary numbers A and B, 2 bits of the 1st bit A1 of A and the 0th bit A0 which is the least significant bit of A, and 4-bit S ₀₃ S ₀₂ S ₀₁ S ₀₀ is output as a result of multiplying 2 bits of B1 which is the 1st bit of B and the 0th bit B0 which is the least significant bit of B, and S ₀₃ S ₀₂ S ₀₁ S ₀₀ 1st bit S ₀₁ and 0th bit S ₀₀ are the 1st bit and 0th bit of the final result, respectively, the first combinational logic cell, the 2 bits of A1 and A0, and the 3rd bit of B A second combinational logic cell that outputs a 4-bit binary number SB as a result of multiplying B3 and the 2-bit signal of B2, which is the second bit of B, A3 that is the third bit of A, and A2 that is the second bit of A A third combinational logic cell for outputting a 4-bit binary number SC as a result of multiplying 2 bits of B1 and the 2-bit signals of B0, 2 bits of A3 and A2, and 2 bits of B3 and B2 4-bit binary number SD as the result of multiplying by A fourth combinational logic cell for outputting , a fifth combinational logic cell for outputting a 4-bit binary number SE and 1-bit carry C0 as a result of the sum of the SB and the SC, the SE and the S ₀₃ S ₀₂ 4-bit D3 D2 D1 D0 and 1-bit carry C1 are output as a result of adding 4 bits 0 0 S ₀₃ S ₀₂ with 2 bits and filling the upper 2 bits with 0, and the D1 and the D0 are the final results, respectively. A sixth combinational logic cell that becomes the 3rd bit and the 2nd bit value of the value, and the SD and the 4-bit C0 0 D3 D2 with the D3 D2 as the lower 2 bits and the upper 2 bits with the C0 and 0 4 bits E3 E2 E1 E0 and carry C2 are output as result values, and the E3, E2, E1, and E0 are the 7th bit, 6th bit, 5th bit, and 4th bit of the final result value, respectively. and a seventh combinational logic cell that becomes a bit.

And, in order to achieve the above object, in the present invention, it is possible to provide a quantum dot cellular automata device including the QCA Veda multiplier.

According to the present invention, it is possible to provide a QCA multiplier having a structure capable of fast arithmetic processing by reducing complexity in time and space based on a Vedic mathematical algorithm. In addition, it is possible to provide a QCA multiplier having a structure with high energy efficiency by using a QCA half adder using a QCA XOR gate based on cell interaction. In addition, the QCA multiplier according to the present invention can be efficiently used in various devices using quantum dot cellular automata.

1 is a diagram referenced to describe a quantum dot cellular automata;
2 is a diagram referenced in the description of the QCA wiring;
3 is a diagram referenced in the description of various combinational logic cells;
4 is a diagram illustrating a QCA clock having four clock steps;
5 is a diagram showing the structure of a QCA half adder used in the present invention;
6 is a diagram referenced in the description of the operation process of the 2×2 Vedic multiplier;
7 is a block diagram of a QCA 2×2 Vedic multiplier according to an embodiment of the present invention;
8 is a diagram showing the structure of a QCA 2×2 Vedic multiplier according to an embodiment of the present invention;
9 and 10 are diagrams referenced for the description of the operation process of the 4×4 Vedic multiplier;
11 is a block diagram of a QCA 4×4 Vedic multiplier according to an embodiment of the present invention;
12 is a diagram showing the structure of a full adder used in the ripple carry adder used in the present invention;
13 is a diagram showing the structure of a QCA 4×4 Vedic multiplier according to an embodiment of the present invention;
14 is a view showing the simulation result of the QCA 2×2 Vedic multiplier shown in FIG. 8;
15 is a table showing parameters used for simulation;
16 is a table summarizing the results of comparing the QCA Vedic multiplier and other QCA multipliers according to the present invention;
17 is a graph comparing the area of a QCA 4×4 Vedic multiplier according to the present invention and a QCA multiplier according to a previous design;
18 to 20 are tables showing power loss analysis of QCA Vedic multipliers and other QCA multipliers according to the present invention, and
21 is a graph showing a comparison result of a QCA Vedic multiplier according to the present invention and another QCA multiplier.

In this specification, when a component is referred to as being “connected” or “connected” to another component, the component may be directly connected or connected to another component, but another component in between. It should be understood that elements may exist. Also, other expressions describing the relationship between elements, such as "between" or "neighboring", etc., such as that one element "transmits" a signal to another element, should be interpreted similarly. do.

Hereinafter, the present invention will be described in more detail with reference to the drawings.

1 is a diagram referenced to describe a quantum dot cellular automata.

Quantum-dot Cellular Automata (QCA) is a next-generation technology that represents a logical state not as a voltage state but as a pair of electronic states in the cell. It has the advantage of high device density of about 1012 devices/cm2.

Referring to FIG. 1 , a QCA cell is usually composed of four quantum dots, and has two transient electrons capable of tunneling between the quantum dots. Because of the coulombic repulsion, these electrons tend to be located within the diagonally opposite quantum dots, and due to the high potential barrier between each pair of quantum dots, the electrons are split into individual points, resulting in two stable states (0 and 1) in the cell. is displayed in

The polarization P is determined by one of the two diagonals according to the charge distribution. That is, in the QCA cell, there are two types of polarization having energy equivalent, and this can be expressed as P=-1 polarization corresponding to 0 of the logic bit or P=+1 polarization corresponding to 1 of the logic bit.

로 지정하면, 편광(P)는 다음의 식과 같이 정의된다.Calculate the electron density at the i-th point for the four points i = 1 to 4 clockwise from the top right of the cell.

If designated as , the polarization P is defined as the following equation.

2 is a diagram referred to in the description of the QCA wiring.

A QCA wire can be viewed as a series of horizontal cells that transmit information from one cell to another, and binary information can be transmitted by neighboring cell interactions along the QCA cell line.

Figure 2 (a) shows the basic QCA wiring, it can be designed by continuously arranging normal 90° cells. Fig. 2(b) shows a QCA inverter chain, and is a QCA wiring formed by a cell rotated by 45°.

In such QCA wiring, binary information can be transmitted by neighboring cell interactions along QCA cell lines in the input-to-output direction. Thus, information can be transmitted without current flow.

For intersecting QCA wirings, coplanar wiring crossings, multilayer wiring crossings, and logic wiring crossings are widely used. Coplanar wire crossings cross normal (90°) wires using inverter chains made up of cells rotated 45°. In this process, the two types of cells do not interact with each other.

Multilayer interconnection crossings include three-dimensional structures across interconnections using one or more layers. This interconnect crossover is more stable in simulation, but not easy to fabricate.

Logical wiring crossing is implemented in a single layer and requires only one type of QCA cell. This method is based on the interference of the clocking phase. For example, cells in the switch and hold phases may intersect cells in the release and relaxation phases, respectively.

3 is a diagram referenced in the description of various QCA combinational logic cells.

3(a)(b) shows the configuration of a combinational logic cell performing a majority gate function. In FIG. 2(a) is a 3-input majority vote gate, FIG. 2(b) is a 5-input majority vote gate indicates

The majority vote gate provides a function of outputting 1 when the number of 1's is greater than 0 among input signals, and outputting 0 when the number of 0's is greater than 1 among input signals. The following [Equation 1] shows the logic of a 3-input majority vote gate.

The basic logic gates, AND gates and OR gates, can be constructed using a three-input majority vote gater. That is, as shown in the following equation, an AND gate can be made by fixing one of the three inputs to 0, and an OR gate can be made by fixing one of the three inputs to 1.

The innovative 5-input majority vote gate consists of 10 cells, and the design based on the majority vote is more area efficient compared to previous designs. The following equation shows the logic of a 5-input majority vote gate.

3(c)(d) shows the configuration of a combinational logic cell performing an inverter function. When the QCA cells are arranged diagonally, the direction of the excess electrons is changed by the Coulomb repulsion force, and an inverted value can be output to the input value.

In the case of FIG. 3(c), compared to the inverter shown in FIG. 3(d), the inverter is weaker but concisely configured. Fig. 3(d) shows a more powerful inverter that has a stronger logical structure and outputs a stable value than that shown in Fig. 3(c).

4 shows a QCA clock having four clock steps.

The QCA circuit uses a clock system to synchronize and manage data transfers. In other words, since the electrons in a quantum dot require high potential energy to tunnel through the junction, clocking plays a very important role in the synchronization and flow of information along a specific direction. The main advantage of the QCA clock system is that the quantum cell does not require an external power supply, so it can power the circuit.

As shown in Fig. 4, the clock is composed of four stages of switch, hold, release and relax separated by π/2 intervals, and can be operated according to the activation of electrons. can

During the switch phase, the barrier corresponding to a dot in the inactive cell gradually increases, and in the hold phase, in a state where the barrier corresponding to the dot is increased, the corresponding values 0 and 1 are encoded to prevent tunneling of electrons. The release phase means a state in which the barrier is gradually lowered, and the relaxation phase means a state in which the barrier is lowered and electron tunneling is promoted.

5 shows the structure of the QCA half adder used in the present invention.

Most QCA half adders have an equation structure based design, i.e. a combination of an inverter and a majority gate. However, it is also possible to implement a QCA half adder using an XOR gate. The QCA half adder used in the present invention uses a QCA XOR gate based on cell interaction.

Referring to FIG. 5 , the QCA half adder 100 uses an XOR gate based on cell interaction, and includes one XOR gate and a 3-input majority vote gate. The value of the two fixed cells is 0, and the QCA half adder 100 is regarded as a structure based on cell interaction. The QCA inverter 100 consists of 39 cells, and the output is generated after 3 clock steps. The QCA half adder is defined as follows, and the truth table is shown in [Table 1].

Input
Output
A
B
Sum
Carry
0
0
0
0
0
One
One
0
One
One
One
0
One
One
0
One

On the other hand, the vertical and cruciform Vedic multiplication method called Urdhva-Tiryakbhyam (UT) can be used for both decimal and binary multiplication. This method is an algorithm that can be used to multiply numbers N×N.

Vedic multipliers do not depend on the clock frequency of the processor because the sum and partial products are computed in parallel. This means that Vedic multipliers can be used to reduce energy loss and speed up multiplication.

In Vedic mathematics, the multiplication of ax + b and cx + d is based exactly on the UT sutra, and the resulting expression is acx ² + (ad + bc)x + bd . The principles of the UT Sutra are:

● The coefficient of x ² represents the vertical multiplication of a and c.

● The coefficient of x represents the sum of both output values along with the cross multiplication of a and d and b and c.

● The constant is the vertical multiplication of b and d.

6 is a diagram referenced in the description of an operation process of a 2×2 Vedic multiplier.

In FIG. 6 , when a 2-bit binary number A = [A ₁ A ₀ ], B = [B ₁ B ₀ ], first the least significant bit (LSB) of the binary number A, that is, the least significant bit (LSB) of B at (A ₀ ) , that is, multiply by (B ₀ ). The generated result (A ₀ B ₀ ) is stored as the LSB of the final result value. A single AND gate is required to multiply A ₀ and B ₀ .

In the next step, the LSB of binary A is multiplied by the most significant bit (MSB) of binary B (A ₀ × B ₁ ). At the same time, the MSB of binary A is multiplied by the LSB of binary B (A ₁ ×B ₀ ). The resulting result is added as [(A ₀ ×B ₁ ) + (A ₁ ×B ₀ )] using a half adder.

The 2-bit result [C ₁ S ₁ ] produced by the first half adder is considered as the first bit (S ₁ ) of the final result, and (C ₁ ) is stored as the previous carry for the next step. In the last step, MSB(A ₁ ) of binary number A is multiplied by MSB(B ₁ ) of binary number B, and the result (A ₁ ×B ₁ ) is added to the previous carry (C ₁ ) via a second half adder.

The 2-bit result [C ₂ S ₂ ] is obtained from the second full adder. That is, (S ₂ ) and (C ₂ ) are the third and fourth bits of the final result value, respectively. Finally, a 4-bit number [C ₂ S ₂ S ₁ S ₀ ] is formed as an output.

[Table 2] is for the simulation of a 2×2 Vedic multiplier.

A1
A0
B1
B0
Output
One
One
One
One
1001
One
One
0
One
0011
One
0
0
One
0010
0
One
0
One
0001

7 is a block diagram of a QCA 2×2 Vedic multiplier according to an embodiment of the present invention.

Referring to FIG. 7 , the 2×2 Vedic multiplier consists of four majority gates (MG) and two half adders (HA) performing an AND gate function, and the operation process is defined as follows.

8 shows the structure of a QCA 2×2 Vedic multiplier according to an embodiment of the present invention.

Referring to FIG. 8, the QCA 2×2 Vedic multiplier 200 includes first to fourth combinational logic cells 150a, 150b, 150c, and 150d performing an AND gate function, and fifth and It includes a sixth combinational logic cell (100a, 100b).

Assuming there is a 2-bit binary number A and a 2-bit binary number B,

The first combinational logic cell 150a is inputted with A ₀ , which is the least significant bit (LSB) of A, and B ₀ , which is the least significant bit (LSB) of B, and performs an AND gate function to perform an AND gate function to perform an AND gate function, which is the least significant bit of the final result value. Outputs S ₀ corresponding to the value.

The second combinational logic cell 150b performs an AND gate function when A ₁ and B ₀ , which are the most significant bits (MSB) of A, are input.

The third combinational logic cell 150c performs an AND gate function when A ₀ and B ₁ which is the most significant bit of B are input.

A ₁ and B ₁ are input to the fourth combinational logic cell 150d, and performs an AND gate function.

The fifth combinational logic cell 100a receives the output signal of the second combinational logic cell 150b and the output signal of the third combinational logic cell 150c, and performs a half adder function to finalize the sum value with the carry C ₁ . Outputs S ₁ corresponding to the 1st bit value of the result value.

The sixth combinational logic cell 100b receives the output signal of the fourth combinational logic cell 150d and the carry C ₁ input, performs a half adder function, and as a sum value, S corresponding to the second bit value of the final result value ₁ is output, and C ₂ corresponding to the 3rd bit value of the final result is output as a carry signal.

In the QCA 2×2 Vedic multiplier 200, logical wiring crossing is widely used to cross wiring, and the fifth and sixth combinational logic cells 100a and 100b performing the half adder function are designed with a low complexity structure, and the same It is a flat design.

9 and 10 are diagrams referenced for the description of the operation process of the 4×4 Vedic multiplier.

In Fig. 9, when two binary numbers A = [A ₃ A ₃ A ₁ A ₀ ] and B = [B ₃ B ₃ B ₁ B ₀ ], in the first step, the LSB of the binary number A is multiplied by the LSB of the binary number B, and the final Generates the LSB of the result value. The remaining steps are similar to the operation process of the 2×2 Vedic multiplier described above.

According to the general concept, the generated carry (C _n ) is passed to the next step in each step. This process continues until the last step. Outputs C ₆ and S ₆ are taken from the last step. Finally, all generated results are obtained in the form of [C ₆ S ₆ S ₅ S ₄ S ₃ S ₂ S ₁ S ₀ ], and the operation process is defined as follows.

Referring to FIG. 10 , the structural design of a 4×4 beta multiplier using a 2×2 Veda multiplier may improve the complexity of the operation. That is, four 2×2 Vedic multipliers M1, M2, M3, and M4 perform multiplication operations between defined inputs and generate 16 results (S ₀₀ , S ₀₁ … S ₃₂ , S ₃₃ ). The results obtained from the generated units are placed in three specific locations: Part 1, Part 2, and Part 3. Part 1 contains the last 2 bits of the M1 result (S ₀₁ S ₀₀ ), and part 3 contains the primary 2 bits of the M4 result (S ₃₃ S ₃₂ ). However, Part 2 is the multiple operation part of the summing unit that performs the main cross multiplication on the following 4x4 structure.

The Vedic multiplier is obtained after calculating the summing units in the form [R ₇ R ₆ R ₅ R ₄ R ₃ R ₂ R ₁ R ₀ ], where there is a '0' value in part 2 if necessary.

11 is a block diagram of a QCA 4×4 Vedic multiplier according to an embodiment of the present invention.

Referring to FIG. 11 , a basic component of a 4×4 Vedic multiplier is a 2×2 Vedic multiplier, and the 4×4 Vedic multiplier includes four 2×2 Vedic multipliers and three 4-bit ripple carry adders (RCA). ) is composed of

The partial product generated by the 2×2 multiplier is passed to the ripple carry adder to perform the addition. The result obtained from the first ripple carry adder is passed to the next ripple carry adder, and there are two zero inputs to the second ripple carry adder. In any case, a zero input is provided to some ripple carry adder whenever needed.

12 shows the structure of a full adder used in the ripple carry adder used in the present invention.

A 4-bit ripple carry adder may be configured by sequentially connecting the QCA full adders 250 as shown in FIG. 12 . Depending on the usage environment, other types of full adders may be used to construct the ripple carry adder.

13 shows the structure of a QCA 4x4 Vedic multiplier according to an embodiment of the present invention.

Referring to FIG. 13 , the QCA 4×4 Vedic multiplier 400 includes first to fourth combinational logic cells 200a, 200b, 200c, and 200d performing a 2×2 Vedic multiplier function, and a ripple carry adder function. It includes fifth to seventh combinational logic cells 300a, 300b, and 300c to perform.

Assuming we have 4-bit binary numbers A and B,

In the first combinational logic cell 200a, the first bit A ₁ of A and 2 bits of the 0th bit A ₀ which is the least significant bit of A, B ₁ which is the 1st bit of B and the 0th bit B which is the least significant bit of B 4 bits S ₀₃ S ₀₂ S ₀₁ S ₀₀ are output as the result of multiplying 2 bits of _0. In S ₀₃ S ₀₂ S ₀₁ S ₀₀ , the 1st bit S ₀₁ and the 0th bit S ₀₀ are the final result values, respectively. It becomes R ₁ corresponding to the 1st bit and R ₀ corresponding to the 0th bit.

In the second combinational logic cell 200b, a 4-bit binary number SB is obtained as a result of multiplying 2 bits of A ₁ and A ₀ and a 2-bit signal of B ₃ which is the 3rd bit of B and B ₂ which is the 2nd bit of B. print out

The third combinational logic cell 200c is a 4-bit binary number SC as a result of multiplying the 2 bits of A ₃ which is the 3rd bit of A and A ₂ which is the 2nd bit of A, and the 2 bit signals of B ₁ and B ₀ print out

The fourth combinational logic cell 200d is a 4-bit binary number SD as a result of multiplying 2 bits of A ₃ and A ₂ and 2 bits of B ₃ and B ₂ to output

The fifth combinational logic cell 300a outputs a 4-bit binary number SE and 1-bit carry C ₀ as a result of summing SB and SC.

The sixth combinational logic cell 300b is the result of summing 4 bits 0 0 S ₀₃ S ₀₂ with SE and S ₀₃ S ₀₂ as the lower 2 bits and filling the upper 2 bits with 0 with 4 bits D3 D2 D1 D0, Outputs 1-bit carry C ₁ , and D1 and D0 become R ₃ corresponding to the 3rd bit of the final result value and R ₂ corresponding to the 2nd bit, respectively.

The seventh combinational logic cell 300c is the result of summing the SD and D3 D2 as the lower 2 bits, and the 4 bits C ₀ 0 D3 D2 filled with the upper 2 bits with C ₀ and 0, with 4 bits E3 E2 E1 E0 and carry output C ₂ , where E3, E2, E1, and E0 are R ₇ corresponding to the 7th bit of the final result, R ₆ corresponding to the 6th bit, R ₅ corresponding to the 5th bit, and the 4th bit, respectively. It becomes R ₄ corresponding to the bit.

This QCA 4×4 Vedic multiplier 400 is constructed using logical and multiple cross wiring, and if the full adder is changed to the same plane, the entire structure can be a coplanar layout. This architecture is well pipelined within 5,25 clock cycles.

FIG. 14 is a diagram showing simulation results of the QCA 2×2 Vedic multiplier shown in FIG. 8, and FIG. 15 is a table showing parameters used in the simulation.

As shown in FIG. 14 , the QCA 2×2 Vedic multiplier 200 and the following simulations according to the present invention can be performed using the QCADesigner 2.0.3 tool.

The QCA circuit can be simulated using a bistable approximation and a coherence vector simulation engine, and parameters used for the simulation are as shown in FIG. 14 .

In FIG. 14 , input/output values are indicated by red rectangles, respectively. The output corresponding to the rectangle indicated by the dashed line within the red rectangle indicating the input is indicated by the value within the rectangle indicated by the dashed line at the bottom indicated by the arrow. For example, multiplying binary number '11'(A ₁ A ₀ ) by '11'(B ₁ B ₀ ) is equivalent to binary number '1001'(C ₂ S ₂ S ₁ S ₀ ), and the result obtained as a result of simulation is [ It can be confirmed that the values in Table 2] match.

16 is a comparison arrangement of the QCA Vedic multipliers 200 and 400 according to the present invention and the QCA multipliers according to the previous design.

16 and 17, [33] is a QCA multiplier proposed by Kim, S.W. (Kim, S.W. Design of Parallel Multipliers and Dividers in QCA. UT Electronic Theses and Dissertations. University of Texas at Austin, Austin, TX, USA, May 2011), [34] in Kim, S.W. (Kim, S.W.; Swartzlander, E.E. Parallel Multipliers for Quantum-Dot Cellular Automata. In Proceedings of the IEEE Nanotechnology Materials and Devices Conference, Traverse City, MI, USA, 2.5 June 2009; pp. 68.72), [ 35] is a QCA multiplier ( Chudasama, A.; Sasamal, T.N. Implementation of 4x4 Vedic Multiplier using Carry Save Adder in Quantum-Dot Cellular Automata. In Proceedings of the 2016 International Conference on Communication and Signal Processing ( ICCSP), Melmaruvathur, India, 6.8 April 2016; pp. 1260.1264). And, 'Proposed' denotes the QCA multipliers 100 and 200 according to the present invention.

As can be seen from FIG. 16 , it can be seen that the QCA multipliers 200 and 400 according to the present invention are improved over the previous design in terms of the number of cells, area, time delay, and the like.

17 is a graph comparing the area of a QCA 4×4 multiplier according to the present invention and a QCA multiplier according to a previous design.

As shown in FIG. 17 , it can be seen that the QCA multiplier according to the present invention exhibits greater performance in terms of area compared to the QCA multiplier according to the previous design.

This result is because the QCA multiplier according to the present invention is improved over the previous AND-OR-INVERTER-based structure in all aspects by using the cell interaction-based XOR gate.

Meanwhile, the QCAPo tool was used to estimate the energy loss, and the energy loss can be analyzed by considering three energy levels (0.5 E _k , 1.0 E _k , 1.5 E _k ) at 2K temperature. And, the energy lost can be measured based on the Hamiltonian matrix using the Hartree-Fock approximation for the Coulomb interaction between cells defined as follows.

로 표현된다. Ek는 두 셀(i 및 j)의 에너지 비용과 관련된 꼬임 에너지이며, 이 꼬임 에너지는 극성이 반대되는 두 셀의 에너지 비용과 관련이 있다. 그리고,

은 클럭에 의해 제어되는 셀 내부의 전자 터널링 에너지를 나타낸다.In the above equation, the polarization of the i-th parallel cell is expressed as Ci, and the geometric factor identifying the electrostatic interaction between cells i and j is due to the geometric distance

is expressed as Ek is the twist energy related to the energy cost of the two cells (i and j), and this twist energy is related to the energy cost of the two cells with opposite polarities. and,

represents the electron tunneling energy inside the cell controlled by the clock.

18 to 20 are tables showing power loss analysis of the QCA Vedic multiplier according to the present invention and another QCA multiplier according to the previous design.

18 to 20 are calculated for three different tunneling energy levels at a temperature of 2K. FIG. 18 shows the average leakage energy, FIG. 19 shows the switching energy, and FIG. 20 shows the circuit energy loss.

18 to 21, [7] is a QCA circuit proposed by Cho, H. et al. (Cho, H.; Swartzlander, E.E. Adder designs and analyzes for quantum-dot cellular automata. IEEE Trans. Nanotechnol. 2007, 6, 374.383 ), [15] are the QCA circuits proposed by Chudasama, A. et al. (Chudasama, A.; Sasamal, T.N.; Yadav, J. An efficient design of Vedic multiplier using ripple carry adder in Quantum-dot Cellular Automata. Comput. Electr. Eng. 2017, 65, 527.542), [29] are QCA circuits proposed by Balali, M. et al. (Balali, M.; Rezai, A.; Balali, H.; Rabiei, F.; Emadi, S. Towards coplanar quantum). -dot cellular automata adders based on efficient three-input XOR gate. Results Phys. 2017, 7, 1389.1395). And "Proposed" represents the QCA circuit according to the present invention.

21 is a graph showing the results of comparison with other QCA multipliers in order to clearly show the power loss of the QCA multiplier according to the present invention.

As shown in FIG. 21, it can be seen that the QCA multiplier according to the present invention consumes the least energy compared to the previous design.

On the other hand, the QCA Vedic multiplier according to the present invention is not limited to the configuration and method of the described embodiments as described above, but all or part of each embodiment is selective so that various modifications can be made to the embodiments. It may be configured in combination with .

In addition, although preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above, and the technical field to which the present invention belongs without departing from the gist of the present invention as claimed in the claims In addition, various modifications may be made by those of ordinary skill in the art, and these modifications should not be individually understood from the technical spirit or perspective of the present invention.

Claims (5)

For 2-bit binary numbers A and B,
A first combination logic cell in which A0, which is the least significant bit (LSB) of A, and B0, which is the least significant bit (LSB) of B are input, and performs an AND gate function to output a 0th bit value that is the least significant bit of the final result value ;
a second combinational logic cell that performs an AND gate function when A1, which is the most significant bit (MSB) of A, and B0 are input;
a third combinational logic cell performing an AND gate function when the A0 and B1, which is the most significant bit of the B, are input;
a fourth combinational logic cell to which the A1 and the B1 are input and performing an AND gate function;
A fifth combination in which the output signal of the second combinational logic cell and the output signal of the third combinational logic cell are input, and performing a half adder function to output the first bit value of the final result value as the sum value with the carry C1 logic cell; and
The output signal of the fourth combinational logic cell and the C1 are input, a half adder function is performed to output the second bit value of the final result value as the summed value, and the third bit of the final result value as a carry signal A QCA Vedic multiplier including a sixth combinatorial logic cell that outputs a value. The method of claim 1,
The first to fourth combinational logic cells are combinational logic cells in which one of the inputs of the 3-input QCA majority vote gate is fixed to a value corresponding to logic bit 0. QCA Vedic multiplier, characterized in that. For 4-bit binary numbers A and B,
The result of multiplying the 1st bit A1 of A and 2 bits of the 0th bit A0 which is the least significant bit of A, and 2 bits of B1 which is the 1st bit of B and the 0th bit B0 which is the least significant bit of B 4 bits S ₀₃ S ₀₂ S ₀₁ S ₀₀ are output, and in S ₀₃ S ₀₂ S ₀₁ S ₀₀ , the 1st bit S ₀₁ and the 0th bit S ₀₀ are the 1st bit and 0th bit of the final result value, respectively. A first combinational logic cell to be;
a second combinational logic cell for outputting a 4-bit binary number SB as a result of multiplying 2 bits of the A1 and A0 with a 2-bit signal of B3 which is the 3rd bit of B and B2 which is the 2nd bit of B;
a third combinational logic cell for outputting a 4-bit binary number SC as a result of multiplying 2 bits of A3 which is the 3rd bit of A and 2 bits of A2 which is the 2nd bit of A, and the 2 bit signals of B1 and B0;
A 4-bit binary number SD as a result of multiplying 2 bits of A3 and A2 by 2 bits of B3 and B2 a fourth combinational logic cell that outputs
a fifth combinational logic cell for outputting a 4-bit binary number SE and 1-bit carry C0 as a result of the sum of the SB and the SC;
4-bit D3 D2 D1 D0 and 1-bit carry C1 are output as the result of summing the SE and the 4-bit 0 0 S ₀₃ S ₀₂ with the lower 2 bits of the S ₀₃ S ₀₂ and the upper 2 bits filled with 0, , a sixth combinational logic cell in which the D1 and the D0 are the third bit and the second bit of the final result value, respectively; and
4 bits E3 E2 E1 E0 and carry C2 are output as the result of summing the SD and the 4 bits C0 0 D3 D2 with the D3 D2 as the lower 2 bits and the upper 2 bits with the C0 and 0, and the E3, and a seventh combinational logic cell in which the E2, the E1, and the E0 are the 7th bit, the 6th bit, the 5th bit, and the 4th bit of the final result value, respectively. 4. The method of claim 3,
The fifth to seventh combinational logic cells are QCA Vedic multipliers, characterized in that they are 4-bit QCA ripple carry adders. A quantum dot cellular automata device comprising the QCA Veda multiplier of claim 1 or 2.

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