KR20220131002A - Arithmethic system based on field programmable gate array, memory apparatus, and arithmethic apparatus based on field programmable gate array - Google Patents

Abstract

The present invention relates to an FPGA operation system that effectively reduces a processing delay caused by a Galois field multiplication operation, a memory device, and an FPGA operation device. The FPGA operation system comprises: a memory device; and an FPGA operation device.

Description

FPGA arithmetic system, memory device, and FPGA arithmetic unit

The present invention relates to Galois/Counter mode (GCM), and to a method for reducing processing delay caused by a finite field (Galois Field) multiplication operation.

Authenticated encryption operation mode is designed to ensure the same security with one encryption key instead of applying an independent encryption key to the confidentiality operation mode and authentication operation mode to provide confidentiality and authentication for data at the same time. method.

Due to the convenience and safety advantages of the authentication encryption operation mode, major encryption protocols such as SSL (Secure Sockets Layer)/TLS (Transport Layer Security), IPsec (Internet Protocol security), and SRTP (Secure RTP) The application of authentication encryption operation mode is supported.

Among these authentication encryption operation modes, GCM (Galois/Counter mode) is an authentication encryption operation mode designed to use one encryption key by combining CTR (CounTeR), which is a confidential operation mode, and authentication operation mode.

Since GCM does not need to determine the information of input data in advance, online processing is possible. In the encryption process, CTR mode is applied to plaintext to calculate C _CTR , and then a function defined as a finite-body operation with additional authentication data. You can create an output value C _GCM by inputting it in to generate an authentication value and concatenating the two values.

However, in order to maximize the performance advantage of GCM, the 128-bit finite field multiplication operation must operate efficiently.

However, in order to implement the 128-bit finite field multiplication operation in hardware, 128 cycles are required, which causes a lot of delay to process data such as Synchronous Digital Hierarchy (SDH) or Optional Transport Network (OTN) frames, resulting in network delay. It can cause problems.

Accordingly, the present invention intends to propose a method for effectively reducing the processing delay caused by the finite field multiplication operation.

The present invention was created in view of the above circumstances, and an object of the present invention relates to a Galois/Counter mode (GCM), and effectively reduces processing delay caused by a finite field (Galois Field) multiplication operation. It's about how to do it.

An FPGA operation system according to an embodiment of the present invention for achieving the above object includes a memory device in which a finite field (Galois Field) multiplication operation result related to a hash subkey (H) is recorded in a memory as a data value for each address; and inputting a bit value of the input data as an address value for the memory, and returning a data value output from the memory according to the input of the bit value of the input data as a result of a finite-body multiplication operation between the input data and the hash subkey It is characterized in that it includes an FPGA arithmetic unit.

In order to achieve the above object, a memory device according to an embodiment of the present invention provides, for each bit digit of input data, between first data matched with the input data and second data matched with a hash subkey (H). a first memory in which a Galois Field multiplication operation result is recorded as a data value; a second memory in which, for each bit digit of the input data, a bit digit of the hash subkey having a bit value of 1 is an address value, and a data value output from the first memory is recorded as a data value for each bit digit of the input data; and a data value output from the second memory as an address value for each bit digit where a bit value becomes 1 in the input data for all bit values that the input data may have in a lookup table (LUT) and a third memory in which a data value of the same address as the bit value of the input data is written.

Specifically, the first memory may include, for each bit position of the input data, the second data for a bit string in which a bit value in the same bit position in the first data is set to 1 and a bit value in the remaining bit positions is set to 0. In , the result of finite-body multiplication operation on the bit string for each case where the bit value of each bit digit is 1 may be recorded as the data value of each address.

Specifically, in the second memory, for each bit position of the bit string of the input data, when the data value output from the first memory is 2 or more, an XOR operation is performed on all of the 2 or more data values. Results can be recorded as data values.

Specifically, in the third memory, when each bit digit at which the bit value becomes 1 in the input data is 2 or more, the result of XOR operation on all data values of each of the 2 or more bit positions is the data value. can be recorded.

An FPGA computing device according to an embodiment of the present invention for achieving the above object includes a lookup table (LUT) in which a result of a Galois Field multiplication operation related to a hash subkey (H) is pre-recorded as a data value for each address; an input unit for inputting a bit value of input data as an address value for the Look Up Table; and a return unit that returns a data value output from the lookup table as a result of a finite-body multiplication operation between the input data and the hash subkey according to the bit value input of the input data.

Specifically, the input unit may divide the entire bit string of the input data into two or more bit strings of the same length, and input a bit value of each of the two or more bit strings as an address value of the lookup table.

Specifically, the return unit is configured to return an exclusive-OR (XOR) operation result on all data values output from the lookup table according to the bit value input of each of the two or more bit columns, as a finite object between the input data and the hash subkey. It can be returned as a result of a multiplication operation.

Accordingly, according to the FPGA operation system, the memory device, and the FPGA operation device of the present invention, the pre-calculation method regarding the hash sub-key (H) is applied for the finite-body multiplication operation between the fixed hash sub-key and arbitrary input data. By writing the result value to the memory and outputting the result of the finite-body multiplication operation between the input data and the hash subkey by inputting the bit value of the input data as the address value of the corresponding memory, the processing delay caused by the finite-body multiplication operation is efficiently improved can do.

1 is a block diagram of a GCM according to an embodiment of the present invention.
2 is a schematic configuration diagram of a finite field multiplication operation system according to an embodiment of the present invention.
3 is a schematic configuration diagram for explaining a memory device according to an embodiment of the present invention;
Figure 4 is a schematic configuration diagram for explaining the FPGA arithmetic device according to an embodiment of the present invention.
5 is a flowchart for explaining a method of operating an FPGA arithmetic device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

In one embodiment of the present invention, GCM (Galois / GCM) presented by the operating mode standards of various encryption algorithms, including LEA (Light weight Encryption Algorithm), ARIA (Academy, Research Institute, Agency), and AES (Advanced Encryption Standard), etc. Counter mode) is dealt with.

In this regard, the CCM (Counter with CBC-MAC) mode and GCM suggested by the LEA operation mode standard are designed to use a single encryption key by combining the confidential operation mode CTR (CounTeR) and the authentication operation mode. is the mode

Like the confidentiality operation mode, the authentication encryption operation mode uses an initial value together with an encryption key, and the initial value must have a nonce characteristic.

At this time, as the initial value, the same value used for encryption should be used for decryption as in the encryption key, so a method for sharing it must be separately defined before decryption.

In addition, associated data can be received as input during encryption (decryption) along with the encryption key, initial value, and plain text (cipher text). It is not included in the ciphertext and does not have to be recoverable from the ciphertext.

CCM mode is assumed to be used in an environment where all data information is determined before encryption, and online processing like streaming services is not supported. In the encryption process, an authentication value is generated by applying CBC-MAC to the plaintext, additional authentication data, and initial value, and then CTR mode is applied to the plaintext and authentication value to generate an output value C _CCM .

On the other hand, in GCM, online processing is possible because the information of the input data does not need to be determined in advance.

In the encryption process, C _CTR is calculated by applying the CTR mode to the plaintext, and then the authentication value is generated by inputting the additional authentication data to the function defined by the finite field operation, and the output value C _GCM is generated by concatenating the two values.

In more detail, the cipher text C _AE output through the encryption process of GCM can be viewed as a configuration in which the value C _CTR generated by the CTR mode and the authentication value T generated by the message authentication code are concatenated.

The receiver can recover the plaintext candidate P′ from the received ciphertext C _AE for the given encryption key K, initial value N, and additional authentication data A, and calculate the authentication confirmation value T′.

At this time, if no error occurs during the recovery process of the plaintext candidate P′, this is a strong evidence that the received ciphertext C _AE is generated from (K, N, A).

As such, the GCM can be understood as a structure in which the message authentication code using finite field multiplication is combined with the CTR mode.

At this time, the GHASH function is an element constituting the message authentication process of GCM, and is defined as the following pseudo code.

을 이용하여 다음의 의사 코드로 정의할 수 있다.Here, the multiplication operation '·' on the finite field GF(2 ¹²⁸ ) used in the GHASH function is the following subtraction polynomial

can be defined as the following pseudo code using

That is, for two 128-bit values U and V, the finite field product W = U·V used in the message authentication process of GCM is defined as the above pseudo code.

However, 128 cycles are required to implement the 128-bit finite field multiplication in hardware as in the pseudo code above, which causes a lot of delay in processing data such as SDH (Synchronous Digital Hierarchy) or OTN (Optional Transport Network) frames. This may cause delay problems on the network.

In order to help the understanding of the description, FIG. 1 shows a block diagram of the GCM by way of example.

In the block diagram of FIG. 1, '⊙' indicates a finite-body multiplication operation, and it can be seen that the finite-body multiplication operation is performed between the additional authentication data (A) and the fixed hash subkey (H).

However, since this finite-body multiplication operation requires 128 cycles every time additional authentication data A is input, it causes delay in network equipment that has to process continuous frames such as SDH (Synchronous Digital Hierarchy) or OTN (Optional Transport Network). This can have a huge impact on service quality.

Accordingly, an embodiment of the present invention intends to propose a method for effectively reducing the processing delay caused by the finite field multiplication operation.

In this regard, FIG. 2 exemplarily shows a finite field multiplication operation system according to an embodiment of the present invention.

As shown in FIG. 2 , the finite-body multiplication operation system according to an embodiment of the present invention includes a memory device 100 in which a result of a Galois Field multiplication operation related to a hash sub-key H is recorded, and an additional It may include an FPGA arithmetic unit 200 that processes a 128-bit finite field multiplication operation between authentication data (A; hereinafter referred to as 'input data') and a fixed hash subkey (H).

The memory device 100 refers to a device for pre-recording the result of a Galois Field multiplication operation with respect to the hash sub-key H as a data value for each address in the memory.

In this regard, FIG. 3 exemplarily shows the structure of the memory device 100 according to an embodiment of the present invention.

As shown in FIG. 3 , the memory device 100 according to an embodiment of the present invention performs finite-body multiplication between first data matching input data A and second data matching hash subkey H. The first memory 110 (ROM) in which the operation result is recorded, the second memory 120 in which the result value of the first memory 110 according to the hash sub-key H is recorded, and the finite body according to the hash sub-key H The third memory 130 may include a third memory 130 in which the result of the multiplication operation is pre-recorded as a data value for each address matching a bit value of the input data A in a look-up table (LUT).

Each configuration in the memory device 100 will be described in more detail as follows.

In the first memory 110, each bit digit (BIT0 to BIT127) of the bit string of the input data (A) is set as an address value (add = 0 to 127) for each bit (BIT0 to BIT127), and the input data ( A finite-body multiplication operation result between the first data matching A) and the second data matching the hash subkey H is recorded as the data value of each address.

In other words, in the first memory 110, for each bit digit (BIT0 to BIT127) of the input data A, the bit value of the same bit digit in the first data is set to 1, and the bit value of the remaining bit digit is set to 0. With respect to the bit string, the result of the finite-body multiplication operation of the bit string in each case where the bit value of each bit digit of the second data is 1 is recorded as the data value of each address.

For example, in ROM BIT0 of the first memory 110 , first data (corresponding to the value A)=”00000000… … 001" and second data (corresponding to H value)="00000000...001" to "10000000... … The result of the finite field multiplication operation performed while shifting the bit position up to 000” can be recorded from addresses 0 to 127, and the data values of ROM0 to ROM127 recorded in this way are independent of the hash subkey (H) value. It always has a fixed value.

In the second memory 120, whenever the hash subkey H is generated, for each bit position (BIT0 to BIT127) of the bit string of the input data A, one of the bit strings of the corresponding hash subkey H When a bit digit having a bit value of 1 is input as an address value of the first memory 110 , a data value output from the first memory 110 is recorded.

At this time, in the second memory 120 , when the data value output from the first memory 110 is 2 or more for each bit digit BIT0 to BIT127 of the bit string of the input data A, all of the data values of 2 or more A result of XOR operation may be recorded as a data value.

Accordingly, the pseudo code for writing the data value of the second memory 120 may be defined, for example, as follows.

In the third memory 130 , the result of the finite-body multiplication operation with respect to the hash sub-key H is pre-recorded as a data value for each address in the lookup table with reference to the data value recorded in the second memory 120 .

In other words, in the third memory 130 , in all cases where the bit value of the input data A is increased by 1, the data of each bit position (BIT0 to BIT127) in which the bit value becomes 1 in the input data A A value may be obtained from the second memory 120 and written as a data value having the same address as the bit value of the input data A in the lookup table.

At this time, in the lookup table, when each bit digit at which the bit value becomes 1 in the input data A is 2 or more, the result of XOR operation on all data values of each of the 2 or more bit positions is recorded.

On the other hand, in one embodiment of the present invention, the entire bit string of the input data (A) is converted to 8 bits (BIT0 to BIT7, BIT 8 to BIT15,??, BIT 120 to BIT127 for convenience of finite field (Galois Field) multiplication operation. ) to configure a lookup table in the second memory 120 and the third memory 130 having corresponding address values.

Accordingly, in the lookup table in the second memory 120 and the third memory 130, the 128 bits of the entire bit string of the input data A are divided into 16 bundles (#0 to #15) of 8 bits each. This is recorded.

In this regard, the pseudo code for writing the data value of the lower first 8 bits (BIT0 to BIT7) among the entire bit string of the input data A on the lookup table in the third memory 130 is defined as follows, for example. can be

In addition, the pseudo code for writing the data value of the second lower 8 bits (BIT8 to BIT15) among the entire bit string of the input data A on the lookup table in the third memory 130 may be defined, for example, as follows. have.

In addition, a pseudo code for writing data values of the last 8 bits (BIT120 to BIT127) of the entire bit string of the input data A on the lookup table in the third memory 130 may be defined, for example, as follows.

In summary, in the first memory 110 according to an embodiment of the present invention, the bit-to-bit finite field multiplication operation result between the first data matching the input data A and the second data matching the hash subkey H is recorded as a fixed value, and whenever a hash sub-key H is generated in the second memory 120 and the third memory 130, a data value corresponding to the corresponding hash sub-key H is sequentially displayed in a lookup table. It is recorded, and with reference to this, an exclusive-OR (XOR) operation required to derive a finite-body multiplication operation result between the input data A and the hash sub-key H is provided in a fast manner.

On the other hand, the hash subkey (H), where the input data (A) and the finite-body multiplication operation is performed, is a value when 0 values are input to all encryption blocks whenever the encryption key K is generated, and 0 ¹²⁸ is encrypted with the encryption key K can be understood as a result.

At this time, since the encryption key K is predetermined to be two or more, sufficient time can be secured for the pre-calculation method of the finite field multiplication operation proposed in the embodiment of the present invention.

The FPGA arithmetic device 200 refers to a device to which the finite field multiplication operation method between the input data (A) and the hash subkey (H) according to an embodiment of the present invention is implemented and applied to an FPGA (Field Programmable Gate Array).

The FPGA arithmetic device 200 applies a line calculation method regarding the hash sub-key (H) for the finite-body multiplication operation between the fixed hash sub-key (H) and the arbitrary input data (A) and calculates the result value. A finite-body multiplication operation result between the input data A and the hash subkey H may be output by writing to the memory and inputting the bit value of the input data A as the address value of the memory device 100 .

As described above, in the finite-body multiplication operation environment according to an embodiment of the present invention, the processing delay caused by the finite-body multiplication operation can be effectively reduced through the above-described configuration. The configuration will be described in more detail.

4 shows a schematic configuration of an FPGA computing device 200 according to an embodiment of the present invention.

As shown in FIG. 4 , the FPGA arithmetic device 200 according to an embodiment of the present invention includes an input unit 210 that inputs a bit value of the input data A as an address value and a bit value of the input data A It may have a configuration including a return unit 220 that returns a data value output according to an input as a result of a finite field multiplication operation between the input data A and the hash subkey H.

As such, all or at least a part of the configuration of the FPGA arithmetic device 200 including the input unit 210 and the return unit 220 may be implemented in the form of a field programmable gate array (FPGA).

As described above, the FPGA arithmetic device 200 according to an embodiment of the present invention can effectively reduce the processing delay caused by the finite field multiplication operation through the above-described configuration according to the above-described configuration. A more detailed description of each configuration within the FPGA arithmetic unit 200 will be continued.

Meanwhile, prior to the description, in the first memory 110 , the result of the finite-body multiplication operation between bits between the first data matching the input data A and the second data matching the hash subkey H is set as a fixed value. It is assumed that the data value according to the generation of the hash subkey H is pre-recorded in the lookup table in the second memory 120 and the third memory 130 .

In addition, in the lookup table in the third memory 130 , it is premised that data values are recorded in the form of dividing 128 bits of the entire bit string of the input data A into 16 bundles (#0 to #15) of 8 bits each. do.

The input unit 210 performs a function of inputting a bit value of the input data A as an address value.

More specifically, when the input data (A) is confirmed, the input unit 210 converts the bit value of the input data (A) into a finite field (Galois) multiplication operation result regarding the hash subkey (H) as a data value for each address in advance. It is input as an address value for a lookup table in the recorded third memory 130 .

In this case, the input unit 210 may divide the entire bit string of the input data into two or more bit strings of the same length, and input the bit value of each divided bit string as the address value of the lookup table in the third memory 130 .

For example, 128 bits of the entire bit string of input data (A) is converted into 16 bit strings of 8 bits each (A[7:0], A[15:8],??, A[127:120]). It is possible to divide and input the bit values (0 to 255) of each divided bit string as an address value of a lookup table in the third memory 130 .

In this case, according to an embodiment of the present invention, the data value recorded in the lookup table 30 is 16 bundles of 128 bits of the entire bit string of the input data A in the lookup table 30 (#0~# 15) to consider the recorded form.

The return unit 220 performs a function of returning the result of the finite field multiplication operation.

More specifically, the return unit 220 returns a data value output from the lookup table 30 according to the bit value input of the input data A as a result of a finite-body multiplication operation between the input data A and the hash subkey B. will be returned as

At this time, if the bit values of each of the two or more bit columns divided from the input data A are input, the return unit 220 may input the lookup table in the third memory 130 according to the input of the bit values of the two or more bit columns. An exclusive OR (XOR) operation result for all data values output from , may be returned as a result of a finite-body multiplication operation between the input data (A) and the hash subkey (H).

For example, 128 bits of the entire bit string of input data (A) is converted into 16 bit strings of 8 bits each (A[7:0], A[15:8],??, A[127:120]). If the bit values (0 to 255) of each divided bit string are input as the address value of the lookup table in the third memory 130, each bit string (A[7:0], A[15:8] All of the data values (R0[127:0], R1[127:0], …, R15[127:0]) output from the lookup table 30 for the bit values of , …, A[127:120]) The result of the XOR operation is returned as a result (W) of a finite-body multiplication operation between the input data (A) and the hash subkey (H).

As described above, according to the configuration of the FPGA arithmetic unit 200 according to an embodiment of the present invention, the FPGA arithmetic unit 200 is a finite field between a fixed hash sub-key (H) and arbitrary input data (A). For the multiplication operation, the pre-calculation method for the hash sub-key (H) is applied, the result value is recorded in the memory, and the bit value of the input data (A) is input as the address value of the corresponding memory to obtain the input data (A) and A finite-body multiplication operation result between hash subkeys (H) can be output. In this case, 1 cycle of inputting the bit value of the input data (A) as the address value of the memory as the address value of the memory and data according to the address value from the memory compared to the existing 128 cycles required when implementing the 128-bit finite-body multiplication operation in hardware Since it is possible to perform the finite-body multiplication operation in only 3 cycles, including 1 cycle of outputting a value and 1 cycle of performing an exclusive-OR (XOR) operation on the output data value and returning the result of the finite-body multiplication operation, it is possible to perform the finite-body multiplication operation. It is possible to perform the GCM operation of the delay. Furthermore, as this 128-bit finite-body multiplication operation-based ultra-low-delay GCM operation becomes possible, the low-latency LEA GCM of 10Gbps data to be installed in the encryption transmission equipment that can operate the LEA encryption message authentication function in conjunction with the quantum cryptography QKD It can be seen that the 256-bit authentication encryption operation mode can be efficiently implemented.

Hereinafter, an operation method of the FPGA computing device 200 according to an embodiment of the present invention will be described with reference to FIG. 5 .

Meanwhile, prior to the description, in the first memory 110 , the result of the finite-body multiplication operation between bits between the first data matching the input data A and the second data matching the hash subkey H is set as a fixed value. It is assumed that the data value according to the generation of the hash subkey H is pre-recorded in the lookup table in the second memory 120 and the third memory 130 .

In addition, in the lookup table in the third memory 130 , it is premised that data values are recorded in the form of dividing 128 bits of the entire bit string of the input data A into 16 bundles (#0 to #15) of 8 bits each. do.

First, when the input data (A) is confirmed, the input unit 210 performs a finite field (Galois) multiplication operation on the hash subkey (H) of the bit value of the input data (A) in advance as a data value for each address. It is input as an address value for a lookup table in the third memory 130 (S110-S120).

In this case, the input unit 210 may divide the entire bit string of the input data into two or more bit strings of the same length, and input the bit value of each divided bit string as the address value of the lookup table in the third memory 130 .

For example, 128 bits of the entire bit string of input data (A) is converted into 16 bit strings of 8 bits each (A[7:0], A[15:8],??, A[127:120]). It is possible to divide and input the bit values (0 to 255) of each divided bit string as an address value of a lookup table in the third memory 130 .

In this case, according to an embodiment of the present invention, the data value recorded in the lookup table 30 is 16 bundles of 128 bits of the entire bit string of the input data A in the lookup table 30 (#0~# 15) to consider the recorded form.

Thereafter, the return unit 220 returns the data value output from the lookup table 30 according to the bit value input of the input data A as the result of the finite-body multiplication operation between the input data A and the hash subkey B. Do (S140-S150)

At this time, if the bit values of each of the two or more bit columns divided from the input data A are input, the return unit 220 may input the lookup table in the third memory 130 according to the input of the bit values of the two or more bit columns. An exclusive OR (XOR) operation result for all data values output from , may be returned as a result of a finite-body multiplication operation between the input data (A) and the hash subkey (H).

For example, 128 bits of the entire bit string of input data (A) is converted into 16 bit strings of 8 bits each (A[7:0], A[15:8],??, A[127:120]). If the bit values (0 to 255) of each divided bit string are input as the address value of the lookup table in the third memory 130, each bit string (A[7:0], A[15:8] All of the data values (R0[127:0], R1[127:0], …, R15[127:0]) output from the lookup table 30 for the bit values of , …, A[127:120]) The result of the XOR operation is returned as a result (W) of a finite-body multiplication operation between the input data (A) and the hash subkey (H).

As such, in the operating method of the FPGA arithmetic device 200 according to an embodiment of the present invention, 1 cycles (S110-S130) of inputting the bit value of the input data A as the address value of the memory as the address value of the memory and Includes 1 cycles (S140) in which data values according to address values are output from memory, and 1 cycles (S140-S150) in which an exclusive OR (XOR) operation is performed on the output data values to return the result of finite-body multiplication operation. A finite-body multiplication operation can be performed with only 3 cycles in total.

As described above, according to the method of operation of the FPGA arithmetic unit 200 according to an embodiment of the present invention, the FPGA arithmetic unit 200 has a finite relationship between the fixed hash subkey (H) and the arbitrary input data (A). For the sieve multiplication operation, the pre-calculation method for the hash subkey (H) is applied, the result value is recorded in the memory, and the bit value of the input data (A) is input as the address value of the corresponding memory to obtain the input data (A) A finite field multiplication operation result between and the hash subkey (H) can be output. In this case, 1 cycle of inputting the bit value of the input data (A) as the address value of the memory as the address value of the memory and data according to the address value from the memory compared to the existing 128 cycles required when implementing the 128-bit finite-body multiplication operation in hardware Since it is possible to perform the finite-body multiplication operation in only 3 cycles, including 1 cycle of outputting a value and 1 cycle of performing an exclusive-OR (XOR) operation on the output data value and returning the result of the finite-body multiplication operation, it is possible to perform the finite-body multiplication operation. It is possible to perform the GCM operation of the delay. Furthermore, as this 128-bit finite-body multiplication operation-based ultra-low-delay GCM operation becomes possible, the low-latency LEA GCM of 10Gbps data to be installed in the encryption transmission equipment that can operate the LEA encryption message authentication function in conjunction with the quantum cryptography QKD It can be seen that the 256-bit authentication encryption operation mode can be efficiently implemented.

Meanwhile, the operating method of the FPGA arithmetic device 200 according to an embodiment of the present invention may be implemented in the form of a program command that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, etc. alone or in combination. The program instructions recorded on the medium may be specially designed and configured for the present invention, or may be known and available to those skilled in the art of computer software. Examples of the computer-readable recording medium include magnetic media such as hard disks, floppy disks and magnetic tapes, optical media such as CD-ROMs and DVDs, and magnetic such as floppy disks. - includes magneto-optical media, and hardware devices specially configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. Examples of program instructions include not only machine language codes such as those generated by a compiler, but also high-level language codes that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the present invention, and vice versa.

Although the present invention has been described in detail with reference to preferred embodiments so far, the present invention is not limited to the above-described embodiments, and without departing from the gist of the present invention as claimed in the following claims, the technical field to which the present invention pertains It will be said that the technical idea of the present invention extends to a range where various modifications or modifications can be made by anyone having ordinary knowledge in the present invention.

According to the FPGA arithmetic system, the memory device, and the FPGA arithmetic device according to the present invention, it is possible to effectively reduce the processing delay caused by the finite field (Galois Field) multiplication operation. It is an invention with industrial applicability because the possibility of marketing or business of the applied device, not just the use of the technology, is sufficient and it can be clearly implemented in reality.

100: memory device
110: first memory (ROM)
120: second memory
130: third memory (lookup table)
200: FPGA arithmetic unit
210: input unit 220: return unit

Claims (8)

a memory device in which a result of a Galois Field multiplication operation for a hash subkey (H) is recorded in a memory as a data value for each address; and
Inputting a bit value of input data as an address value to the memory, and returning a data value output from the memory according to the bit value input of the input data as a result of a finite-body multiplication operation between the input data and the hash subkey An FPGA computing system comprising an FPGA computing device. a first memory for recording, as a data value, a result of a Galois Field multiplication operation between the first data matched with the input data and the second data matched with the hash subkey (H) for each bit digit of the input data;
a second memory in which, for each bit digit of the input data, a bit digit of the hash subkey having a bit value of 1 is an address value, and a data value output from the first memory is recorded as a data value for each bit digit of the input data; and
With respect to all bit values that the input data may have, each bit digit where the bit value becomes 1 in the input data is an address value, and the data value output from the second memory is stored in a lookup table (LUT). and a third memory in which a data value of an address identical to a bit value of the input data is written. 3. The method of claim 2,
The first memory is
For each bit position of the input data, the bit value of each bit position in the second data is 1 for a bit string in which the bit value of the same bit position in the first data is set to 1 and the bit value of the remaining bit positions is set to 0 A memory device, characterized in that a result of a finite-body multiplication operation on a bit string in each case is recorded as a data value of each address. 3. The method of claim 2,
The second memory,
For each bit position of the bit string of the input data, when the data value output from the first memory is 2 or more, a result of XOR operation on all of the 2 or more data values is recorded as a data value memory device with 3. The method of claim 2,
The third memory is
In the input data, when each bit digit at which a bit value becomes 1 is 2 or more, a result of XOR operation on all data values of each of the 2 or more bit digit is recorded as a data value. an input unit for inputting a bit value of input data as an address value with respect to a look-up table (LUT) in which a Galois Field multiplication operation result for a hash sub-key (H) is pre-recorded as a data value for each address; and
and a return unit for returning a data value output from the lookup table as a result of a finite-body multiplication operation between the input data and the hash subkey according to the bit value input of the input data. 7. The method of claim 6,
The input unit,
The entire bit string of the input data is divided into two or more bit strings of the same length, and a bit value of each of the two or more bit strings is input as an address value of the lookup table. 8. The method of claim 7,
The return unit,
Returning an exclusive-OR (XOR) operation result on all data values output from the lookup table according to the bit value input of each of the two or more bit columns as a finite-body multiplication operation result between the input data and the hash subkey FPGA computing device characterized by.

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