KR20220130636A - Semiconductor memory device - Google Patents

Abstract

Provided is a semiconductor memory device capable of improving device performance and reliability. The semiconductor memory device comprises: a substrate; a base insulating layer disposed on the substrate; a plurality of electrode layers and a plurality of gate structures alternately stacked on the base insulating layer in a first direction; and a channel structure passing through the plurality of electrode layers and the plurality of gate structures. Each gate structure includes a gate electrode and a ferroelectric layer surrounding the gate electrode. The channel structure includes a semiconductor layer and a filling insulating layer provided in the semiconductor layer to extend in the first direction. The semiconductor layer includes a first region in contact with the electrode layer and a second region in contact with the gate structure. The semiconductor layer includes single crystal silicon (Si). Impurities doped in the first region are the same as those doped in the second region. The concentration of the impurities in the first region is the same as that of the impurities in the second region.

Description

Semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly, to a dynamic random access memory (DRAM) including a ferroelectric.

As semiconductor devices are increasingly highly integrated, individual circuit patterns are becoming more miniaturized in order to implement more semiconductor devices in the same area. That is, as the degree of integration of the semiconductor device increases, the design rules for the components of the semiconductor device are decreasing.

In order to improve the density of DRAM, new materials and new structures have been proposed. In order to improve structural stability and operational reliability, a memory device using a ferroelectric material is being studied.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of improving device performance and reliability.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

One aspect of the semiconductor memory device of the present invention for solving the above problems is a substrate, a base insulating layer disposed on the substrate, a plurality of electrode layers alternately stacked on the base insulating layer in a first direction, and a plurality of a gate structure and a plurality of electrode layers and a channel structure penetrating the plurality of gate structures, each gate structure including a gate electrode and a ferroelectric layer surrounding the gate electrode, the channel structure including a semiconductor layer and a first structure in the semiconductor layer a filling insulating layer extending in one direction, wherein the semiconductor layer includes a first region in contact with the electrode layer and a second region in contact with the gate structure, the semiconductor layer includes single crystal silicon (Si), and the first region The impurity doped in the ? is the same as the impurity doped in the second region, and the concentration of the impurity in the first region is the same as the concentration of the impurity in the second region.

Another aspect of the semiconductor memory device of the present invention for solving the above problems is a substrate, on the substrate, a first insulating layer disposed in a first direction perpendicular to an upper surface of the substrate, on the first insulating layer, alternately A first memory structure including a first electrode layer and a first gate structure stacked with a first memory structure, a second insulation layer disposed on the first memory structure, and a second electrode layer and a second gate alternately stacked on the second insulation layer a second memory structure including the structure and a channel structure penetrating the first memory structure and the second memory structure and the second insulating layer, wherein each of the first gate structure and the second gate structure surrounds the gate electrode and the gate electrode. includes a ferroelectric layer, the channel structure includes a semiconductor layer, and a filling insulating layer extending in the first direction within the semiconductor layer, the semiconductor layer comprising: a first region in contact with the first electrode layer or the second electrode layer; a second region in contact with the first gate structure or the second gate structure, wherein the semiconductor layer includes single crystal silicon (Si), the impurity doped in the first region is the same as the impurity doped in the second region, The concentration of the impurity in the first region is the same as the concentration of the impurity in the second region.

Other specific details of the invention are included in the detailed description and drawings.

1 is a schematic layout diagram of a semiconductor memory device according to some embodiments.
FIG. 2 is a cross-sectional view taken along line A - A of FIG. 1 .
3 is an exemplary circuit diagram of a semiconductor memory device according to some embodiments.
4 is a diagram for describing a semiconductor memory device according to some exemplary embodiments.
5 is a diagram for describing a semiconductor memory device according to some exemplary embodiments.
6 is a diagram for describing a semiconductor memory device according to some exemplary embodiments.
7 to 18 are intermediate steps for explaining a method of manufacturing a semiconductor memory device according to some embodiments.

1 is a schematic layout diagram of a semiconductor memory device according to some embodiments. FIG. 2 is a cross-sectional view taken along line A - A of FIG. 1 .

In the drawings of the semiconductor memory device according to some embodiments, a dynamic random access memory (DRAM) is illustratively illustrated, but the present invention is not limited thereto.

1 and 2 , the semiconductor memory device may include a substrate 100 , a base insulating layer 105 , an electrode layer 110 , a gate structure GS, and a channel structure CH.

The substrate 100 may be a silicon substrate or a silicon-on-insulator (SOI). Alternatively, the substrate 100 may include, but is not limited to, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. .

The base insulating layer 105 may be disposed on the substrate 100 . The base insulating layer 105 may extend in the third direction D3 or the second direction D2 along the upper surface 100US of the substrate 100 . The base insulating layer 105 may include, for example, at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, but is not limited thereto.

In some embodiments, a peripheral logic structure may be included between the substrate 100 and the base insulating layer 105 . The peripheral logic structure may include, for example, a transistor, but is not limited thereto. For example, the peripheral logic structure may include not only various active elements such as transistors, but also various passive elements such as capacitors, resistors, and inductors. .

The electrode layer 110 may include first to fifth electrode layers 110a, 110b, 110c, 110d, and 110e. The electrode layer 110 may be disposed on the base insulating layer 105 . Each of the electrode layers 110 may be disposed to be spaced apart from each other in the first direction D1 on the base insulating layer 105 . The first direction D1 may be a direction perpendicular to the upper surface 100US of the substrate 100 . A portion of the electrode layer 110 may contact the channel structure CH in the second direction D2 and/or the third direction D3 . The electrode layer 110 is illustrated as being five, but is not limited thereto. For example, there may be six or more electrode layers 110 .

The electrode layer 110 is illustrated in a circular shape in a plan view, but is not limited thereto. For example, the electrode layer 110 may have a rectangular shape in a plan view. In this case, one end of the first to fifth electrode layers 110a, 110b, 110c, 110d, and 110e may be stacked in a sequentially protruding step shape.

The electrode layer 110 may include a conductive material. The electrode layer 110 may be formed of, for example, tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), or iridium oxide (IrO). ), tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), tungsten carbide (WC), titanium carbide (TiC), tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide (RuO) or two thereof It may include a combination of the above, but is not limited thereto.

The gate structure GS may be disposed on the electrode layer 110 . The gate structure GS may be spaced apart from each other in the first direction D1 . The gate structure GS may be alternately stacked with the electrode layer 110 in the first direction D1 . In other words, the gate structure GS may be disposed between the electrode layers 110 in the first direction D1 . For example, the gate structure GS may be disposed between the first electrode layer 110a and the second electrode layer 110b.

A portion of the gate structure GS may contact the channel structure CH in the second direction D2 and/or the third direction D3 . Although the gate structure GS is illustrated as having four, it is not limited thereto. For example, when the number of gate structures GS is N, the number of electrode layers 110 may be N+1, and the number of electrode layers 110 may be greater than N+1.

The gate structure GS may include a gate electrode 130 and a ferroelectric layer 140 . In some embodiments, the gate structure GS may further include a buffer layer 135 .

The buffer layer 135 may surround the gate electrode 130 and the ferroelectric layer 140 . The buffer layer 135 may contact the electrode layer 110 in the second direction D2 and the third direction D3 . The buffer layer 135 may extend in the second direction D2 and the third direction D3 along the surface of the electrode layer 110 . The buffer layer 135 may directly contact the channel structure CH in the first direction D1 . In this case, the ferroelectric layer 140 does not directly contact the channel structure CH. Here, the term "direct contact" means that another component is not interposed between one component and another component, and that one component and another component are in contact.

The buffer layer 135 may be an insulating layer that electrically insulates the gate electrode 130 and the electrode layer 110 . The buffer layer 135 may include an insulating material. The buffer layer 135 may include, for example, at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer, but is not limited thereto.

Although the buffer layer 135 is illustrated as being formed of one insulating layer, it is only for convenience of description and is not limited thereto. For example, the buffer layer 135 may include an insulating layer and a high-k layer.

The ferroelectric layer 140 may be disposed between the gate electrode 130 and the buffer layer 135 . In other words, the channel structure CH, the buffer layer 135 , the ferroelectric layer 140 , and the gate electrode 130 in the second direction D2 and/or the third direction D3 with the channel structure CH as the center. ) may be sequentially arranged. Since the buffer layer 135 is disposed between the ferroelectric layer 140 and the electrode layer 110 , the ferroelectric layer 140 may not directly contact the electrode layer 110 . Since the buffer layer 135 is disposed between the ferroelectric layer 140 and the channel structure CH, the ferroelectric layer 140 may not directly contact the channel structure CH.

The ferroelectric layer 140 may store the residual polarization generated in the ferroelectric layer 140 by the polarization write voltage applied between the gate electrode 130 and the channel structure CH. By the stored residual polarization, signal information can be stored non-volatile. That is, the ferroelectric layer 140 may function as a non-volatile memory layer.

The ferroelectric layer 140 may include, for example, hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination thereof. In addition, the ferroelectric layer 140 may include, for example, a ferroelectric material having a perovskite structure, such as PZT (PbZrxTi1-xO3), BaTiO3, PbTiO3, or the like. The ferroelectric layer 140 includes carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), nitrogen (N), germanium (Ge), tin (Sn), and strontium (Sr). , lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Gd), and may include at least one dopant selected from lanthanum (La). The ferroelectric layer 140 may be formed of crystalline material. For example, the ferroelectric layer 140 may have an orthorhombic system crystal structure.

The gate electrode 130 may be disposed on the ferroelectric layer 140 . The gate electrode 130 may include a conductive material. For example, the gate electrode 130 includes at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a conductive metal silicide, a doped semiconductor material, a conductive metal oxynitride, and a conductive metal oxide. can do. The cell gate electrode 112 is, for example, TiN, TaC, TaN, TiSiN, TaSiN, TaTiN, TiAlN, TaAlN, WN, Ru, TiAl, TiAlC-N, TiAlC, TiC, TaCN, W, Al, Cu, Co , Ti, Ta, Ni, Pt, Ni-Pt, Nb, NbN, NbC, Mo, MoN, MoC, WC, Rh, Pd, Ir, Ag, Au, Zn, V, RuTiN, TiSi, TaSi, NiSi, CoSi , IrO, RuO, and combinations thereof, but is not limited thereto.

The channel structure CH may pass through the gate structure GS and the electrode layer 110 . The channel structure CH may penetrate the base insulating layer 105 . The channel structure CH may extend in the first direction D1 . A side surface of the channel structure CH may contact the electrode layer 110 and the gate structure GS. A lower portion of the channel structure CH may contact the upper surface 100US of the substrate 100 .

The channel structure CH may include a semiconductor layer 160 and a filling insulating layer 165 .

The semiconductor layer 160 may include single crystal silicon (Si), polycrystalline silicon, or the like. In some embodiments, the semiconductor layer 160 may be single crystal silicon. In this case, the semiconductor layer 160 may be formed by annealing the polysilicon layer. In some embodiments, the semiconductor layer 160 may be doped with an n-type impurity or a p-type impurity. In this case, the concentration of the n-type impurity or the p-type impurity doped in the semiconductor layer 160 may be 1E19 (/cm3) or more.

In an embodiment, the semiconductor layer 160 may have a thickness W1 in the third direction D3. In another embodiment, the semiconductor layer 160 may have a thickness W1 in the second direction D2 . The thickness W1 of the semiconductor layer 160 may be 25 nm or less.

The semiconductor layer 160 may include a first region R1 in contact with the electrode layer 110 . The semiconductor layer 160 may include a second region R2 in contact with the gate structure GS. The first region R1 may be a source/drain region in the semiconductor memory device. The second region R2 may be a channel region in the semiconductor memory device. The impurity doped in the first region R1 is the same as the impurity doped in the second region R2 . The concentration of the impurity in the first region R1 may be the same as the concentration of the impurity in the second region R2 .

Since the first region R1 and the second region R2 of the semiconductor layer 160 are doped with the same type of impurity, they may function as a junctionless transistor. Here, the junctionless transistor refers to a transistor in which a pn junction does not exist at the boundary of the transistor because the source/drain region and the channel region are doped with the same impurity, unlike a conventional NPN junction transistor. Accordingly, the semiconductor device does not have a difference in doping concentration between the source/drain and the channel, so the electric field at the junction between the source and the channel and between the drain and the channel is relatively weaker than when using the conventional junction transistor, so impact ionization or The effect of Gate Induced Drain Leakage (GIDL) is small.

The filling insulating layer 165 may be disposed in the semiconductor layer 160 . The filling insulating layer 165 may extend in the first direction D1 . The filling insulating layer 165 may be surrounded by the semiconductor layer 160 . A semiconductor layer 160 may be disposed between the filling insulating layer 165 and the base insulating layer 105 . The filling insulating layer 165 may include an insulating material. The filling insulating layer 165 may include, for example, at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer, but is not limited thereto.

3 is an exemplary circuit diagram of a semiconductor memory device according to some embodiments.

3 is an exemplary circuit diagram of the semiconductor memory device of FIG. 2 . An operation of the semiconductor memory device will be described with reference to FIGS. 2 and 3 .

In FIG. 3 , the first to fourth unit memory cells UC1 , UC2 , UC3 , and UC4 each include corresponding ferroelectric layers F1 , F2 , F3 and F4 and gate electrodes G1 , G2 , G3 and G4 respectively. It may be a ferroelectric memory device in the form of a transistor. The first and second unit memory cells UC1 and UC2 share the source electrode S1 and may include separate drain electrodes DR1 and DR2, respectively. The third and fourth unit memory cells UC3 and UC4 share the source electrode S2 and may include separate drain electrodes DR2 and DR3, respectively. In this case, the source electrodes S1 and S2 may be connected to the ground line, and the drain electrodes DR1 , DR2 and DR3 may be connected to the bit line BL. The gate electrodes G1, G2, G3, and G4 may be connected to different word lines. Accordingly, separate gate voltages may be applied to the gate electrodes G1, G2, G3, and G4, respectively.

The unit memory cells UC1, UC2, UC3, and UC4 have source electrodes S1, S2 and drain electrodes D1, D2, and D3, respectively, and are applied to the corresponding gate electrodes G1, G2, G3, and G4. By independently controlling the gate voltage to be applied, it is possible to individually access the signal information stored in the ferroelectric layers F1, F2, F3, and F4. That is, the semiconductor memory device may implement a random access operation for the unit memory cells UC1 , UC2 , UC3 , and UC4 .

In order to perform a write operation on the unit memory cells UC1, UC2, UC3, and UC4, write to a part of the ferroelectric layer F1, F2, F3, F4 corresponding to the unit memory cells UC1, UC2, UC3, UC4. A voltage may be applied. The write voltage may be applied, for example, by applying an appropriate voltage to the corresponding word line and the corresponding bit line BL. In the write operation of the unit memory cells UC1, UC2, UC3, and UC4, a predetermined write voltage is applied to the word line to implement different residual polarizations in the ferroelectric layers F1, F2, F3, and F4, and A process of storing the residual polarization as signal information may be performed.

In order to perform a read operation on the unit memory cells UC1 , UC2 , UC3 , and UC4 , a read voltage (eg, a voltage between a low threshold voltage and a high threshold voltage) is applied to the corresponding word line. The read operation of the unit memory cells UC1, UC2, UC3, UC4 uses the property that the threshold voltage of the field effect transistor changes according to the size or orientation of the residual polarization stored in the ferroelectric layer F1, F2, F3, F4. can be performed.

Referring back to FIG. 2 , in some embodiments, the first electrode layer 110a , the third electrode layer 110c , and the fifth electrode layer 110e may be drain electrodes. The second electrode layer 110b and the fourth electrode layer 110d may be source electrodes. In this case, the first electrode layer 110a, the third electrode layer 110c, and the fifth electrode layer 110e may be connected to the bit line BL. The second electrode layer 110b and the fourth electrode layer 110d may be connected to a ground line.

4 is a diagram for describing a semiconductor memory device according to some exemplary embodiments. For convenience of description, points different from those described in FIGS. 1 and 2 will be mainly described.

Referring to FIG. 4 , the channel structure CH may include a semiconductor layer 160 and a filling insulating layer 165 .

The semiconductor layer 160 may penetrate the electrode layer 110 and the gate structure GS. The semiconductor layer 160 may be disposed on the base insulating layer 105 . The semiconductor layer 160 may contact the upper surface 105US of the base insulating layer 105 . The semiconductor layer 160 may not contact the substrate 100 .

The filling insulating layer 165 may be disposed in the semiconductor layer 160 . The filling insulating layer 165 may extend in the first direction D1 . One end of the filling insulating layer 165 may contact the base insulating layer 105 .

5 is a diagram for describing a semiconductor memory device according to some exemplary embodiments. 5 is a cross-sectional view taken along line A - A of FIG. 1 .

Referring to FIG. 5 , the semiconductor memory device may include a substrate 200 , a first insulating layer 205 , a second insulating layer 215 , a first memory structure MS1 , and a second memory structure MS2 . have.

The substrate 200 may be a silicon substrate or a silicon-on-insulator (SOI). Alternatively, the substrate 200 may include, but is not limited to, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. .

The first insulating layer 205 may be disposed on the substrate 200 . The first insulating layer 205 may extend in the second direction D2 or the third direction D3 along the upper surface 200US of the substrate 200 . The first insulating layer 205 may include, for example, at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, but is not limited thereto.

The first memory structure MS1 may be disposed on the first insulating layer 205 . The first memory structure MS1 may include a first electrode layer 210 and a first gate structure GS1 .

The first electrode layers 210 may be spaced apart from each other in the first direction D1 . The first electrode layer 210 may be disposed on the first insulating layer 205 . The first gate structure GS1 may be alternately stacked with the first electrode layer 210 . In other words, the first electrode layer 210 may be disposed on the bottom and top of the first memory structure MS1 , and the first gate structure GS1 may be disposed between the first electrode layers 210 . A portion of the first electrode layer 210 may contact the channel structure CH in the second direction D2 and/or the third direction D3 .

The first electrode layer 210 may include a conductive material. The first electrode layer 210 may include, for example, tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), or iridium oxide. (IrO), tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), tungsten carbide (WC), titanium carbide (TiC), tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide (RuO) or these It may include a combination of two or more of, but is not limited thereto

2 and 5 , the description of the first gate structure GS1 may be similar to the description of the gate structure GS of FIG. 2 . The first gate structure GS1 may include a first gate electrode 230a, a first ferroelectric layer 240a, and a first buffer layer 235a. The first gate electrode 230a corresponds to the gate electrode 130, the first ferroelectric layer 240a corresponds to the ferroelectric layer 140, and the first buffer layer 235a corresponds to the buffer layer 135, respectively. may be similar. Hereinafter, the first gate structure GS1 will be described with a focus on points different from the description of the gate structure GS.

The number of the first gate structures GS1 is less than the number of the first electrode layers 210 . Although it is illustrated that there are two first gate structures GS1, the present invention is not limited thereto. For example, when the number of the first gate structures GS1 is N, the number of the first electrode layers 210 may be N+1.

The second insulating layer 215 may be disposed on the first memory structure MS1 . The second insulating layer 215 may be disposed between the first memory structure MS1 and the second memory structure MS2 . Specifically, the second insulating layer 215 is formed between the first electrode layer 210c disposed at the uppermost portion of the first memory structure MS1 and the second electrode layer 220a disposed at the lowermost portion of the second memory structure MS2. can be placed in The second insulating layer 215 may electrically insulate the first memory structure MS1 and the second memory structure MS2 .

The second insulating layer 215 may include an insulating material. The second insulating layer 215 may include, for example, at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer, but is not limited thereto.

The first memory structure MS1 may be disposed on the first insulating layer 205 . The first memory structure MS1 may include a first electrode layer 210 and a first gate structure GS1 .

The second memory structure MS2 may be disposed on the second insulating layer 215 . The second memory structure MS2 may include a second electrode layer 220 and a second gate structure GS2 . The description of the second gate structure GS2 may be the same as the description of the first gate structure GS1 .

The second electrode layers 220 may be disposed to be spaced apart from each other in the first direction D1 . The second electrode layer 220 may be disposed on the second insulating layer 215 . The second gate structure GS2 may be alternately stacked with the second electrode layer 220 . In other words, the second electrode layer 220 may be disposed on the bottom and top of the second memory structure MS2 , and the second gate structure GS2 may be disposed between the second electrode layers 220 . A portion of the second electrode layer 220 may contact the channel structure CH in the second direction D2 and/or the third direction D3 .

The second electrode layer 220 may include a conductive material. A material of the second electrode layer 220 may be the same as that of the first electrode layer 210 .

The second gate structure GS1 may include a second gate electrode 230b, a second ferroelectric layer 240b, and a second buffer layer 235b. A description of the second gate structure GS2 may be similar to a description of the first gate structure GS1 .

The channel structure CH may pass through the first insulating layer 205 , the second insulating layer 215 , the first memory structure MS1 , and the second memory structure MS2 . The channel structure CH may extend in the first direction D1 . A side surface of the channel structure CH may contact the first electrode layer 210 , the first gate structure GS1 , the second electrode layer 220 , and the second gate structure GS2 . A lower portion of the channel structure CH may contact the upper surface 200US of the substrate 200 .

The channel structure CH may include a semiconductor layer 260 and a filling insulating layer 265 . The semiconductor layer 260 may include single crystal silicon, polycrystalline silicon, or the like. In some embodiments, the semiconductor layer 260 may be single crystal silicon. In this case, the semiconductor layer 260 may be formed by annealing the polysilicon layer. In some embodiments, the semiconductor layer 260 may be doped with an n-type impurity or a p-type impurity. In this case, the concentration of the n-type impurity or the p-type impurity doped in the semiconductor layer 260 may be 1E19 (/cm3) or more.

In an embodiment, the semiconductor layer 260 may have a thickness W2 in the third direction D3 . In another embodiment, the semiconductor layer 260 may have a thickness W2 in the second direction D2 . The thickness W2 of the semiconductor layer 260 may be 25 nm or less.

The semiconductor layer 260 may include a third region R3 in contact with the first electrode layer 210 or the second electrode layer 220 . The semiconductor layer 260 may include a fourth region R4 in contact with the first gate structure GS1 or the second gate structure GS2 . The third region R3 may be a source/drain region in the semiconductor memory device. The fourth region R4 may be a channel region in the semiconductor memory device. The impurity doped in the third region R3 is the same as the impurity doped in the fourth region R4 . The concentration of the impurity in the third region R3 may be the same as the concentration of the impurity in the fourth region R4 .

Since the third region R3 and the fourth region R4 of the semiconductor layer 260 are doped with the same type of impurity, they may function as a junctionless transistor. The junctionless transistor is the same as described above with reference to FIG. 2 .

The filling insulating layer 265 may be disposed in the semiconductor layer 260 . The filling insulating layer 265 may extend in the first direction D1 . The filling insulating layer 265 may be surrounded by the semiconductor layer 260 . A semiconductor layer 260 may be disposed between the filling insulating layer 265 and the first insulating layer 205 . The filling insulating layer 165 may include an insulating material. The filling insulating layer 265 may include, for example, at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer, but is not limited thereto.

6 is a diagram for describing a semiconductor memory device according to some exemplary embodiments. For convenience of explanation, points different from those described with reference to FIGS. 1 to 5 will be mainly described.

Referring to FIG. 6 , the channel structure CH may be disposed on the first insulating layer 205 . The semiconductor layer 260 may pass through the second insulating layer 215 , the first memory structure MS1 , and the second memory structure MS2 . The semiconductor layer 260 may not penetrate the first insulating layer 205 . The semiconductor layer 260 may contact the upper surface 205US of the first insulating layer 205 . The semiconductor layer 260 may not contact the substrate 200 .

The filling insulating layer 265 may be disposed in the semiconductor layer 260 . The filling insulating layer 265 may extend in the first direction D1 . One end of the filling insulating layer 265 may contact the first insulating layer 205 .

7 to 18 are intermediate steps for explaining a method of manufacturing a semiconductor memory device according to some embodiments.

Referring to FIG. 7 , a substrate 100 may be provided. The substrate 100 may be a silicon substrate or a silicon-on-insulator (SOI). Alternatively, the substrate 100 may include, but is not limited to, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. .

A base insulating layer 105 may be formed on the substrate 100 . The base insulating layer 105 may include, for example, at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The base insulating layer 105 may be formed by, for example, a coating method, a chemical vapor deposition method, or an atomic layer deposition method.

Although not shown, in some embodiments, a peripheral logic structure may be included between the substrate 100 and the base insulating layer 105 . The peripheral logic structure may include, for example, an active element such as a transistor, and various passive elements such as a capacitor and an inductor.

Referring back to FIG. 7 , the first sacrificial layer SCL1 and the second sacrificial layer SCL2 may be alternately stacked on the base insulating layer 105 in the third direction. The first sacrificial layer SCL1 and the second sacrificial layer SCL2 may have an etch selectivity. As an example, when the first sacrificial layer SCL1 includes an oxide, the second sacrificial layer SCL2 may include a nitride or silicon. As another example, when the first sacrificial layer SCL1 includes nitride, the second sacrificial layer SCL2 may include oxide or silicon. As another example, when the first sacrificial layer SCL1 includes silicon, the second sacrificial layer SCL2 may include an oxide or nitride.

Referring to FIG. 8 , a first trench T1 penetrating through the base insulating layer 105 , the first sacrificial layer SCL1 , and the second sacrificial layer SCL2 may be formed on the substrate 100 . . The base insulating layer 105 , the first sacrificial layer SLC1 , and the second sacrificial layer SLC2 may be exposed along the sidewall surface of the first trench T1 . The substrate 100 may be exposed along the bottom surface of the first trench T1 . The first trench T1 may have a cylindrical shape, but is not limited thereto. For example, the first trench T1 may have a shape of a quadrangular prism. The first trench T1 may be formed by an anisotropic etching method.

Referring to FIG. 9 , a free semiconductor layer 160P may be formed along sidewalls and a lower surface of the first trench T1 . The free semiconductor layer 160P may be formed on the first sacrificial layer SCL1 , the second sacrificial layer SCL2 , the base insulating layer 105 , and the substrate 100 . The free semiconductor layer 160P may include polycrystalline silicon (Si). The free semiconductor layer 160P may be doped with an n-type impurity or a p-type impurity. The concentration of the n-type impurity or the p-type impurity doped in the free semiconductor layer 160P may be 1E19 (/cm3) or more. The free semiconductor layer 160P may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). In this case, a second trench T2 may be formed in the free semiconductor layer 160P. The second trench T2 may be defined by the free semiconductor layer 160P.

Referring to FIG. 10 , a heat conductive layer TCL may be formed on the first sacrificial layer SCL1 disposed on the uppermost part of the second trench T2 and the first sacrificial layer SCL1 . The thermal conductive layer TCL may include a material having high thermal conductivity. The heat conductive layer TCL may include, for example, titanium nitride (TiN). The heat conductive layer TCL may cover the free semiconductor layer 160P and the uppermost first sacrificial layer SCL1 . The thermal conductive layer TCL may be formed by a chemical vapor deposition method or an atomic layer deposition method.

Referring to FIG. 11 , a laser 10 may be irradiated to the heat conductive layer TCL to perform a laser annealing process. Since the heat conductive layer TCL is in direct contact with the free semiconductor layer 160P, heat applied to the heat conductive layer TCL may be conducted to the free semiconductor layer 160P through the laser annealing process. The free semiconductor layer 160P may be recrystallized by the conducted heat to form the semiconductor layer 160 . Specifically, polycrystalline silicon in the free semiconductor layer 160P may be recrystallized into single crystal silicon.

Referring to FIG. 12 , the heat conductive layer TCL may be removed. The heat conductive layer TCL may be removed by an etching process. When the thermal conductive layer TCL includes titanium nitride, chlorine (Cl ₂ ) may be used in the etching process. After the etching process is performed, the semiconductor layer 160 may be exposed. Also, a third trench T3 may be formed in the semiconductor layer 160 . The third trench T3 may be defined by the semiconductor layer 160 .

Referring to FIG. 13 , the filling insulating layer 165 may be formed by filling the inside of the third trench T3 with an insulating material. As a method of filling the inside of the third trench T3 with the insulating material, for example, a chemical vapor deposition method, an atomic layer deposition method, or the like may be applied. In this case, the insulating material may be formed outside the third trench T3 . By selectively removing the insulating material formed on the outside, the filling insulating layer 165 may be formed. The filling insulating layer 165 may include oxide, nitride, or oxynitride.

Referring to FIG. 14 , the first sacrificial layer SCL1 may be selectively removed. Accordingly, the semiconductor layer 160 may be selectively exposed. The first sacrificial layer SCL1 may be removed by wet etching using an etch selectivity between the first sacrificial layer SLC1 and the second sacrificial layer SCL2 . As a result, unlike the first sacrificial layer SLC1 , the second sacrificial layer SCL2 may remain.

Referring to FIG. 15 , the electrode layer 110 may be formed in the space of the first sacrificial layer SCL1 removed in FIG. 14 . The electrode layer 110 may include a conductive material. The electrode layer 110 is, for example, tungsten, titanium, copper, aluminum, ruthenium, platinum, iridium, iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, It may include ruthenium oxide or a combination of two or more thereof. The electrode layer 110 may have an etch selectivity with the second sacrificial layer SCL2 . The electrode layer 110 may be formed by, for example, a chemical vapor deposition method or an atomic layer deposition method.

Referring to FIG. 16 , the second sacrificial layer SLC2 may be selectively removed. Accordingly, the semiconductor layer 160 may be selectively exposed. The second sacrificial layer SCL2 may be removed by wet etching using an etch selectivity between the second sacrificial layer SLC2 and the electrode layer 110 . As a result, unlike the second sacrificial layer SLC2 , the electrode layer 110 may remain.

Referring to FIG. 17 , a buffer layer 135 may be formed in a space from which the second sacrificial layer SCL2 of FIG. 16 is removed. The second sacrificial layer SCL2 may be removed and formed on the exposed electrode layer 110 and the semiconductor layer 160 . The buffer layer 135 may be formed by, for example, an atomic layer deposition method.

Subsequently, the ferroelectric layer 140 may be formed on the buffer layer 135 . The ferroelectric layer 140 may include, for example, hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination thereof. In addition, the ferroelectric layer 140 may include, for example, a ferroelectric material having a perovskite structure, such as PZT (PbZrxTi1-xO3), BaTiO3, PbTiO3, or the like. The ferroelectric layer 140 includes carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), nitrogen (N), germanium (Ge), tin (Sn), and strontium (Sr). , lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Gd), and may include at least one dopant selected from lanthanum (La). The ferroelectric layer 140 may be formed of crystalline material. For example, the ferroelectric layer 140 may have an orthorhombic system crystal structure.

The ferroelectric layer 140 may be formed by, for example, an atomic layer deposition method. In one embodiment, the ferroelectric layer 140 may be formed in a crystalline state. In another embodiment, after forming the ferroelectric layer 140 in an amorphous state, it may be converted to a crystalline state through a crystallization heat treatment.

Referring to FIG. 18 , the gate electrode 130 may be formed on the ferroelectric layer 140 to form a gate structure GS. The gate electrode 130 may include a conductive material. The material of the gate electrode 130 is the same as described above for the gate electrode 130 of FIG. 2 .

Although the embodiments of the present invention have been described with reference to the accompanying drawings, those of ordinary skill in the art to which the present invention pertains can realize that the present invention can be embodied in other specific forms without changing its technical spirit or essential features. you will be able to understand Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

100: substrate 105: base insulating layer
110: electrode layer 130: gate electrode
135: buffer layer 140: ferroelectric layer
160: semiconductor layer 165: filling insulating layer
GS: gate structure CH: channel structure
R1: first region R2: second region

Claims (10)

Board;
a base insulating layer disposed on the substrate;
a plurality of electrode layers and a plurality of gate structures alternately stacked on the base insulating layer in a first direction; and
A channel structure penetrating the plurality of electrode layers and the plurality of gate structures,
Each of the gate structures includes a gate electrode and a ferroelectric layer surrounding the gate electrode,
The channel structure includes a semiconductor layer and a filling insulating layer extending in the first direction in the semiconductor layer,
The semiconductor layer includes a first region in contact with the electrode layer and a second region in contact with the gate structure,
The semiconductor layer includes single crystal silicon (Si),
The impurity doped in the first region is the same as the impurity doped in the second region,
and a concentration of the impurity in the first region is the same as a concentration of the impurity in the second region. The method of claim 1,
A thickness of the semiconductor layer in a second direction perpendicular to the first direction is 25 nm or less. The method of claim 1,
and impurity doping concentrations of the first region and the second region are greater than or equal to 1E19 (/cm ³ ). The method of claim 1,
The electrode layer is
A semiconductor memory device comprising: a source electrode layer; and a drain electrode layer spaced apart from the source electrode layer in the first direction. 5. The method of claim 4,
The source electrode layer is connected to a ground line,
wherein the drain electrode layer is connected to a bit line. The method of claim 1,
and the filling insulating layer is in direct contact with the base insulating layer. The method of claim 1,
The gate structure is
The semiconductor memory device, disposed on the electrode layer, further comprising a buffer layer surrounding the dielectric layer. The method of claim 1,
The ferroelectric layer is
Carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), nitrogen (N), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), A semiconductor memory device comprising at least one dopant selected from calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Gd), hafnium (Hf), and lanthanum (La). Board;
a first insulating layer disposed on the substrate in a first direction perpendicular to an upper surface of the substrate;
a first memory structure including first electrode layers and a first gate structure alternately stacked on the first insulating layer;
a second insulating layer disposed on the first memory structure;
a second memory structure including second electrode layers and second gate structures alternately stacked on the second insulating layer; and
a channel structure penetrating the first memory structure, the second memory structure, and a second insulating layer;
Each of the first gate structure and the second gate structure includes a gate electrode and a ferroelectric layer surrounding the gate electrode,
The channel structure includes a semiconductor layer and a filling insulating layer extending in the first direction in the semiconductor layer,
The semiconductor layer includes a first region in contact with the first electrode layer or the second electrode layer, and a second region in contact with the first gate structure or the second gate structure,
The semiconductor layer includes single crystal silicon (Si),
The impurity doped in the first region is the same as the impurity doped in the second region,
and a concentration of the impurity in the first region is the same as a concentration of the impurity in the second region. The method of claim 1,
The thickness of the semiconductor layer in a second direction perpendicular to the first direction is 25 nm or less,
and impurity doping concentrations of the first region and the second region are equal to or greater than 1E19 (/cm3).

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