KR20220127716A - Electronic device - Google Patents

Abstract

An electronic device includes: an electronic module; a display panel that is divided into a first region including a display region, a wiring region, and a transmission region, and a second region adjacent to the first region, and that includes a base layer, a light blocking layer disposed on the base layer, a plurality of insulating layers disposed on the base layer, a first pixel disposed in the first region, and a second pixel disposed in the second region display panel; and an input sensor disposed on the display panel and including sensing insulating layers. The electronic module overlaps the first region. The light blocking layer overlaps the display region and the wiring region and does not overlap the transmission region.

Description

Electronic device {ELECTRONIC DEVICE}

The present invention relates to an electronic device, and to an electronic device including a region having improved transmittance.

The electronic device is activated according to an electrical signal. The electronic device may include devices composed of various electronic components, such as a display unit that displays an image or a sensing unit that senses an external input. Electronic components may be electrically connected to each other by variously arranged signal lines.

An object of the present invention is to provide an electronic device including a region having improved transmittance in an active region.

The electronic device is divided into a first area including a display area, a wiring area, and a transmission area, and a second area adjacent to the first area, and includes a base layer, a barrier layer disposed on the base layer, and the barrier layer a display panel including a light blocking layer disposed thereon, a plurality of insulating layers disposed on the base layer, a first pixel disposed in the first area, and a second pixel disposed in a second area, and the display an input sensor disposed on a panel and including sensing insulating layers, wherein the first region has a relatively higher light transmittance than the second region, and the light blocking layer overlaps the display region and the wiring region and non-overlapping the transmissive region.

In a plan view, the transmissive area may be surrounded by the display area and the wiring area.

The display panel may include a circuit element layer including the base layer, the barrier layer, the light blocking layer, a buffer layer disposed on the barrier layer, the insulating layers, and transistors disposed between the insulating layers, the transistor a light emitting diode including a first electrode and a second electrode connected to each other, and a light emitting layer disposed between the first electrode and the second electrode, and a pixel defining layer having an opening exposing at least a portion of the first electrode defined a display element layer comprising: a thin film encapsulation layer covering the display element layer, the thin film encapsulation layer including a first inorganic layer, a second inorganic layer, and an organic layer disposed between the first inorganic layer and the second inorganic layer It can be characterized as

The insulating layers include first to seventh insulating layers, and any one of the transistors is disposed on the buffer layer and covered by the first insulating layer, and includes a first active including polysilicon. a first semiconductor pattern disposed on the first insulating layer, covered by the second insulating layer, and a first gate overlapping the first active layer, disposed on the second insulating layer and formed on the third insulating layer and an upper electrode overlapping the first gate, wherein the other of the transistors is disposed on the third insulating layer and covered by the fourth insulating layer, the third insulating layer including a metal oxide A second semiconductor pattern including two actives, a second gate disposed on the fourth insulating layer, covered by the fifth insulating layer, and overlapping the second actives may be included.

a first connection electrode disposed on the fifth insulating layer, covered by the sixth insulating layer, and connected to the transistors through a first contact hole defined through the first to fifth insulating layers; a first electrode disposed on the sixth insulating layer, covered by the seventh insulating layer, and connecting between the first electrode and the first connection electrode through a second contact hole defined through the sixth insulating layer 2 It may be characterized in that it further comprises a connection electrode.

The wiring region may include a first gate line disposed on the first insulating layer and branched from the first gate, an upper electrode line disposed on the second insulating layer and branched from the upper electrode, and the fourth a second gate line disposed on the insulating layer and branched from the second gate, a first connection electrode line disposed on the fifth insulating layer and branched from the first connection electrode, and on the sixth insulating layer and a second connection electrode line branched from the second connection electrode.

The transmission region may overlap the base layer, the barrier layer, the buffer layer, the sixth insulating layer, the first inorganic layer, the organic layer, and the second organic layer.

The display area may further include a protective pattern adjacent to the transmissive area, disposed on at least one of the sixth insulating layer and the seventh insulating layer, and including a metal.

The display device may further include a black matrix overlapping the pixel defining layer and disposed on the input sensor, a color filter overlapping the emission layer, and an overcoat layer covering the color filter.

The sensing insulating layers may overlap the first region and the second region.

Among the overcoat layers, an overcoat layer overlapping the transmission region may be in contact with any one of the sensing insulating layers.

Among the black matrices, a portion of an upper surface of the black matrix adjacent to the transmission region may be covered by the overcoat layer.

The pixel defining layer may have a black color.

It may further include an additional light blocking layer disposed in the second region.

The light blocking layer may have a shape in which a plurality of holes exposing a portion of the barrier layer are patterned.

Each of the first pixel and the second pixel includes a plurality of sub-pixels providing light of first to third colors, and the arrangement of the sub-pixels included in the first pixel and the second pixel is different from each other. can be characterized as being different.

Each of the first pixel and the second pixel includes a plurality of sub-pixels providing light of the first to third colors, and the area between the sub-pixels providing the same light is equal to that of the first pixel. It may be characterized in that it is larger than the second pixel.

The transmissive area may be surrounded by the wiring area and the display area.

The transmission region may be characterized in that it has a cross shape.

An electronic module overlapping the first region and disposed under the display panel, wherein the electronic module includes at least one of a sound output module, a light emitting module, a light receiving module, and a camera module can do.

The electronic device according to the present invention may provide a display module having improved light transmittance. Accordingly, even when the electronic module is disposed inside the active region, it is possible to provide an electronic device with improved performance of the electronic module.

1 is a perspective view of an electronic device according to an embodiment of the present invention.
2A is an exploded perspective view of an electronic device according to an embodiment of the present invention.
2B is a block diagram of an electronic device according to an embodiment of the present invention.
3 is an equivalent circuit diagram of a pixel according to an exemplary embodiment of the present invention.
4 is a plan view of an active region according to an embodiment of the present invention.
FIG. 5 is a cross-sectional view taken along line I-I' of FIG. 4 .
6 is a cross-sectional view taken along II-II' of FIG. 4 .
7 is a cross-sectional view taken along line III-III' of FIG. 4 .
8 is a cross-sectional view of an active region according to an embodiment of the present invention.
9 is a cross-sectional view of an active region according to an embodiment of the present invention.
10 is a cross-sectional view of an active region according to an embodiment of the present invention.
11 is a plan view of an active region according to an embodiment of the present invention.
12 is a plan view of an active region according to an embodiment of the present invention.

In this specification, when an element (or region, layer, portion, etc.) is referred to as being “on,” “connected to,” or “coupled to” another element, it is placed/directly placed on the other element. It means that it can be connected/coupled or a third component can be placed between them.

Like reference numerals refer to like elements. In addition, in the drawings, thicknesses, ratios, and dimensions of components are exaggerated for effective description of technical content. “and/or” includes any combination of one or more that the associated elements may define.

Terms such as first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component. The singular expression includes the plural expression unless the context clearly dictates otherwise.

In addition, terms such as "below", "below", "above", and "upper side" are used to describe the relationship between the components shown in the drawings. The above terms are relative concepts, and are described with reference to directions indicated in the drawings.

Terms such as “comprise” or “have” are intended to designate that a feature, number, step, operation, component, part, or combination thereof described in the specification is present, and includes one or more other features, number, or step. , it should be understood that it does not preclude in advance the possibility of the presence or addition of an operation, component, part, or combination thereof.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. In addition, terms such as terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related art, and unless explicitly defined herein, it should be interpreted in a too idealistic or overly formal sense. shouldn't be

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1 is a perspective view of an electronic device according to an embodiment of the present invention. 2A is an exploded perspective view of an electronic device according to an embodiment of the present invention. 2B is a block diagram of an electronic device according to an embodiment of the present invention. 3 is an equivalent circuit diagram of a pixel according to an exemplary embodiment of the present invention.

The electronic device 1000 may be a device activated according to an electrical signal. The electronic device 1000 may include various embodiments. For example, the electronic device 1000 may include a tablet, a notebook computer, a computer, a smart television, and the like. In this embodiment, the electronic device 1000 is exemplarily shown as a smart phone.

The electronic device 1000 may display the image IM in the third direction DR3 on the display surface IS parallel to each of the first direction DR1 and the second direction DR2 . The display surface FS on which the image IM is displayed may correspond to the front surface of the electronic device EA, and may correspond to the front surface FS of the window 100 .

Hereinafter, the same reference numerals will be used for the display surface of the electronic device 1000 , the front surface, and the front surface of the window 100 . The image IM may include a still image as well as a dynamic image. In FIG. 1 , a clock and a plurality of icons are illustrated as an example of the image IM.

In the present embodiment, the front (or upper surface) and the rear (or lower surface) of each member are defined based on the direction in which the image IM is displayed. The front surface and the rear surface may be opposed to each other in the third direction DR3 , and a normal direction of each of the front surface and the rear surface may be parallel to the third direction DR3 . A separation distance between the front surface and the rear surface in the third direction DR3 may correspond to a thickness of the display panel DP in the third direction DR3 .

The electronic device 1000 according to an embodiment of the present invention may sense the user's input TC applied from the outside. The user's input TC includes various types of external inputs, such as a part of the user's body, light, heat, or pressure. In this embodiment, the user's input TC is shown as the user's hand applied to the front side. However, this is illustrated by way of example, and as described above, the user's input TC may be provided in various forms, and the electronic device 1000 may be configured according to the structure of the electronic device 1000 . ) may sense the user's input TC applied to the side or back side, and the present invention is not limited to any one embodiment.

Meanwhile, in the present exemplary embodiment, the first area A1 may be defined inside the light transmitting area TA. The first area A1 may be an area overlapping the electronic module 400 among the display modules 300 to be described later. In FIG. 2A , the first area A1 is illustrated in the upper right corner in the shape of a single circle, but the present invention is not limited thereto. The number and shape of the first area A1 may vary in the display module 300 according to the number and shape of the electronic module 400 . It may be provided in a shape and is not limited to any one embodiment.

The electronic device 1000 may receive an external signal required for the electronic module 400 through the first area A1 or may provide a signal output from the electronic module 400 to the outside. According to the present invention, since the first area A1 is provided to overlap the light transmitting area TA, the area of the bezel area BZA for forming the light transmitting area TA may be reduced. A detailed description thereof will be provided later.

Referring to FIG. 2A , the electronic device 1000 includes a window 100 , a housing 200 , a display module 300 , and an electronic module 400 . In the present embodiment, the window 100 and the housing 200 are combined to form an exterior of the electronic device 1000 .

The window 100 may include an insulating panel. For example, the window 100 may be made of glass, plastic, or a combination thereof.

As described above, the front surface FS of the window 100 defines the front surface of the electronic device EA. The light transmitting area TA may be an optically transparent area. For example, the light transmitting area TA may be an area having a visible light transmittance of about 90% or more.

The bezel area BZA may be an area having relatively low light transmittance compared to the light transmitting area TA. The bezel area BZA defines the shape of the light transmitting area TA. The bezel area BZA may be adjacent to the light transmitting area TA and may surround the light transmitting area TA.

The bezel area BZA may have a predetermined color. The bezel area BZA may be defined by a bezel layer provided separately from the transparent substrate defining the light transmitting area TA, or may be defined by an ink layer formed by being inserted or colored in the transparent substrate.

The display module 300 may include an electronic panel EP and a driving circuit IC.

The electronic panel EP may display the image IM and sense the external input TC. The front surface IS of the electronic panel EP includes an active area AA and a peripheral area NAA. The active area AA may be an area activated according to an electrical signal.

In the present exemplary embodiment, the active area AA may be an area in which the image IM is displayed and may be an area in which the external input TC is sensed at the same time. The active area AA may be an area in which a plurality of pixels PX _ij to be described later are disposed.

The light transmitting area TA overlaps at least the active area AA. For example, the light transmitting area TA overlaps the entire surface or at least a part of the active area AA. Accordingly, the user may recognize the image IM through the light transmitting area TA or may provide an external input TC. However, this is illustrated by way of example, and the area in which the image IM is displayed and the area in which the external input TC is sensed may be separated from each other in the active area AA, and the present invention is not limited to any one embodiment. does not

The peripheral area NAA may be an area covered by the bezel area BZA. The peripheral area NAA is adjacent to the active area AA. The peripheral area NAA may surround the active area AA. The peripheral area NAA may be an area in which the image IM is not displayed. A driving circuit or a driving line for driving the active area AA may be disposed in the peripheral area NAA.

In the present embodiment, the electronic panel EP is assembled in a flat state in which the active area AA and the peripheral area NAA face the window 100 . However, this is illustrated by way of example, and a portion of the peripheral area NAA of the electronic panel EP may be bent. For example, a portion of the peripheral area NAA may face the rear surface of the electronic device EA, so that the bezel area BZA seen on the front surface of the electronic device EA may be reduced. Alternatively, the electronic panel EP may be assembled in a state where a portion of the active area AA is bent. Alternatively, in the electronic panel EP according to an exemplary embodiment, the peripheral area NAA may be omitted.

The active area AA may include a first area A1 and a second area A2 . In the present invention, the first area A1 may have a relatively higher light transmittance than the second area A2 . The first area A1 may be defined as an area overlapping an area in which the electronic module 400 is disposed inside the housing 200 among the display modules 300 . In the present embodiment, the first area A1 is illustrated in a circular shape, but may have various shapes such as a polygon, an ellipse, or a figure having at least one curve, and is not limited to any one embodiment.

The second area A2 is adjacent to the first area A1 . In the present embodiment, the second area A2 is shown to have a shape enclosing the entire first area A1, but this is illustrated by way of example, and the second area A2 is the edge of the first area A1. It may be defined adjacent to only some of them, and is not limited to any one embodiment.

Referring to FIG. 2B , the electronic panel EP may include a display panel 310 and an input sensor 320 . The display panel 310 may be configured to generate an image IM. The image IM generated by the display panel 310 is displayed on the display surface IS through the light-transmitting area TA and visually recognized by the user from the outside.

The input sensor 320 detects an external input TC applied from the outside. As described above, the input sensor 320 may detect the external input TC provided to the window 100 .

Again, referring to FIG. 2A , the electronic panel EP may include a flat part FN and a bending part BN. The planar part FN may be assembled in a state substantially parallel to a plane defined by the first direction DR1 and the second direction DR2 . The active area AA may be provided in the planar portion FN.

The bending portion BN may extend from the flat portion FN and be bent. The bending portion BN may be bent from the flat portion FN and assembled to be positioned on the rear side of the flat portion FN. When the bending part BN is assembled, the bezel area of the electronic device 1000 may be reduced because it overlaps the planar part FN on a plane. Meanwhile, this is illustrated by way of example, and in the electronic panel EP, the bending part BN may be omitted.

The driving circuit IC may be mounted on the bending part BN. The driving circuit IC is illustrated as an embodiment provided in the form of a chip, but is not limited thereto, and may be provided on a separate circuit board and electrically connected to the electronic panel EP through a flexible film or the like.

The driving circuit IC is electrically connected to the active area AA to transmit an electrical signal to the active area AA. For example, the driving circuit IC may include a data driving circuit and provide data signals to pixels disposed in the active area AA. Alternatively, the driving circuit IC may include a touch driving circuit and may be electrically connected to an input sensor disposed in the active area AA. Meanwhile, this has been described as an example, and the driving circuit IC may include various circuits in addition to the above-described circuits or may be designed to provide various electrical signals to the active area AA, and is not limited to any one embodiment. does not

Meanwhile, although not shown, the electronic device 1000 may further include a main circuit board electrically connected to the electronic panel EP and the driving circuit IC. The main circuit board may include various driving circuits for driving the electronic panel EP or connectors for supplying power. The main circuit board may be a rigid printed circuit board (PCB), but is not limited thereto, and may be a flexible circuit board, but is not limited to any one embodiment.

The electronic module 400 is disposed below the display module 300 . The electronic module 400 may receive an external input transmitted through the first area A1 or output a signal through the first area A1 . According to the present invention, by providing the first area A1 having a relatively high transmittance inside the active area AA, the electronic module 400 may be disposed to overlap the active area AA. Accordingly, an increase in the bezel area BZA may be prevented.

Referring to FIG. 2B , the electronic device 1000 may include a display module 300 , a power supply module PM, a first electronic module EM1 , and a second electronic module EM2 . The display module 300 , the power supply module PM, the first electronic module EM1 , and the second electronic module EM2 may be electrically connected to each other. In FIG. 2B , the display panel 310 and the input sensor 320 among the configuration of the display module 300 are exemplarily illustrated.

The power supply module PM supplies power required for the overall operation of the electronic device EA. The power supply module PM may include a conventional battery module.

The first electronic module EM1 and the second electronic module EM2 include various functional modules for operating the electronic device EA. The first electronic module EM1 may be directly mounted on a motherboard electrically connected to the electronic panel EP or may be mounted on a separate board and electrically connected to the motherboard through a connector (not shown).

The first electronic module EM1 may include a control module CM, a wireless communication module TM, an image input module IIM, an audio input module AIM, a memory MM, and an external interface IF. have. Some of the modules may not be mounted on the motherboard, but may be electrically connected to the motherboard through a flexible circuit board.

The control module CM controls the overall operation of the electronic device EA. The control module CM may be a microprocessor. For example, the control module CM activates or deactivates the display module 300 . The control module CM may control other modules such as the image input module IIM and the audio input module AIM based on the touch signal received from the electronic panel EP.

The wireless communication module (TM) may transmit/receive a wireless signal to/from another terminal using a Bluetooth or Wi-Fi line. The wireless communication module (TM) may transmit/receive a voice signal using a general communication line. The wireless communication module TM includes a transmitter TM1 that modulates and transmits a signal to be transmitted, and a receiver TM2 that demodulates a received signal.

The image input module IIM processes the image signal and converts it into image data that can be displayed on the electronic panel EP. The sound input module (AIM) receives an external sound signal by a microphone in a recording mode, a voice recognition mode, and the like, and converts it into electrical voice data.

The external interface IF serves as an interface connected to an external charger, a wired/wireless data port, a card socket (eg, a memory card, a SIM/UIM card), and the like.

The second electronic module EM2 may include an audio output module AOM, a light emitting module LM, a light receiving module LRM, and a camera module CMM. The components may be directly mounted on the motherboard, mounted on a separate board, and electrically connected to the electronic panel EP through a connector (not shown), or electrically connected to the first electronic module EM1.

The sound output module (AOM) converts the sound data received from the wireless communication module (TM) or the sound data stored in the memory (MM) and outputs it to the outside.

The light emitting module LM generates and outputs light. The light emitting module LM may output infrared rays. The light emitting module LM may include an LED element. The light receiving module (LRM) may detect infrared rays. The light receiving module LRM may be activated when an infrared ray of a predetermined level or more is sensed. The light receiving module LRM may include a CMOS sensor. After the infrared light generated by the light emitting module LM is output, it is reflected by an external object (eg, a user's finger or face), and the reflected infrared light may be incident on the light receiving module LRM. The camera module (CMM) captures an external image.

The electronic module 400 according to an embodiment of the present invention may include at least one of the components of the second electronic module EM2. For example, the electronic module 400 may include at least one of a camera, a speaker, an optical sensor, and a thermal sensor. The electronic module 400 may detect an external object received through the first area A1 or may provide a sound signal such as a voice through the first area A1 to the outside. Also, the electronic module 400 may include a plurality of components, and is not limited to any one embodiment. Meanwhile, although not shown, the electronic module 400 may be attached to the electronic panel EP through a separate adhesive.

Again, referring to FIG. 2A , the housing 200 is coupled to the window 100 . The housing 200 is coupled to the window 100 to provide a predetermined internal space. The display module 300 and the electronic module 400 may be accommodated in an internal space.

The housing 200 may include a material having a relatively high rigidity. For example, the housing 200 may include a plurality of frames and/or plates made of glass, plastic, metal, or a combination thereof. The housing 200 may stably protect the components of the electronic device 1000 accommodated in the internal space from external impact.

3 is an equivalent circuit diagram of a pixel PXij illustrated in the display module 300 according to an exemplary embodiment. The equivalent circuit diagram of the pixel PXij shown in FIG. 3 is equally applicable to the first pixel disposed in the first area A1 and the second pixel disposed in the second area A2 only with a difference in size. can

3 , the pixel PXij connected to the i-th scan line SLi among the scan lines SL1 to SLn of the first group and connected to the j-th data line DLj among the plurality of data lines DL1 to DLm. ) is shown as an example.

In the present exemplary embodiment, the pixel driving circuit may include first to seventh transistors T1 to T7 and a capacitor Cst. In this embodiment, the first to seventh transistors T1 to T7 are described as P-type transistors. However, the present invention is not limited thereto, and the first to seventh transistors T1 to T7 may be implemented as either a P-type transistor or an N-type transistor.

Also, in an embodiment of the present invention, at least one of the first to seventh transistors T1 to T7 may be omitted. Also, at least one of the first to seventh transistors T1 to T7 may include a semiconductor layer including an oxide, and the rest may include a semiconductor layer including silicon.

In this embodiment, the first transistor T1 may be a driving transistor, and the second transistor T2 may be a switching transistor. The capacitor Cst is connected between the first voltage line PL receiving the first power voltage ELVDD and the reference node RD. The capacitor Cst includes a first electrode Cst1 connected to the reference node RD and a second electrode Cst2 connected to the first voltage line PL.

The first transistor T1 is connected between the first voltage line PL and one electrode of the light emitting diode OLED. The source S1 of the first transistor T1 is electrically connected to the first voltage line PL. Another transistor may be disposed or omitted between the source S1 of the first transistor T1 and the first voltage line PL.

As used herein, "electrically connected between a transistor and a signal line or a transistor and a transistor" means "a source, a drain, and a gate of a transistor have an integral shape with the signal line or are connected through a connection electrode" .

The drain D1 of the first transistor T1 is electrically connected to the anode of the light emitting diode OLED. Another transistor may be disposed or omitted between the drain D1 of the first transistor T1 and the anode of the light emitting diode OLED. The gate G1 of the first transistor T1 is electrically connected to the reference node RD.

The second transistor T2 is connected between the j-th data line DLj and the source of the first transistor T1 . The source S2 of the second transistor T2 is electrically connected to the j-th data line DLj, and the drain D2 of the second transistor T2 is electrically connected to the source S1 of the first transistor T1. is connected to In this embodiment, the gate G2 of the second transistor T2 may be electrically connected to the i-th scan line SLi of the first group.

The third transistor T3 is connected between the reference node RD and the drain D1 of the first transistor T1 . The drain D3 of the third transistor T3 is electrically connected to the drain D1 of the first transistor T1, and the source S3 of the third transistor T3 is electrically connected to the reference node RD. do. In this embodiment, the gate G3 of the third transistor T3 may be electrically connected to the i-th scan line GLi of the second group.

The fourth transistor T4 is connected between the reference node RD and the second voltage line RL. The drain D4 of the fourth transistor T4 is electrically connected to the reference node RD, and the source S4 of the fourth transistor T4 is electrically connected to the second voltage line RL. In this embodiment, the gate G4 of the fourth transistor T4 may be electrically connected to the i-th scan line HLi of the third group.

The fifth transistor T5 is connected between the first voltage line PL and the source S1 of the first transistor T1 . The source S5 of the fifth transistor T5 is electrically connected to the first voltage line PL, and the drain D5 of the fifth transistor T5 is electrically connected to the source S1 of the first transistor T1. is connected to The gate G5 of the fifth transistor T5 may be electrically connected to the i-th light emitting line ELi.

The sixth transistor T6 is connected between the drain D1 of the first transistor T1 and the light emitting diode OLED. The source S6 of the sixth transistor T6 is electrically connected to the drain D1 of the first transistor T1, and the drain D5 of the sixth transistor T6 is electrically connected to the anode of the light emitting diode OLED. is connected to The gate G6 of the sixth transistor T6 may be electrically connected to the i-th light emitting line ELi.

The seventh transistor T7 is connected between the drain D6 of the sixth transistor T6 and the second voltage line RL. The source S7 of the seventh transistor T7 is electrically connected to the drain D6 of the sixth transistor T6, and the drain D7 of the seventh transistor T7 is electrically connected to the second voltage line RL. is connected to The gate G7 of the seventh transistor T7 may be electrically connected to the i+1th scan line SLi+1 of the first group.

4 is a plan view of an active region according to an embodiment of the present invention. FIG. 5 is a cross-sectional view taken along line I-I' of FIG. 4 . 6 is a cross-sectional view taken along II-II' of FIG. 4 . 7 is a cross-sectional view taken along line III-III' of FIG. 4 .

4 , the display module 300 according to the present invention may include a first pixel EP1M disposed in a first area A1 and a second pixel EP2M disposed in a second area A2. can The first pixel EP1M and the second pixel EP2M may have different emission areas, and the first pixel EP1M and the second pixel EP2M may have different arrangement shapes. A plurality of first pixels EP1M may be provided in the first area A1 and may be arranged to be spaced apart from each other in the first direction DR1 and the second direction DR2 .

The first pixel EP1M may include a plurality of sub-pixels E11M, E12M, and E13M.

The 1-1 th sub-pixels E11M are spaced apart in the second direction DR2 with the 1-2 th sub-pixels E12M interposed therebetween, and the two 1-1 th sub-pixels E11M spaced apart from each other are It may be disposed in a diagonal direction along the fourth direction DR4 . In the present exemplary embodiment, the first-first sub-pixels E11M may provide red light.

The 1-2 th sub-pixels E12M may be disposed between the 1-1 th sub-pixels E11M and the 1-3 th sub-pixels E13M. Four first-second sub-pixels E12M according to the present exemplary embodiment may be provided to be spaced apart from each other in the first direction DR1 . In the present exemplary embodiment, the first-second sub-pixels E12M may provide green light.

The 1-3 th sub-pixels E13M are spaced apart in the second direction DR2 with the 1-2 th sub-pixels E12M interposed therebetween, and the two 1-3 th sub-pixels E13M spaced apart from each other are It may be disposed in a diagonal direction along the fifth direction DR5 . In the present exemplary embodiment, the 1-3 th sub-pixels E13M may provide blue light.

In the present exemplary embodiment, one 1-3 th sub-pixel E13M disposed on the left with respect to the 1-2 th sub-pixels E12M is one 1-1 th sub-pixel E11M in the first direction DR1 . ), and the other first 1-3 sub-pixels E13M disposed on the right with respect to the 1-2 first sub-pixels E12M are the other first sub-pixels E13M in the first direction DR1 . -1 may be disposed under the sub-pixel E11M.

Each of the sub-pixels E11M, E12M, and E13M has a light emission area that becomes wider in the order of the 1-2 sub-pixel E12M, the 1-3 sub-pixel E13M, and the 1-1 sub-pixel E11M. can get

Each of the second pixels EP2M may include a plurality of sub-pixels E21M, E22M, and E23M. The second pixels EP2M may be arranged to be spaced apart from each other in the first direction DR1 and the second direction DR2 .

In the present exemplary embodiment, the arrangement structure of the sub-pixels E21M, E22M, and E23M disposed in the second area A2 may be referred to as a pentile structure.

The 2-2nd sub-pixel E22M is spaced apart from the 2-1-th sub-pixel E21M along the fourth direction DR4, and the 2-3-th sub-pixel E23M is the 2-1th sub-pixel It may be spaced apart along the fifth direction DR5 with respect to (E21M). The 2-3th sub-pixel E23M may be spaced apart from the 2-2nd sub-pixel E22M in the second direction DR2 .

The 2-1 th sub-pixel E21M may have a rectangular shape defined in the fourth direction DR4 and the fifth direction DR5 . In the present exemplary embodiment, the 2-1 th sub-pixel E21M may provide green light. The 2-1 th sub-pixel E21M has a rhombus shape based on the 1-2 th sub-pixels E12M providing the same color among the sub-pixels E11M, E12M, and E13M disposed in the first area A1 . can have

The 2-2nd sub-pixel E22M may have a square shape defined in the fourth direction DR4 and the fifth direction DR5 . In the present exemplary embodiment, the second-second sub-pixel E22M may provide blue light. The 2-2nd sub-pixel E22M has a diamond shape based on the 1-3-th sub-pixels E13M providing the same color among the sub-pixels E11M, E12M, and E13M disposed in the first area A1. can have

The 2-3 th sub-pixel E23M may have a square shape defined in the fourth direction DR4 and the fifth direction DR5 . In the present exemplary embodiment, the 2-3 th sub-pixel E23M may provide red light. The 2-3 th sub-pixel E23M has a rhombus shape based on the 1-1 th sub-pixel E11M providing the same color among the sub-pixels E11M, E12M, and E13M disposed in the first area A1 . can have

The emission area of each of the sub-pixels E21M, E22M, and E23M increases in the order of the 2-1 sub-pixel E21M, the 2-2 sub-pixel E22M, and the 2-3-th sub-pixel E23M. can

According to the present invention, the first area A1 may be divided into a display area BA, a wiring area BL, and a transmission area BT. The display area BA and the wiring area BL are areas in which conductive materials constituting the pixel PX _ij are patterned, and when the electronic module 400 transmits/receives light, light reflected by the conductive materials The performance of the electronic module 400 may be degraded.

According to the present invention, as the light blocking layer BMI overlaps the display area BA and the wiring area BL of the first area A1 and does not overlap the transmissive area BT, the above problem is improved. can do. A detailed description will be given later. In FIG. 4 , the display area BA and the wiring area BL on which the light blocking layer BMI is disposed among the first area A1 are shown in a relatively darker color than the transmissive area BT.

5 and 6 illustrate cross-sections of portions corresponding to the first transistor T1 and the third transistor T3 among the first to seventh transistors T1 to T7 described in FIG. 3 .

The area overlapping the second area A2 of the display module 300 includes a display panel 310 (refer to FIG. 2B), an input sensor 90 (corresponding to 320 in FIG. 2B), a black matrix BM, and a color filter ( 100), and an overcoat layer (OC).

The display panel 310 may include a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer 80 .

The display panel 310 may further include functional layers such as an anti-reflection layer and a refractive index adjusting layer. The circuit element layer DP-CL includes at least a plurality of insulating layers and a circuit element. Hereinafter, the insulating layers may include an organic layer and/or an inorganic layer.

An insulating layer, a semiconductor layer, and a conductive layer are formed by coating, vapor deposition, or the like. Thereafter, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by photolithography. In this way, a semiconductor pattern, a conductive pattern, a signal line, and the like are formed.

The base layer BS may be a base layer on which other components of the circuit element layer DP-CL are disposed. The base layer BS may have a structure in which layers including an organic material and layers including an inorganic material are alternately stacked. For example, in the present exemplary embodiment, the base layer BS may include a first base layer PI1 , a first barrier layer BI, and a second base layer PI2 .

The first base layer PI1 may be disposed under the first barrier layer BI. The first base layer PI1 may include an organic material. For example, the first base layer PI1 may include polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyarylate, polycarbonate ( It may include any one of polycarbonate: PC), polyetherimide (PEI), and polyethersulfone (PES).

The first barrier layer BI may be disposed on the first base layer PI1 . The first barrier layer BI may include an inorganic material. For example, the first barrier layer BI may include at least one of silicon oxide, silicon oxynitride, aluminum oxide, titanium oxide, silicon nitride, zirconium oxide, and hafnium oxide.

The second base layer PI2 may be disposed on the first barrier layer BI. The second base layer PI2 may include an organic material. The organic material included in the second base layer PI2 may be the same as the organic material included in the first base layer BI1 .

However, the present invention is not limited thereto, and the base layer BS may be provided as a single layer. In this case, the base layer BS may include a synthetic resin film. The synthetic resin layer may include a thermosetting resin. In particular, the synthetic resin layer may be a polyimide-based resin layer, and the material thereof is not particularly limited. In addition, the base layer BS may include glass, metal, or an organic/inorganic composite material.

The second barrier layer BRL may be disposed on the base layer BS. The second barrier layer BRL may include an inorganic material. For example, the second barrier layer BRL may include at least one of silicon oxide, aluminum oxide, titanium oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

The buffer layer BFL may be disposed on the second barrier layer BRL. The buffer layer BFL improves the bonding force between the second barrier layer BRL and the semiconductor pattern and/or the conductive pattern. The buffer layer BFL may include at least one of silicon oxide and silicon nitride. In addition, the buffer layer BFL may include a silicon oxynitride layer having a single-layer or multi-layer structure, but is not limited to any one embodiment.

A semiconductor pattern is disposed on the buffer layer BFL. Hereinafter, a semiconductor pattern directly disposed on the buffer layer BFL is defined as a first semiconductor pattern. The first semiconductor pattern may include a silicon semiconductor. The first semiconductor pattern may include polysilicon. However, the present invention is not limited thereto, and the first semiconductor pattern may include amorphous silicon.

FIG. 5 illustrates only a portion of the first semiconductor pattern, and a first semiconductor pattern may be further disposed in another area of the pixel PX _ij (refer to FIG. 3 ). The first semiconductor pattern has different electrical properties depending on whether it is doped or not. The first semiconductor pattern may include a doped region and a non-doped region. The doped region may be doped with an N-type dopant or a P-type dopant. A P-type transistor includes a doped region doped with a P-type dopant.

The source S1 , the active A1 , and the drain D1 of the first transistor T1 are formed from the first semiconductor pattern. The source S1 and the drain D1 of the first transistor T1 are formed to be spaced apart from each other with the active A1 interposed therebetween.

A connection signal line SCL may be disposed on the buffer layer BFL. The connection signal line SCL may be connected to the drain D6 of the sixth transistor T6 (refer to FIG. 3 ) on a plane.

A light blocking layer BMI may be disposed on the buffer layer BFL, and the buffer layer BFL may be covered by the first insulating layer 10 . The first insulating layer 10 may be an inorganic layer and/or an organic layer, and may have a single-layer or multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

In the present exemplary embodiment, the first insulating layer 10 is disposed on the buffer layer BFL and covers the first semiconductor pattern and the connection signal line SCL. In this embodiment, the first insulating layer 10 may be a single-layer silicon oxide layer. In addition to the first insulating layer 10 , the insulating layer of the circuit element layer DP-CL to be described later may be an inorganic layer and/or an organic layer, and may have a single-layer or multi-layer structure. The inorganic layer may include at least one of the above-described materials.

A gate G1 of the first transistor T1 is disposed on the first insulating layer 10 . The gate G1 may be a part of the metal pattern. The gate G1 of the first transistor T1 overlaps the active A1 of the first transistor T1. In the process of doping the first semiconductor pattern, the gate G1 of the first transistor T1 is the same as a mask.

A second insulating layer 20 covering the gate G1 is disposed on the first insulating layer 10 . The second insulating layer 20 may be an inorganic layer and/or an organic layer, and may have a single-layer or multi-layer structure. In this embodiment, the second insulating layer 20 may be an inorganic layer and/or an organic layer, and may have a single-layer or multi-layer structure. In this embodiment, the second insulating layer 20 may be a single-layer silicon nitride layer.

An upper electrode UE may be disposed on the second insulating layer 20 . The upper electrode UE may overlap the gate G1. The upper electrode UE may be a part of a metal pattern or a part of a doped semiconductor pattern. A portion of the gate G1 and the upper electrode UE overlapping it may define a capacitor Cst (refer to FIG. 2 ). In an embodiment of the present invention, the upper electrode UE may be omitted.

In an embodiment of the present invention, the second insulating layer 20 may be replaced with an insulating pattern. An upper electrode UE is disposed on the insulating pattern. The upper electrode UE may serve as a mask for forming an insulating pattern from the second insulating layer 20 .

Although not shown separately, the first electrode Cst1 and the second electrode Cst2 of the capacitor Cst (refer to FIG. 3 ) may be formed through the same process as the gate G1 and the upper electrode UE. A first electrode Cst1 may be disposed on the first insulating layer 10 . The first electrode Cst1 may be electrically connected to the gate G1. The first electrode Cst1 may have a shape integral with the gate G1.

A third insulating layer 30 covering the upper electrode UE is disposed on the second insulating layer 20 . In this embodiment, the third insulating layer 30 may include a plurality of silicon oxide layers and silicon nitride layers that are alternately stacked. Although not shown separately, the source (S2, S5, S6, S7, see FIG. 3) of the second, fifth, sixth, and seventh transistors (T2, T5, T6, T7, see FIG. 3), drain (D2, D5, D6, D7 (refer to FIG. 3) and gates G2, G5, G6, G7, see FIG. 3) are the same as the source S1, drain D1, and gate G1 of the first transistor T1, respectively. It can be formed through a process.

A semiconductor pattern is disposed on the third insulating layer 30 . Hereinafter, a semiconductor pattern directly disposed on the third insulating layer 30 is defined as a second semiconductor pattern. The second semiconductor pattern may include a metal oxide. The oxide semiconductor may include a crystalline or amorphous oxide semiconductor.

For example, the oxide semiconductor is a metal oxide such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti) or zinc (Zn), indium (In), gallium (Ga) , tin (Sn), may include a mixture of a metal such as titanium (Ti) and oxides thereof. Oxide semiconductors are indium-tin oxide (ITO), indium-gallium-zinc oxide (IGZO), zinc oxide (ZnO), indium-zinc oxide (IZnO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium-zinc-tin oxide (IZTO), zinc-tin oxide (ZTO), and the like.

As shown in FIG. 5 , the source S3 , the active A3 , and the drain D3 of the third transistor T3 are formed from the second semiconductor pattern. The source S3 and the drain D3 contain metal reduced from the metal oxide semiconductor. The source S3 and the drain D3 may have a predetermined thickness from the upper surface of the second semiconductor pattern and include a metal layer including the reduced metal.

A fourth insulating layer 40 covering the second semiconductor pattern is disposed on the third insulating layer 30 . In this embodiment, the fourth insulating layer 40 may be a single-layer silicon oxide layer. A gate G3 of the third transistor T3 is disposed on the fourth insulating layer 40 . The gate G3 may be a part of the metal pattern. The gate G3 of the third transistor T3 overlaps the active A3 of the third transistor T3.

In an embodiment of the present invention, the fourth insulating layer 40 may be replaced with an insulating pattern. A gate G3 of the third transistor T3 is disposed on the insulating pattern. In this embodiment, the gate G3 may have the same shape as the insulating pattern in plan view.

A fifth insulating layer 50 covering the gate G3 is disposed on the fourth insulating layer 40 . In this embodiment, the fifth insulating layer 50 may include a silicon oxide layer and a silicon nitride layer. The fifth insulating layer 50 may include a plurality of silicon oxide layers and silicon nitride layers that are alternately stacked.

Although not shown separately, the source (S4, see FIG. 3), the drain (D4, see FIG. 3), and the gate (G4, see FIG. 3) of the fourth transistor (T4, see FIG. 3) of the third transistor T3 Each of the source S3, the drain D3, and the gate G3 may be formed through the same process.

At least one insulating layer is further disposed on the fifth insulating layer 50 . As in the present embodiment, the sixth insulating layer 60 and the seventh insulating layer 70 may be disposed on the fifth insulating layer 50 . The sixth insulating layer 60 and the seventh insulating layer 70 may be organic layers, and may have a single-layer or multi-layer structure. The sixth insulating layer 60 and the seventh insulating layer 70 may be a single polyimide-based resin layer.

Without being limited thereto, the fifth insulating layer 50 and the sixth insulating layer 60 may include acrylic resins, methacrylic resins, polyisoprene, vinyl resins, epoxy resins, urethane resins, cellulose resins, and siloxane resins. , may include at least one of a polyamide-based resin and a perylene-based resin.

A first connection electrode CNE1 may be disposed on the fifth insulating layer 50 . The first connection electrode CNE1 may be connected to the connection signal line SCL or the connection electrode through the first contact hole CH1 passing through the first to fifth insulating layers 10 to 50 .

A second connection electrode CNE2 may be disposed on the sixth insulating layer 60 . The second connection electrode CNE2 is connected to the first connection electrode CNE1 through the second contact hole CH-60 passing through the sixth insulating layer 60 .

A light emitting diode OLED-A is disposed on the seventh insulating layer 70 . The anode AE of the light emitting diode OLED is disposed on the seventh insulating layer 70 . A pixel defining layer PDL is disposed on the seventh insulating layer 70 . An opening OP exposing at least a portion of the first electrode AE may be defined in the pixel defining layer PDL. In the present exemplary embodiment, the pixel defining layer PDL may include a light absorbing material. For example, the pixel defining layer PDL may have a black color.

The first to seventh transistors T1 to T7 (refer to FIG. 3 ) connected to the light emitting diode OLED-A may constitute one second pixel EP2M (refer to FIG. 4 ).

The opening OP of the pixel defining layer PDL may define the emission area PXA. For example, the plurality of pixels PX _ij (refer to FIG. 2A ) may be disposed on a plane of the display panel 310 (refer to FIG. 2A ) in a regular manner. An area in which the plurality of pixels PX _ij are disposed may be defined as a pixel area, and one pixel area may include an emission area PXA and a non-emission area NPXA adjacent to the emission area PXA. . The non-emission area NPXA may surround and stack the light emitting area PXA.

The first electrode AE is disposed on the seventh insulating layer 70 . The first electrode AE is connected to the second connection electrode CNE2 through the second contact hole CH-70 penetrating the seventh insulating layer 70 .

The hole control layer HCL may be commonly disposed in the light emitting area PXA and the non-emission area NPXA. A common layer such as the hole control layer HCL may be commonly formed in the plurality of pixels PX _ij . The hole control layer HCL may include a hole transport layer and a hole injection layer.

An emission layer EML is disposed on the hole control layer HCL. The emission layer EML may be disposed only in a region corresponding to the opening OP. The emission layer EML may be formed separately in each of the plurality of pixels PX _ij .

Although the patterned emission layer EML is illustrated as an example in this embodiment, the emission layer EML may be commonly disposed in the plurality of pixels PX _ij . In this case, the emission layer EML may generate white light or blue light. In addition, the light emitting layer EML may have a multilayer structure.

An electronic control layer ECL is disposed on the emission layer EML. The electron control layer (ECL) may include an electron transport layer and an electron injection layer. The second electrode CE is disposed on the electronic control layer ECL. The electronic control layer ECL and the second electrode CE are commonly disposed in the plurality of pixels PX _ij .

The thin film encapsulation layer 80 is disposed on the second electrode CE. The thin film encapsulation layer 80 is commonly disposed on the plurality of pixels PX _ij . In this embodiment, the thin film encapsulation layer 80 directly covers the second electrode CE.

The thin film encapsulation layer 80 may include a first inorganic layer 81 , an organic layer 82 , and a second inorganic layer 83 . However, the present invention is not limited thereto, and the thin film encapsulation layer 80 may further include a plurality of inorganic layers and organic layers.

The first inorganic layer 81 may contact the second electrode CE. The first inorganic layer 81 may prevent external moisture or oxygen from penetrating into the emission layer EML. For example, the first inorganic layer 81 may include silicon nitride, silicon oxide, or a combination thereof. The first inorganic layer 81 may be formed through a deposition process.

The organic layer 82 may be disposed on the first inorganic layer 81 to contact the first inorganic layer 81 . The organic layer 82 may provide a flat surface on the first inorganic layer 81 . The curves formed on the upper surface of the first inorganic layer 81 or particles present on the first inorganic layer 81 are covered by the organic layer 82 , and the surface state of the upper surface of the first inorganic layer 81 is covered by the organic layer 82 . It is possible to block the influence on the components formed on the organic layer 82 . The organic layer 82 may include an organic material and may be formed through a solution process such as spin coating, slit coating, or inkjet process.

The second inorganic layer 83 is disposed on the organic layer 82 to cover the organic layer 82 . The second inorganic layer 83 may be stably formed on a relatively flat surface than that disposed on the first inorganic layer 81 . The second inorganic layer 83 seals moisture emitted from the organic layer 82 and prevents inflow to the outside. The second inorganic layer 83 may include silicon nitride, silicon oxide, or a combination thereof. The second inorganic layer 83 may be formed through a deposition process.

The input sensor 90 ( 320 of FIG. 2B ) may be directly formed on the thin film encapsulation layer 80 . The input sensor 320 may include a plurality of conductive patterns MS1 and MS2 and a sensing insulating layer 90 . The sensing insulating layer 90 may include a first sensing insulating layer 91 , a second sensing insulating layer 92 , and a third sensing insulating layer 93 . Each of the first sensing insulating layer 91 , the second sensing insulating layer 92 , and the third sensing insulating layer 93 may include at least one of an inorganic material and an organic material.

The first sensing insulating layer 91 is disposed on the thin film encapsulation layer 80 . The first conductive patterns MS1 may be disposed on the first sensing insulating layer 91 and covered by the second sensing insulating layer 92 . The second conductive patterns MS2 may be disposed on the second sensing insulating layer 92 and covered by the third sensing insulating layer 93 .

Each of the conductive patterns MS1 and MS2 has conductivity. Each of the conductive patterns MS1 and MS2 may be provided as a single layer or as a plurality of layers, but is not limited to any one embodiment. At least one of the conductive patterns MS1 and MS2 according to the present invention may be provided as mesh lines on a plane.

Mesh lines constituting the conductive patterns MS1 and MS2 may be spaced apart from the light emitting layer EML in a plan view. Accordingly, even if the input sensor 320 is directly formed on the display panel 310 , the light formed from the pixels PX _ij (refer to FIG. 2B ) of the display panel 310 is provided to the user without interference from the input sensor 320 . can be

The color filter 100 may overlap the emission layer EML. The color filter 100 may selectively transmit light corresponding to the light provided from the emission layer EML. For example, when the emission layer EML provides blue light, the color filter 100 may be a blue color filter that transmits blue light.

The color filter 100 may include a polymer photosensitive resin and a pigment or dye. For example, the color filter 100 overlapping the emission layer EML providing blue light includes a blue pigment or dye, and the color filter 100 overlapping the emission layer EML providing green light is a green pigment. Alternatively, the color filter 100 that includes a dye and overlaps the emission layer EML providing red light may include a red pigment or dye.

However, the present invention is not limited thereto, and the color filter 100 overlapping the emission layer EML providing blue light may not include a pigment or dye. In this case, the color filter 100 may be transparent, and the color filter 100 may be formed of a transparent photosensitive resin.

The black matrix BM may be disposed between color filters providing different light. The black matrix BM is a pattern having a black color and may be a grid-shaped matrix. The black matrix BM may include a black coloring agent. The black component may include a black dye and a black pigment. The black component may include a metal such as carbon black or chromium, or an oxide thereof.

The overcoat layer OC may be disposed on the color filter 100 and the black matrix BM. The overcoat layer OC may be a layer that surrounds the unevenness generated during the formation of the color filter 100 and the black matrix BM and provides a flat surface. That is, the overcoat layer OC may be a planarization layer.

The window 100 described with reference to FIG. 2A may be coupled to the overcoat layer OC providing a flat surface by an adhesive layer.

6 is a cross-sectional view of a portion of each of the display area BA and the transmissive area BT of the first area A1 in which the electronic module 400 (see FIG. 2B ) and the display module 300 (see FIG. 2B ) overlap , FIG. 7 is a cross-sectional view illustrating a wiring area BL disposed between the transmission areas BT of the first area A1 .

The first pixel EP1M (refer to FIG. 4 ) disposed in the first area A1 includes first to seventh transistors T1 to T7 (refer to FIG. 3 ) connected to the light emitting diode OLED-B. The stacking relationship of one pixel EP1M may be the same as that of the second pixel EP2M disposed in the second area A2 described with reference to FIG. 5 .

That is, also in the first pixel EP1M, the first semiconductor pattern including polysilicon of the first transistor T1 is disposed on the buffer layer BFL, and the third transistor T3 is disposed on the third insulating layer 30 . ) a second semiconductor pattern including a metal oxide of may be disposed.

Accordingly, differences regarding the arrangement relationship of the insulating layers in the transmission region BT will be mainly described.

According to the present invention, the light blocking layer BMI may be disposed in the display area BA of the first area A1 . That is, the light blocking layer BMI may overlap the display area BA of the first area A1 and may not overlap the transmissive area BT. The light blocking layer BMI may be disposed between the second barrier layer BRL and the buffer layer BFL. The light blocking layer BMI may include a metal.

However, when the second barrier layer BRL is omitted, the light blocking layer BMI may be disposed between the base layer BS and the buffer layer BFL, and the embodiment is not limited thereto.

The light blocking layer BMI is disposed on the second barrier layer BRL, and conductive materials disposed on the base layer BS and the second barrier layer BRL are recognized by the electronic module 400 by external light. can be improved Accordingly, even when the electronic module 400 is disposed in the active area AA (refer to FIG. 2A ), interference with conductive materials disposed on the base layer BS and the second barrier layer BRL is minimized. , the electronic device 1000 having improved performance of the electronic module 400 may be provided.

The display transparent area BT of the first area A1 may be surrounded by the display area BA and the wiring area BL. The transmission region BT may be defined as a region in which conductive materials or insulating layers are not patterned or deposited to improve light transmittance. In the present exemplary embodiment, the transmission area BT may have a cross shape.

However, the present invention is not limited thereto, and the shape of the transmission region BT may vary according to a shape in which the light blocking layer BMI is disposed, and is not limited to any one shape.

The transmissive region BT according to the present invention may be formed by omitting insulating layers overlapping the transmissive region BT among the first to seventh insulating layers 10 to 70 .

In the present embodiment, among the first to seventh insulating layers 10 to 70 included in the display panel 310 , the first insulating layer 10 , the second insulating layer 20 , and the second insulating layer 10 overlapping the transmission region BT The third insulating layer 30 , the fourth insulating layer 40 , the fifth insulating layer 50 , and the seventh insulating layer 70 may be provided in a form in which they are not deposited or are removed by being patterned after deposition. According to an exemplary embodiment, in the process of removing the insulating layers, the edge BMI-E of the light blocking layer BMI may be disposed to be adjacent to the transmission region BT rather than side surfaces of each of the removed insulating layers.

In the present embodiment, the transmissive region BT includes a base layer portion BS-P, a second barrier layer portion BRL-P, a buffer layer portion BFL-P, a sixth insulating layer portion 60-P, First inorganic layer portion 81 -P, organic layer portion 82 -P, second inorganic layer portion 83 -P, first sensing insulating layer portion 91 -P, second sensing insulating layer portion 92 -P), the third sensing insulating layer portion 93 -P, and an overcoat layer OC covering the third sensing insulating layer portion 93 -P may be disposed.

Accordingly, the light blocking layer BMI, the first to fifth insulating layers 10 to 50 , the seventh insulating layer 70 , the color filter 100 , and the black matrix BM overlapping the display area BA are formed. , may not overlap the transmission region BT. In addition, components of the light emitting diode OLED-B may also non-overlapping the transmissive region BT.

According to the present embodiment, the upper surface BM-U of the black matrix BM disposed adjacent to the transmission region BT of the black matrix BM is exposed by the color filter 100 to form the overcoat layer OC. can come into contact with

According to the present invention, the first area A1 has a higher light transmittance than the second area A2 , and is the most transparent area BT disposed between the first pixels EP1M among the first areas A1 . It may have high light transmittance.

In order to compensate for the step difference between the insulating layers not deposited in the transmission region BT or patterned after deposition, the organic layer 82 of the thin film encapsulation layer 80 may have a different thickness for each region. For example, the thickness of the organic layer overlapping the transmission area BT among the organic layers 82 may be greater than the maximum thickness of the organic layer overlapping the second area A2 and the display area BA of the organic layer 82 . .

Since the electronic device 1000 according to the present invention includes the display panel 310 in which some of the insulating layers are removed from the region overlapping the electronic module 400 , the display module 300 with improved light transmittance can be provided. can Accordingly, even if the electronic module 400 is disposed in the active area AA (refer to FIG. 2A ), the electronic device 1000 with improved performance of the electronic module 400 may be provided.

Referring to FIG. 7 , the wiring region BL disposed between the transmissive regions BT includes a light blocking layer BML-L, a first gate line G1-L, an upper electrode line UE-L, and a second wiring region BL. It may include two gate lines G3-L, a first connection electrode line CNE1-L, and a second connection electrode line CNE2-L. The transmission area BT of the area adjacent to the wiring area BL may have the same layer structure as the transmission area BT adjacent to the display area BA described with reference to FIG. 6 .

In FIG. 7 , components disposed on the thin film encapsulation layer 80 will be omitted and described, and repeated description will be omitted.

The first gate lines G1 -L may be disposed on the first insulating layer 10 and covered by the second insulating layer 20 . The first gate line G1 -L may branch from the first gate G1 (refer to FIGS. 5 and 6 ).

The upper electrode line UE-L may be disposed on the second insulating layer 20 and covered by the third insulating layer 30 . The upper electrode line UE-L may be branched from the upper electrode EU (refer to FIGS. 5 and 6 ). The upper electrode line UE-L may be spaced apart from the first gate line G1-L in cross-section.

The second gate line G3-L may be disposed on the fourth insulating layer 40 and covered by the fifth insulating layer 50 . The second gate line G3-L may branch from the second gate G3 (refer to FIGS. 5 and 6 ).

The first connection electrode lines CNE1-L may be disposed on the fifth insulating layer 50 and covered by the sixth insulating layer 60 . The first connection electrode line CNE1-L may be branched from the first connection electrode CNE1 (refer to FIGS. 5 and 6 ).

The second connection electrode line CNE2-L may be disposed on the sixth insulating layer 60 and covered by the seventh insulating layer 70 . The second connection electrode line CNE2-L may be branched from the second connection electrode CNE2 (refer to FIGS. 5 and 6 ).

According to the present invention, the light blocking layer BMI-L may overlap the wiring area BL of the first area A1 . For example, the light blocking layer BMI-L may be disposed between the second barrier layer BRL and the buffer layer BFL overlapping the wiring area BL. Accordingly, even when the wiring area BL including the conductive material together with the display areas BA surrounds the transmission area BT, external light is reflected from the wires by the light blocking layer BMI-L and the electronic module (400, see FIG. 2A) can be prevented from being visually recognized. Accordingly, even if the electronic module 400 is disposed in the active area AA (refer to FIG. 2A ), the electronic device 1000 with improved reliability may be provided.

According to an embodiment of the present invention, the thickness of the second barrier layer overlapping the display area BA and the wiring area BL of the second barrier layer BRL is equal to the thickness of the transmission area (BRL) of the second barrier layer BRL. BT) may be greater than the thickness of the second barrier layer overlapping. This may be formed by removing the second barrier layer overlapping the transmissive region BT by a predetermined thickness in a process of removing the insulating layers disposed on the transmissive region BT.

8 is a cross-sectional view of an active region according to an embodiment of the present invention. 9 is a cross-sectional view of an active region according to an embodiment of the present invention. The same/similar reference numerals are given to the same/similar components as those of FIGS. 1 to 7, and duplicate descriptions will be omitted.

Referring to FIG. 8 , the display panel 310 (refer to FIG. 2B ) according to the present exemplary embodiment may include protection patterns PTL1 and PTL2 . The protection patterns PTL1 and PTL2 are formed to remove components overlapping the transmission area BT among components deposited or coated on the first area A1 and the second area A2 through the laser beam LB. In the step, there may be functional patterns for preventing damage by the laser beam LB.

The protection patterns PTL1 and PTL2 may be disposed in the display area DA of the first area A1 and may be disposed adjacent to the transmission area BT. The protection patterns PTL1 and PTL2 may be disposed on the display area DA to surround the boundary of the transmission area BT.

The first protective pattern PTL1 may be disposed on the sixth insulating layer 60 . The first protective pattern PTL1 may include the same material as the second connection electrode CNE2 and may be patterned simultaneously with the second connection electrode CNE2 .

The second protective pattern PTL2 may be disposed on the seventh insulating layer 70 . The second protective pattern PTL2 may include the same material as the first electrode AE and may be patterned simultaneously with the first electrode AE.

According to the present embodiment, a process of providing a laser beam LB to the transmissive region BT to remove components overlapping the transmissive region BT (eg, the second electrode CE, see FIG. 6 ). In this case, it is possible to improve the problem that components adjacent to the transmission region BT are peeled off by the laser beam LB. Accordingly, it is possible to provide a display module with improved reliability.

Referring to FIG. 9 , the light blocking layer BMI-A according to an exemplary embodiment may have a patterned shape. For example, the light blocking layer BMI-A may be disposed between the second barrier layer BRL and the buffer layer BFL in an area overlapping the display area BA of the first area A1 .

The light blocking layer BMI-A may include a plurality of holes exposing at least a portion of the second barrier layer BRL. The buffer layer BFL may be easily coupled to the second barrier layer BRL through the holes.

10 is a cross-sectional view of an active region according to an embodiment of the present invention. FIG. 10 is a cross-sectional view corresponding to FIG. 5 , and the same/similar reference numerals are used for the same/similar components as those described in FIGS. 1 to 5 , and duplicate descriptions will be omitted.

According to the present exemplary embodiment, an additional light blocking layer BMI-B disposed in an area of the display panel 310 (refer to FIG. 2B ) overlapping the second area A2 may be further included. The additional light blocking layer BMI-B may be disposed between the second barrier layer BRL and the buffer layer BFL. However, the present invention is not limited thereto, and the light blocking layer BMI and the additional light blocking layer BMI-B described with reference to FIG. 6 may be disposed on different layers.

For example, the additional light blocking layer BMI-B of this embodiment may be disposed on the buffer layer BFL, and an insulating layer including silicon oxide is disposed between the light blocking layer BMI and the additional light blocking layer BMI-B. This is additionally provided so that the light blocking layer BMI may be disposed at a lower position than the additional light blocking layer BMI-B.

일 수 있고, 차광층(BMI)의 두께는 2500

일 수 있다. 또한, 추가 차광층(BMI-B)과 차광층(BMI)은 몰리브덴(Mo)을 포함할 수 있다.In this embodiment, the thickness of the additional light blocking layer (BMI-B) is 1000

may be, the thickness of the light blocking layer (BMI) is 2500

can be In addition, the additional light blocking layer BMI-B and the light blocking layer BMI may include molybdenum (Mo).

As the additional light blocking layer BMI-B according to the present exemplary embodiment is disposed under the driving transistor T1 , it is possible to prevent deterioration of the residual-voltage characteristic of the first semiconductor pattern by external light. Accordingly, it is possible to provide a display panel with improved reliability.

11 is a plan view of an active region according to an embodiment of the present invention. 12 is a plan view of an active region according to an embodiment of the present invention. The same/similar reference numerals are used for the same/similar components as those described with reference to FIGS. 1 to 7 , and redundant descriptions are omitted.

The description of the first area A1 and the second area A2 of FIGS. 11 and 12 may correspond to the first area A1 and the second area A2 described with reference to FIGS. 1 to 7 . Accordingly, the first area A1 may be defined as an area having relatively high light transmittance compared to the second area A2 .

The first area A1 may include a transparent area BT, a display area BA and a wiring area BL that surround the transparent area BT. The display area BA and the wiring area BL in which the light blocking layers BMI and BMI-L described with reference to FIGS. 6 and 7 are disposed are shown in a relatively dark color compared to the transmissive area BT.

11 , the first pixel EP1B may have a relatively larger emission area than the second pixel EP2B. In the present exemplary embodiment, the transmissive area BT may be defined as an area surrounded by the display area BA and the wiring area BL. The three sub-pixels E11-B, E12-B, and E13-B have relatively larger areas than the sub-pixels E21, E22, and E23 of the second pixel EP2 emitting corresponding colors. can Also, the spacing between the sub-pixels E11-B, E12-B, and E13-B may be designed to be larger than the spacing between the sub-pixels E21, E22, and E23 of the second pixel EP2.

Although 8 sub-pixels are arranged in one display area BA in FIG. 11 , if the second pixel EP2B includes sub-pixels having a larger area than the sub-pixels of the second pixel EP2B, one display area ( The number of sub-pixels arranged in BA) is not limited to any one.

12 , the first pixel EP1C may have a different arrangement from that of the second pixel EP2C. In the present exemplary embodiment, the transmissive area BT may be defined as an area surrounded by the display area BA and the wiring area BL. The sub-pixels E11-C, E12-C, and E13-C of the first pixel EP1C are arranged in a stripe shape parallel to each other in the first direction DR1 and the second direction DR2, and the second pixel ( The sub-pixels E21 , E22 , and E23 of the EP2C may be arranged in a direction inclined with respect to each of the direction DR1 and the second direction DR2 . Accordingly, the distance between the pixels EP1C in the first area A1 may be increased, so that the light transmittance in the first area A1 may be increased.

According to the present invention, by arranging the pixels in the first area A1 at a lower density than that of the second area A2 and providing the transmission area BT in the first area A1, the first area (A1) can be designed to have high light transmittance.

Although FIG. 12 illustrates that six sub-pixels are disposed in one display area BA, if the second pixel EP2C includes sub-pixels arranged at a lower density and having a different arrangement form than the sub-pixels of the second pixel EP2C, The number of sub-pixels disposed in one display area BA is not limited to any one.

Although the above has been described with reference to the preferred embodiment of the present invention, those skilled in the art or those having ordinary knowledge in the technical field will not depart from the spirit and technical scope of the present invention described in the claims to be described later. It will be understood that various modifications and variations of the present invention can be made without departing from the scope of the present invention.

Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

1000: electronic device 100: window
200: housing unit 300: display module
310: display panel 320: input sensor
A1: first area A2: second area
400: electronic module BMI: light blocking layer

Claims (20)

A first area including a display area, a wiring area, and a transmissive area, and a second area adjacent to the first area are divided into a base layer, a barrier layer disposed on the base layer, and a barrier layer disposed on the barrier layer a display panel including a light blocking layer, a plurality of insulating layers disposed on the base layer, a first pixel disposed in the first area, and a second pixel disposed in a second area; and
an input sensor disposed on the display panel and including sensing insulating layers;
The first region has a relatively higher light transmittance than the second region,
The light-shielding layer,
The electronic device overlaps the display area and the wiring area, and does not overlap the transparent area. The method of claim 1,
on a plane,
The transmission area is
The electronic device of claim 1, wherein the display area is surrounded by the wiring area. The method of claim 1,
The display panel is
a circuit element layer including the base layer, the barrier layer, the light blocking layer, a buffer layer disposed on the barrier layer, the insulating layers, and transistors disposed between the insulating layers;
A light emitting diode including a first electrode connected to the transistors, a second electrode, and a light emitting layer disposed between the first electrode and the second electrode, and a pixel having an opening exposing at least a portion of the first electrode defined a display element layer including a defining layer; and
and a thin film encapsulation layer covering the display element layer and including a first inorganic layer, a second inorganic layer, and an organic layer disposed between the first inorganic layer and the second inorganic layer. . 4. The method of claim 3,
The insulating layers are
Including first to seventh insulating layers,
Any one of the transistors,
a first semiconductor pattern disposed on the buffer layer, covered by the first insulating layer, and including a first active including polysilicon;
a first gate disposed on the first insulating layer, covered by the second insulating layer, and overlapping the first active layer;
an upper electrode disposed on the second insulating layer, covered by the third insulating layer, and overlapping the first gate;
the other of the transistors,
a second semiconductor pattern disposed on the third insulating layer, covered by the fourth insulating layer, and including a second active including a metal oxide;
and a second gate disposed on the fourth insulating layer, covered by the fifth insulating layer, and overlapping a second active layer. 5. The method of claim 4,
a first connection electrode disposed on the fifth insulating layer, covered by the sixth insulating layer, and connected to the transistors through a first contact hole defined through the first to fifth insulating layers;
a first electrode disposed on the sixth insulating layer, covered by the seventh insulating layer, and connecting between the first electrode and the first connection electrode through a second contact hole defined through the sixth insulating layer 2 The electronic device further comprising a connection electrode. 6. The method of claim 5,
The wiring area is
a first gate line disposed on the first insulating layer and branched from the first gate;
an upper electrode line disposed on the second insulating layer and branched from the upper electrode;
a second gate line disposed on the fourth insulating layer and branched from the second gate;
a first connection electrode line disposed on the fifth insulating layer and branched from the first connection electrode; and
and a second connection electrode line disposed on the sixth insulating layer and branched from the second connection electrode. 7. The method of claim 6,
The transmission area is
and overlapping the base layer, the barrier layer, the buffer layer, the sixth insulating layer, the first inorganic layer, the organic layer, and the second organic layer. 6. The method of claim 5,
adjacent to the transmissive area of the display area;
The electronic device of claim 1, further comprising a protective pattern disposed on at least one of the sixth insulating layer and the seventh insulating layer, and comprising a metal. 4. The method of claim 3,
a black matrix overlapping the pixel defining layer and disposed on the input sensor;
a color filter overlapping the light emitting layer; and
The electronic device of claim 1, further comprising an overcoat layer covering the color filter. 10. The method of claim 9,
The sensing insulating layers are
and overlapping the first area and the second area. 10. The method of claim 9,
Among the overcoat layers, the overcoat layer overlapping the transmission region comprises:
An electronic device in contact with any one of the sensing insulating layers. 11. The method of claim 10,
of the black matrix,
A portion of the upper surface of the black matrix adjacent to the transmission region,
An electronic device, characterized in that covered by the overcoat layer. The method of claim 1,
The pixel defining layer,
An electronic device characterized in that it has a black color. The method of claim 1,
The electronic device of claim 1, further comprising an additional light blocking layer disposed on the second region. The method of claim 1,
The light blocking layer,
The electronic device of claim 1, wherein a plurality of holes exposing a portion of the barrier layer have a patterned shape. The method of claim 1,
Each of the first and second pixels includes a plurality of sub-pixels providing light of first to third colors,
The arrangement of the sub-pixels included in the first pixel and the second pixel is,
Electronic devices characterized in that they are different from each other. The method of claim 1,
Each of the first pixel and the second pixel includes a plurality of sub-pixels providing light of first to third colors,
The area between the sub-pixels providing the same light is,
The electronic device of claim 1, wherein the first pixel is larger than the second pixel. The method of claim 1,
The transmission area is
and surrounded by the wiring area and the display area. 19. The method of claim 18,
The electronic device of claim 1, wherein the transmission region has a cross shape. The method of claim 1,
an electronic module overlapping the first area and disposed under the display panel;
The electronic module is
An electronic device comprising at least one of a sound output module, a light emitting module, a light receiving module, and a camera module.

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