KR20220125114A - Method and device for encoding - Google Patents

Abstract

An encoding method and device are disclosed. According to one embodiment of the present invention, the encoding method includes the steps of: receiving input data represented by a 16-bit floating point; adjusting a number of bits of an exponent and a mantissa of the input data to split the input data into 4-bit units; and encoding the input data in which the number of bits has been adjusted such that the exponent is a multiple of 4.

Description

Encoding method and apparatus

The following embodiments relate to an encoding method and apparatus.

An artificial neural network is implemented with reference to a computational architecture. With the recent development of artificial neural network technology, research on analyzing input data and extracting valid information using artificial neural networks in various types of electronic systems is being actively conducted. A device that processes artificial neural networks requires a large amount of computation on complex input data. Therefore, in order to extract desired information by analyzing a large amount of input data in real time using the artificial neural network, a technology capable of efficiently processing the computation of the artificial neural network is required.

An encoding method according to an embodiment includes: receiving input data expressed in 16-bit half floating point; adjusting the number of bits of an exponent and a mantissa of the input data so that the input data can be divided into 4-bit units; and encoding the input data whose number of bits is adjusted so that the exponent part is a multiple of four.

The step of adjusting the number of bits may include: allocating 4 bits to the exponent part; and allocating 11 bits to the mantissa.

The encoding may include: calculating a quotient and a remainder obtained by dividing a value obtained by adding 4 to an exponent of the input data by 4; encoding the exponent portion based on the quotient; and encoding the mantissa part based on the remainder.

The encoding of the exponent part may include encoding the exponent part based on the quotient and a bias.

The encoding of the mantissa may include determining a first bit value of the mantissa to be 1 when the remainder is 0.

In the encoding of the mantissa part, when the remainder is 1, the first bit value of the mantissa part may be determined as 0, and the second bit value of the mantissa part may be determined as 1.

The step of encoding the mantissa part comprises determining, when the remainder is 2, the first bit value of the mantissa part as 0, the second bit value of the mantissa part as 0, and the third bit value of the mantissa part as 1 may include

In the encoding of the mantissa, when the remainder is 3, the first bit value of the mantissa part is set to 0, the second bit value of the mantissa part is set to 0, the third bit value of the mantissa part is set to 0, and the fourth bit determining the value to be 1.

A calculation method according to an embodiment may include: receiving first operand data expressed as a 4-bit fixed point; receiving second operand data having a size of 16 bits; determining a data type of the second operand data; encoding the second operand data when the second operand data is a floating point type; separating the encoded second operand data into four bricks of a 4-bit unit; and performing a MAC operation between the second operand data divided into the four bricks and the first operand data.

The encoding may include: adjusting the number of bits of the exponent part and the mantissa part of the second operand data so that the second operand data can be divided into 4-bit units; and encoding the second operand data in which the number of bits is adjusted so that the exponent part is a multiple of 4.

The separating may include separating the encoded second operand data into one exponential part brick data and three mantissa part brick data.

The performing of the MAC operation may include: performing a multiplication operation between each of the three mantissa part brick data and the first operand data; comparing the accumulated exponential part data stored in the exponential part register with the exponential part brick data; and accumulating the result of performing the multiplication operation on accumulated mantissa data stored in each of the three mantissa registers based on the comparison result.

The accumulating may include aligning the accumulated mantissa data stored in each of the three mantissa registers and an accumulated position of the multiplication operation result based on the comparison result.

The operation method according to an embodiment may further include, when the second operand data is a fixed number type, dividing the second operand data into four blocks of 4-bit units for parallel data operation.

The encoding apparatus according to an embodiment receives input data expressed in 16-bit floating point and divides the input data into 4-bit units, so as to divide the input data into an exponent of the input data. and a processor that adjusts the number of bits of a mantissa and encodes the input data whose number of bits is adjusted so that the exponent part can be a multiple of 4.

The processor may allocate 4 bits to the exponent part and 11 bits to the mantissa part.

The processor may calculate a quotient and a remainder obtained by dividing a value obtained by adding 4 to an exponent part of the input data by 4, encode the exponent part based on the quotient, and encode the mantissa part based on the remainder.

The arithmetic unit according to an embodiment receives first operand data expressed as a 4-bit fixed point, receives 16-bit second operand data, and a data type of the second operand data is determined, and when the second operand data is a floating point type, the second operand data is encoded, the encoded second operand data is divided into four bricks of a 4-bit unit, and the four and a processor that performs a MAC operation between the second operand data separated by bricks and the first operand data.

The processor adjusts the number of bits in the exponent part and mantissa part of the second operand data to separate the second operand data in 4-bit units, and adjusts the number of bits so that the exponent part is a multiple of 4 The second operand data may be encoded.

The processor may separate the encoded second operand data into one exponential part brick data and three mantissa part brick data.

The processor performs a multiplication operation between each of the three mantissa part brick data and the first operand data, compares the accumulated exponent part data stored in the exponent part register with the exponent part brick data, and based on the comparison result , the result of performing the multiplication operation may be accumulated in accumulated mantissa data stored in each of the three mantissa registers.

The processor may align the accumulated mantissa data stored in each of the three mantissa registers and an accumulated position of the multiplication operation result based on the comparison result.

When the second operand data is a fixed number type, the processor may divide the second operand data into four blocks of 4-bit units for parallel data operation.

1A is a diagram for explaining a deep learning calculation method using an artificial neural network.
1B is a diagram for explaining data and a filter of an input feature map provided as an input in a deep learning operation.
1C is a diagram for explaining a process of performing a convolution operation based on deep learning.
1D is a diagram for explaining a method of performing a convolution operation using a systolic array.
2 is a flowchart illustrating an encoding method according to an embodiment.
3 is a diagram for describing an encoding method according to an embodiment.
4 is a diagram for explaining a calculation method according to an embodiment.
FIG. 5 is a diagram for explaining a method of performing a MAC operation between first operand data expressed as a 4-bit fixed point and second operand data expressed as a 16-bit half floating point according to an embodiment.
6 is a diagram illustrating a method of aligning data according to an exponential difference according to an exemplary embodiment.
7 is a block diagram illustrating an arithmetic device according to an embodiment.

Specific structural or functional contents disclosed in this specification are merely exemplified for the purpose of describing embodiments according to technical concepts, and may be embodied in various other forms and are not limited to the described structures or functions.

Terms such as first or second may be used to describe various elements, but these terms should be understood only for the purpose of distinguishing one element from another element. For example, a first component may be termed a second component, and similarly, a second component may also be termed a first component.

When a component is referred to as being “connected” or “connected” to another component, it may be directly connected or connected to the other component, but it is understood that other components may exist in between. it should be On the other hand, when it is said that a certain element is "directly connected" or "directly connected" to another element, it should be understood that the other element does not exist in the middle. Expressions describing the relationship between elements, for example, “between” and “between” or “neighboring to” and “directly adjacent to”, etc. should be interpreted similarly.

The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present specification, terms such as “comprise” or “have” are intended to designate that the described feature, number, step, operation, component, part, or combination thereof exists, and includes one or more other features or numbers. , it is to be understood that it does not preclude the possibility of the presence or addition of steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related art, and should not be interpreted in an ideal or excessively formal meaning unless explicitly defined in the present specification. does not

The embodiments may be implemented in various types of products, such as data centers, servers, personal computers, laptop computers, tablet computers, smart phones, televisions, smart home appliances, intelligent cars, kiosks, wearable devices, and the like. Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Like reference numerals in each figure indicate like elements.

1A is a diagram for explaining a deep learning calculation method using an artificial neural network.

Artificial intelligence (AI) algorithms, including deep learning, input the input data 10 to an artificial neural network (ANN), and learn the output data 30 through operations such as convolution. characterized in that The artificial neural network may refer to a computer scientific architecture modeling a biological brain. In an artificial neural network, nodes corresponding to neurons in the brain are connected to each other and collectively operate to process input data. Examples of various types of neural networks include Convolutional Neural Network (CNN), Recurrent Neural Network (RNN), Deep Belief Network (DBN), Restricted Boltzman Machine Machine, RBM) method, but is not limited thereto. In a feed-forward neural network, neurons in the neural network have links with other neurons. Such connections may extend through the neural network in one direction, for example in the forward direction.

Referring to FIG. 1A , input data 10 is input to an artificial neural network, and an artificial neural network including one or more layers (eg, a convolutional neural network (CNN) 20) is generated. The structure in which the output data 30 is output through the is shown. The artificial neural network may be a deep neural network having two or more layers.

The convolutional neural network 20 may be used to extract “features” such as borders, line colors, etc. from the input data 10 . The convolutional neural network 20 may include a plurality of layers. Each layer may receive data, and may generate data output from the corresponding layer by processing data input to the corresponding layer. The data output from the layer may be a feature map generated by performing a convolution operation on an image or an input feature map input to the convolutional neural network 20 with weight values of one or more filters. have. The initial layers of the convolutional neural network 20 may be operated to extract low-level features such as edges or gradients from the input. Subsequent layers of the convolutional neural network 20 may extract progressively more complex features such as eyes, nose, etc. in the image.

1B is a diagram for explaining data and a filter of an input feature map provided as an input in a deep learning operation.

Referring to FIG. 1B , the input feature map 100 may be a set of pixel values or numerical data of an image input to the artificial neural network, but is not limited thereto. In FIG. 1B , the input feature map 100 may be defined as a pixel value of an image to be learned through an artificial neural network. For example, the input feature map 100 may have a pixel of 256×256 and a depth of K. However, the above values are exemplary, and the pixel size of the input feature map 100 is not limited to the above example.

N filters 110-1 to 110-n may be formed. Each of the plurality of filters 110-1 to 110-n may include a weight value of n by n (n×n). For example, each of the plurality of filters 110-1 to 110-n may have a pixel of 3×3 and a depth value of K. However, the size of the filter is exemplary, and the size of each of the plurality of filters 110 - 1 to 110 - n is not limited to the above example.

1C is a diagram for explaining a process of performing a convolution operation based on deep learning.

Referring to FIG. 1C , in the process of performing the convolution operation in the artificial neural network, multiplication and addition operations are performed between the input feature map 100 and the filter 110 in each layer to generate an output value, and the output value is accumulated and summing them, it may mean a process of generating the output feature map 120 .

The process of performing the convolution operation is a process of performing multiplication and addition operations by applying a filter 110 having a constant size, that is, n×n, from the upper left to the lower right of the input feature map 100 in the current layer. Hereinafter, a process of performing a convolution operation when the size of the filter 110 is 3×3 will be described.

For example, first, in the upper left region 101 of the input feature map 100 , 3×3, that is, a total of 9 data (x11 to 3 data in the first direction and 3 data in the second direction) x33) is multiplied by weight values w11 to w33 of the filter 110, respectively. After that, if all the output values of the multiplication operation, that is, x11*w11, x12*w12, x13*w13, x21*w21, x22*w22, x23*w23, x31*w31, x32*w32, x33*w33, are accumulated and summed, The 1-1 output data y11 of the output feature map 120 is generated.

Thereafter, the operation is performed while moving from the first area 101 at the upper left of the input feature map 100 to the second area 102 by data units. In this case, the number of moving data in the input feature map 100 in the convolution operation process is called a stride, and the size of the generated output feature map 120 may be determined according to the size of the stride. For example, when the stride is 1, a total of nine input data (x12 to x34) included in the second region 102 is multiplied by the weight values w11 to w33 of the filter 110, and multiplication is performed. The output feature map (120 ) of 1-2 output data y12 is generated.

1D is a diagram for explaining a method of performing a convolution operation using a systolic array.

Referring to FIG. 1D , each data of the input feature map 130 is sequentially input to Processing Elements (PEs) 141 to 149 according to a clock having a constant latency. It can be mapped to an array. The processing element may be a multiplication addition operator.

In the first clock, the first-first data (x11) of the first row (①) of the systolic array may be input to the first processing element 141 . Although not shown in FIG. 1D , the 1-1 data (x11) may be multiplied by a weight value of w11 in the first clock. Thereafter, in the second clock, the 1-1 th data (x11) is input to the second processing element 142, the 2-1 th data (x21) is input to the first processing element 141, and the 1-2 th data (x12) may be input to the fourth processing element 144 . Similarly, in the third clock, the 1-1 th data (x11) is input to the third processing element 143, the 2-1 th data (x21) is input to the second processing element 142, and the 1-2 th data The data x12 may be input to the fifth processing element 145 . In the third clock, the 3-1 th data (x31) is input to the first processing element 141, the 2-2 th data (x22) is input to the fourth processing element 144, and the 1-3 th data ( x13) may be input to the seventh processing element 147 .

As described above, the input feature map 130 is input to each processing element in the processing elements 141 to 149 according to a sequential clock, and multiplication and addition operations with the input weight value according to each clock may be performed. . An output feature map may be generated by cumulatively summing values output through multiplication and addition operations of sequentially input data of the input feature map 130 and a weight value.

2 is a flowchart illustrating an encoding method according to an embodiment.

The operations of FIG. 2 may be performed in the illustrated order and manner, but the order of some operations may be changed or some operations may be omitted without departing from the spirit and scope of the illustrated embodiment. A number of the operations shown in FIG. 2 may be performed in parallel or concurrently. One or more blocks and combinations of blocks of FIG. 2 may be implemented by a special-purpose hardware-based computer that performs a particular function, or a combination of special-purpose hardware and computer instructions.

A calculation format required for calculation using a neural network according to an embodiment may be different depending on the type of application. For example, in the case of an application for determining the object type of an image, a bit precision lower than 8 bits may be sufficient, and in the case of an application related to voice, a bit precision higher than 8 bits may be required.

An input operand of a multiply-and-accumulate (MAC) operation, which is an essential operator of deep learning according to an embodiment, may also be configured with various precisions according to circumstances. For example, a gradient, one of the input operands required for training a neural network, requires a precision of about 16-bit half floating point, and the other input operands, the input feature map and weight, are of low precision. Fixed point processing may also be possible.

The basic method for processing data having such various requirements is to create and write hardware components that can perform MAC operation for each input type by using a lot of hardware resources unnecessarily. .

In order to perform MAC operations on various input types using single hardware, hardware operation units should be designed based on the data type with the highest complexity. However, in this case, even when a low-precision operation is entered, it is inefficient because it has to be executed through an operator made based on high-precision data with the highest complexity. More specifically, a hardware implementation area may increase unnecessarily, and power consumed by the hardware may also increase unnecessarily.

According to the encoding method and the operation method according to an embodiment, it is possible to efficiently drive a low-precision reasoning process while maintaining a high-precision gradient operation in a learning process.

In operation 210, the encoding apparatus according to an embodiment receives input data expressed in 16-bit floating point.

In step 220, the encoding apparatus according to an embodiment adjusts the number of bits of the exponent and mantissa of the input data so that the input data can be divided into 4-bit units. . The encoding apparatus according to an embodiment of the present invention provides {sign, The number of constituent bits can be adjusted in the form exponent, mantissa}={1,4,11}. Accordingly, the number of bits allocated to the exponent is reduced by one, and the number of bits allocated to the mantissa is increased by one more to 11 bits.

In step 230, the encoding apparatus according to an embodiment encodes the input data whose number of bits is adjusted so that the exponent part is a multiple of 4. The encoding apparatus according to an embodiment secures an exponent range wider than that of a conventional 16-bit half floating point and at the same time steps the exponent part by 4 to facilitate bit-brick operation. ) can be encoded. In the following, a specific method of encoding is described with reference to FIG. 3 .

3 is a diagram for describing an encoding method according to an embodiment.

Before describing an encoding method according to an embodiment, a method for representing data in floating point numbers will be described in advance. For example, if 263.3 expressed in decimal system is expressed in binary system, it is 100000111.0100110??, which can be expressed as 1.0000011101*2 ⁸ . Furthermore, when expressed as a floating point, the bit (1 bit) of the sign part is 0 (positive number), the bit (5 bits) of the exponent part is 11000 (8+16 (bias)), and the mantissa bit is 0000011101 (10 bits), and finally It can be expressed as 0110000000011101.

Referring to FIG. 3 , the encoding apparatus according to an embodiment may adjust the number of constituent bits in the form {sign, exponent, mantissa}={1,4,11}. For example, by adjusting 1.0000011101*2 ⁸ in the above example to 0.10000011101*2 ⁹ , 1 bit can be allocated to the sign part, 4 bits to the exponent part, and 11 bits to the mantissa part.

The encoding apparatus according to an embodiment may encode the input data in which the number of bits is adjusted so that the exponent part may be a multiple of 4. More specifically, the encoding apparatus may calculate a quotient and a remainder obtained by dividing a value obtained by adding 4 to an exponent part of the input data by 4, encode the exponent part based on the quotient, and encode the mantissa part based on the remainder.

The encoding apparatus according to an embodiment may encode the exponent part based on a quotient and a bias.

The encoding apparatus according to an embodiment may determine the first bit value of the mantissa part as 1 when the remainder is 0, and when the remainder is 1, the first bit value of the mantissa part is set to 0, and the second bit value of the mantissa part is set to 0. The bit value may be determined to be 1, and if the remainder is 2, the first bit value of the mantissa part may be determined as 0, the second bit value of the mantissa part may be determined as 0, and the third bit value of the mantissa part may be determined as 1. , the remainder is 3, it is possible to determine the first bit value of the mantissa part as 0, the second bit value of the mantissa part as 0, and the third bit value of the mantissa part as 1. If this is expressed in a table, it is shown in Table 1.

For example, the encoding device may convert 0.10000011101*2 ⁹ into 0.10000011101*2 ^4*3-3 , and may convert it back into 0.00010000011101*2 ^4*3 . Based on this, the encoding apparatus may encode bits (4 bits) of the exponent part as 1011 (3+8 (bias)), bits (1 bit) of the sign part as 0 (positive numbers), and bits of the mantissa part as 00010000011.

The encoding apparatus according to an embodiment may divide and express encoded data into one exponential part brick data and three mantissa part brick data. The three mantissa brick data can be divided into top brick data, middle brick data, and bottom brick data, and the top brick can be composed of 1 sign bit and 3 mantissa bits. have. In the above example, the index brick data may be 1011, the top brick data may be 0000, the middle brick data may be 1000, and the bottom brick data may be 0011.

According to an embodiment, the 4-bit exponential part brick data and the 4-bit top/middle/bottom brick data may be easily separated in hardware. In addition, since the exponential difference, which is always considered in the floating-point addition operation, always differs by a multiple of 4, the multiplied values are converted to fixed-point adders without special shifting. A structure capable of fusing may become possible.

4 is a diagram for explaining a calculation method according to an embodiment.

Referring to FIG. 4 , the arithmetic unit according to an embodiment may receive first operand data 410 expressed as a 4-bit fixed point and second operand data 420 having a size of 16 bits. can The computing device according to an embodiment may include the encoding device described above with reference to FIGS. 2 to 3 . The first operand data may be a weight and/or an input feature map, and the second operand data may be a gradient.

In operation 430 , the computing device according to an embodiment may determine the data type of the second operand data.

In the operation device according to an embodiment, in step 440-1, when the second operand data 420 is of a fixed-point type, the second operand data 420 is converted into four blocks of 4-bit units for parallel data operation. can be separated into

In step 440-2, the arithmetic device according to an embodiment converts the second operand data 420 to the method described above with reference to FIGS. 2 to 3 when the second operand data 420 is a floating point type. can be encoded accordingly. For example, the arithmetic unit may adjust the number of bits of the exponent part and mantissa part of the second operand data so as to separate the second operand data 420 in units of 4 bits, and the exponent part may be a multiple of 4. It is possible to encode the second operand data whose number of bits is adjusted so as to be able to do so.

In operation 450 , the arithmetic device according to an embodiment may divide the encoded second operand data into four bricks in units of 4 bits. More specifically, the arithmetic unit may separate the encoded second operand data into one exponential part brick data and three mantissa part brick data.

In operation 460 , the computing device according to an embodiment may perform a MAC operation between the second operand data and the first operand data 410 separated into four blocks. The arithmetic unit may perform a multiplication operation between each of the three mantissa block data and the first operand data 410 . A specific method of performing a MAC operation between the second operand data and the first operand data 410 separated into four bricks will be described below with reference to FIG. 5 .

In operation 470 , the computing device according to an embodiment may determine the data type of the second operand data.

In operation 480-1, the arithmetic device according to an embodiment may sum the four separate outputs when the data of the second operand data 420 is a fixed-point type.

In step 480-2, the arithmetic device according to an embodiment compares the accumulated exponent data stored in the exponent register and the exponent block data when the data of the second operand data 420 is of a floating point type, Based on the comparison result, the result of performing the multiplication operation may be accumulated in the accumulated mantissa data stored in each of the three mantissa registers. More specifically, the arithmetic unit may align and accumulate accumulated mantissa data stored in each of the three mantissa registers based on the above-described comparison result and an accumulated position of a result of performing a multiplication operation. A detailed method of accumulating a result of performing a multiplication operation in accumulated mantissa data stored in each of the three mantissa registers based on the comparison result will be described below with reference to FIG. 6 .

FIG. 5 is a diagram for explaining a method of performing a MAC operation between first operand data expressed as a 4-bit fixed point and second operand data expressed as a 16-bit half floating point according to an embodiment.

Referring to FIG. 5 , an arithmetic unit according to an embodiment may include a 4*4 unit multiplier, an exponent register, and three mantissa registers. The three mantissa registers may include a top brick register storing an operation result of the top brick data, a middle brick register storing an operation result of the middle brick data, and a bottom brick register storing an operation result of the bottom brick data.

If the second operand data is a 16-bit half floating-point type, the arithmetic unit according to an embodiment divides three mantissa parts into three 4-bit brick data, and multiplies the first operand data with the first operand data through a multiplier designed as 4*4. can be done The resulting three multiplication results are aligned according to the exp diff, which is the difference between the accumulated exponent data stored in the exponent register and the exponential block data, and the accumulated mantissa stored in each mantissa register. A result of performing a multiplication operation may be accumulated and stored in data.

6 is a diagram illustrating a method of aligning data according to an exponential difference according to an exemplary embodiment.

Referring to FIG. 6 , the mantissa register provided for accumulating 8-bit (4bit*4bit) data that is the output of the multiplier according to an embodiment consists of 12 bits. The arithmetic device according to an embodiment may accumulate by designating the positions of the outputs of the multiplier according to the exponential difference.

For example, when the exponent difference is 0 (when the exponent of the second operand data is greater than the stored accumulated exponent data), the result of the multiplication operation and the accumulated mantissa data stored in each of the three mantissa registers are arranged in the same position so it can be accumulated.

In addition, when the exponent difference is -1 (when the exponent of the second operand data is larger than the stored accumulated exponent data), the result of the multiplication operation is shifted by 4 bits to the right from the accumulated mantissa data stored in each of the three mantissa registers. It can be accumulated by sorting it so that it can be indexed.

In addition, when the exponent difference is 1 (when the exponent of the second operand data is smaller than the stored accumulated exponent data), the result of the multiplication operation is shifted by 4 bits to the left of the accumulated mantissa data stored in each of the three mantissa registers It can be accumulated by sorting it so that it becomes possible.

7 is a block diagram illustrating an arithmetic device according to an embodiment.

Referring to FIG. 7 , a computing device 700 according to an embodiment includes a processor 710 . The computing device 700 may further include a memory 730 and a communication interface 750 . Processor 710 , memory 730 , communication interface 750 , and sensors 770 may communicate with each other via communication bus 705 .

The processor 710 receives first operand data expressed in 4-bit fixed point, receives 16-bit second operand data, determines a data type of the second operand data, When the second operand data is a floating-point type, the second operand data is encoded, the encoded second operand data is divided into 4 bricks of a 4-bit unit, and the second operand data divided into 4 bricks and MAC operation between the first operand data is performed.

The memory 730 may be a volatile memory or a non-volatile memory.

According to an embodiment, the processor 710 adjusts the number of bits in the exponent part and mantissa part of the second operand data so that the second operand data can be divided into 4-bit units, and the exponent part becomes a multiple of 4 The second operand data of which the number of bits is adjusted may be encoded.

The processor 710 may separate the encoded second operand data into one exponential part brick data and three mantissa part brick data.

The processor 710 performs a multiplication operation between each of the three mantissa part brick data and the first operand data, compares the accumulated exponent part data stored in the exponent part register and the exponent part brick data, and based on the comparison result, 3 A result of performing a multiplication operation may be accumulated in accumulated mantissa data stored in each of the n mantissa registers.

The processor 710 may align the accumulated mantissa data stored in each of the three mantissa registers and the accumulated position of the multiplication operation result based on the comparison result.

In addition, the processor 710 may perform at least one method described above with reference to FIGS. 1A to 6 or an algorithm corresponding to the at least one method. The processor 710 may execute a program and control the computing device 700 . The program code executed by the processor 710 may be stored in the memory 730 . The computing device 700 may be connected to an external device (eg, a personal computer or a network) through an input/output device (not shown), and may exchange data. The computing device 700 may be mounted on various computing devices and/or systems, such as a smart phone, a tablet computer, a laptop computer, a desktop computer, a television, a wearable device, a security system, and a smart home system.

The embodiments described above may be implemented by a hardware component, a software component, and/or a combination of a hardware component and a software component. For example, the apparatus, methods and components described in the embodiments may include a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a PLU. It may be implemented using one or more general purpose or special purpose computers, such as a programmable logic unit, microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. The processing device may also access, store, manipulate, process, and generate data in response to execution of the software. For convenience of understanding, although one processing device is sometimes described as being used, one of ordinary skill in the art will recognize that the processing device includes a plurality of processing elements and/or a plurality of types of processing elements. It can be seen that may include For example, the processing device may include a plurality of processors or one processor and one controller. Other processing configurations are also possible, such as parallel processors.

The software may comprise a computer program, code, instructions, or a combination of one or more thereof, which configures a processing device to operate as desired or is independently or collectively processed You can command the device. The software and/or data may be any kind of machine, component, physical device, virtual equipment, computer storage medium or device, to be interpreted by or to provide instructions or data to the processing device. , or may be permanently or temporarily embody in a transmitted signal wave. The software may be distributed over networked computer systems and stored or executed in a distributed manner. Software and data may be stored in one or more computer-readable recording media.

The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions recorded on the medium may be specially designed and configured for the embodiment, or may be known and available to those skilled in the art of computer software. Examples of the computer-readable recording medium include magnetic media such as hard disks, floppy disks and magnetic tapes, optical media such as CD-ROMs and DVDs, and magnetic such as floppy disks. - includes magneto-optical media, and hardware devices specially configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. Examples of program instructions include not only machine language codes such as those generated by a compiler, but also high-level language codes that can be executed by a computer using an interpreter or the like.

As described above, although the embodiments have been described with reference to the limited drawings, those skilled in the art may apply various technical modifications and variations based on the above. For example, the described techniques are performed in a different order than the described method, and/or the described components of the system, structure, apparatus, circuit, etc. are combined or combined in a different form than the described method, or other components Or substituted or substituted by equivalents may achieve an appropriate result.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (24)

receiving input data represented by 16-bit half floating point;
adjusting the number of bits of an exponent and a mantissa of the input data so that the input data can be divided into 4-bit units; and
encoding the input data whose number of bits is adjusted so that the exponent part is a multiple of four;
An encoding method comprising .
According to claim 1,
The step of adjusting the number of bits is
allocating 4 bits to the exponent part; and
allocating 11 bits to the mantissa
Including, encoding method.
According to claim 1,
The encoding step
calculating a quotient and remainder obtained by dividing a value obtained by adding 4 to an exponent of the input data by 4;
encoding the exponent portion based on the quotient; and
encoding the mantissa based on the remainder;
An encoding method comprising .
4. The method of claim 3,
The step of encoding the exponent part is
encoding the exponent part based on the quotient and a bias;
Including, encoding method.
4. The method of claim 3,
The step of encoding the mantissa is
determining the first bit value of the mantissa to be 1 when the remainder is 0
Including, encoding method.
4. The method of claim 3,
The step of encoding the mantissa is
When the remainder is 1, determining the first bit value of the mantissa part as 0 and the second bit value of the mantissa part as 1;
Including, encoding method.
4. The method of claim 3,
The step of encoding the mantissa is
When the remainder is 2, determining the first bit value of the mantissa part as 0, the second bit value of the mantissa part as 0, and the third bit value of the mantissa part as 1;
Including, encoding method.
4. The method of claim 3,
The step of encoding the mantissa is
When the remainder is 3, determining the first bit value of the mantissa part as 0, the second bit value of the mantissa part as 0, the third bit value of the mantissa part as 0, and the fourth bit value as 1;
Including, encoding method.
Receiving first operand data represented by a 4-bit fixed point (fixed point);
receiving second operand data having a size of 16 bits;
determining a data type of the second operand data;
encoding the second operand data when the second operand data is a floating point type;
separating the encoded second operand data into four bricks of a 4-bit unit; and
performing a MAC operation between the second operand data and the first operand data divided into the four blocks
Including, calculation method.
10. The method of claim 9,
The encoding step
adjusting the number of bits in the exponent part and the mantissa part of the second operand data so that the second operand data can be divided into 4-bit units; and
encoding the second operand data whose number of bits is adjusted so that the exponent part is a multiple of four;
Including, calculation method.
10. The method of claim 9,
The separating step
Separating the encoded second operand data into one exponential part brick data and three mantissa part brick data
Including, calculation method.
12. The method of claim 11,
The step of performing the MAC operation is
performing a multiplication operation between each of the three mantissa part brick data and the first operand data;
comparing the accumulated exponential part data stored in the exponential part register with the exponential part brick data; and
accumulating the result of performing the multiplication operation on accumulated mantissa data stored in each of the three mantissa registers based on the comparison result
Including, calculation method.
13. The method of claim 12,
The accumulating step
aligning the accumulated mantissa data stored in each of the three mantissa registers and the accumulated position of the multiplication operation result based on the comparison result;
Including, calculation method.
10. The method of claim 9,
separating the second operand data into four blocks of 4-bit units for parallel data operation when the second operand data is a fixed number point type;
Further comprising, a calculation method.
A computer-readable storage medium storing one or more programs including instructions for performing the method of any one of claims 1 to 14.
Bits of an exponent and a mantissa of the input data to receive input data expressed in 16-bit floating point and separate the input data into 4-bit units A processor that adjusts the number and encodes the input data with the number of bits adjusted so that the exponent part is a multiple of four.
Encoding device comprising a.
17. The method of claim 16,
the processor
and assigning 4 bits to the exponent part and assigning 11 bits to the mantissa part.
17. The method of claim 16,
the processor
calculating a quotient and a remainder obtained by dividing a value obtained by adding 4 to an exponent part of the input data by 4, encoding the exponent part based on the quotient, and encoding the mantissa part based on the remainder.
Receives first operand data represented by a 4-bit fixed point, receives second operand data of 16-bit size, determines a data type of the second operand data, and the second operand When the data is a floating-point type, the second operand data is encoded, the encoded second operand data is divided into four bricks of a 4-bit unit, and the second operand data divided into the four bricks and a processor that performs a MAC operation between the first operand data
Computing device comprising.
20. The method of claim 19,
the processor
A second second in which the number of bits of the exponent and mantissa of the second operand data is adjusted so that the second operand data can be divided into 4-bit units, and the number of bits is adjusted so that the exponent part is a multiple of 4 An encoding device for encoding operand data.
20. The method of claim 19,
the processor
and separating the encoded second operand data into one exponential part brick data and three mantissa part brick data.
22. The method of claim 21,
the processor
A multiplication operation is performed between each of the three mantissa part brick data and the first operand data, the accumulated exponent part data stored in the exponent part register is compared with the exponent part brick data, and based on the comparison result, three and accumulating a result of performing the multiplication operation on accumulated mantissa data stored in each mantissa register.
23. The method of claim 22,
the processor
and aligning an accumulated position of the accumulated mantissa data stored in each of the three mantissa registers and a result of performing the multiplication operation based on the comparison result.
20. The method of claim 19,
the processor
When the second operand data is a fixed decimal point type, the encoding apparatus of claim 1, wherein the second operand data is divided into four blocks of a 4-bit unit for parallel data operation.

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