KR20220120611A - Automatic memory overclocking - Google Patents

Abstract

Automatic memory overclocking includes increasing the memory frequency setting for the memory module until the memory stability test fails; determining an overclocked memory frequency setting comprising a highest memory frequency setting that passes a memory stability test; and creating a profile including the overclocked memory frequency setting.

Description

Automatic memory overclocking

Settings for memory modules can be configured according to vendor profiles or user input specifications. These profiles are often created and tested using a system configuration that is different from the user's system. In addition, user input specifications may be constrained using margins determined and tested using these different system configurations.

1 is a block diagram of an exemplary processor for automatic memory overclocking in accordance with some embodiments.
2 is a flow diagram of an exemplary method for automatic memory overclocking in accordance with some embodiments.
3 is a flow diagram of an exemplary method for automatic memory overclocking in accordance with some embodiments.
4 is a flow diagram of an exemplary method for automatic memory overclocking in accordance with some embodiments.
5 is a flow diagram of an exemplary method for automatic memory overclocking in accordance with some embodiments.

In some embodiments, the automatic memory overclocking method includes increasing a memory frequency setting for a memory module until a memory stability test fails; determining an overclocked memory frequency setting comprising a highest memory frequency setting that passes a memory stability test; and creating a profile including the overclocked memory frequency setting.

In some embodiments, increasing the memory frequency setting for the memory module until the memory stability test fails comprises determining one or more memory timing settings, the method corresponding to the overclocked memory frequency setting determining one or more overclocked memory timing settings including one or more memory timing settings; Here, generating the profile includes generating a profile including one or more overclocked memory timing settings. In some embodiments, the one or more memory timing settings are: column access strobe (CAS) latency, row address strobe (RAS) to column address strobe (CAS) delay (write), row address strobe (RAS) to column address strobe (CAS) ) delay (read), low precharge time, and/or low active time. In some embodiments, the method further comprises determining one or more subtiming settings based on the overclocked memory frequency setting and/or one or more overclocked memory timing settings; Here, generating the profile includes generating a profile including one or more subtiming settings. In some embodiments, the one or more subtiming settings are based on an overclocked memory frequency setting and/or one or more rules applied to the one or more memory timing settings. In some embodiments, the method further comprises storing the profile in a storage location. In some embodiments, the method includes loading a profile from a storage location; and applying the profile to the memory module.

In some embodiments, an apparatus for automatic memory overclocking performs steps comprising: increasing a memory frequency setting for a memory module until a memory stability test fails; determining an overclocked memory frequency setting comprising a highest memory frequency setting that passes a memory stability test; and creating a profile including the overclocked memory frequency setting.

In some embodiments, increasing the memory frequency setting for the memory module until the memory stability test fails comprises determining one or more memory timing settings, wherein the steps correspond to the overclocked memory frequency setting. determining one or more overclocked memory timing settings including one or more memory timing settings; Here, generating the profile includes generating a profile including one or more overclocked memory timing settings. In some embodiments, the one or more memory timing settings are: column access strobe (CAS) latency, row address strobe (RAS) to column address strobe (CAS) delay (write), row address strobe (RAS) to column address strobe (CAS) ) delay (read), low precharge time, and/or low active time. In some embodiments, the steps further comprise determining one or more subtiming settings based on the overclocked memory frequency setting and/or one or more overclocked memory timing settings; Here, generating the profile includes generating a profile including one or more subtiming settings. In some embodiments, the one or more subtiming settings are based on an overclocked memory frequency setting and/or one or more rules applied to the one or more memory timing settings. In some embodiments, the steps further comprise storing the profile in a storage location. In some embodiments, the steps include loading a profile from a storage location; and applying the profile to the memory module.

In some embodiments, a computer program product disposed on a non-transitory computer-readable medium comprises computer program instructions for automatic memory overclocking that, when executed, cause a computer to perform steps comprising: The steps include increasing the memory frequency setting for the memory module until the memory stability test fails; determining an overclocked memory frequency setting comprising a highest memory frequency setting that passes a memory stability test; and creating a profile including the overclocked memory frequency setting.

In some embodiments, increasing the memory frequency setting for the memory module until the memory stability test fails comprises determining one or more memory timing settings, wherein the steps correspond to the overclocked memory frequency setting. determining one or more overclocked memory timing settings including one or more memory timing settings; Here, generating the profile includes generating a profile including one or more overclocked memory timing settings. In some embodiments, the one or more memory timing settings are: column access strobe (CAS) latency, row address strobe (RAS) to column address strobe (CAS) delay (write), row address strobe (RAS) to column address strobe (CAS) ) delay (read), low precharge time, and/or low active time. In some embodiments, the steps further comprise determining one or more subtiming settings based on the overclocked memory frequency setting and/or one or more overclocked memory timing settings; Here, generating the profile includes generating a profile including one or more subtiming settings. In some embodiments, the one or more subtiming settings are based on an overclocked memory frequency setting and/or one or more rules applied to the one or more memory timing settings. In some embodiments, the steps further comprise storing the profile in a storage location. In some embodiments, the steps include loading a profile from a storage location; and applying the profile to the memory module.

Automatic memory overclocking according to the present disclosure is generally implemented with computers, ie with automated computing machines. Accordingly, for further explanation, FIG. 1 presents a block diagram of an automated computing machine that includes an exemplary computer 100 configured for automatic memory overclocking. The computer 100 of FIG. 1 includes a random access memory 104 (RAM) coupled to the processor 102 and other components of the computer 100 via a high-speed memory bus 106 and a bus adapter 108 , as well as a random access memory 104 (RAM). but at least one computer processor 102 or 'CPU'.

The RAM 104 stores the operating system 110 . Useful operating systems for computers configured for automatic memory overclocking include UNIX(TM), Linux(TM), Microsoft Windows(TM), and others known to those skilled in the art. Although the operating system 110 of the example of FIG. 1 is shown in RAM 104, many components of such software are typically also stored in non-volatile memory, eg, data storage 112, such as, for example, a disk drive. . In addition, a configuration module 114, a module for automatic memory overclocking, is stored in RAM.

The computer 100 of FIG. 1 includes an expansion bus 118 and a disk drive adapter 116 that is coupled to the processor 102 and other components of the computer 100 via a bus adapter 108 . Disk drive adapter 116 connects non-volatile data storage to computer 100 in the form of data storage 112 . Disk drive adapters useful for computers configured for automatic memory overclocking include integrated drive electronic device (IDE) adapters, small computer system interface (SCSI) adapters, and others known to those skilled in the art. In some embodiments, non-volatile computer memory is implemented as an optical disk drive, electrically erasable programmable read-only memory (so-called 'EEPROM' or 'flash memory'), RAM drives, and those known to those skilled in the art, and the like.

The example computer 100 of FIG. 1 includes one or more input/output (I/O) adapters 120 . The I/O adapter is user-oriented, for example, through software drivers and computer hardware, for controlling output to a display device, such as a computer display screen, and user input from user input devices 122, such as a keyboard and mouse. Implement input/output. The example computer 100 of FIG. 1 includes a video adapter 124 , which is an example of an I/O adapter specifically designed for graphics output to a display device 126 , such as a display screen or computer monitor. The video adapter 124 is coupled to the processor 102 via a high-speed video bus 128 , a bus adapter 108 , and a front side bus 130 , which is also a high-speed bus.

The exemplary computer 100 of FIG. 1 includes a communication adapter 132 for data communication with other computers and data communication with a data communication network. Such data communication is performed serially via an RS-232 connection, via an external bus, such as a Universal Serial Bus (USB), via a data communication network, such as an IP data communication network, and/or in other manners known to those skilled in the art. A communication adapter implements the hardware level of data communication, in which one computer sends data communication to another computer, either directly or through a data communication network. Examples of communication adapters useful in computers configured for automatic memory overclocking include modems for wired dial-up communications, Ethernet (IEEE 802.3) adapters for wired data communications, and 802.11 adapters for wireless data communications.

For further clarification, FIG. 2 illustrates automatic memory overclocking that includes increasing 202 (eg, by configuration module 114 ) a memory frequency setting for the memory module until the memory stability test fails. A flowchart illustrating an example method for a king is presented. A memory module is a set of one or more random access memory chips within the same circuit board (eg, the same dual in-line memory module (DIMM)). The memory frequency setting is the clock rate (eg, 1000 megahertz, 3000 megahertz, etc.) for the memory module.

For example, the configuration module 114 may configure a predefined interval (eg, a baseline memory frequency setting) starting from a baseline memory frequency setting (eg, a current memory frequency setting for the memory module, a predefined minimum frequency setting, etc.). , 100 MHz, or other intervals) increase the memory frequency setting. After increasing the memory frequency setting, the configuration module 114 performs one or more memory stability tests on the memory module. Memory stability tests are based on one or more data integrity checks including error correcting code checks or other approaches for detecting bit errors as can be recognized. For example, the configuration module 114 may perform one or more reads and/or writes of data to the memory module and determine whether errors were found in the read and/or written data.

If the memory module passes one or more memory stability tests, the configuration module 114 increases the memory frequency setting and performs one or more memory stability tests. This process is repeated until the memory stability test fails. In some embodiments, in response to a memory stability test failure, the configuration module 114 sets the memory frequency setting to a memory frequency setting that is greater than the memory frequency setting that last passed the memory stability tests but less than the memory frequency setting that failed the memory stability test. Decrease by setting. For example, suppose a memory module passes the memory stability test at 2800 MHZ. After increasing the memory frequency setting in predefined 200 MHz increments, the memory module fails the memory stability test at 3000 MHz. Then, the configuration module 114 reduces the memory frequency setting to 2900 MHz and performs a memory stability test. Those skilled in the art will appreciate that such an approach can be performed iteratively to effectively search for the highest memory frequency setting that will pass memory stability tests.

The method of FIG. 2 also includes determining ( 204 ) an overclocked memory frequency setting that includes the highest memory frequency setting that passes the memory stability test (eg, by the configuration module 114 ). For example, suppose the configuration module 114 increases the memory frequency setting for the memory module in steps of 100 megahertz, the memory frequency setting for 2900 megahertz will result in memory stability while the setting for 3000 megahertz fails. pass the test The overclocked memory frequency setting is determined from 204 to 2900 MHZ.

The method of FIG. 2 also includes generating 206 a profile 208 that includes the overclocked memory frequency settings (eg, by the configuration module 114 ). For example, profile 208 is generated 206 as data indicative of one or more settings for the memory module, including overclocked memory frequency settings. One of ordinary skill in the art would recognize that the method of FIG. 2 may be repeated for each memory module in the computing system so that a profile 208 is generated for each memory module, or a profile 208 is generated indicating the settings for each memory module. you will understand that you can The configuration module 114 is described as a software-based process (eg, implemented in the random access memory 104 ). Those skilled in the art will appreciate that, in alternative embodiments, the configuration module 114 is implemented at least in part in a memory controller or other hardware component.

For further illustration, FIG. 3 illustrates (eg, by configuration module 114 ) increasing ( 202 ) the memory frequency setting for the memory module until the memory stability test fails; determining (204) an overclocked memory frequency setting comprising a highest memory frequency setting that passes the memory stability test; A flow diagram is presented illustrating an example method for automatic memory overclocking that includes generating ( 206 ) a profile 208 that includes an overclocked memory frequency setting.

The method of FIG. 3 differs from FIG. 2 in that increasing the memory frequency setting 202 for the memory module until the memory stability test fails also includes determining 302 one or more memory timing settings. do. Memory timing settings are, for example, column access strobe (CAS) latency, row address strobe (RAS) to column address strobe (CAS) delay (write), row address strobe (RAS) to column address strobe (CAS) delay (read out). ), a low precharge time, and/or a low active time.

In one embodiment, determining 302 one or more memory timing settings includes determining 302 one or more memory timing settings as one or more minimum timing settings. For example, the memory module includes default minimum thresholds for one or more of the memory timing settings. Then, one or more of the memory timing settings is determined as a minimum threshold. In one embodiment, determining 302 one or more memory timing settings includes determining 302 one or more of the memory timing settings as a function of one or more other minimum timing settings. For example, the first memory timing setting is determined as the minimum timing setting, and the second memory timing setting is determined as a function of the first memory timing setting (eg, using a formula or other rules). After determining 302 one or more minimum timing settings, the memory timing settings are applied to the memory module prior to performing the one or more memory timing settings.

In one embodiment, after failing the memory stability test at a given frequency, the configuration module 114 configures one or more of the memory timing settings until a threshold for the memory timing setting is reached, or the memory stability test passes. increase Thus, the memory frequency setting passes the memory stability test using the increased memory timing settings.

The method of FIG. 3 also includes determining one or more overclocked memory timing settings including one or more memory timing settings corresponding to the overclocked memory frequency setting. In other words, the one or more overclocked memory timing settings are those minimum memory timing settings applied to the memory module when the overclocked memory frequency setting passes the memory stability test.

The method of FIG. 3 includes the steps of generating ( 206 ) the profile 208 including the overclocked memory frequency settings, and also generating ( 306 ) the profile 208 including one or more overclocked memory timing settings. ) is further different from FIG. 2 in that it includes. Accordingly, the generated 206 profile 208 indicates an overclocked memory frequency setting and one or more overclocked memory timing settings for the memory module.

For further illustration, FIG. 4 illustrates a memory frequency setting (eg, to configuration module 114 ) for a memory module until a memory stability test that includes determining one or more memory timing settings ( 302 ) fails. by) increasing 202 ; determining (204) an overclocked memory frequency setting comprising a highest memory frequency setting that passes the memory stability test; determining (304) one or more overclocked memory timing settings including one or more memory timing settings corresponding to the overclocked memory frequency setting; and generating a profile 208 comprising the overclocked memory frequency setting by generating a profile comprising the one or more overclocked memory timing settings; A flow chart illustrating the method is presented.

The method of FIG. 4 is that the method of FIG. 4 also includes determining 402 one or more subtiming settings based on the overclocked memory frequency setting and/or one or more overclocked timing settings. different from FIG. 3 . Examples of subtiming settings include: page timeline duration settings; RAS to RAS delay, different bank group settings (eg delay between activation of two rows across different bank groups), RAS to RAS delay, same bank group setting (eg within the same bank group) delay between two row activations) ; setting four activation windows (eg, the time during which four row activations can occur within the same rank); write-to-read delays, different bank group settings (eg, delay between successful write and read commands across different bank groups); write-to-read delay, setting the same bank group (eg, the delay between a successful write command and a read command within the same bank group); Write recovery time settings (eg, delay between a successful write command and the active bank being precharged), and other settings that may be recognized.

In one embodiment, the one or more subtiming settings are determined based on one or more of the overclocked memory timing settings. For example, in the overclocked memory frequency setting, the row cycle time setting is determined by the sum of the row precharge time setting and the row address strobe (RAS) active time setting. In one embodiment, the one or more subtiming settings are determined based on one or more thresholds. For example, a setting determined through a formula that is less than a threshold may be determined as a threshold amount instead. In one embodiment, one or more subtiming settings are determined based on one or more other subtiming settings. For example, a setting of 4 activation windows is determined by RAS to RAS delay, 4 times the setting of different bank groups. In other words, the one or more subtiming settings are determined based on the one or more rules.

The method of FIG. 4 states that generating ( 206 ) the profile 208 including the overclocked memory frequency settings also includes generating ( 404 ) the profile 208 including one or more subtiming settings. It differs further from FIG. 3 in that it is. Accordingly, the generated 206 profile 208 indicates an overclocked memory frequency setting, one or more overclocked memory timing settings, and one or more subtiming settings for the memory module.

For further clarification, FIG. 5 illustrates incrementing ( 202 ) a memory frequency setting for a memory module (eg, by configuration module 114 ) until the memory stability test fails; determining (204) an overclocked memory frequency setting comprising a highest memory frequency setting that passes the memory stability test; A flow diagram is presented illustrating an example method for automatic memory overclocking that includes generating ( 206 ) a profile 208 that includes an overclocked memory frequency setting.

The method of FIG. 5 differs from FIG. 2 in that the method of FIG. 5 also includes a step 502 of storing the profile in a storage location 504 . In one embodiment, storage location 504 includes non-volatile memory of the computing system including memory modules (eg, disk storage, basic input/output system scratch tables, etc.). In another embodiment, the storage location 504 is an on-module (eg, on a dual in-line memory module (DIMM)) a memory module, such as a Serial Presence Detect (SPD) Electrically Erasable Programmable Read-Only Memory (EEPROM). It includes non-volatile storage on its own.

The method of FIG. 5 also includes loading 506 the profile from the storage location 504 . For example, the profile 208 is loaded 506 from the storage location 504 as part of a boot process of a computing system including the memory module. The method of FIG. 5 also includes applying 508 the profile 208 to the memory module. Step 508 of applying the profile 208 to the memory module includes the settings indicated in the profile 208 (eg, overclocked memory frequency settings, overclocked memory timing settings, and/or subtiming settings). configuring the memory module to operate using the settings).

In traditional solutions, memory modules are configured using profiles provided by the memory module's manufacturer or vendor, and tested under configuration settings that may differ from the end user (eg different chip or motherboard manufacturer or designer). Users can modify settings in these profiles, but they are limited to using margins based on these different configuration settings. Using the approach described above, the configuration settings of the memory module are determined and optimized based on the actual capabilities of the computing system in which the memory module is implemented.

In view of the description presented above, the reader will recognize that the benefits of automatic memory overclocking include:

● Improve the performance of your computing system by optimizing memory overclocking settings to reflect your current system configuration and operating environment.

Exemplary embodiments of the present disclosure are primarily described in the context of a full-featured computer system for automatic memory overclocking. However, those skilled in the art will recognize that the present disclosure may also be embodied as a computer program product disposed on a computer readable storage medium for use with any suitable data processing system. Such computer-readable storage media can be any storage media for machine-readable information, including magnetic media, optical media, or other suitable media. Examples of such media include magnetic disks on hard drives or diskettes, compact disks for optical drives, magnetic tapes, and others known to those skilled in the art. Those skilled in the art will readily recognize that any computer system having suitable programming means will be capable of carrying out the steps of the methods of the present disclosure as embodied in a computer program product. Those skilled in the art will appreciate that while some of the exemplary embodiments described herein are directed to software installed and executed on computer hardware, nevertheless alternative embodiments implemented as firmware or hardware are well within the scope of the present disclosure. will also recognize that

The present disclosure may be a system, method, and/or computer program product. A computer program product may include a computer readable storage medium (or media) having computer readable program instructions for causing a processor to perform aspects of the present disclosure.

A computer-readable storage medium can be a tangible device that can hold and store instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exclusive list of more specific examples of computer-readable storage media includes: portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM) ) or flash memory, static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, punch card ( mechanically encoded devices, such as punch-cards, or raised structures in grooves on which instructions are recorded, and any suitable combination thereof. A computer-readable storage medium as used herein includes, per se, propagating or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (eg, light pulses passing through a fiber optic cable). , or electrical signals transmitted over wires.

The computer readable program instructions described herein can be transmitted from a computer readable storage medium to respective computing/processing devices, or to an external computer via a network, eg, the Internet, a local area network, a wide area network, and/or a wireless network. Alternatively, it may be downloaded to an external storage device. The network may include copper transmission cables, optical transmission fibers, radio transmissions, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium in each computing/processing device.

Computer readable program instructions for performing the operations of this disclosure include assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or Smalltalk , source code or object code written in any combination of one or more programming languages, including an object-oriented programming language such as , C++, and the like, and conventional procedural programming languages such as the "C" programming language or similar programming languages. . The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a standalone software package, partly on the user's computer and partly on a remote computer or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or (eg, the Internet using an Internet service provider). ), a connection can be made to an external computer. In some embodiments, for example, programmable logic circuitry, field programmable gate arrays (FPGA), or electronic circuitry including programmable logic arrays (PLA), to perform aspects of the present disclosure, The computer readable program instructions may be executed by using the state information of the computer readable program instructions to personalize the electronic circuitry.

Aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, may be implemented by computer readable program instructions.

These computer readable program instructions are such that the instructions, which are executed by a processor of a computer or other programmable data processing apparatus, produce means for implementing the functions/acts specified in the flowchart and/or block or blocks in the block diagrams. , may be provided on the processor of a general purpose computer, special purpose computer, or other programmable data processing device to create a machine. These computer readable program instructions may also be stored on a computer readable storage medium capable of instructing a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable program having the instructions stored therein The capable storage medium includes an article of manufacture comprising instructions implementing aspects of the function/acting specified in the block or blocks of the flowchart and/or block diagrams.

The computer readable program instructions may also be loaded on a computer, other programmable data processing apparatus, or other device, such that a series of operational steps on the computer, other programmable apparatus, or other device to create a computer implemented process is performed. be performed, whereby instructions executed on a computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block or blocks in the block diagram.

The flowchart and block diagrams in the drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products in accordance with various embodiments. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions recited in the blocks may occur out of the order recited in the figures. For example, two blocks shown in succession may, in fact, be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order, depending on the functionality involved. In addition, each block in the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, may be specific to perform specific functions or operations or perform combinations of special purpose hardware and computer instructions. It will be noted that the purpose may be implemented by hardware-based systems.

It will be understood from the foregoing description that modifications and variations may be made in various embodiments of the present disclosure. The description herein is for illustrative purposes only and should not be construed in a limiting sense. The scope of the present disclosure is limited only by the language of the following claims.

Claims (20)

A method for automatic memory overclocking, comprising:
increasing the memory frequency setting for the memory module until the memory stability test fails;
determining an overclocked memory frequency setting comprising the highest memory frequency setting that passes the memory stability test; and
and generating a profile comprising the overclocked memory frequency setting. According to claim 1,
Increasing the memory frequency setting for the memory module until the memory stability test fails comprises determining one or more memory timing settings, the method comprising:
determining one or more overclocked memory timing settings comprising the one or more memory timing settings corresponding to the overclocked memory frequency setting; and
wherein generating the profile comprises generating the profile including the one or more overclocked memory timing settings. 3. The method of claim 2,
The one or more memory timing settings may include column access strobe (CAS) latency, row address strobe (RAS) to column address strobe (CAS) delay (write), row address strobe (RAS) to column address strobe (CAS) delay (read). , a low precharge time, and/or a low active time. 3. The method of claim 2,
determining one or more subtiming settings based on the overclocked memory frequency setting and the one or more overclocked memory timing settings; and
wherein generating the profile comprises generating the profile including the one or more subtiming settings. 5. The method of claim 4,
wherein the one or more subtiming settings are based on the overclocked memory frequency setting and/or one or more rules applied to the one or more memory timing settings. According to claim 1,
and storing the profile in a storage location. 7. The method of claim 6,
loading the profile from the storage location; and
and applying the profile to the memory module. A device for automatic memory overclocking, the device comprising:
increase the memory frequency setting for the memory module until the memory stability test fails;
determine an overclocked memory frequency setting comprising a highest memory frequency setting that passes the memory stability test; and
and generate a profile comprising the overclocked memory frequency setting. 9. The method of claim 8,
Increasing the memory frequency setting for the memory module until the memory stability test fails comprises determining one or more memory timing settings, the apparatus further comprising:
determine one or more overclocked memory timing settings comprising the one or more memory timing settings corresponding to the overclocked memory frequency setting; and
wherein generating the profile comprises generating the profile including the one or more overclocked memory timing settings. 10. The method of claim 9,
The one or more memory timing settings may include column access strobe (CAS) latency, row address strobe (RAS) to column address strobe (CAS) delay (write), row address strobe (RAS) to column address strobe (CAS) delay (read). , a low precharge time, and/or a low active time. 10. The method of claim 9,
further configured to determine one or more subtiming settings based on the overclocked memory frequency setting and the one or more overclocked memory timing settings; and
wherein generating the profile comprises generating the profile including the one or more subtiming settings. 12. The method of claim 11,
wherein the one or more subtiming settings are based on the overclocked memory frequency setting and/or one or more rules applied to the one or more memory timing settings. 9. The method of claim 8,
and store the profile in a storage location. 14. The method of claim 13,
load the profile from the storage location; and
and apply the profile to the memory module. A computer program product disposed on a non-transitory computer readable medium, the computer program product comprising computer program instructions for automatic memory overclocking that, when executed, cause a computer to perform steps comprising: :
increasing the memory frequency setting for the memory module until the memory stability test fails;
determining an overclocked memory frequency setting comprising the highest memory frequency setting that passes the memory stability test; and
and generating a profile comprising the overclocked memory frequency setting. 16. The method of claim 15,
Increasing the memory frequency setting for the memory module until the memory stability test fails includes determining one or more memory timing settings, the steps comprising:
determining one or more overclocked memory timing settings comprising the one or more memory timing settings corresponding to the overclocked memory frequency setting; and
wherein generating the profile comprises generating the profile comprising the one or more overclocked memory timing settings. 17. The method of claim 16,
The one or more memory timing settings may include column access strobe (CAS) latency, row address strobe (RAS) to column address strobe (CAS) delay (write), row address strobe (RAS) to column address strobe (CAS) delay (read). , a low precharge time, and/or a low active time. 17. The method of claim 16, wherein the steps are:
determining one or more subtiming settings based on the overclocked memory frequency setting and the one or more overclocked memory timing settings; and
wherein generating the profile comprises generating the profile comprising the one or more subtiming settings. 19. The method of claim 18,
wherein the one or more subtiming settings are based on the overclocked memory frequency setting and/or one or more rules applied to the one or more memory timing settings. 16. The method of claim 15,
wherein the steps further comprise storing the profile in a storage location.

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