KR20220111887A - Gallium nitride-based semiconductor device with excessive source fingers for enhancing thermal characteristic - Google Patents

Abstract

The present disclosure relates to a semiconductor device and, specifically, to a gallium nitride (GaN)-based semiconductor device such as an AlGaN/GaN HFET and, more specifically, to a layout structure of a gallium nitride-based semiconductor device including a source finger for enhancing thermal characteristics.

Description

GALLIUM NITRIDE-BASED SEMICONDUCTOR DEVICE WITH EXCESSIVE SOURCE FINGERS FOR ENHNCING THERMAL CHARACTERISTIC

The present disclosure relates to a semiconductor device, specifically a gallium nitride (GaN) based semiconductor device such as an AlGaN/GaN HFET, and more specifically, a gallium nitride based semiconductor including a source finger for improving thermal properties. It is about the layout structure.

In general, a gallium nitride-based semiconductor device such as GaN or AlGaN includes a drain region, a source region, and a gate region that are alternately disposed. In various fields requiring excellent RF (radio frequency) characteristics, it has a high carrier concentration and high electron mobility, so it shows a high electric field saturation rate, while having less carrier scattering, which is advantageous for high-speed switching (i.e., high-frequency operation). is being used for However, since this device generates a lot of heat, various heat dissipation means are required to allow the semiconductor to stay in a temperature range where it can stably operate.

Wang, Wei-Chou et al. "Development and Control of a 0.25 μm Gate Process Module for AlGaN / GaN HEMT Production." (2013).

An object of the present disclosure is to provide an arrangement structure of a gallium nitride-based semiconductor in which the arrangement structure of drain, source, and gate fingers is improved while not having a complicated manufacturing process compared to a conventional gallium nitride-based semiconductor.

In addition, an object of the present disclosure is to replace a wire bonding process widely used in a conventional gallium nitride-based semiconductor so that a device can be connected to an input/output terminal through a via hole.

And, an object of the present disclosure is to provide a range of specific design dimensions capable of optimizing performance when a gate length of a gallium nitride-based semiconductor is around 0.35 μm.

The characteristic configuration of the present invention for achieving the object of the present invention as described above and for realizing the characteristic effects of the present invention to be described later is as follows.

According to the present disclosure, there is provided a gallium nitride-based semiconductor device, wherein the semiconductor device includes two or more unit cells, each of which is a plurality of units repeatedly arranged alternately in order on an upper surface of the semiconductor device. an active region comprising a source region, a first gate region, a drain region and a second gate region, the repeating arrangement starting from a starting source region and ending with an ending source region; a plurality of first gate fingers respectively disposed in the plurality of first gate regions; a plurality of drain fingers respectively disposed in the plurality of drain regions; a plurality of second gate fingers respectively disposed in the plurality of second gate regions; a unit gate pad formed on one side of the active region outside the active region and electrically connected to the plurality of first gate fingers and the plurality of second gate fingers; a unit drain pad formed on the other side of the active region opposite to the one side of the active region outside the active region and electrically connected to the plurality of drain fingers; and a plurality of source regions other than the start source region and the end source region among the plurality of source regions to be surrounded by the unit drain pad, the first gate finger, the second gate finger, and the unit gate pad, respectively. An isolated source finger comprising: a source finger including at least one first conductive via hole passing through an upper surface and a lower surface of the semiconductor device and electrically connected to the first conductive via hole; each of the active regions is coupled to each other, the unit gate pad of each of the unit cells is electrically connected to each other, the unit drain pad of each of the unit cells is electrically connected to each other, and among the adjacent pairs of the unit cells Any one of the end source regions is formed to be shared as the start source region of the other one of the adjacent pairs or is formed to be separated from the other one of the start source regions, at least one of the positions between the unit cells. In a position, the one end source region is separated from the other start source region, and the semiconductor device further includes a source pad electrically connected to each of the first conductive via holes on the lower surface.

Advantageously, the number of the unit cells is an even number of 2 or more, and at least one adjacent unit cell pair for every two unit cells is formed so that the end source region and the start source region are separated from each other.

Preferably, the gate region is formed of a T-gate (T-gate), the gate length of the T-type gate is 0.315 micrometers to 0.385 micrometers, and the head of the T-type gate (T-gate) The width of the gate head is 0.75 micrometers to 0.85 micrometers, and the source-drain spacing (S-D spacing) is 5.2 micrometers to 5.8 micrometers, and the legs of the T-type gate ( A horizontal distance from one of the endpoints of the T-gate foot in the direction of the drain region to one of the endpoints of the head in the direction of the drain region is 0.245 micrometers to 0.255 micrometers.

According to an embodiment of the present disclosure, a lower surface gate pad and a lower surface drain pad electrically separated from the source pad and electrically separated from each other are further included on a lower surface of the semiconductor device, wherein the lower surface gate pad is electrically separated from the upper surface and at least one second conductive via hole passing through a lower surface, the lower drain pad includes at least one third conductive via hole penetrating the upper and lower surfaces, and the second conductive via hole is the unit gate It is electrically connected to at least one of the pads, and the third conductive via hole is electrically connected to at least one of the unit drain pads.

According to the semiconductor device of the present disclosure, there is an effect that high performance can be maintained by reducing thermal interference between the same cell structures repeated in the arrangement structure of the gallium nitride-based semiconductor. According to an embodiment of the semiconductor device of the present disclosure, there is an effect of reducing inductance and parasitic components by replacing wire bonding, thereby improving performance and reducing the cost of a process involved in wire bonding. In addition, according to an embodiment of the semiconductor device of the present disclosure, when the gate length is around 0.35 μm, performance is optimized according to the specific design dimension of the present disclosure.

Embodiments will be described with reference to the accompanying drawings in order to show the process in which the method of the present disclosure is actually performed for an understanding of the present disclosure, which is only a non-limiting example, and is common in the technical field to which the present disclosure belongs It goes without saying that other drawings may be obtained based on these drawings by a person having the knowledge of (hereinafter referred to as "a person skilled in the art") without additional efforts to arrive at another invention.
1A is a conceptual plan view illustrating a unit cell of a semiconductor device according to an embodiment of the present disclosure, and FIG. 1B is a conceptual bottom view of the semiconductor device unit cell shown in FIG. 1A .
2 is a plan view conceptually illustrating a semiconductor device according to an exemplary embodiment of the present disclosure.
3A is a conceptual diagram illustrating a side cross-section taken along line AA′ shown in FIG. 1A, and FIG. 3B is an enlarged conceptual diagram of the T-type gate shown in FIG. 3A.
4A is a conceptual plan view of a semiconductor device according to another exemplary embodiment of the present disclosure, and FIG. 4B is a conceptual bottom view of the semiconductor device shown in FIG. 4A .

The detailed description of the principle of a semiconductor device according to the present disclosure to be described below is provided by way of illustration of a specific embodiment in which the present invention may be practiced in order to clarify the objects, technical solutions and advantages of the present disclosure appearing in the present disclosure. Reference is made to the accompanying drawings that show. In the description with reference to the accompanying drawings, the same components are assigned the same reference numerals regardless of the reference numerals, and the overlapping description thereof will be omitted. It will be understood that the semiconductor structure according to the present disclosure does not have a length ratio as shown in the drawings, and dimensions and ratios of respective parts in the drawings are merely shown for illustrative purposes without limiting the scope of the present invention. For example, dimensions and proportions of some of the elements shown in the drawings are provided to aid understanding of various embodiments. Incidentally, the description and drawings are not meant to be in the order in which they are described. Skilled artisans will appreciate that acts and/or steps described or depicted in a particular order may not require special limitations on that order.

In addition, in the present disclosure, a source finger, a first gate finger, a drain finger, and a second gate finger are respectively disposed in the source region, the first gate region, the drain region, and the second gate region. For convenience of reference, each region and corresponding fingers may be referred to by the same reference numerals without being confused with each other by those skilled in the art.

Specific structural or functional descriptions of the embodiments are disclosed for purposes of illustration only, and may be changed and implemented in various forms. Accordingly, the embodiments are not limited to a specific disclosure form, and the scope of the present specification includes changes, equivalents, or substitutes included in the technical spirit.

Although terms such as first or second may be used to describe various elements, these terms should be interpreted only for the purpose of distinguishing one element from another. For example, a first component may be termed a second component, and similarly, a second component may also be termed a first component.

In the present disclosure, the term “layer” refers to a material disposed over at least a portion of an underlying surface in a continuous or discontinuous manner. Also, the term “layer” does not necessarily mean that the material on which it is disposed has a constant thickness. The disposed material may have either a constant thickness or a varying thickness. Moreover, any “layer” as used herein may refer to a single layer or a plurality of layers, unless the context clearly indicates otherwise. In the present disclosure, the expression "disposed on" or the expression "disposed on" and "disposed between" means, unless otherwise specified, the expressions disposed to be in direct contact with each other or interposed therebetween. It means that they are so arranged indirectly through the other layers. Moreover, "on" and "on" merely indicate the relative positions between the layers/elements, since they may look different depending on the viewpoint of the observer. Also, "formed on (on)" has a broad meaning, and the fact that a layer is formed on another layer does not mean direct physical contact with the other layer. For example, when "Y is formed over X", there may be one or more intervening layers between X and Y. On the other hand, "formed directly on" means direct physical contact.

When a component is referred to as being “connected” to another component, it may be directly connected or connected to the other component, but it should be understood that another component may exist in between. Also, when it is mentioned that a certain element is 'on' another element, it may be 'on top' of the other element, but it should be understood that another element may exist in the middle.

The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present specification, terms such as "comprise" or "have" are intended to designate that the described feature, number, step, operation, component, part, or combination thereof exists, but one or more other features, number, step , it should be understood that it does not preclude the possibility of the existence or addition of , operation, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related art, and should not be interpreted in an ideal or excessively formal meaning unless explicitly defined in the present specification. does not

In the present disclosure, "gallium nitride-based semiconductor" refers to a semiconductor including gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and compositions interposed therebetween.

Moreover, the invention encompasses all possible combinations of the embodiments indicated herein. It should be understood that various embodiments of the present invention are different but need not be mutually exclusive. For example, certain shapes, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention in relation to one embodiment. That is, the embodiments of the present invention are described with reference to the conceptual diagrams of ideal embodiments of the present invention, but should not be regarded as being limited to a specific shape of a specific region of the structure as shown, and the result may vary according to a specific manufacturing process. Various modifications that are a shape to have may be included. The regions shown in the drawings are conceptually shown in their characteristics and shapes, and are not intended to show the structure or the exact shape of the region, nor to limit the scope of the present invention. For example, an area shown as a rectangular block in the figures may often be tapered, curved, or rounded.

It should be understood that the location or arrangement of individual components within each disclosed embodiment may be changed without departing from the spirit and scope of the present invention. Accordingly, the detailed description set forth below is not intended to be taken in a limiting sense, and the scope of the present invention, if properly described, is limited only by the appended claims, along with all scope equivalents to those claimed.

Unless otherwise indicated herein or otherwise clearly contradicted by context, items referred to in the singular encompass the plural unless the context requires otherwise. In addition, in describing the present invention, if it is determined that the detailed description of the related known configuration or function relates to materials, processes, etc. well known to those skilled in the art of the semiconductor technology, and may obscure the gist of the present invention, it is excessive. A detailed description will be omitted.

Hereinafter, in order to enable those skilled in the art to easily practice the present invention, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A is a conceptual plan view illustrating a unit cell of a semiconductor device according to an embodiment of the present disclosure, and FIG. 1B is a conceptual bottom view of the semiconductor device unit cell shown in FIG. 1A .

Referring to FIG. 1A , in the unit cell 100 of the gallium nitride-based semiconductor device according to the first embodiment of the present disclosure, a plurality of rectangular source regions, a first rectangular gate region, and a rectangular drain region are formed on the upper surface 110 of the unit cell 100 . , an active region 120 including a second rectangular gate region is formed.

The source region, the first gate region, the drain region, and the second gate region are alternately arranged in plurality in that order, and a start source region and an end source region are respectively arranged at the beginning and end of the repeated arrangement. The start source region and the end source region are essentially the same as the other source regions.

A first gate finger 124 is disposed in each of the plurality of first gate regions, a drain finger 126 is disposed in each of the plurality of drain regions, and a second gate finger 125 is respectively disposed in a plurality of second gate regions. is disposed, and a source finger 122 is disposed in each of the plurality of source regions.

In addition, the unit gate pad 134 is a metal pattern formed on one side of the active region 120 outside the active region 120 of the upper surface 110 , and includes a plurality of first gate fingers 124 and a plurality of second gate fingers ( 125 are electrically connected to each other, for example, the first gate finger 124 , the second gate finger 125 , and the unit gate pad 134 may be integrally formed at once, but are different so as to be electrically connected to each other. Each of them may be formed in the process, or only two of them may be formed integrally.

On the other hand, the unit drain pad 136 is a metal pattern formed on the other side of the active region 120 outside the active region 120 of the upper surface 110 , and is electrically connected to the plurality of drain fingers 126 and is electrically connected to each other. The finger 126 and the unit drain pad 136 may also be formed integrally or may be respectively formed through different processes.

Among the source fingers 122 , the source fingers disposed in a source region other than the start source region 122a and the end source region 122b are a unit drain pad 136 , a first gate finger 124 , and a second gate finger. 125 and the unit gate pad 134 are arranged to be surrounded and isolated from each other. Each of the source fingers 122 includes at least one first conductive via hole 160 penetrating the upper surface 110 and the lower surface 150 of the device, and is electrically connected to the first conductive via hole. connected

The upper surface 110 may further include an extra conductive pad 190 , and the extra conductive pad 190 may be used for electrical connection between unit cells, forming a ground, and the like.

Referring to FIG. 1B , a source pad 152 electrically connected to each of the first conductive via holes 160 is disposed on a lower surface 150 of the unit cell 100 , and the source pad 152 is a source finger. (122) and electrically connected.

2 is a plan view conceptually illustrating a semiconductor device according to an exemplary embodiment of the present disclosure.

Referring to FIG. 2 , in the semiconductor device according to the present disclosure, the end source region of any one of the adjacent pairs of unit cells arranged in series on the upper surface 110 is the start source region of the other of the adjacent pairs. Formed to be shared (222a) or formed to be separated from the other start source region 222c (222b), the end source region 222b included in at least one unit cell is a start source included in an adjacent unit cell. It is formed separately from the region 222c.

Then, the source finger 222b corresponding to the end source region and the source finger 222c corresponding to the start source region do not overlap each other or are surrounded by both the first gate finger and the second gate finger. Therefore, it is relatively less affected by heat generation. If the extra source fingers are configured in such a way that the end source finger 222b and the start source finger 222c do not overlap each other, design and manufacture are relatively easy and the number of unit cells is increased without causing a significant increase in cost. Accordingly, thermal interference between unit cells may be reduced.

Each of the plurality of unit cells constituting the semiconductor device according to the present disclosure is configured to be coupled to each other, and the active regions of each of the unit cells are coupled to each other to form one active region 220 , and each of the unit cells The unit gate pads 134 of , are electrically connected 144 to each other, and similarly, the unit drain pads 136 of each of the unit cells are electrically connected 146 to each other.

The number of unit cells shown in FIG. 2 is exemplary, and for convenience in the process, the number of unit cells is configured as an even number of 2 or more, but at least one pair of adjacent unit cells for each two unit cells is connected to the terminal source region ( 222b) and the start source region 222c may be separated from each other, but the present invention is not limited thereto.

3A is a conceptual diagram illustrating a side cross-section taken along line A-A' shown in FIG. 1A, and FIG. 3B is an enlarged conceptual diagram of the T-type gate shown in FIG. 3A.

Referring to FIG. 3A , a gallium nitride-based semiconductor device includes a base substrate 310 made of SiC or diamond, etc., a gallium nitride-based epitaxial layer 320, and an ohmic metal that is an ohmic metal in ohmic contact with the epitaxial layer. layer 112 and a drain side metal layer 116 , and a gate side metal layer 114 in Schottky contact with the epi layer 320 , as known to those skilled in the art.

In the epitaxial layer 320 , AlN, GaN, AlGaN, GaN, etc. are stacked on the base substrate 310 to induce a two-dimensional electron gas (2DEG) to form a 2DEG channel through which current can flow.

One or more metal layers for forming the source finger 122 as a source terminal may be stacked on the source-side metal layer 112 , and also on the drain-side metal layer 116 for configuring the drain finger 126 as a drain terminal. One or more metal layers may be laminated.

In addition, as a metal layer for improving the operating voltage and frequency characteristics of the semiconductor device, the gate-side metal is insulated from the gate-side metal layer 114 and electrically connected to the source terminal. It may be formed over the layer 114 .

At least one passivation layer (330, 360, 370) for electrically and physically isolating and protecting the respective terminals may be further included. For example, such passivation layers 330 and 360 may be composed of, but not limited to, SiNx. For example, the final passivation layer 370 may be made of polybenzoxazole (PBO).

In the gallium nitride-based semiconductor according to the exemplary embodiment of the present disclosure, the metal layer 114 forming the gate is a T-shaped, so-called, T-gate.

3B is an enlarged conceptual view of the T-type gate 114 shown in FIG. 3A.

Referring to FIG. 3B, the length L2 of the region 340 in which the epitaxial layer 320 and the T-type gate 114 are in Schottky contact with each other is referred to as a gate length, and the Schottky contact region ( Except for 340 , a passivation layer 330 may be interposed between the epitaxial layer 320 and the T-type gate 114 . The passivation layer 330 includes a first passivation layer 330a and a second passivation layer 330b, wherein a T-type gate 114 is formed over the first passivation layer 330a, after which a second passivation layer ( 330b) is raised.

Referring to FIG. 3B , the gate length of the T-type gate 114 is indicated by reference symbol L2, and the DRES length, that is, the width of the T-gate head, is indicated by reference symbol L3. is indicated. DRES overhand to drain, that is, from one of the endpoints of the T-gate foot in the direction of the drain region to one of the endpoints of the head of the T-type gate in the direction of the drain region The horizontal distance to the end point is denoted by reference symbol L4. A horizontal distance from one of the end points of the legs of the T-type gate in the source region direction to one of the end points of the head of the T-shaped gate in the source region direction is also indicated by reference numeral L5. Meanwhile, the S-D spacing, which is the spacing between the source region and the drain region, is indicated by reference numeral L1 in FIG. 3A .

The present inventors performed an experiment to confirm the structure of the semiconductor device embodied by the numerical values of L1 to L5 shown in FIG. 3B. Table 1 below shows the characteristics of the semiconductor device according to the values of L1 to L5 shown in FIG. 3B. It is measured and shown. Here, a gate length (L2) of 0.45 μm was used experimentally.

Gate Length (L2)
0.45μm
Frequency 3.6 GHz Maximum output power (dBm) Power Density (W/mm) Gain (dB) efficiency(%) type A
GFP: 0.15 / 0.20 μm
SD Spacing: 5.5 μm 46.5
46.5 12.4
12.4 17.3
17.2 68.0
67.5 type B
GFP: 0.15 / 0.27 μm
SD Spacing: 6.0 μm 46.4 12.2 16.8 65.8

Type A in Table 1 means a structure in which L5 is 0.15 μm, L4 is 0.20 μm, and the S-D spacing (L1) is 5.5 μm, which corresponds to the gate field plate (GFP) value, and Type B means that L5 is 0.15 μm, L4 is 0.27 μm, and S-D spacing (L1) is 6.0 μm.

And, since DRES length (L3) = L2 + L4 + L5, type A has a DRES length of 0.80 μm and type B has a DRES length of 0.87 μm.

Comparing with reference to the result values shown in Table 1, since type A is superior to type B in terms of maximum output power, power density, gain and efficiency, the DRES length (L3) is 0.80 micrometer or less like type A. It will preferably be in the vicinity of, for example, 0.75 micrometers to 0.85 micrometers. With a similar optimization, the gate length L2 of the T-type gate 114 is 0.315 micrometers to 0.385 micrometers, and the DRES overhand to drain, i.e. the T-gate The horizontal distance L4 from one of the endpoints of the foot) in the direction of the drain region to the endpoint in the direction of the drain region among the endpoints of the head of the T-type gate is preferably 0.245 micrometers to 0.255 micrometers.

Also, preferably, the S-D spacing L1 that is the spacing between the source region and the drain region may be 5.2 micrometers to 5.8 micrometers.

4A is a conceptual plan view of a semiconductor device according to another embodiment of the present disclosure, and FIG. 4B is a conceptual bottom view of a semiconductor device according to another embodiment of the present disclosure.

4A and 4B , a lower surface gate pad 154 and a lower surface drain pad 156 electrically separated from the source pad 152 ′ may be formed on the lower surface 150 ′ of the semiconductor device. The bottom gate pad 154 and the bottom drain pad 156 are also electrically isolated from each other.

The lower gate pad 154 includes at least one second conductive via hole 170 penetrating the upper surface 110 ′ and the lower surface 150 ′, and the lower drain pad 156 includes the upper surface 110 ′ and the lower surface 150 ′. and at least one third conductive via hole 180 passing through 150 ′. The second conductive via hole 170 is electrically connected to at least one 134' of the unit gate pads of the upper surface 110', and the third conductive via hole 180 is one of the unit drain pads of the upper surface 110'. It is electrically connected to at least one 136'.

According to this embodiment, since each of the source terminal, the gate terminal, and the drain terminal is formed of the pads 152 ′, 154 , and 156 , simple direct bonding is possible compared to wire bonding. Accordingly, since inductance and parasitic components due to wire bonding can be minimized, it is easy to implement an impedance matching circuit of a semiconductor device, and in particular, since high-frequency characteristics can be improved, overall performance of the semiconductor device can be improved. In addition, there is an effect of reducing the process cost for wire bonding.

In all of the above-described embodiments, there is an effect of maintaining high performance by reducing thermal interference between the same cell structures that are repeated in the arrangement structure of the gallium nitride-based semiconductor. By configuring each terminal through a via hole process, it is possible to reduce inductance and parasitic components by replacing wire bonding in the conventional process, thereby improving performance and reducing process costs involved in wire bonding.

Although the present invention has been described only in some selected embodiments above, those skilled in the art can easily understand the concept based on the present disclosure, and as a basis for designing other structures and processes for carrying out some purposes of the present invention. You will be able to use the concept easily

In some examples, only approximate ranges of numerical values may be provided corresponding to the accuracy of the equipment for measuring numerical values. It will be readily understood by those skilled in the art that the specified range is due to deviations in numerical values that may occur unless there is a significant change in the performance of the gallium nitride-based semiconductor device presented in the present disclosure.

Although the present invention has been described with specific details such as specific components and limited embodiments and drawings, these are provided only to help a more general understanding of the present invention, and the present invention is not limited to the above embodiments, A person skilled in the art can devise various modifications and variations from these descriptions.

Therefore, the spirit of the present invention should not be limited to the above-described embodiments, and not only the claims appended to the present disclosure but also all modifications equivalently or equivalently to the claims attached to the present disclosure are the spirit of the present invention. would fall into the category of For example, the described techniques are performed in an order different from the described method, and/or the described elements, structures, devices, etc., are combined or combined in a different form than the described method, or other components or equivalents Appropriate results can be achieved even if displaced or displaced by water.

Such equivalent or equivalent modifications will include, for example, a method capable of producing the same result as that performed by the method according to the present invention, and the spirit and scope of the present invention is limited by the above-described examples. should not be, and should be understood in the broadest sense permitted by law.

100, 100': unit cell
110, 110': the top surface of the unit cell
112: source side metal layer
114: gate side metal layer (T-type gate)
116: drain side metal layer
120, 220: active area
122: source finger
122a: source finger of the starting source area
122b: source finger of the end source region
222a: a source finger in a source region that is a start source region and an end source region
222b: source finger of non-overlapping end source region
222c: source finger of non-overlapping start source area
124: first gate finger
125: second gate finger
126: drain finger
134, 134': unit gate pad
136, 136': unit drain pad
144: connection between unit gate pads
146: connection between unit drain pads
150, 150': bottom of unit cell
152, 152': source pad
154: lower gate pad
156: bottom drain pad
160: first conductive via hole
170: second conductive via hole
180: third conductive via hole
190: extra conductive pad
310: base substrate
320: epilayer (epilayer)
330, 330a, 330b: first passivation layer
340: schottky contact area
350: source field plate
360: second passivation layer
370: final passivation layer
L1: SD spacing
L2: gate length
L3: DRES length
L4: DRES overhang to drain

Claims (4)

A gallium nitride-based semiconductor device comprising two or more unit cells, comprising:
Each of the unit cells is on the upper surface of the semiconductor device,
an active region comprising a plurality of source regions, a first gate region, a drain region and a second gate region alternately arranged in an alternating sequence, the repeating arrangement starting from a starting source region and ending with an ending source region;
a plurality of first gate fingers respectively disposed in the plurality of first gate regions;
a plurality of drain fingers respectively disposed in the plurality of drain regions;
a plurality of second gate fingers respectively disposed in the plurality of second gate regions;
a unit gate pad formed on one side of the active region outside the active region and electrically connected to the plurality of first gate fingers and the plurality of second gate fingers;
a unit drain pad formed on the other side of the active region opposite to the one side of the active region outside the active region and electrically connected to the plurality of drain fingers; and
a plurality of source regions other than the start source region and the end source region among the plurality of source regions, respectively, so as to be surrounded by the unit drain pad, the first gate finger, the second gate finger, and the unit gate pad. An isolated source finger comprising: a source finger including at least one first conductive via hole penetrating through an upper surface and a lower surface of the semiconductor device and electrically connected to the first conductive via hole;
the active region of each of the unit cells is coupled to each other, the unit gate pad of each of the unit cells is electrically connected to each other, and the unit drain pad of each of the unit cells is electrically connected to each other;
The end source region of any one of the adjacent pairs of the unit cells is formed to be shared with the start source region of the other one of the adjacent pairs or is formed to be separated from the other start source region of the unit cells, At least one of the positions between cells, the one end source region is distinguished from the other one of the start source regions,
The semiconductor device is
The gallium nitride-based semiconductor device further comprising a source pad electrically connected to each of the first conductive via holes on the lower surface. According to claim 1,
The number of unit cells is an even number of 2 or more,
At least one pair of adjacent unit cells for each of the two unit cells is formed such that the end source region and the start source region are separated from each other. According to claim 1,
The gate region is formed of a T-gate,
A gate length of the T-type gate is 0.315 micrometers to 0.385 micrometers, a width of the T-gate head is 0.75 micrometers to 0.85 micrometers, and the source region and the A source-drain spacing is 5.2 micrometers to 5.8 micrometers, from one of the endpoints of the T-gate foot in the direction of the drain region to one of the endpoints of the head. A gallium nitride based semiconductor device, wherein the horizontal distance to the endpoint in the direction of the drain region is 0.245 micrometers to 0.255 micrometers. According to claim 1,
On the lower side,
and a lower gate pad and a lower drain pad electrically separated from the source pad and electrically separated from each other, wherein the lower gate pad includes at least one second conductive via hole penetrating the upper and lower surfaces, and The bottom drain pad includes at least one third conductive via hole penetrating the top and bottom surfaces, the second conductive via hole is electrically connected to at least one of the unit gate pads, and the third conductive via hole includes: At least one of the unit drain pads is electrically connected, a gallium nitride-based semiconductor device.

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