KR20220109685A - 3-Terminal Synapse Device and Maximum Conductance Limiting Method Using the Same - Google Patents

Abstract

Disclosed are a 3-terminal synaptic element having a channel layer exposed from a gate stack and a maximum conductance limiting method using the same. This causes the channel layer to include a first region having a variable resistance component and a second region having a fixed resistance component and the maximum conductance can be predicted by using fixed resistance characteristics of the second region so as to adjust a driving range of an element according to an intended purpose. In addition, the maximum current flowing through the element can be limited by the fixed resistance component of the channel layer to prevent damage of the element and risk about a short circuit due to an overcurrent, thereby stably driving the element.

Description

3-Terminal Synapse Device and Maximum Conductance Limiting Method Using the Same

The present invention relates to a three-terminal synaptic device and a maximum conductance limiting method using the same, and more particularly, to a three-terminal synaptic device having a channel layer exposed from a gate stack and a maximum conductance limiting method using the same.

A neuromorphic system can be implemented using the principle of a nerve cell. The pneumomorphic system refers to a system that mimics how the brain processes data by implementing neurons constituting the human brain using a plurality of devices. Therefore, by using a neuromorphic system including a neuron element, it is possible to process and learn data in a manner similar to that of the brain.

1 is a view showing a general neuromorphic system.

Referring to FIG. 1 , a neuron device may be connected to another neuron device through a synapse of the neuron device, and may receive data from another neuron device through the synapse. At this time, the neuron device stores and integrates the received data, and when the threshold voltage (Vt) is higher than the threshold voltage (Vt), it is ignited and output. That is, the neuron element functions to accumulate and fire data. In addition, the synaptic device enhances (potentiation) or suppresses (depression) input data to transmit it to the neuron device. That is, the synaptic device selectively outputs according to the input voltage.

Among these synaptic devices, the two-terminal synaptic device uses the same two electrodes for writing, erasing, and reading. Therefore, it is difficult to accurately control the resistance change, and it is relatively difficult to implement the STDP characteristic. In order to solve this problem, a three-terminal synaptic device for controlling the amount of current flowing between the source and the drain by adding a gate electrode has been introduced, and the possibility of using these devices as a synaptic device is increasing.

2 is a view showing a neuromorphic system in which the conventional three-terminal synaptic device is arranged in an array form.

Figure 3 is a view showing a conventional three-terminal synaptic device.

Referring to FIGS. 2 and 3 , the three-terminal synaptic device has a source connected to a row line and a drain connected to a column line in a neuromorphic system, respectively. Also, the gate has a configuration connected to the gate line.

In this conventional three-terminal synaptic device, as shown in FIG. 3 , the source electrode 20 and the drain electrode 30 are disposed on both sides of the channel layer 10 , and the gate electrode 43 is disposed on the channel layer 10 . A gate stack 40 is disposed. For example, in the case of an ion-based three-terminal synaptic device, a positive or negative gate bias is applied to the gate electrode 43 to transfer active ions from the gate stack 40 to the channel layer 10 or from the channel layer 10 to the gate stack. It operates as a mechanism for changing the conductance of the channel layer 10 by moving it to (40).

That is, in the channel layer 10, the entire channel layer 10 has one variable resistance characteristic by the gate bias applied to the gate electrode 43, and the channel layer 10 according to the movement of active ions by the gate bias. The total resistance of

However, in such a conventional three-terminal synaptic device, if there is no restriction on the resistance value of the channel layer 10, the resistance continues to decrease, and accordingly, the conductance value can become infinitely large, so that an overcurrent in the channel layer 10 is There is a problem that the element is damaged by the flow.

Korean Patent Publication 10-2014-0032186

An object of the present invention is to provide a three-terminal synaptic device capable of limiting the maximum conductance of the entire channel layer using the channel layer exposed from the gate stack and a method of limiting the maximum conductance using the same.

In order to solve the above problems, the three-terminal synaptic device of the present invention is arranged spaced apart from each other with a semiconductor substrate, a channel layer disposed on the semiconductor substrate, and the channel layer interposed therebetween, so as to be in contact with both sides of the channel layer, respectively. a source electrode and a drain electrode disposed on the channel layer, and a gate stack disposed on the channel layer, wherein the channel layer includes a first region overlapping the gate stack and a second region exposed from the gate stack.

The first region may have a variable resistance component, and the second region may have a fixed resistance component.

The total resistance value of the channel layer may be a resistance value obtained by adding the resistance value of the first region and the resistance value of the second zero region.

The total resistance value of the channel layer is

에 따르고, 여기서, R_ch1 : 상기 제1 영역의 저항값, R_ch2 : 상기 제2 영역의 저항값, L_ch1 : 상기 제1 영역의 길이, L_ch : 상기 채널층의 전체 길이, W_ch : 상기 채널층의 폭을 각각 나타낼 수 있다.

Wherein, R _ch1 : resistance value of the first region, R _ch2 : resistance value of the second region, L _ch1 : length of the first region, L _ch : total length of the channel layer, W _ch : Each width of the channel layer may be indicated.

The minimum resistance value of the channel layer may be a resistance value of the channel layer when the resistance value in the first region is 0.

Active ions formed in the gate stack may migrate from the gate stack to the first region or from the first region to the gate stack.

The channel layer may include any one of Pr _0.7 Ca _0.3 MNO _3-x (0<x≤0.5) or WO _x (2.5≤x≤3).

The gate stack may include an intermediate layer disposed on the first region, an ion storage layer disposed on the intermediate layer, and a gate electrode disposed on the ion storage layer.

The first region may be in contact with the intermediate layer, and the second region may be exposed from the intermediate layer.

In order to solve the above problems, the method for limiting the maximum conductance of a three-terminal synaptic device of the present invention includes a first region where a channel layer disposed on a semiconductor substrate overlaps a gate stack and a second region exposed from the gate stack. In the terminal synapse device, measuring the total resistance value of the channel layer according to the length change of the first region, respectively, deriving the resistance value of the second region using the measured total resistance value of the channel layer calculating a resistance value of the first region using the derived resistance value of the second region, calculating a minimum resistance value of the channel layer, and using the minimum resistance value to increase the maximum resistance of the channel layer and calculating a conductance value.

Measuring each of the total resistance values of the channel layer may further include setting a trend line using the measured total resistance values of the channel layer.

Calculating the resistance value of the first region and the minimum resistance value is performed by the following equation

에 따르고, 여기서, R_ch1 : 상기 제1 영역의 저항값, R_ch2 : 상기 제2 영역의 저항값, L_ch1 : 상기 제1 영역의 길이, L_ch : 상기 채널층의 전체 길이, W_ch : 상기 채널층의 폭을 각각 나타낼 수 있다.

Wherein, R _ch1 : resistance value of the first region, R _ch2 : resistance value of the second region, L _ch1 : length of the first region, L _ch : total length of the channel layer, W _ch : Each width of the channel layer may be indicated.

In calculating the minimum resistance value of the channel layer, the minimum resistance value of the channel layer may be a resistance value of the channel layer when the resistance value in the first region is 0.

The gate stack may include an intermediate layer disposed on the first region, an ion storage layer disposed on the intermediate layer, and a gate electrode disposed on the ion storage layer.

According to the present invention described above, the channel layer includes a first region having a variable resistance component and a second region having a fixed resistance component, and is used because the maximum conductance can be predicted using the fixed resistance characteristic of the second region. The driving range of the device can be adjusted according to the intended purpose.

In addition, since the maximum current flowing through the device can be limited by the fixed resistance component of the channel layer, the risk of breakdown or short circuit due to overcurrent can be prevented, thereby stably driving the device. have.

The technical effects of the present invention are not limited to those mentioned above, and other technical effects not mentioned will be clearly understood by those skilled in the art from the following description.

1 is a view showing a general neuromorphic system.
2 is a view showing a neuromorphic system in which the conventional three-terminal synaptic device is arranged in an array form.
Figure 3 is a view showing a conventional three-terminal synaptic device.
Figure 4 is a view showing a three-terminal synaptic device of the present invention.
5 is an equivalent circuit for the channel layer of the three-terminal synaptic device shown in FIG.
6 is a flowchart illustrating a method for deriving the maximum conductance of a 3-terminal synaptic device according to the present invention.
7 is a view showing the operation of a three-terminal synaptic device in which the channel layer of the present invention is formed of Pr _0.7 Ca _0.3 MNO _3-x (0<x≤0.5).
8 is a graph showing a measured resistance value and a corresponding trend line according to the first embodiment of the present invention.
9 is a graph showing measurement results for comparing the maximum conductance calculated according to the first embodiment of the present invention.
10 is a diagram illustrating the operation of a three-terminal synaptic device in which the channel layer of the present invention is formed of WO _x (2.5≤x≤3).
11 is a graph showing a measured resistance value according to a second embodiment of the present invention.
12 is a graph showing measurement results for comparing the maximum conductance calculated according to the second embodiment of the present invention.

Since the present invention can apply various transformations and can have various embodiments, specific embodiments are illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the present invention to specific embodiments, and should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the present invention, if it is determined that a detailed description of a related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings. do it with

Figure 4 is a view showing a three-terminal synaptic device of the present invention.

Referring to Figure 4, the three-terminal synaptic device according to the present invention is a semiconductor substrate 110, the channel layer 120 disposed on the semiconductor substrate 110, the channel layer 120 is disposed spaced apart from each other. It includes a source electrode 130 , a drain electrode 140 , and a gate stack 150 disposed on the channel layer 120 .

The semiconductor substrate 110 may be a silicon substrate, a silicon on insulator (SOI) substrate, a germanium substrate, a germanium on insulator (GOI) substrate, or a silicon-germanium substrate, but is not limited thereto. does not In the embodiment of the present invention, a commonly used silicon substrate may be used, and the semiconductor substrate 110 may be a p-type semiconductor substrate doped with a p-type impurity or an n-type semiconductor substrate doped with an n-type impurity.

A channel layer 120 may be disposed on the semiconductor substrate 110 . The channel layer 120 is formed of any one of a low molecular weight organic semiconductor, an organic semiconductor, a conductive polymer, an inorganic semiconductor, an oxide semiconductor, a two-dimensional semiconductor, and a material formed of quantum dots, or W, Co, Mo, Ti, Ta. It is formed of any one of metal materials, and is preferably formed of a material whose conductance is changed by active ions. For example, the channel layer 120 may be formed of any one of Pr _0.7 Ca _0.3 MNO _3-x (0<x≤0.5) or WO _x (2.5≤x≤3).

A source electrode 130 and a drain electrode 140 formed to be spaced apart from each other with the channel layer 120 interposed therebetween may be disposed on the semiconductor substrate 110 .

The source electrode 130 and the drain electrode 140 are adjacent to a gate stack 150 to be described later, that is, adjacent to the gate stack 150 positioned above the surface of the semiconductor substrate 110 . may be formed on the The source electrode 130 and the drain electrode 140 may include at least one metal material selected from among aluminum, copper, nickel, iron, chromium, titanium, zinc, lead, gold, and silver material. and may include a conductive polymer material such as poly(3,4-ethylenedioxythiophene):polystyrenesulfonate (PEDOT:PSS), and may include a doped polymeric material.

A gate stack 150 may be formed on the channel layer 120 . The gate stack 150 includes an intermediate layer 151 disposed on the channel layer 120 , an ion storage layer 152 disposed on the intermediate layer 151 , and a gate electrode 153 disposed on the ion storage layer 152 . may include

The gate stack 150 has a form in which an intermediate layer 151 , an ion storage layer 152 , and a gate electrode 153 are sequentially stacked through a gate mask, a region overlapping the channel layer 120 and a channel A region that does not overlap layer 120 may be deposited to form. That is, the channel layer 120 includes the channel layer 120 corresponding to the first region 121 overlapping the gate stack 150 and the channel layer corresponding to the second region 122 exposed from the gate stack 150 . 120) can be distinguished. A detailed description of the first region 121 and the second region 122 of the channel layer 120 will be described later.

The intermediate layer 151 may be formed on the channel layer 120 to be in contact with the channel layer 120 . The intermediate layer 151 is preferably formed of an electrolyte material such that active ions move from the ion storage layer 152 to the channel layer 120 or from the channel layer 120 to the ion storage layer 152 .

An ion storage layer 152 may be disposed on the intermediate layer 151 . As the ion storage layer 152 includes an ionic material, it has synaptic properties. For example, the synaptic stimulation spike (spike) moves active ions toward the channel layer 120 formed under the ion storage layer 152, and synaptic response current (excitatory post-synaptic current, drain current) generate Accordingly, the active ions that have migrated to the channel layer 120 attract and accumulate electric charges. Thereafter, when the synaptic stimulation spike ends, the synaptic reaction current gradually decreases, and at the same time, the active ions gradually return to the equilibrium level of the ion gel of the ion storage layer 152 and have synaptic characteristics.

Here, the active ions formed in the ion storage layer 152 may include cations such as H+, Li+, Na+, or anions such as O2-. In addition, the channel layer 120 through which the active ions of the ion storage layer 152 move is preferably formed of a material whose conductivity is changed by the active ions.

A gate electrode 153 may be formed on the ion storage layer 152 . The gate electrode 153 may include a barrier metal layer and a metal layer. For example, the barrier metal layer may be formed of a metal nitride layer such as titanium nitride, tantalum nitride, tungsten nitride, hafnium nitride, and zirconium nitride. The metal layer may be formed of any one selected from tungsten, copper, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal nitrides or a combination thereof.

When a voltage or current is externally applied to the gate electrode 153 , active ions move between the ion storage layer 152 and the channel layer 120 by the applied input signal, and the channel layer by movement of the active ions Since the amount of active ions in 120 is changed to change the conductivity of the channel layer 120 , it has synaptic properties such as a depression property and a potentiation property.

5 is an equivalent circuit for the channel layer of the three-terminal synaptic device shown in FIG.

Referring to FIG. 5 , the channel layer 120 of the three-terminal synaptic device according to the present invention has a first region 121 overlapping the gate stack 150 and a second exposed from the gate stack 150 , as described above. region 122 . That is, the first region 121 is disposed to contact the intermediate layer 151 of the gate stack 150 , and the ion storage layer 152 and the gate electrode 153 are disposed on the intermediate layer 151 in contact with the first region 121 . These are arranged sequentially. For example, the length L _ch1 corresponding to the first region 121 of the channel layer 120 may have the same length as the lengths of the intermediate layer 151 , the ion storage layer 152 , and the gate electrode 153 . .

The second region 122 may be a region in which the gate stack 150 is not deposited and is exposed from the gate stack 150 to form only the channel layer 120 . Accordingly, the length L _ch2 corresponding to the second region 122 of the channel layer 120 is the length L _ch1 corresponding to the first region 121 in the total length L _ch of the channel layer 120 . It may be a length excluding .

For example, the second region 122 may have a shape disposed on both sides of the first region 121 . This may be in the form of exposing both sides of the channel layer 120 by reducing the length of the gate stack 150 in both directions in the conventional three-terminal synaptic device shown in FIG. 3 . Accordingly, the source electrode 130 and the drain electrode 140 may be disposed to be spaced apart from the first region 121 and to be in contact with a side surface of the second region 122 , respectively. Here, both the first region 121 and the second region 122 may have the same channel width W _ch . In addition, the length L _ch1 of the first region 121 may be changed according to an embodiment, and the lengths L _ch2 of the second regions 122 disposed on both sides of the first region 121 are respectively different from each other. They may have the same length, or they may have different lengths.

As shown in FIG. 5 , the first region 121 and the second region 122 may have a variable resistance component and the second region 122 may have a fixed resistance component. For example, since the first region 121 of the channel layer 120 has a structure in which the gate stack 150 is formed on the first region 121 , active ions are released to the gate according to a voltage applied to the gate electrode 153 . The stack 150 may be moved to the first region 121 of the channel layer 120 , or from the first region 121 to the gate stack 150 . Accordingly, the resistance component of the first region 121 may be changed. That is, the first region 121 may have variable resistance characteristics due to movement of active ions.

However, since the second region 122 is a region exposed from the gate stack 150 , movement of active ions does not occur between the gate stack 150 and the second region 122 . Accordingly, the second region 122 may have a fixed resistance characteristic in which the resistance component does not change.

That is, the channel layer 120 according to the present invention may have a fixed resistance characteristic as well as a variable resistance characteristic. Accordingly, the minimum resistance value of the channel layer 120 may be calculated using the fixed resistance characteristic of the second region 122 . Also, the maximum conductance of the channel layer 120 may be obtained using the calculated minimum resistance value. For example, even if the variable resistance component of the first region 121 is minimized according to the voltage applied to the gate electrode 153 , the maximum current flowing through the device may be limited by the fixed resistance component of the second region 122 . Therefore, it is possible to prevent damage to the device due to overcurrent.

6 is a flowchart illustrating a method for deriving the maximum conductance of a 3-terminal synaptic device according to the present invention.

6, in the method for deriving the maximum conductance of the three-terminal synaptic device according to the present invention, the total resistance value (R _total ) of the channel layer 120 according to the length change of the first region 121 , respectively Measuring ( S210 ), deriving the resistance value R _ch2 of the second region 122 using the measured total resistance value R _total of the channel layer 120 ( S220 ), the derived second Calculating the resistance value R _ch1 of the first region 121 using the resistance value R _ch2 of the region 122 ( S230 ), calculating the minimum resistance value of the channel layer 120 ( S240 ) ) and calculating the maximum conductance value of the channel layer 120 using the minimum resistance value ( S250 ).

First, in the three-terminal synaptic device having the first region 121 and the second region 122 of the channel layer 120, the length (L _ch1 ) of the first region 121 is changed and the channel layer 120 is ( S210 ) For example, the length L _ch1 of the first region 121 is changed by changing the length of the gate stack 150 , and the length of the first region 121 is changed. The total resistance value R _total of the channel layer 120 according to the change L _ch1 is measured, respectively. In addition, a trend line may be set using data of the total resistance value of each channel layer 120 that is changed according to a change in the length L _ch1 of the first region 121 . Here, the trend line may be a line estimating a tendency of the total resistance value of the channel layer 120 to change according to a change in the length L _ch1 of the first region 121 .

In the step of deriving the resistance value R _ch2 of the second region 122 , the resistance value R _ch2 of the second region 122 may be derived using each measured total resistance value or the set trend line. (S220) For example, the resistance value R _ch2 of the second region 122 is a resistance value corresponding to the fixed resistance of the channel layer 120 , and the length L _ch1 of the first region 121 . It may be the total resistance value of the channel layer 120 when is 0. This is because the first region 121 has a variable resistance characteristic in which the resistance is changed according to an applied voltage, so that the resistance value R _ch2 of the second region 122 is 0 when the variable resistance value of the first region 121 is 0. , that is, when the length L _ch1 of the first region 121 is 0, it may be the same as the total resistance of the channel layer 120 . Accordingly, by checking the total resistance value of the channel layer 120 when the length L _ch1 of the first region 121 is 0 using the measured total resistance value or trend line, the resistance value ( R _ch2 ) can be derived.

In the step of calculating the resistance value R _ch1 of the first region 121 , the total resistance R _total of the channel layer 120 according to the length of the first region 121 and the derived second region ( By substituting the resistance value R _ch2 of 122) into the equation, the resistance value R _ch1 of the first region 121 may be calculated ( S230 ).

A formula for calculating the resistance value R _ch1 of the first region 121 may be expressed as Equation 1 below.

Here, R _ch1 is the resistance value of the first region 121 , R _ch2 is the resistance value of the second region 122 , L _ch1 is the length of the first region 121 , and L _ch is the entire channel layer 120 . The length and W _ch represent the width of the channel layer 120 .

That is, the resistance value R _ch1 of the first region 121 is unknown, the total resistance R _total measured according to the length L _ch1 of the first region 121 , and the The resistance value R of the first region 121 by applying the overall length L _ch , the width W _ch of the channel layer 120 , and the resistance value R _ch2 of the second region 122 to Equation 1 _ch1 ) can be calculated.

In the step of calculating the minimum resistance value of the channel layer 120, the minimum resistance value of the channel layer ₁₂₀ is the channel layer ( 120). (S240) That is, the total resistance of the channel layer 120 is obtained by adding a variable resistance value corresponding to the first region 121 and a fixed resistance value corresponding to the second region 122. Since it may be a resistance value, the minimum resistance value of the channel layer 120 may be the total resistance when the variable resistance value to which the resistance is changed is 0, that is, the resistance value of the fixed resistance excluding the variable resistance value.

Accordingly, if the total length L _ch of the channel layer 120 , the width W _ch of the channel layer 120 , and the resistance value of the second region 122 R _ch2 are known, the channel layer using Equation 1 The minimum resistance value (R _ch1 ) of (120) can be calculated.

In addition, after calculating the minimum resistance value, the maximum conductance of the channel layer 120 may be calculated using the calculated minimum resistance value ( S250 ). That is, the maximum conductance is obtained by taking the reciprocal of the calculated minimum resistance value. can be derived

As described above, the three-terminal synaptic device according to the present invention can predict the maximum conductance using the second region 122 of the channel layer 120 having a fixed resistance characteristic, so that the device can be driven according to the intended purpose. The range can be adjusted. In addition, since the risk of breakdown or short circuit due to overcurrent can be prevented by using the predicted conductance range, the device can be driven stably.

first embodiment

7 is a view showing the operation of a three-terminal synaptic device in which the channel layer of the present invention is formed of Pr _0.7 Ca _0.3 MNO _3-x (0<x≤0.5).

8 is a graph showing a measured resistance value and a corresponding trend line according to the first embodiment of the present invention.

7 and 8 , the channel layer 120 includes a first region 121 overlapping the gate stack 150 and a second region 122 exposed from the gate stack 150 . In this case, the channel layer 120 may be formed of a material of Pr _0.7 Ca _0.3 MNO _3-x (0<x≤0.5).

For example, when a positive pulse is applied to the gate electrode 153 , active ions are moved from the channel layer 120 to the ion storage layer 152 , and when a negative pulse is applied, the active ions are ions It moves from the storage layer 152 to the channel layer 120 . That is, the conductance of the channel layer 120 is changed according to the pulse applied to the gate electrode 153 .

At this time, the channel layer 120 using Pr _0.7 Ca _0.3 MNO _3-x (0<x≤0.5) is a conduction composed of Mn-O-Mn present in the channel layer 120 as active ions are de-serted. It has a characteristic that conductance is reduced due to the collapse of the conductive path.

For the channel layer 120 having these characteristics, the width and length of the channel layer 120 are respectively formed to be 100 μm, and the length (L _ch1 ) of the first region 121 and the length (L) of the second region 122 . _ch2 ) When the resistance (R _total ) of the entire channel layer 120 according to the change is measured, it can be shown in Table 1 below.

Length of the first region (μm) Length of the second region (μm) Total resistance of the channel layer (MΩ) 0 100 12.82 4 96 12.26 10 90 11.81 20 80 10.98 40 60 9.85 60 40 8.76

In addition, in Table 1, the total resistance value of the channel layer 120 measured according to the length L _ch1 of the first region 121 and a trend line corresponding thereto may be shown as shown in FIG. 8 .

The resistance value R _ch2 of the second region 122 may be obtained by using the trend line of FIG. 8 . For example, the resistance value R _ch2 of the second region 122 is a resistance value corresponding to the fixed resistance of the channel layer 120 , and the length L _ch1 of the first region 121 is zero. It may be the same as the total resistance of the channel layer 120 . Accordingly, when the trend line is used, the resistance value R _ch2 of the second region 122 may have 12.023 MΩ/□.

Here, using the resistance value R _ch2 of the second region 122 and Equation 1, the resistance value R _ch1 of the first region 121 according to the length L _ch1 of the first region 121 is obtained. can be saved For example, when the length L _ch1 of the first region 121 is 40 μm, the resistance value R _ch1 of the first region 121 is, when the length L _ch1 of the first region 121 is 40 μm The total resistance of R _total = 9.85 MΩ, the length of the first region 121 (L _ch1 ) = 40 μm, the resistance of the second region 122 (R _ch2 ) = 12.023 MΩ/□, the channel layer 120 ) length (L _ch )=100 μm and width (W _ch )=100 μm of the channel layer 120 are applied to Equation 1 to obtain a resistance value of 6.593 MΩ/□.

In addition, since the minimum resistance value of the channel layer 120 is the total resistance value when the variable resistance value is 0, the fixed resistance value corresponding to the second region 122 may be the minimum resistance value of the channel layer 120 . Accordingly, when the total resistance of the first region 121 is 0 in Equation 1, a minimum resistance value of 10.82 MΩ can be calculated. In order to obtain the maximum conductance using the calculated minimum resistance value, the maximum conductance of 92.415nS can be obtained by converting the minimum resistance value to a reciprocal number. That is, the maximum conductance may be obtained using the fixed resistance component of the second region 122 of the channel layer 120 .

9 is a graph showing measurement results for comparing the maximum conductance calculated according to the first embodiment of the present invention.

Referring to FIG. 9 , the measured value of FIG. 9 represents the measured conductance when a gate bias of 0.5V to 4.0V is applied. As shown in FIG. 9 , it can be seen that the measured maximum conductance has a conductance value similar to the calculated maximum conductance of 76.64 nS.

second embodiment

10 is a view showing the operation of a three-terminal synaptic device formed of the channel layer of the present invention WO _x (2.5≤x≤3).

11 is a graph showing a measured resistance value according to a second embodiment of the present invention.

10 and 11 , the channel layer 120 includes a first region 121 overlapping the gate stack 150 and a second region 122 exposed from the gate stack 150 . Here, the channel layer 120 may be formed of a material of WO _x (2.5≤x≤3).

At this time, the three-terminal synaptic device having the channel layer 120 formed of WO _x (2.5≤x≤3) is the first synaptic device having Pr _0.7 Ca _0.3 MNO _3-x (0<x≤0.5) as the channel layer 120 . Compared with the three-terminal synaptic device according to the embodiment, as the active ions are eliminated (desertion), the conductance has the opposite characteristic of increasing.

For the channel layer 120 having the opposite characteristics to the first embodiment, the width (W _ch ) of the channel layer 120 is 10 μm, the length (L _ch ) of the channel layer 120 is formed to be 60 μm, When the resistance R _total of the entire channel layer 120 according to the change in the length L _ch1 of the first region 121 and the length L _ch2 of the second region 122 is measured, respectively, as shown in Table 2 below. can indicate

Length of the first region (μm) Length of the second region (μm) Total resistance of the channel layer (MΩ) 0 60 3.73 4 56 29 10 50 90.1 20 40 145 40 20 286

In addition, in Table 2, the total resistance value R _total of the channel layer 120 measured according to the length L _ch1 of the first region 121 may be expressed as a graph as shown in FIG. 11 .

When the resistance value R _ch1 of the first region 121 and the resistance value R _ch2 of the second region 122 according to the second embodiment are obtained in the same manner as in the first embodiment, 71.437 MΩ/□ and A resistance value of 0.622MΩ/□ can be obtained.

In addition, when the length R _ch1 of the first region 121 is 4 μm, 10 μm, 20 μm, and 40 μm using the calculated resistance value R _ch2 of the second region 122 , the minimum of the channel layer 120 is If the resistance value is obtained, the minimum resistance value of 3.48MΩ, 3.11MΩ, 2.48MΩ, and 1.24MΩ can be obtained, respectively. If the maximum conductance is obtained by taking the reciprocal of each calculated minimum resistance value, the maximum conductance of 287nS, 321nS, 401nS, and 803nS can be obtained, respectively.

12 is a graph showing measurement results for comparing the maximum conductance calculated according to the second embodiment of the present invention.

12, when the conductance at 4 μm, 10 μm, 20 μm and 40 μm is measured, respectively, as shown in (a), (b), (c) and (d) of FIG. 12, 273 nS, 301 nS, 363 nS, and 663 nS, respectively It can be seen that the conductance of is measured and has a conductance value similar to the calculated maximum conductance.

As described above, in the three-terminal synaptic device according to the present invention, the channel layer 120 includes a first region 121 having a variable resistance component and a second region 122 having a fixed resistance component, and the second Since the maximum conductance can be predicted using the fixed resistance characteristic of the region 122 , the driving range of the device can be adjusted according to the intended purpose.

In addition, since the maximum current flowing through the device can be limited by the fixed resistance component of the channel layer 120, the risk of breakdown or short circuit due to overcurrent can be prevented, so that the device can be stably operated. can be driven

On the other hand, the embodiments of the present invention disclosed in the present specification and drawings are merely presented as specific examples to aid understanding, and are not intended to limit the scope of the present invention. It will be apparent to those of ordinary skill in the art to which the present invention pertains that other modifications based on the technical spirit of the present invention can be implemented in addition to the embodiments disclosed herein.

110: semiconductor substrate 120: channel layer
121: first region of channel layer 122: second region of channel layer
130: source electrode 140: drain electrode
150: gate stack 151: intermediate layer
152: ion storage layer 153: gate electrode

Claims (14)

semiconductor substrate;
a channel layer disposed on the semiconductor substrate;
a source electrode and a drain electrode disposed to be spaced apart from each other with the channel layer interposed therebetween, and disposed so as to be in contact with both sides of the channel layer; and
a gate stack disposed on the channel layer;
The channel layer is a three-terminal synaptic device comprising a first region overlapping the gate stack and a second region exposed from the gate stack. According to claim 1,
The first region has a variable resistance component, the second region is a three-terminal synaptic device having a fixed resistance component. The method of claim 1,
The total resistance value of the channel layer is a three-terminal synaptic device that is the sum of the resistance value of the first region and the resistance value of the second zero region. According to claim 1,
The total resistance value of the channel layer is

according to
here,
R _ch1 : resistance value of the first region
R _ch2 : resistance value of the second region
L _ch1 : length of the first region
L _ch : the total length of the channel layer
W _ch : A three-terminal synaptic device that represents the width of the channel layer, respectively. According to claim 1,
The minimum resistance value of the channel layer is a three-terminal synaptic device that is the resistance value of the channel layer when the resistance value in the first region is 0. According to claim 1,
The active ions formed in the gate stack, a three-terminal synaptic device that moves from the gate stack to the first region or from the first region to the gate stack. According to claim 1,
The channel layer is a 3-terminal synaptic device comprising any one of Pr _0.7 Ca _0.3 MNO _3-x (0 < x ≤ 0.5) or WO _x (2.5 ≤ x ≤ 3). The method of claim 1 , wherein the gate stack comprises:
an intermediate layer disposed on the first region;
an ion storage layer disposed on the intermediate layer; and
A three-terminal synaptic device comprising a gate electrode disposed on the ion storage layer. 9. The method of claim 8,
The first region is in contact with the intermediate layer, the second region is a three-terminal synaptic device that is exposed from the intermediate layer. In the three-terminal synaptic device comprising a first region and a second region exposed from the gate stack, the channel layer disposed on the semiconductor substrate overlapping the gate stack,
measuring a total resistance value of the channel layer according to a change in the length of the first region;
deriving a resistance value of the second region using the measured total resistance value of the channel layer;
calculating a resistance value of the first region using the derived resistance value of the second region;
calculating a minimum resistance value of the channel layer; and
Maximum conductance limiting method of a three-terminal synaptic device comprising the step of calculating a maximum conductance value of the channel layer using the minimum resistance value. 11. The method of claim 10, wherein each of the measuring the total resistance of the channel layer comprises:
Maximum conductance limiting method of a three-terminal synaptic device further comprising the step of setting a trend line (trend line) using the total resistance value of the measured channel layer. 11. The method of claim 10,
Calculating the resistance value of the first region and the minimum resistance value is performed by the following equation

according to
here,
R _ch1 : resistance value of the first region
R _ch2 : resistance value of the second region
L _ch1 : length of the first region
L _ch : the total length of the channel layer
W _ch : A method of limiting the maximum conductance of a three-terminal synaptic device that represents the width of the channel layer, respectively. 11. The method of claim 10, In the step of calculating the minimum resistance value of the channel layer,
The minimum resistance value of the channel layer is a maximum conductance limiting method of a three-terminal synaptic device that is the resistance value of the channel layer when the resistance value in the first region is 0. 11. The method of claim 10, wherein the gate stack comprises:
an intermediate layer disposed on the first region;
an ion storage layer disposed on the intermediate layer; and
A method of limiting the maximum conductance of a three-terminal synaptic device comprising a gate electrode disposed on the ion storage layer.

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