KR20220107808A - A mixed-signal binarized neural network circuit device - Google Patents

Abstract

The present invention relates to a neural network circuit technology. More specifically, the present invention relates to a mixed signal binarization neural network circuit device that realizes an edge computing of a neural network by implementing a circuit that performs a core operation of a binarization neural network. Therefore, the present invention is capable of reducing a power consumption and an area.

Description

Mixed-signal binarized neural network circuit device {A MIXED-SIGNAL BINARIZED NEURAL NETWORK CIRCUIT DEVICE}

The present invention relates to neural network circuit technology, and more particularly, to a mixed-signal binarized neural network circuit device that realizes edge computing of a neural network by implementing a circuit that performs a core operation of a binarized neural network.

Artificial neural networks are built through successive multiply-and-accumulate (MAC) operations.

where x _i is the input, w _i is the weight, b is the bias, and y is the output. The calculation of this formula, which is often performed with a digital circuit, is performed with an analog circuit to increase power efficiency and operating speed.

A binary neural network (BNN) is a neural network in which inputs, outputs, and weights are binary 0 and 1 (or -1 and 1) in a neural network. Binary Neural Network (BNN) is one of the neural network algorithms that can perform artificial intelligence functions through machine learning. Binary Neural Network (BNN) algorithm is suitable to perform in hardware by greatly reducing memory size, computational complexity and power consumption by using binary weight and activation function with binary output.

In the past, MAC, which is the core operation of neural networks, was performed on a GPU that is advantageous for parallel operation to speed up the learning speed, but the GPU has a problem in that power consumption is large and the density is low.

Korean Patent Publication No. 10-2019-0094679 (2019.08.14)

The present invention performs the core operation of the BNN in a chip in order to solve the existing problems. The current mirror neurons in the circuit perform MAC operations in the current domain and use a comparator to compute the sign activation function. This circuit is an important technology that can be used in various fields such as voice recognition, Internet of Things (IoT), image processing, autonomous driving, and image classification because it has designed a neural network that is widely used in the field of artificial intelligence.

An embodiment of the present invention implements a circuit that performs a core operation of a binarized neural network to realize edge computing of a neural network, and performs a neural network operation using a GPU in a chip to reduce power consumption and area. would like to provide

When performing artificial intelligence-related functions on a specific device, various problems occur when neural network learning is performed in the cloud and then the information is communicated to and received. Because the computation required for neural network learning is processed within the data center, communication delay occurs depending on the distance between the data center and the device, and the communication speed is affected by the bandwidth of the network. In other words, even if the neural network learning in the cloud is fast, the speed may be greatly reduced in the communication process with the device.

In addition, high security is also required for data transmission between the cloud and the edge. When learning neural networks in the cloud, there are also problems in terms of hardware. In data centers, general-purpose CPUs and GPUs are used as arithmetic processing units, but when the computation required for neural network learning is performed on the GPU, the speed is high, but the power consumption is high and the degree of integration is low.

To solve these problems, neural network computation is performed at the edge. In addition, memory size and power consumption are reduced by using a BNN structure that learns by limiting the bit size of weights used in calculations to 1 bit among neural network algorithms. In order to perform the MAC operation and the sign activation function, which are the core operations of BNN, the circuit shown in FIG. 1 is configured.

In order for the circuit of the present invention to operate, parameters necessary for neural network operation must be stored in a memory. If input data, weight, and bias values are input, MAC operation is performed in the current mirror neuron as shown in FIG. 1 . When applied to BNN, multiplication of an input value and a weight in the MAC operation is performed by the XNOR gate as shown in FIG. 6 . The bias value is applied by adjusting the width of the NMOS mirror with a switch in the case of a digital signal and adjusting the gate-source voltage of the NMOS mirror in the case of an analog signal. The multiplied value of the input and the weight and the sign of the bias determine the sign of the current by adjusting the current switch connected to each NMOS mirror. The positive current switch is connected to the diode-connected PMOS and the negative current switch is connected to the PMOS mirror. At this time, the difference in currents of different signs determines the drain node voltage vd. Finally, the comparator compares the reference voltage and vd to perform the sign activation function.

The disclosed technology may have the following effects. However, this does not mean that a specific embodiment should include all of the following effects or only the following effects, so the scope of the disclosed technology should not be construed as being limited thereby.

A mixed-signal binarized neural network circuit device according to an embodiment of the present invention realizes edge computing of a neural network by implementing a circuit that performs a core operation of a binarized neural network, and performs neural network computation using GPU in a chip to reduce power consumption and area can

1 is a diagram illustrating a current mirror neuron circuit for performing a Neural Network operation.
Fig. 2 is a diagram showing a circuit for adjusting a weight size with a digital value;
Fig. 3 is a diagram showing a circuit for adjusting a weight size with an analog value V _control .
Fig. 4 is a diagram showing a circuit for adjusting a bias magnitude with a digital value;
5 is a diagram illustrating a circuit for adjusting a bias magnitude by adjusting a gate voltage.
6 is a diagram illustrating a current mirror neuron circuit that performs a BNN (binary neural network) operation.
FIG. 7 is a diagram illustrating an RC equivalent circuit viewed from the vd node of FIG. 6 .

Since the description of the present invention is merely an embodiment for structural or functional description, the scope of the present invention should not be construed as being limited by the embodiment described in the text. That is, since the embodiment is capable of various changes and may have various forms, it should be understood that the scope of the present invention includes equivalents capable of realizing the technical idea. In addition, since the object or effect presented in the present invention does not mean that a specific embodiment should include all of them or only such effects, it should not be understood that the scope of the present invention is limited thereby.

On the other hand, the meaning of the terms described in the present application should be understood as follows.

Terms such as “first” and “second” are for distinguishing one component from another, and the scope of rights should not be limited by these terms. For example, a first component may be termed a second component, and similarly, a second component may also be termed a first component.

When a component is referred to as being “connected” to another component, it may be directly connected to the other component, but it should be understood that other components may exist in between. On the other hand, when it is mentioned that a certain element is "directly connected" to another element, it should be understood that the other element does not exist in the middle. On the other hand, other expressions describing the relationship between elements, that is, "between" and "between" or "neighboring to" and "directly adjacent to", etc., should be interpreted similarly.

The singular expression is to be understood to include the plural expression unless the context clearly dictates otherwise, and terms such as "comprises" or "have" refer to the embodied feature, number, step, action, component, part or these It is intended to indicate that a combination exists, and it should be understood that it does not preclude the possibility of the existence or addition of one or more other features or numbers, steps, operations, components, parts, or combinations thereof.

Identifiers (eg, a, b, c, etc.) in each step are used for convenience of description, and the identification code does not describe the order of each step, and each step clearly indicates a specific order in context. Unless otherwise specified, it may occur in a different order from the specified order. That is, each step may occur in the same order as specified, may be performed substantially simultaneously, or may be performed in the reverse order.

All terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, unless otherwise defined. Terms defined in general used in the dictionary should be interpreted as having the meaning consistent with the context of the related art, and cannot be interpreted as having an ideal or excessively formal meaning unless explicitly defined in the present application.

Artificial neural networks are built through successive multiply-and-accumulate (MAC) operations.

Here, for the i-th input, x _i is the input, w _i is the weight, b is the bias, and y is the output. In order to implement the above equation as a current mirror, it is expressed as in FIG. 1 . After multiplying the input x _i by the weight w _i by the ratio of the input current mirror (the ratio of the size of the MOSFET constituting the current mirror), it is converted into a current, and all currents corresponding to the bias b are summed in the summing current mirror. Through this process, the operation of the above equation can be implemented as a current mirror-based circuit (FIG. 1). In the method of adding current, in order to handle negative input current (-) as well as positive input current (+), multiply the input current by weight w _i , and if the copied current w _i x _i is positive, add it to the reference current , configure the circuit to be subtracted by subtracting from the radiant current node when it is negative (FIG. 1).

The weight w _i is the current radiation ratio of the current mirror and can be variously adjusted by analog and digital methods ( FIGS. 2 and 3 ). In some examples, it is possible to adjust the current radiation ratio with a digital signal, or to adjust the weight by connecting a variable resistor to the radiation end transistor of the current mirror and adjusting the control voltage (Vcontrol). In FIG. 2, digital signals b _n-1 b _n-2 ... b ₀ are digital control signals composed of sign-magnitude, and b _n-1 is a sign bit.

The bias b can be adjusted in analog and digital ways with respect to the corresponding voltage v _b . The circuit of FIG. 4 is a circuit for adjusting the bias size to a digital value. In this case, n means the number of bits of bias. Each bit of bias is implemented as an NMOS with a width of 2 _n-1 times, and a current corresponding to the corresponding bias value flows. Transistors reflecting each bit size are connected to a current switch controlled by the bit value of the bias to flow a current proportional to the actual bias value. The circuit of FIG. 5 is an example of a circuit for adjusting the gate voltage in an analog manner. The two circuits of FIG. 5 adjust the magnitude of the bias by changing the gate-source voltage v _b of the bias transistor. The operation of the circuit (1) can be explained by dividing it into two phases. In the first phase, the first switch is on and the second switch is off, so that vrefp or vrefn is connected to the sampling capacitor C _p (v _refp or v _refn ) to charge the charge of C _p . As a fragmentary example, v _refp may be applied to V _DD , and v _refn may be applied to the ground. In the second phase, the two switches are operated in reverse to connect C _p and C _b and change the bias input voltage v _b . The value of v _b can be adjusted through the capacity of the two capacitors, the magnitude of the input voltage, and the number of operations. The circuit (2) of FIG. 5 uses a method of converting a digital bias value into an analog voltage v _b using a Digital-to-Analog Converter (DAC). The change in v _b through the DAC regulates the current in the bias transistor.

In order to perform such MAC operation, a current mirror neuron circuit, which is an analog circuit configured in the form of a current mirror, is constructed (FIG. 1).

A binary neural network is a neural network in which inputs and outputs are binary 0 and 1. Binary Neural Network (BNN) algorithm is performed. BNN is characterized by using an activation function that produces a 1-bit weight and 1-bit output. The core operation of BNN, the multiply-and-accumulate (MAC) operation, is

It can be expressed by the same formula as , where w _i is the weight and x _i is the input value. The BNN algorithm is used to give non-linearity to the computation process.

Use the sign activation function as in the formula of Finally, the output node operation of the hidden layer is

, where b is the bias. In this case, the weight w _i , the input value x _i , and the output value y are all binary values. The processor uses a current mirror neuron to calculate the MAC operation in the current domain and performs a sign activation function using a latched voltage comparator.

6 is a circuit of an N×1 current mirror neuron. The input node includes a diode-connected NMOS of minimal size. The transistors are designed so that the minimum input current I _LSB flows in consideration of noise and mismatch. The drains of the input NMOSs are connected to a current switch that is regulated by a weight multiplied by the input. In this case, since both the weight and the input value are binary numbers, the product of the two values can be performed as an XNOR gate. The sign of the bias adjusts the current switch connected to the XNOR circuit, and the ratio of the NMOS current mirror is used when the bias size is determined by the digital bit size. The ratio of the current mirror is controlled by the width of the NMOS mirror. If the bias magnitude is determined in an analog manner, the gate voltage v _b of the NMOS mirror is adjusted. The current flowing through the positive switches accumulates in the diode-connected PMOS. The difference between the current radiated to the PMOS mirror and the current flowing through the negative switches determines the drain node voltage v _d . Finally, the sign activation function is performed by receiving v _d and the reference voltage v _ref as inputs of the comparator.

7 shows an RC equivalent circuit viewed from the v _d node of FIG. 6 . In the equivalent circuit of FIG. 2 , _ro is the output resistance of the transistors connected to the v _d node, and C _p is the parasitic capacitor component at the node. I _diff represents the difference between positive and negative currents

can be expressed by the formula of This formula represents the value obtained by multiplying the output of the MAC operation by I _LSB . The voltage change with time at the v _d node through the equivalent circuit of FIG.

It can be derived by the same formula as By appropriately designing the parameters included in the above equation, the amount of change in voltage and settling time can be adjusted.

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art can variously modify and change the present invention within the scope without departing from the spirit and scope of the present invention as set forth in the claims below. You will understand that it can be done.

100: current mirror neuron circuit

Claims (10)

A mixed-signal binarized neural network circuit device that implements a neural network circuit based on electric current.
According to claim 1,
A mixed-signal binarization neural network circuit device that implements the Multiply and Acculmulate of the neural network circuit as a current mirror.
According to claim 1,
A hybrid signal binarization neural network circuit device that implements the addition of the neural network circuit by adding a current using a current mirror.
According to claim 1,
A mixed signal binarization neural network circuit device for implementing multiplication by a method of amplifying a current using a current mirror for multiplication of the neural network circuit.
According to claim 1,
A hybrid signal binarization neural network circuit device that implements addition and subtraction by applying a bias current source to a reference current or a radiation current direction using the bias of the neural network circuit as a current.
According to claim 1,
A mixed-signal binary neural network circuit device that controls the input of a current mirror by using an XNOR gate to implement a binary neural network.
According to claim 1,
A mixed-signal binary neural network circuit device that adjusts the gate (or base) voltage of a transistor serving as a current source to adjust the bias.
According to claim 1,
A mixed-signal binary neural network circuit device that adjusts the width of the gate (or base) of the transistor serving as the current source to adjust the bias.
According to claim 1,
A mixed-signal binarized neural network circuit device that adjusts the gate (base) or source (emitter) voltage of the corresponding radiant current transistor to adjust the weight.
According to claim 1,
A mixed-signal binary neural network circuit device that adjusts the width of the gate (or base) of the transistor serving as the current source to adjust the bias.

Images