KR20220104511A - Controller and memory system having the controller - Google Patents

Abstract

The present technology includes: a light queue configured to queue commands including a zone ID and a light pointer in the order in which the commands are input; and a queue controller configured to allocate temporary buffers to zone IDs of the commands and store the commands output from the light queue in the temporary buffers classified according to the zone IDs. The queue controller includes a controller configured to output the commands stored in a temporary buffer filled with a set storage size among the temporary buffers.

Description

Controller and memory system having the controller}

The present invention relates to a controller and a memory system including the same, and more particularly, to a controller for managing storage devices included in the memory system in units of zones, and to a memory system including the same.

The electronic system may include hosts and a memory system.

The hosts may be devices such as mobile phones or computers, and the memory system may be a system that stores data or outputs read data according to the control of the hosts. The memory system may include a memory device in which data is stored and a controller controlling the memory device. Memory devices are classified into volatile memory devices and non-volatile memory devices.

A volatile memory device stores data only when power is supplied, and is a memory device in which stored data is lost when power supply is cut off. Volatile memory devices include static random access memory (SRAM) and dynamic random access memory (DRAM).

A non-volatile memory device is a memory device in which data is not destroyed even when power is cut off. Memory (Flash Memory), etc.

An embodiment of the present invention provides a controller and a memory system including the same, which can prevent commands from being accumulated by increasing the priority of commands that can be processed for each zone in a memory system that manages a storage device in units of zones.

A controller according to an embodiment of the present invention includes: a write queue configured to queue commands including a zone ID and a write pointer in an input order; and a queue controller configured to allocate temporary buffers to zone IDs of the commands and to store the commands output from the write queue in the temporary buffers classified according to the zone ID, wherein the queue controller comprises: and output the commands stored in a temporary buffer filled with a set storage size among the temporary buffers.

A memory system according to an embodiment of the present invention includes a storage device including dies for storing data; and a controller configured to generate commands in response to requests output from a host and queue the commands according to states of the dies, wherein the controller manages the storage device by classifying the dies into zone IDs and , give priority to a zone ID in which all write pointers are filled among the zone IDs regardless of the order of the queued commands during a program operation, and output the commands assigned to the zone ID having the priority.

The controller according to an embodiment of the present invention generates commands corresponding to requests received from the host, allocates write pointers to the commands according to the order in which the commands are generated, and stores the state of the storage device in which data is stored. a command management unit configured to queue the commands according to a write queue configured to temporarily store the queued commands; temporary buffers separated by zone ID; and a controller including a zone manager configured to store the commands output from the write queue in the temporary buffers according to the zone ID and the order of the write pointers, and output the commands in the temporary buffer filled with a set size. do.

The present technology can prevent a phenomenon in which commands are accumulated by increasing the priority of commands that can be processed for each zone.

1 is a diagram for explaining a memory system according to an embodiment of the present invention.
FIG. 2 is a view for explaining the die shown in FIG. 1 .
FIG. 3 is a diagram for explaining the memory block shown in FIG. 2 .
4A to 4C are diagrams for explaining a zone according to an embodiment of the present invention.
5 is a view for explaining a controller according to an embodiment of the present invention.
6 is a diagram for explaining an operation of a controller according to an embodiment of the present invention.
7 is a view for explaining a zone management unit according to an embodiment of the present invention.
8 is a diagram for explaining an operation of a zone management unit according to an embodiment of the present invention.
9 is a diagram for explaining a memory interface according to an embodiment of the present invention.
10 is a diagram for explaining an operation of a controller accessing dies.
11 to 18B are diagrams for sequentially explaining the operation of the memory system according to the first embodiment of the present invention.
19A and 19B are diagrams for explaining an operation of a memory system according to a second embodiment of the present invention.
20A and 20B are diagrams for explaining an operation of a memory system according to a third embodiment of the present invention.
21 is a view showing a memory card system to which the controller of the present invention is applied.
22 is a view showing a solid state drive (SSD) system to which the controller of the present invention is applied.

1 is a diagram for explaining a memory system according to an embodiment of the present invention.

Referring to FIG. 1 , a memory system 1000 may include a storage device 1100 capable of storing data and a controller 1200 capable of controlling the storage device 1100 .

The storage device 1100 may include a plurality of dies D01 to Dnm. The dies D01 to Dnm may be configured to be identical to each other. The dies D01 to Dnm may perform a program, read, or erase operation in response to a command output from the controller 1200 . The dies D01 to Dnm may be configured as nonvolatile memory devices. For example, non-volatile memory devices include EEPROM (Electrically Erasable and Programmable ROM), NAND flash memory, NOR flash memory, PRAM (Phase-change RAM), ReRAM (Resistive RAM), FRAM (Ferroelectric RAM), STT-MRAM (STT-MRAM) Spin Transfer Torque - Magnetic RAM) and the like.

The controller 1200 may communicate between a host 2000 and the storage device 1100 . For example, the controller 1200 may generate a program, read, or erase command according to a request output from the host 2000 , and transmit the generated command to the storage device 1100 .

The host 2000 may output a program request, a write pointer, and data to the controller 1200 during a program operation. The write pointer may indicate the order in which program requests are output. For example, whenever a program request is output, the write pointer may have a value that increases in steps.

The controller 1200 according to the present embodiment may manage the dies D01 to Dnm included in the storage device 1100 in units of zones. For example, the controller 1200 divides the memory blocks included in each of the dies D01 to Dnm in units of logical block addresses according to a predetermined storage capacity, and divides the plurality of logical block addresses into zones. ) can be divided into groups of units. That is, a plurality of logical block addresses may be mapped to one region. The controller 1200 according to the present embodiment may be configured to output commands in units of zones. Accordingly, the controller 1200 may be configured to queue and output commands for each zone using the write pointer. For example, the controller 1200 may queue commands according to the state of the storage device 1100 irrespective of the order of requests received from the host 2000 , and use a write pointer to queue commands for each zone again. It is possible to prevent a phenomenon in which commands are accumulated.

FIG. 2 is a diagram for explaining the die shown in FIG. 1 , and since the 01 th to nm th dies D01 to Dnm shown in FIG. 1 may be configured identically to each other, among them, the nm th die (Dnm) will be described as an example.

Referring to FIG. 2 , a die Dnm may include at least one plane, and FIG. 2 shows a die nm including a plurality of planes PL1 to PLj. The first to j-th planes PL1 to PLj may have the same configuration as each other, and may include first to i-th memory blocks BLK1 to BLKi, respectively. Each of the first to i-th memory blocks BLK1 to BLKi includes a plurality of memory cells in which data may be stored. During a program, read, or erase operation, at least one memory block may be selected from among the first to i-th memory blocks BLK1 to BLKi included in each of the first to j-th planes PL1 to PLj. That is, when a program, read, or erase operation is performed on the die (nm), a plurality of memory blocks may be simultaneously selected. The die Dnm further includes peripheral circuits configured to program, read, or erase selected memory blocks included in the first to j-th planes PL1 to PLj, and the peripheral circuits vary according to the die (nm). Since it can be configured in a simple manner, a detailed description thereof will be omitted in the present embodiment.

FIG. 3 is a diagram for explaining the memory block shown in FIG. 2 .

Referring to FIG. 3 , any one of the plurality of memory blocks BLK1 to BLKi illustrated in FIG. 2 is illustrated as an embodiment.

The memory block BLKi may include a plurality of strings ST connected between the first to mth bit lines BL1 to BLm (m is a positive integer) and the source line SL. Each of the strings ST includes a source select transistor SST and first to nth memory cells C1 to Cn connected in series between the source line SL and the first to mth bit lines BL1 to BLm. and a drain select transistor DST.

The memory block BLKi illustrated in FIG. 3 is a diagram for explaining the configuration of the memory block, and thus the number of the source select transistor SST, the first to nth memory cells C1 to Cn, and the drain select transistor DST. is not limited to the number shown in FIG. 3 .

Gates of the source select transistors SST connected to different strings ST are connected to the source select line SSL, and gates of each of the first to nth memory cells C1 to Cn are first to nth It may be connected to the word lines WL1 to WLn, and gates of the drain select transistors DST may be connected to the drain select line DSL.

A group of memory cells connected to the same word line and included in different strings ST may constitute one page PG. A program operation and a read operation may be performed in units of pages PG.

4A to 4C are diagrams for explaining a zone according to an embodiment of the present invention.

Referring to FIG. 4A , the storage device 1100 includes dies D01 to Dnm physically separated as shown in FIGS. 1 and 2 and a memory block physically separated from each of the dies D01 to Dnm. Although the memory blocks BLK1 to BLKi are included, in the present embodiment, all memory blocks included in the storage device 1100 may be logically divided. All memory blocks included in the dies D01 to Dnm may be divided in units of logical block addresses (LBAs). For example, a logical block address LBA may be allocated to all memory blocks included in the storage device 1100 . That is, first to i-th logical block addresses LBA01 to LBAi may be mapped to the memory blocks, and the memory blocks mapped to consecutive logical block addresses are physically discontinuously disposed in the storage device 1100 . can be

Referring to FIG. 4B , the logical block addresses LBA01 to LBAi may be grouped into a plurality of zones, and a zone ID (Zid) may be assigned to each zone group. That is, the zone ID Zid may be an index of groups in which memory blocks are grouped according to a predetermined storage capacity. For example, the logical block addresses LBA01 to LBAi may be divided into a plurality of zones divided by first to x-th zone IDs Zid01 to Zidx. The storage capacity of each of the first to xth zone IDs Zid01 to Zidx may be set to be the same as each other or may be set differently. When the storage capacities are set to be the same, the number of logical block addresses allocated to each of the first to xth zone IDs Zid01 to Zidx may be the same. When the storage capacity is set differently, the number of logical block addresses allocated to the first to xth zone IDs Zid01 to Zidx may be different from each other. Alternatively, the storage capacities of some zone IDs among the first to x-th zone IDs Zid01 to Zidx may be set to be the same, and the storage capacities of the remaining zone IDs may be set differently.

Referring to FIG. 4C , an x-th zone ID Zidx is shown as an example among the first to x-th zone IDs Zid01 to Zidx shown in FIG. 4B . It is assumed that nth to ith logical block addresses LBAn to LBAi are allocated to the xth zone ID Zidx. A write pointer (WP) received from the host may indicate a logical block address selected when storing consecutive data, and a start pointer (SP) is the first logical block of the x-th zone ID (Zidx). It can be an address. For example, the write pointer may indicate the sequence of requests sent by the host to the controller. Referring to Figure 4c, LBAn, LBAn+1, LBAn+2, ... Each of , LBAi becomes a write pointer (WP), and among them, the first write pointer LBAn becomes a start pointer (SP). Accordingly, start pointers of different zone IDs may be assigned to different logical block addresses.

5 is a view for explaining a controller according to an embodiment of the present invention.

5, the controller 1200 includes a zone manager 500, a system buffer 510, a command manager 520, a host interface 530, and a memory interface ( memory interface; 540). The zone manager 500 , the system buffer 510 , the command manager 520 , the host interface 530 , and the memory interface 540 may communicate with each other through a bus BUS.

When the write pointers corresponding to the commands are discontinuous during the program operation, the zone manager 500 may adjust the queuing order of commands so that the write pointers are continuous in the same zone ID. Also, when a zone ID in which all the write pointers are filled occurs, the zone management unit 500 may increase the priority of outputting a command corresponding to the zone ID. For example, the zone manager 500 may preferentially output a command corresponding to a zone ID in which all write pointers are filled over a command corresponding to a zone ID in which the write pointers are not filled.

The system buffer 510 may be configured to store various pieces of information necessary for the operation of the controller 1200 . For example, the system buffer 510 may store mapping information between logical block addresses and physical block addresses. For example, the system buffer 510 may store a map table including logical block addresses corresponding to write pointers and physical block addresses mapped to logical block addresses. The physical block address may be an address assigned to each of the die and memory blocks that may be managed in the storage device, and the logical block address may be an address that may be managed by the host. Accordingly, non-sequential physical block addresses may be mapped to sequential logical block addresses.

When a request output from the host 2000 is input, the command manager 520 may generate a command corresponding to the request and change the order of the commands according to the state of the storage device 1100 . In this case, commands may be queued regardless of the order of the write pointers. The queued commands may be transmitted to the area management unit 500 .

The host interface 530 may be configured to exchange a request, an address, or data between the host 2000 and the controller 1200 .

The memory interface 540 may be configured to exchange commands, addresses, or data between the controller 1200 and the storage device 1100 . The memory interface 540 may include buffers for temporarily storing commands output from the zone manager 500 before outputting the commands to the storage device 1100 . The memory interface 540 may receive physical block addresses respectively corresponding to the write pointers output from the zone manager 500 from the system buffer 510 , and output commands and physical block addresses to the storage device 1100 . .

6 is a diagram for explaining an operation of a controller according to an embodiment of the present invention.

Referring to FIG. 6 , the command manager 520 receives requests RQ# and write pointers WP# output from the host, commands CMD# for performing the requests RQ#. , and the execution order of the commands CMD# may be adjusted according to the operating states of dies in which the commands CMD# are to be executed. That is, the command manager 520 may queue the commands CMD# according to the operating states of dies included in the storage device regardless of the order of the write pointers WP#. For example, the command manager 520 may check idle dies and dies in operation, and change the execution order of commands so that commands that can be executed on the idle dies have a higher priority. In addition, the command manager 520 may change the execution order of the commands in various ways.

The zone management unit 500 temporarily stores the commands CMD# output from the command management unit 520 and controls the order of the commands CMD# according to the zone ID Zid and the write pointers WP#. can be adjusted again. When a zone ID Zid in which all commands CMD# corresponding to a set write size are generated, the zone management unit 500 sends commands CMD# of the zone ID Zid to the memory interface may be transmitted to 540 . Here, the commands CMD# may be program commands.

The memory interface 540 may include a plurality of output buffers B1 to Bp for storing the commands CMD output from the zone management unit 500 for each zone ID Zid#. For example, the output buffers B1 to Bp may correspond to the zone IDs Zid# 1:1. The memory interface 540 may output the physical block addresses PBA# and commands CMD# corresponding to the write pointers WP# to the die corresponding to the zone ID Zid#.

7 is a view for explaining a zone management unit according to an embodiment of the present invention.

Referring to FIG. 7 , the zone manager 500 may include a write queue 710 and a queue controller 720 .

The write queue 710 is a queue buffer for temporarily storing the commands CMD# output from the command manager (520 in FIG. 6 ), a zone ID and a write pointer respectively corresponding to the commands CMD#. buffer; 711). The order of the zone IDs and write pointers of the commands CMD# input to the queue buffer 711 may be discontinuous.

The queue controller 720 may include temporary buffers 721 for storing the commands CMD# output from the write queue 710 for each zone ID and each write pointer. The queue controller 720 may sequentially store the commands CMD# in the temporary buffers 721 according to the zone ID and the write pointer. The queue controller 720 may output the commands CMD# stored in the temporary buffer when the temporary buffer with all the set sizes is filled.

8 is a diagram for explaining an operation of a zone management unit according to an embodiment of the present invention.

Referring to FIG. 8 , when commands CMD# are input, the zone management unit 500 generates commands CMD# and zone IDs Zid# corresponding to the commands CMD# in the order in which they are input. The write pointers WP# may be stored in the queue buffer 711 . For example, it is assumed that memory blocks included in the storage device are logically divided into five zones, five zone IDs are set, and five write pointers are assigned to each zone ID. That is, the zone ID Zid# may include the first to fifth zone IDs Zid1 to Zid5, and different light pointers WP to each of the first to fifth zone IDs Zid1 to Zid5. #) can be assigned.

In FIG. 8 , the number of commands in the queue buffer 711 indicates the order in which they are input to the queue buffer 711 . For example, the first command CMD01 represents a command first input to the queue buffer 711 . A first zone ID Zid1 and a first write pointer WP01 may be allocated to the first command CMD01. In this way, first to twenty-third commands CMD01 to CMD23 may be sequentially input to the queue buffer 711 . However, the write pointers allocated to the first to twenty-third commands CMD01 to CMD23 are discontinuous differently from the order in which the commands are input. This means that the order of the commands requested by the host has changed. For example, since the first to fourth write pointers WP01 to WP04 are assigned to the first to fourth commands CMD01 to CMD04, the order of the first to fourth commands CMD01 to CMD04 is same order as requested. Since the eighth write pointer WP08 is assigned to the fifth command CMD05 input after the fourth command CMD04, the fifth command CMD05 is discontinuous from the fourth command CMD04, which is CMD05) indicates that the order requested by the host is different.

The queue controller 720 may store the commands CMD# output from the write queue 710 in temporary buffers TB1 to TB5 classified according to the zone ID Zid#. For example, each of the first to fifth temporary buffers TB1 to TB5 may include sub-buffers for respectively storing a set number of commands CMD#. For example, when the first temporary buffer TB1 is allocated with a larger storage capacity than that of the second to fifth temporary buffers TB2 to TB5, the first temporary buffer TB1 is the first temporary buffer TB1_1 and a first_2 temporary buffer TB1_2. The first_1 temporary buffer TB1_1 and the first_2 temporary buffer TB1_2 may be allocated to the first zone ID Zid1, and the second to fifth temporary buffers TB2 to TB5 are the second to fifth zone IDs. They may be assigned to each of the fields Zid2 to Zid5. The queue controller 720 selects a temporary buffer according to the zone ID Zid# of the command CMD# stored in the queue buffer 711, and writes the command CMD# from among the sub-buffers included in the selected temporary buffer. After selecting one sub-buffer according to the pointer WP#, the command CMD# may be stored in the selected sub-buffer.

For example, when the start pointer SP of the first_1 temporary buffer TB1_1 is set to 01 and the start pointer SP of the first_2 temporary buffer TB_1_2 is set to 06, the first_1 temporary buffer TB1_1 has The first, second, third, fourth, and seventh commands CMD01, CMD02, CMD03, CMD04, CMD07 to which the first to fifth write pointers WP01 to WP05 are allocated may be stored, and the first to fifth write pointers WP01 to WP05 may be stored. The eighth, ninth, fifth, sixth and twelfth commands CMD08, CMD09, CMD05, CMD06, CMD12 to which the sixth to tenth write pointers WP06 to WP10 are allocated to the 1_2 temporary buffer TB1_2. This can be saved. Here, since the first write pointer WP01 designated as the start pointer SP 01 is allocated to the first sub-buffer of the first_1 temporary buffer TB1_1, the first sub-buffer to which the first write pointer WP01 is allocated The first command CMD01 is stored, and the eighth command CMD08 of the sixth write pointer WP06 to which the start pointer SP 06 is designated is stored in the first sub-buffer of the first_2 temporary buffer TB1_2.

For example, when the tenth command CMD10 stored in the queue buffer 711 is output from the write queue 710 , the tenth command CMD10 includes the third zone ID Zid3 and the sixteenth write pointer WP16 . Since is allocated, the third temporary buffer TB3 to which the third zone ID Zid3 is allocated may be selected from among the first to fifth temporary buffers TB1 to TB5. Since the start pointer SP of the third temporary buffer TB3 is 16, the tenth command CMD10 to which the 16th write pointer WP16 is allocated may be stored in the sub-buffer corresponding to the start pointer SP 16 . .

The first to twenty-third commands CMD01 to CMD23 temporarily stored in the queue buffer 711 in the above-described manner may be stored in the temporary buffers 721 according to the zone ID and the write pointer.

When a temporary buffer in which all commands are filled in sub-buffers of the first to fifth temporary buffers TB1 to TB5 occurs, the queue controller 720 may output commands stored in the corresponding temporary buffer. For example, first, second, third, fourth, and seventh commands in which first to fifth write pointers WP01 to WP05 are allocated to sub-buffers included in the first_1 temporary buffer TB1_1 When (CMD01, CMD02, CMD03, CMD04, CMD07) are all stored, the queue controller 720 stores the first, second, third, fourth and seventh commands CMD01, CMD02, CMD03, CMD04, CMD07) can be output. That is, according to the first to fifth write pointers WP01 to WP05, the first, second, third, fourth, and seventh commands CMD01, CMD02, CMD03, CMD04, CMD07 are executed in the order requested by the host. can be rearranged. When all of the sixth to tenth write pointers WP06 to WP10 are stored in the sub-buffers included in the first_2 temporary buffer TB1_2, the queue controller 720 controls the eighth and tenth write pointers stored in the first_2 temporary buffer TB1_2. The ninth, fifth, sixth, and twelfth commands CMD08, CMD09, CMD05, CMD06, and CMD12 may be output. When all of the commands CMD# are stored in the second and third temporary buffers TB2 and TB3 in this way, the queue controller 720 outputs the commands of the temporary buffer filled with the commands CMD# first. can

If the commands CMD# are not all filled in the fourth and fifth temporary buffers TB4 and TB5, the queue controller 720 controls the fourth and fifth temporary buffers until all of the commands CMD# are filled. The output of the commands CMD# stored in the TB4 and TB5 may be held. For example, the twenty-first to twenty-fifth write pointers WL21 to WP25 are allocated to the fourth temporary buffer TB4, and among them, the twenty-third and twenty-fifth write pointers corresponding to the twenty-first and twenty-second write pointers WP21 and WP22. When only the eighteenth commands CMD23 and CMD18 are stored, the commands CMD# to which the remaining twenty-third to twenty-fifth write pointers WP23 to WP25 are allocated are not stored. Continuous data cannot be programmed into the mapped memory areas. Accordingly, the queue controller 720 may delay output of commands until all commands are filled in the fourth temporary buffer TB4 .

When the fifth temporary buffer TB5 is filled with commands earlier than the fourth temporary buffer TB4 , the queue controller 720 may output the commands stored in the fifth temporary buffer TB5 .

9 is a diagram for explaining a memory interface according to an embodiment of the present invention.

9 and 8 , the memory interface 540 may include first to fifth output buffers B1 to B5 divided by first to fifth zone IDs Zid1 to Zid5. The first output buffer B1 may store first to fifth physical block addresses PBA01 to PBA05 mapped to the first to fifth write pointers WP01 to WP05, respectively. The first to fifth physical block addresses PBA01 to PBA05 may be information searched in the system buffer ( 510 of FIG. 5 ) by the command manager ( 520 of FIG. 5 ).

When the first zone ID Zid1 is assigned to the first output buffer B1 in the memory interface 540 , the commands CMD output from the first_1 temporary buffer TB1_1 or the first_2 temporary buffer TB1_2 are Physical block addresses PBA# of the allocated write pointers WP01 to WP05 or WP06 to WP10 may be temporarily stored in the first output buffer B1 and then output. The memory interface 540 stores first to fifth physical block addresses PBA01 to PBA05 mapped to the first to fifth write pointers WP01 to WP05, respectively, and then includes a first zone ID Zid1 and The command CMD may be transmitted to the dies included in the storage device according to the first to fifth physical block addresses PBA01 to PBA05.

Since stored commands are not output from temporary buffers in which some commands are not stored, such as the fourth and fifth temporary buffers TB4 and TB5, the 21st , even if commands to which the 22nd or 26th write pointers WP21, WP22, or WP26 are allocated are stored, the fourth output buffer B4 corresponding to the fourth temporary buffer TB4 and the fifth temporary buffer TB5 Physical block addresses PB# are not stored in the fifth output buffer B5 corresponding to .

10 is a diagram for explaining an operation of a controller accessing dies.

Referring to FIG. 10 , the controller 1200 controls the dies selected according to the physical block addresses PBA# stored in the memory interface 540 and the zone ID Zid# corresponding to the physical block addresses PBA#. physical block addresses (PBA#) and a command (CMD) to

Based on the above description, a method in which the area management unit rearranges the output order of commands will be described in detail as follows.

11 to 18B are diagrams for sequentially explaining the operation of the memory system according to the first embodiment of the present invention.

Referring to FIG. 11 , when commands CMD# are input to the write queue 710 , the write queue 710 displays the commands CMD# and zone IDs Zid1 assigned to the commands CMD#. ~Zid5) and the write pointers WP01 to WP25 may be stored in the queue buffer 711 in the order in which they are input. In the first embodiment, a case in which the first to 22nd commands CMD01 to CMD22 are input is described as an example, but if there is an empty area in the queue buffer 711, the commands CMD# are continuously input it might be All of the first to twenty-second commands CMD01 to CMD22 may be program commands, and the numbers '01 to 22' of the commands CMD# indicate the order in which the commands CMD# are input.

Since the first zone ID Zid1 and the first to fourth write pointers WP01 to WP04 are allocated to the first to fourth commands CMD01 to CMD04, the first zone ID Zid1 among the temporary buffers 721 is The first temporary buffer TB1 corresponding to Zid1) may be selected. The first temporary buffer TB1 may include first_1 and first_2 temporary buffers TB1_1 and TB1_2 . Since the start pointer SP of the first_1 temporary buffer TB1_1 is 01, the first command CMD01 to which the first write pointer WP01 is assigned is input to the first sub-buffer of the first_1 temporary buffer TB1_1, The second, third, and fourth commands CMD02, CMD03, and CMD04 to which the second to fourth write pointers WP02 to WP04 are respectively allocated may be sequentially input to the remaining sub-buffers.

Referring to FIG. 12 , although the first zone ID Zid1 is assigned to the fifth command CMD05 input after the fourth command CMD04, the eighth write pointer WP08 is not the fifth write pointer WP05. Therefore, the order of the light pointers is discontinuous. Accordingly, the queue controller 720 may input the fifth command CMD05 to which the eighth write pointer WP08 is assigned to the third sub-buffer from the first_2 temporary buffer TB1_2 having the start pointer SP of 06. . Since the sixth command CMD06 to which the ninth write pointer WP09 of the first zone ID Zid1 is assigned is input next to the eighth write pointer WP08, the sixth command to which the ninth write pointer WP09 is assigned is input. (CMD06) may be input to the fourth sub-buffer of the first_2 temporary buffer TB1_2.

Referring to FIG. 13A , since the fifth write pointer WP05 of the first zone ID Zid1 is allocated to the seventh command CMD07 input after the sixth command CMD06, the order of the write pointers is discontinuous. Accordingly, the queue controller 720 may input the seventh command CMD07 to which the fifth write pointer WP05 is assigned to the fifth sub-buffer in the first_1 temporary buffer TB1_1 . Accordingly, first, second, third, fourth and seventh commands ( ) to which first to fifth write pointers WP01 to WP05 are respectively allocated to all sub-buffers of the first_1 temporary buffer TB1_1 . CMD01, CMD02, CMD03, CMD04, CMD07) can be filled. Since all of the five sub-buffers, which are the storage size for programming continuous data, are filled, the queue controller 720 determines where the first zone ID Zid1 and the first to fifth write pointers WP01 to WP05 are allocated. The first, second, third, fourth, and seventh commands CMD01, CMD02, CMD03, CMD04, and CMD07 may be output. In the present embodiment, five storage sizes for programming continuous data are described, but since this is an example for describing the present embodiment, the storage size may be changed according to the memory system. Since the sub-buffers of the 1st_2 temporary buffer TB1_2 are not completely filled with commands, the first, second, and When the third, fourth, and seventh commands CMD01, CMD02, CMD03, CMD04, and CMD07 are output, the eighth and ninth write pointers WP08 and WP09 are allocated from the first_2 temporary buffer TB1_2. The fifth and sixth commands CMD05 and CMD06 are not output.

Referring to FIG. 13B , the commands CMD for the first zone ID Zid1 output from the zone manager 500 may be transmitted to the memory interface 540 . The memory interface 540 provides first to fifth physical block addresses mapped to the first to fifth write pointers WP01 to WP05 in the first output buffer B1 corresponding to the first zone ID Zid1. PBA01 to PBA05 may be stored, and first to fifth physical block addresses PBA01 to PBA05 and a command CMD may be transmitted to the storage device 1100 . The storage device 1100 may perform a program operation on the dies corresponding to the zone ID according to the physical block addresses PBA# and the command CMD.

Referring to FIG. 14 , since the first, second, third, fourth and seventh commands CMD01 , CMD02 , CMD03 , CMD04 and CMD07 stored in the first_1 temporary buffer TB1_1 are output (see FIG. 13A ) The first_1 temporary buffer TB1_1 may be emptied. Since the first zone ID Zid1 and the sixth write pointer WP06 are assigned to the eighth command CMD08 input after the seventh command CMD07, the queue controller 720 sets the start pointer SP to 06. An eighth command CMD08 to which the sixth write pointer WP06 is allocated may be input to the first sub-buffer in the first_2 temporary buffer TB1_2. Since the first zone ID Zid1 and the seventh write pointer WP07 are input to the ninth command CMD09 input after the eighth command CMD08, the ninth command ( ) to which the seventh write pointer WP07 is assigned. CMD09) may be input to the second sub-buffer of the first_2 temporary buffer TB1_2.

Referring to FIG. 15 , since the third zone ID Zid3 and the 16th write pointer WP16 are assigned to the tenth command CMD10 input after the ninth command CMD09, the queue controller 720 sets the start pointer The tenth command CMD10 to which the sixteenth write pointer WP16 is allocated may be input to the first sub-buffer of the third temporary buffer TB3 having an SP of 16 . Since the 17th write pointer WP17 of the third zone ID Zid3 is queued after the 16th write pointer WP16, the eleventh command CMD11 to which the 17th write pointer WP17 is assigned is transferred to the third temporary buffer ( It can be input to the second sub-buffer of TB3).

Referring to FIG. 16A , since the tenth write pointer WP10 of the first zone ID Zid1 is allocated to the twelfth command CMD12 input after the eleventh command CMD11, the queue controller 720 performs the first_2 The twelfth command CMD12 to which the tenth write pointer WP10 is allocated may be input to the fifth sub-buffer of the temporary buffer TB1_2 . Accordingly, the eighth, ninth, fifth, sixth and twelfth commands CMD08 to which the sixth to tenth write pointers WP06 to WP10 are allocated to all sub-buffers of the first_2 temporary buffer TB1_2. , CMD09, CMD05, CMD06, CMD12) can be filled. Since all of the five sub-buffers, which are the storage size for programming continuous data, are filled, the queue controller 720 receives the sixth to tenth write pointers WP06 to WP10 in the first zone ID Zid1. The eighth, ninth, fifth, sixth, and twelfth commands CMD08, CMD09, CMD05, CMD06, and CMD12 may be output.

Referring to FIG. 16B , the eighth, ninth, fifth, sixth and twelfth commands CMD08, CMD09, CMD05, CMD06, CMD12 for the first zone ID Zid1 output from the zone management unit 500 may be transmitted to the memory interface 540 . The memory interface 540 stores the eighth, ninth, fifth, sixth and twelfth commands CMD08, CMD09, CMD05, CMD06, CMD12 in the first output buffer B1 corresponding to the first zone ID Zid1. ) and store the sixth to tenth physical block addresses PBA06 to PBA10 mapped to the sixth to tenth write pointers WP06 to WP10 allocated to ), and the sixth to tenth physical block addresses PBA06 to PBA06 to According to PBA10), the eighth, ninth, fifth, sixth, and twelfth commands CMD08, CMD09, CMD05, CMD06, and CMD12 may be transmitted to the storage device 1100 . The storage device 1100 provides physical block addresses (PBA#) and eighth, ninth, fifth, sixth and twelfth commands (CMD08, CMD09, CMD05, CMD06, CMD12) in the dies corresponding to the zone ID. program operation can be performed according to the

Referring to FIG. 16C , the eighth, ninth, fifth, sixth and twelfth commands in which sixth to tenth write pointers WP06 to WP10 are allocated to all sub-buffers of the first_2 temporary buffer TB1_2. When the fields CMD08, CMD09, CMD05, CMD06, and CMD12 are filled but the first output buffer B1 of the memory interface 540 is not emptied, the area management unit 500 performs the eighth, ninth, fifth, and fourth Outputs of the sixth and twelfth commands CMD08, CMD09, CMD05, CMD06, and CMD12 may be delayed. For example, if the first to fifth physical block addresses PBA01 to PBA05 corresponding to previous commands are stored in the first output buffer B1 of the memory interface 540 , the area management unit 500 may The eighth, ninth, fifth, sixth and twelfth commands CMD08, CMD09, CMD05, to which the sixth to tenth write pointers WP06 to WP10 are allocated until the first output buffer B1 is reset. CMD06, CMD12) output can be delayed. When the first output buffer B1 is reset, as described with reference to FIG. 16B , the zone management unit 500 controls the eighth, ninth, fifth, and eighth write pointers WP06 to WP10 to which the sixth to tenth write pointers WP06 to WP10 are allocated. The sixth and twelfth commands CMD08, CMD09, CMD05, CMD06, and CMD12 may be output.

Referring to FIG. 17A , since the eighth, ninth, fifth, sixth and twelfth commands CMD08, CMD09, CMD05, CMD06, and CMD12 stored in the first_2 temporary buffer TB1_2 are output (refer to FIG. 16A ) The first_1 temporary buffer TB1_1 may be emptied. Since the second zone ID Zid2 and the eleventh to fifteenth write pointers WP11 to WP15 are assigned to the thirteenth to seventeenth commands CMD13 to CMD17 input after the twelfth command CMD12, the queue controller In 720, the thirteenth, fourteenth, fifteenth, and thirteenth write pointers WP11 to WP15 are allocated to sub-buffers of the second temporary buffer TB2 whose start pointer SP is 11. The sixteenth and seventeenth commands CMD13, CMD14, CMD15, CMD16, and CMD17 may be sequentially input. Accordingly, the thirteenth, fourteenth, fifteenth, sixteenth and seventeenth commands CMD13 to which the eleventh to fifteenth write pointers WP11 to WP15 are allocated to all sub-buffers of the second temporary buffer TB2 . , CMD14, CMD15, CMD16, CMD17) can be filled. Since all of the five sub-buffers, which are the storage size for programming continuous data, are filled, the queue controller 720 determines where the eleventh to fifteenth write pointers WP11 to WP15 are allocated in the second zone ID Zid2. The thirteenth, fourteenth, fifteenth, sixteenth, and seventeenth commands CMD13, CMD14, CMD15, CMD16, and CMD17 may be output.

Referring to FIG. 17B , the thirteenth, fourteenth, fifteenth, sixteenth, and eleventh to fifteenth write pointers WP11 to WP15 and the second zone ID Zid2 output from the zone management unit 500 are allocated. The seventeenth commands CMD13 , CMD14 , CMD15 , CMD16 , and CMD17 may be transmitted to the memory interface 540 . The memory interface 540 provides eleventh to fifteenth physical block addresses mapped to the eleventh to fifteenth write pointers WP11 to WP15 in the second output buffer B2 corresponding to the second zone ID Zid2. PBA11 to PBA15), and the thirteenth, fourteenth, fifteenth, sixteenth and seventeenth commands CMD13, CMD14, CMD15, CMD16, CMD17 according to the eleventh to fifteenth physical block addresses PBA11 to PBA15. ) to the storage device 1100 . The storage device 1100 provides physical block addresses (PBA#) and thirteenth, fourteenth, fifteenth, sixteenth and seventeenth commands (CMD13, CMD14, CMD15, CMD16, CMD17) in the dies corresponding to the zone ID. program operation can be performed according to the

Referring to FIG. 18A , the eighteenth to twenty-second commands CMD18 to CMD22 input after the seventeenth command CMD17 include a fourth zone ID Zid4 and the twenty-first to twenty-fifth write pointers WP21 to WP25. is allocated, the queue controller 720 controls the 18th and 25th write pointers WP21 to WP25 in which the 21st to 25th write pointers WP21 to WP25 are allocated to the sub-buffers of the fourth temporary buffer TB4 having the start pointer SP of 21. The 19th, 20th, 21st, and 22nd commands CMD18, CMD19, CMD20, CMD21, and CMD22 may be sequentially input. Accordingly, the 18th, 19th, 20th, 21st and 22nd commands CMD18 to which the 21st to 25th write pointers WP21 to WP25 are allocated to all sub-buffers of the fourth temporary buffer TB4. , CMD19, CMD20, CMD21, CMD22) can be filled. Since all five sub-buffers, the storage size of which can be programmed with continuous data, are filled, the queue controller 720 gives priority to the fourth zone ID (Zid4) over the third zone ID (Zid3), The 18th, 19th, 20th, 21st, and 22nd commands CMD18, CMD19, CMD20, CMD21, CMD22 to which the 4 zone ID Zid4 is allocated may be output.

Referring to FIG. 18B , 18th, 19th, 20th, 21st, and 18th to which the fourth zone ID Zid4 output from the zone management unit 500 and the 21st to 25th write pointers WP21 to WP25 are allocated. The twenty-second commands CMD18 , CMD19 , CMD20 , CMD21 , and CMD22 may be transmitted to the memory interface 540 . The memory interface 540 provides the twenty-first to twenty-fifth physical block addresses mapped to the twenty-first to twenty-fifth write pointers WP21 to WP25 in the fourth output buffer B4 corresponding to the fourth zone ID Zid4. PBA21 to PBA25 are stored, and the 18th, 19th, 20th, 21st and 22nd commands CMD18, CMD19, CMD20, CMD21, CMD22 according to the 21st to 25th physical block addresses PBA21 to PBA25. ) to the storage device 1100 . The storage device 1100 may perform a program operation on the dies corresponding to the zone ID according to the physical block addresses PBA# and the command CMD.

19A and 19B are diagrams for explaining an operation of a memory system according to a second embodiment of the present invention.

Referring to FIG. 19A , even when a temporary buffer in which all commands are filled occurs, the zone manager 500 may wait without outputting the write pointers WP# before an output request is received from the host 2000 . For example, when all commands are filled in the first, first, first, second, second, and fourth temporary buffers TB1_1 , TB1_2 , TB2 and TB4 , the zone manager 500 determines whether an output request is received from the host 2000 . can be checked. If there is no output request received, the area management unit 500 may hold the output of the commands.

Referring to FIG. 19B , when the host 2000 outputs an output request RQ_out, the area management unit 500 responds to the output request RQ_out with first_1, first_2, second, and fourth temporary buffers TB1_1 , TB1_2, TB2, TB4 may output the commands CMD.

20A and 20B are diagrams for explaining an operation of a memory system according to a third embodiment of the present invention.

Referring to FIG. 20A , some light pointers may include a control key CON_KEY. The control key CON_KEY may be an index designating a write pointer that can be output only in response to an output request from the host 2000 . The control key CON_KEY may be designated by the host 2000 or by a command manager ( 520 of FIG. 5 ) included in the controller. Accordingly, the normal write pointers may be configured only with the logical block address LBA, and the write pointers selected by the host 2000 or the command manager 520 may be configured with the control key CON_KEY and the logical block address LBA. can be configured.

When a temporary buffer in which all commands are filled occurs, the zone management unit 500 may immediately output the commands included in the temporary buffer. It is possible to hold the output of commands until an output request is received. For example, when all commands are filled in the first_1, first_2, second, and fourth temporary buffers TB1_1, TB1_2, TB2, and TB4, the area manager 500 may It may be checked whether a command to which a write pointer to which the control key CON_KEY is set is assigned from among the commands stored in the 4 temporary buffers TB1_1, TB1_2, TB2, and TB4 is included. When it is determined that only commands to which normal write pointers are assigned are stored in the second and fourth temporary buffers TB2 and TB4, the zone manager 500 stores commands stored in the second and fourth temporary buffers TB2 and TB4. (CMD) can be printed immediately. The zone management unit 500 sets the control key CON_KEY among the commands to which the write pointers WP01 to WP10 stored in the first_1 and first_2 temporary buffers TB1_1 and TB1_2 are assigned, the write pointers WP03 to WP06. If it is determined that the assigned commands are stored, it may be checked whether an output request has been received from the host 2000 . If there is no output request received, the zone management unit 500 holds the output of the commands CMD stored in the first and second temporary buffers TB1_1 and TB1_2 and to which the write pointers WP01 to WP10 are assigned. can

Referring to FIG. 20B , when the host 2000 outputs an output request RQ_out, the area management unit 500 responds to the output request RQ_out and stores commands stored in the first and second temporary buffers TB1_1 and TB1_2. CMDs can be output.

21 is a view showing a memory card system to which the controller of the present invention is applied.

Referring to FIG. 21 , the memory card system 3000 includes a controller 3100 , a memory device 3200 , and a connector 3300 .

The controller 3100 is connected to the memory device 3200 . The controller 3100 is configured to access the memory device 3200 . For example, the controller 3100 may be configured to control a program, read, or erase operation of the memory device 3200 or to control a background operation. The controller 3100 may have the same configuration as the controller 1200 illustrated in FIG. 5 . The controller 3100 is configured to provide an interface between the memory device 3200 and a host. The controller 3100 is configured to drive firmware for controlling the memory device 3200 .

For example, the controller 3100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error correction unit. have.

The controller 3100 may communicate with an external device through the connector 3300 . The controller 3100 may communicate with an external device (eg, a host) according to a specific communication standard. Illustratively, the controller 3100 is a USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment) , Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, NVMe It is configured to communicate with an external device through at least one of various communication standards, such as. For example, the connector 3300 may be defined by at least one of the various communication standards described above.

Exemplarily, the memory device 3200 may include electrically erasable and programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and STT-MRAM. It may be composed of various non-volatile memory devices such as (Spin Transfer Torque - Magnetic RAM).

The controller 3100 and the memory device 3200 may be integrated into one semiconductor device to constitute a memory card. For example, the controller 3100 and the memory device 3200 are integrated into one semiconductor device, such as a personal computer memory card international association (PCMCIA), a compact flash card (CF), and a smart media card (SM, SMC). , memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro, eMMC), SD cards (SD, miniSD, microSD, SDHC), universal flash storage (UFS), etc.

22 is a view showing a solid state drive (SSD) system to which the controller of the present invention is applied.

Referring to FIG. 22 , the SSD system 4000 includes a host 4100 and an SSD 4200 . The SSD 4200 transmits and receives a signal SIG to and from the host 4100 through the signal connector 4001 , and receives power PWR through the power connector 4002 . The SSD 4200 includes a controller 4210 , a plurality of flash memories 4221 to 422n , an auxiliary power supply 4230 , and a buffer memory 4240 .

According to an embodiment of the present invention, the controller 4210 may perform the function of the controller 1200 described with reference to FIG. 5 .

The controller 4210 may control the plurality of flash memories 4221 to 422n in response to a signal received from the host 4100 . For example, the signals may be signals based on an interface between the host 4100 and the SSD 4200 . For example, signals can be USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial- Interfaces such as ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, NVMe, etc. It may be a signal defined by at least one of them.

The auxiliary power supply 4230 is connected to the host 4100 through the power connector 4002 . The auxiliary power supply 4230 may receive a power voltage input from the host 4100 and may be charged. The auxiliary power supply 4230 may provide a power voltage of the SSD 4200 when the power supply from the host 4100 is not smooth. For example, the auxiliary power supply 4230 may be located within the SSD 4200 or may be located outside the SSD 4200 . For example, the auxiliary power supply 4230 is located on the main board and may provide auxiliary power to the SSD 4200 .

The buffer memory 4240 operates as a buffer memory of the SSD 4200 . For example, the buffer memory 4240 may temporarily store data received from the host 4100 or data received from the plurality of flash memories 4221 to 422n, or metadata of the flash memories 4221 to 422n. For example, a mapping table) may be temporarily stored. The buffer memory 4240 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, or non-volatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM.

1000: memory system 1100: storage device
1200: controller 2000: host
500: zone management unit 510: system buffer
520: command management unit 530: host interface
540: memory interface 710: light cue
711: queue buffer 720: queue controller
721: temporary buffers

Claims (20)

a light queue configured to queue commands including a zone ID and a light pointer in the order in which they are entered; and
a queue controller configured to allocate temporary buffers to zone IDs of the commands, and to store the commands output from the write queue in the temporary buffers divided according to zone IDs,
The queue controller is
a controller configured to output the commands stored in a temporary buffer filled with a set storage size among the temporary buffers.
According to claim 1,
The zone IDs are indices allocated to memory areas separated by consecutive logical block addresses,
wherein the write pointers are logical block addresses selected after the selected logical block address within the selected zone ID.
The method of claim 1, wherein the light queue comprises:
and a queue buffer configured to temporarily store the commands.
According to claim 1, wherein the queue controller,
and select the temporary buffer according to the zone ID of the commands output from the write queue, and store the commands in the selected temporary buffer according to the order of the write pointers.
5. The method of claim 4,
and each of the temporary buffers includes sub-buffers for storing the commands according to the write pointer.
6. The method of claim 5,
and a command to which a write pointer designated as a start pointer is assigned is stored in a first sub-buffer among the sub-buffers included in each of the temporary buffers.
The method of claim 6, wherein the queue controller comprises:
a controller configured to store the commands in the sub-buffers according to the write pointers.
The method of claim 5, wherein the queue controller comprises:
hold the output of the commands stored in a temporary buffer including at least one empty sub-buffer among the temporary buffers;
and output the commands stored in the selected temporary buffer when the commands are stored in all the sub-buffers included in the temporary buffer selected from among the temporary buffers.
According to claim 1,
a command management unit configured to convert requests output from a host into the commands, change an execution order of the commands according to a state of a storage device, and transmit the changed commands to the write queue;
a system buffer configured to store mapping information of physical block addresses and logical block addresses of dies included in the storage device, and mapping information between the logical block addresses and the zone ID; and
and a memory interface configured to store the physical block addresses mapped to the write pointers output from the queue controller, and to transmit the mapped physical block addresses and the command to the dies corresponding to the zone ID controller that does.
10. The method of claim 9, wherein the memory interface,
A controller including output buffers corresponding to each of the zone IDs on a one-to-one basis.
The method of claim 9, wherein the command management unit,
When the write pointers are output from the queue controller, the physical block addresses mapped to the write pointers are searched using the map information stored in the system buffer, and the searched physical block addresses are stored in the memory A controller configured to store to the output buffers of an interface.
The method of claim 11 , wherein the queue controller comprises:
When the physical block addresses are stored in an output buffer corresponding to a selected zone ID from among the output buffers, and all of the write pointers are stored in sub-buffers included in a temporary buffer corresponding to the selected zone ID,
a controller configured to delay output of the write pointers stored in the sub-buffers until the output buffer is emptied.
a storage device comprising dies for storing data; and
a controller configured to generate commands in response to requests output from a host and to queue the commands according to states of the dies;
The controller is
The dies are divided into zone IDs to manage the storage device, and, regardless of the order of the commands queued during program operation, priority is given to a zone ID in which all write pointers are filled among the zone IDs, and the priority is given to the zone ID having the priority. A memory system configured to output the commands assigned to a zone ID.
14. The method of claim 13,
and each of the dies includes a plurality of memory blocks for storing the data.
The method of claim 13, wherein the controller,
a command manager configured to convert the requests output from the host into the commands and change an execution order of the commands according to a state of the storage device;
a system buffer configured to store a mapping table of physical block addresses, logical block addresses, and zone IDs of the dies;
When the order of the write pointers corresponding to the command is discontinuous during the program operation, the queuing of the commands is adjusted so that the order of the write pointers assigned to the same zone ID is continuous, and the temporary buffer is filled with all the commands. a zone management unit configured to give priority to the zone ID when . and
and a memory interface configured to store the commands output from the area manager and the physical block addresses corresponding to the commands, and transmit the mapped physical block addresses and the commands to the dies; .
The method of claim 15, wherein the area management unit,
a write queue to which the zone IDs and the write pointers are allocated and configured to queue the commands output from the command management unit in the order in which they are input; and
a memory including a queue controller configured to store the commands in temporary buffers corresponding to the zone IDs in the order stored in the write queue, and output the commands stored in a temporary buffer filled with a set storage size among the temporary buffers; system.
17. The method of claim 16,
The temporary buffers include sub-buffers to which write pointers are allocated,
The commands are stored in the sub-buffers corresponding to the write pointers.
18. The method of claim 17,
When the queue controller includes temporary buffers in which all the commands are filled and temporary buffers in which the write pointers are not filled,
and the queue controller gives priority to temporary buffers filled with the commands, and outputs the commands stored in the temporary buffers having the priority to the memory interface.
The method of claim 13, wherein the controller,
When write pointers including a control key are included among the write pointers, commands assigned to the write pointers including the control key are output to a memory interface in response to an output request from the host;
Commands assigned to write pointers that do not include the control key are output to the memory interface regardless of the output request.
A command management unit configured to generate commands corresponding to requests received from the host, allocate write pointers to the commands according to the order in which the commands are generated, and queue the commands according to a state of a storage device in which data is stored ;
a write queue configured to temporarily store the queued commands;
Temporary buffers separated by zone ID; and
and a zone manager configured to store the commands output from the write queue in the temporary buffers according to the zone ID and the order of the write pointers, and output the commands in the temporary buffer filled with a set size.

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