KR20220090900A - Error detecting apparatus - Google Patents

Abstract

A failure detection apparatus according to an embodiment of the present invention includes a state memory circuit that, upon receiving a failure occurrence signal from the failure detection unit, switches to a failure state and outputs a power input cutoff signal to a cutoff unit that cuts off the power supply, wherein the state The memory circuit maintains the above fault state until it is initialized.

Description

Error detecting apparatus

The present invention relates to a failure detection apparatus, and more particularly, to a failure detection apparatus that maintains a failure state until initialized using a state memory circuit.

Electrical devices such as a shift-by-wire system (SBW) applied to vehicles, etc. are converted to a safe state when a failure occurs for functional safety for the electric field. In this case, when an operation is performed before the state in which a failure occurs, a problem may occur, there is a need for a technology capable of maintaining the information of the failure state.

The technical problem to be solved by the present invention is to provide a failure detection device that maintains a failure state until it is initialized using a state memory circuit.

In order to solve the above technical problem, the failure detection device according to an embodiment of the present invention converts to a failure state upon receiving a failure signal from the failure detection unit, and outputs a power input cutoff signal to the cutoff unit for cutting off the power supply and a memory circuit, wherein the state memory circuit maintains the fault state until it is initialized.

Also, the state memory circuit may be initialized by transmitting fault state information to the controller and receiving a function activation/deactivation signal from the controller.

In addition, the state memory circuit may include: a first AND gate and a second AND gate receiving the function activation/deactivation signal; an OR gate receiving the fault occurrence signal and an output signal of the first AND gate; and a NOT gate that receives and inverts the output of the OR gate, wherein the first AND gate receives the output of the OR gate together with the function activation/deactivation signal, and the second AND gate includes the function An output of the NOT gate may be input together with an activation/deactivation signal, and an output of the second AND gate may be output to the blocking unit.

In addition, when the function activation/deactivation signal is high and the failure signal is low, when the failure signal is changed to high, the output of the second AND gate is changed from high to low, and the output of the second AND gate is changed to low. The output of the second AND gate may be maintained until the function activation/deactivation signal is changed to low in a state in which the failure occurrence signal is low and is changed to high.

In addition, the state memory circuit may include: a first diode having one end connected to a function activation/deactivation signal input terminal; a second diode having one end connected to the fault occurrence signal input terminal; a third diode having one end connected to the first diode and the other end connected to an output terminal of the state memory circuit; a fourth diode and a fifth diode having one end connected to a first node between the first diode and the third diode, the other end connected to the second diode, and connected to each other in parallel; a first resistor having one end connected to the other end of the second diode; a second resistor having one end connected to the reference voltage input terminal; A gate is connected to a second node to which the second diode, the fourth diode, the fifth diode, and the first resistor are commonly connected, a source is connected to the other end of the first resistor, and a source is connected to the second resistor. FET to which the drain is connected; and a sixth diode having one end connected to the drain of the FET and the other end connected to the output terminal of the state memory circuit.

In addition, the first diode, the fourth diode, and the fifth diode have an anode connected to the first node, a cathode connected to the second node, and the third diode and the second diode connected to the second diode. The 6-diode may have an anode connected to the output terminal of the state memory circuit.

In addition, the controller may determine the current state through the fault state information, and when determining that the normal state is restored, input the function activation/deactivation signal to the state memory circuit.

In addition, the state memory circuit may receive a fault occurrence signal from the fault detection unit when overvoltage, low voltage, or overcurrent occurs at the power input terminal, and operate the blocking unit to cut off the power of the power input terminal.

In order to solve the above technical problem, a state memory circuit according to an embodiment of the present invention includes: a first AND gate and a second AND gate receiving a function activation/deactivation signal from a controller; an OR gate that receives a failure occurrence signal from a failure detection circuit for detecting a failure of an input power source and receives an output signal of the first AND gate; and a NOT gate that receives the output of the OR gate and inverts it, wherein the first AND gate receives the output of the OR gate together with the function activation/deactivation signal, and the second AND gate receives the function activation/deactivation signal An output of the NOT gate is input together with a deactivation signal, and an output of the second AND gate is output to a blocking circuit that cuts off the input power.

In addition, when the function activation/deactivation signal is high and the failure signal is low, when the failure signal is changed to high, the output of the second AND gate is changed from high to low, and the output of the second AND gate is changed to low. The output of the second AND gate may be maintained until the function activation/deactivation signal is changed to low in a state in which the failure occurrence signal is low and is changed to high.

According to embodiments of the present invention, it is possible to block the power input by detecting a fault state using a state memory circuit implemented as a logic circuit. It can return to the normal state only through a separate initialization process, thereby preventing malfunction.

1 is a block diagram of a failure detection apparatus according to an embodiment of the present invention.
2 is a block diagram of an apparatus to which a failure detection apparatus according to an embodiment of the present invention is applied.
3 is a detailed block diagram of a state memory circuit according to an embodiment of the present invention.
4 is a diagram for explaining an operation of a state memory circuit according to an embodiment of the present invention.
5 shows an implementation example of a state memory circuit according to an embodiment of the present invention.
6 is a flowchart of a failure detection method according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

However, the technical spirit of the present invention is not limited to some of the described embodiments, but may be implemented in various different forms, and within the scope of the technical spirit of the present invention, one or more of the components may be selected between the embodiments. It can be used by combining or substituted with

In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be generally understood by those of ordinary skill in the art to which the present invention belongs, unless specifically defined and described explicitly. It may be interpreted as a meaning, and generally used terms such as terms defined in advance may be interpreted in consideration of the contextual meaning of the related art.

In addition, the terminology used in the embodiments of the present invention is for describing the embodiments and is not intended to limit the present invention.

In the present specification, the singular form may also include the plural form unless otherwise specified in the phrase, and when it is described as "at least one (or more than one) of A and (and) B, C", it is combined as A, B, C It may include one or more of all possible combinations.

In addition, in describing the components of the embodiment of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only used to distinguish the component from other components, and are not limited to the essence, order, or order of the component by the term.

And, when it is described that a component is 'connected', 'coupled', or 'connected' to another component, the component is directly 'connected', 'coupled', or 'connected' to the other component. In addition to the case, it may include a case of 'connected', 'coupled', or 'connected' due to another element between the element and the other element.

In addition, when it is described as being formed or disposed on "above (above)" or "below (below)" of each component, "above (above)" or "below (below)" means that two components are directly connected to each other. It includes not only the case where they are in contact, but also the case where one or more other components are formed or disposed between two components. In addition, when expressed as "upper (upper)" or "lower (lower)", the meaning of not only an upper direction but also a lower direction based on one component may be included.

1 is a block diagram of a failure detection apparatus according to an embodiment of the present invention.

The failure detection apparatus 110 according to an embodiment of the present invention includes a state memory circuit 111 .

When the state memory circuit 111 receives a failure occurrence signal from the failure detection unit 120 , it switches to a failure state and outputs a power input cutoff signal to the cutoff unit 130 that cuts off the power supply.

More specifically, when the state memory circuit 111 receives a failure signal from the failure detection unit 120 that detects a failure of the device to which the failure detection device 110 is applied, it switches to a failure state, and sets the device according to the failure. In order to protect, a power input cutoff signal is output to the cutoff unit 130 that cuts off the power supply.

The failure detection unit 120 measures the voltage or current applied to the power input terminal 150 receiving power from the power source 200 as shown in FIG. 2 , and when an overvoltage, undervoltage, or overcurrent occurs in the power input terminal 150 , a failure occurs Generates an occurrence signal. Here, the power input terminal 150 may receive power from the power source 200 and transmit it to a device requiring power, such as a motor, a three-phase bridge operating the motor, and the controller 140 . The fault detection unit 120 transmits a fault occurrence signal generated according to the fault detection to the state memory circuit 111 . In this case, the failure detection unit 120 may transmit a failure occurrence signal to the controller 140 so that the controller 140 operates in a safe state.

The blocking unit 130 cuts off the power supply to prevent damage to the internal circuit. The blocking unit 130 may receive the power input blocking signal from the state memory circuit 111 to cut off the power at the power input terminal as shown in FIG. 2 . The cut-off unit 130 may be an input power cutoff switch, and may cut off the input power by operating according to a power manpower cutoff signal. The blocking unit 130 may be implemented as a protection IC including a protection circuit.

When the state memory circuit 111 receives a failure occurrence signal from the failure detection unit 120 , it switches to a failure state and maintains the failure state until it is initialized. The state memory circuit 111 is initialized by transmitting fault state information to the controller and receiving a function activation/deactivation signal from the controller. The state memory circuit 111 transmits the failure state information to the controller 140 so that the controller 140 is switched to a safety mode. The controller 140 may control other devices to safely operate in the safe mode, and may stop the operation. When the controller 140 operates again, it is necessary to check whether there has been a previous failure state in order to operate accordingly. The state memory circuit 111 maintains the failure state, and when the controller 140 operates again , to verify the information.

When the fault condition is released, the controller 140 may determine whether the fault is temporarily released or returned to a normal state through the status memory circuit 111 or the fault detection unit 120 . The controller ( ) may be a micro control unit (MCU) or an SBW control unit (SCU) of the SBW system.

The controller 140 may determine the current state through the failure state information, and when determining that the normal state is returned, the controller 140 may output the function activation/deactivation signal to the state memory circuit 111 . The controller 140 sends a function activation/deactivation signal to the state memory circuit in order to check the fault state, to check a situation or condition that can operate normally, and to initialize the state memory circuit 111 in a state where the normal operation is possible. Send to (111). After deactivating the function, the state memory circuit 111 may be initialized by activating the function.

In maintaining the fault state, if a D flip-flop is used instead of the state memory circuit 111, the material cost of the circuit increases, and the state must be restored through two or more GPIOs in the signal initialization process, the circuit becomes complicated, It takes up a lot of space. On the other hand, by maintaining the fault state with the state memory circuit 111, it is more efficient in cost and space constraints than in the case of using the D flip-flop.

The state memory circuit 111 may be implemented with a plurality of logic gates, and specifically, a first AND gate 111 and a second AND gate 112 receiving the function activation/deactivation signal, the failure signal and an OR gate 113 receiving the output signal of the first AND gate 111 and a NOT gate 114 receiving the output of the OR gate 113 and inverting the output signal; ) receives the output of the OR gate 113 together with the function activation/deactivation signal, and the second AND gate 112 receives the output of the NOT gate 114 together with the function activation/deactivation signal The input may be received, and the output of the second AND gate 112 may be output to the blocking unit 130 .

The state memory circuit 111 may include a plurality of logic gates including two AND gates, one OR gate, and one NOT gate, as shown in FIG. 3 , in order to maintain a fault state. The function activation/deactivation signal 121 is input to the first input terminal, the fault occurrence signal HW Fault 141 is input to the second input terminal, and the outputs Q and 131 output through the logic gates are the blocking unit 130 ) to transmit a power input cutoff signal. All. The first input terminal receives a function activation/deactivation signal from the controller 140 and may be implemented as one GPIO. General-Purpose Input/Output (GPIO) is a general-purpose input/output, digital signal pin on an integrated circuit or electrical circuit board whose operation, including input or output, can be controlled by the user at runtime. The second input terminal may receive a fault occurrence signal from a fault detection circuit that detects a fault in the input power source. When the function activation/deactivation signal 121 is high and the fault occurrence signal 141 is low, when the fault occurrence signal 141 is changed to high, the output of the second AND gate 112 changes from high to low The output of the second AND gate 112 changed to low is maintained until the function activation/deactivation signal 121 is changed to low and changed to high in a state in which the failure occurrence signal 141 is low. Here, high means High and low means Low, and may be represented by 1 and 0, respectively.

As shown in FIG. 3 , the logic table of the implemented state memory circuit 111 is shown in FIG. 4 . When the output Q 131 is high 1, it means normal, and when it is 0, it means Fault or initialization.

When the initial function is activated in the normal state, that is, when the function activation/deactivation signal 121 is high and the fault occurrence signal 141 is low, x(115), the output of the OR gate 113, has no value. , the output of the first AND gate 111 becomes low, and the output x 115 of the OR gate 113 also becomes low. The NOT gate 114 to which the low x (115) is input outputs a high. Accordingly, the high output of the function activation/deactivation signal 121 and the high output of the NOT gate 114 are input to the second AND gate 112 , and the output Q 131 is output high. It corresponds to case 3 of FIG. 4 .

Thereafter, when a failure occurs and the failure signal 141 is changed to high, x 115 , which is the output of the OR gate 113 , becomes high, and the output of the first AND gate 111 becomes high. The NOT gate 114 to which x (115), which is high, is input, outputs a low. Accordingly, the high output of the function activation/deactivation signal 121 and the output low of the NOT gate 114 are input to the second AND gate 112 , and the output Q 131 is output low. It corresponds to case 1 of FIG. 4 . At this time, the blocking unit 130 receiving the low-in output Q 131 blocks the power input to protect the entire circuit.

Since x(115) becomes high when the fault occurrence signal 141 is changed to high, the output of the first AND gate 111 is maintained high while the function activation/deactivation signal 121 is high. Accordingly, the OR gate is also held high, so that Q (131) remains low.

Thereafter, even if the failure signal 141 is changed to low, x(115), the output of the OR gate, continues to remain high, due to the characteristics of the OR gate, Q(131) continues to remain low, and the blocking unit ( 130) continues to cut off the power input. It corresponds to case 3 of FIG. 4 .

In order to supply power again, a process of initializing the state memory circuit 111 is required. That is, an initialization process of changing the function activation/deactivation signal 121 low and then high to deactivate the function is required. When the function activation/deactivation signal 121 is changed to low, the output of the first AND gate 111 is changed to low. The output x(115) of is low. Since the function activation/deactivation signal 121 is low, the output Q 131 of the second AND gate is also maintained low. It corresponds to case 5 of FIG. 4 . In addition, since the function activation/deactivation signal 121 is low, the output Q 131 of the second AND gate is also maintained low even when the fault occurrence signal 141 is high. It corresponds to case 4 of FIG.

As the function enable/disable signal 121 is changed to low, x(115) becomes low, and then, in order to activate the function, the function enable/disable signal 121 is changed to high, and the fault occurrence signal ( When 141 is low, x(115), the output of the OR gate 113, is low, the output of the first AND gate 111 is low, and the output x(115) of the OR gate 113 is low. keep The NOT gate 114 to which the low x (115) is input outputs a high. Accordingly, the high output of the function activation/deactivation signal 121 and the high output of the NOT gate 114 are input to the second AND gate 112 , and the output Q 131 is output high and operates in a normal state again. That is, it corresponds to case 3 of FIG. 4 again.

That is, the steady state-failure occurrence-failure resolution-initialization process is performed as the process of case 3-case 1-case 2-case 5-case 3 of FIG. 4 .

The logic circuit implementing the state memory circuit 111 has been described as an example, and it is of course possible to implement a logic circuit having a different structure for storing the state.

The state memory circuit 111 may be implemented with a plurality of diodes, resistors, and FETs. Specifically, as shown in FIG. 5 , one end of the first diode D1 is connected to the function activation/deactivation signal input terminal 501 , the second diode D2 has one end connected to the failure signal input terminal 502 , and one end is A third diode D3 connected to the first diode D1 and the other end connected to the output terminal 503 of the state memory circuit, one end connected between the first diode D1 and the third diode D3 A fourth diode D4 and a fifth diode D5 connected in parallel to the first node 504, the other end connected to the second diode D2, and one end of the second diode D2 A first resistor R1 connected to the other end of (D5) and a gate connected to a second node 505 to which the first resistor R1 is commonly connected, a source connected to the other end of the first resistor R1, and the second resistor R3 It may include a FET Q1 having a drain connected to the FET Q1 and a sixth diode D6 having one end connected to the drain of the FET Q1 and the other end connected to the output terminal 503 of the state memory circuit.

The first diode D1, the fourth diode D4, and the fifth diode D5 have an anode connected to the first node 504, and the second diode D2 is connected to the second node A cathode may be connected to 505 , and an anode of the third diode D3 and the sixth diode D6 may be connected to the output terminal 503 of the state memory circuit.

6 is a flowchart of a failure detection method according to an embodiment of the present invention. The detailed description of each step of FIG. 6 corresponds to the detailed description of the failure detection apparatus of FIGS. 1 to 5 , and thus the redundant description will be omitted.

When a failure occurs (601), the failure occurrence is detected and a failure occurrence signal (602) is generated. The operation for generating the fault occurrence signal is stopped (603). Thereafter, it is determined whether the failure state has returned to normal ( 604 ), and, if it has returned to normal, the controller determines whether the system is able to operate normally ( 605 ) whether it is temporarily released or returned to the normal state. If the normal operation is possible, the state memory circuit is initialized (606) and the operation is returned (607).

A person of ordinary skill in the art related to this embodiment will understand that it may be implemented in a modified form within a range that does not deviate from the essential characteristics of the above description. Therefore, the disclosed methods are to be considered in an illustrative rather than a restrictive sense. The scope of the present invention is indicated in the claims rather than the foregoing description, and all differences within the scope equivalent thereto should be construed as being included in the present invention.

110: fault detection device
111: state memory circuit
120: fault detection unit
130: blocking unit
140: controller
150: power input terminal
200: power

Claims (10)

and a state memory circuit that switches to a fault state when receiving a fault occurrence signal from the fault detection unit, and outputs a power input cutoff signal to a blocking unit that cuts off the power supply;
The failure detection device maintains the failure state until the state memory circuit is initialized. According to claim 1,
The state memory circuit,
A failure detection device initialized by transmitting failure state information to a controller and receiving a function activation/deactivation signal from the controller. 3. The method of claim 2,
The state memory circuit,
a first AND gate and a second AND gate receiving the function activation/deactivation signal;
an OR gate receiving the fault occurrence signal and an output signal of the first AND gate; and
a NOT gate that receives the output of the OR gate and inverts it;
The first AND gate is
receiving the output of the OR gate together with the function activation/deactivation signal;
The second AND gate is
receiving the output of the NOT gate together with the function activation/deactivation signal;
and an output of the second AND gate is output to the blocking unit. 4. The method of claim 3,
When the fault occurrence signal is changed to high while the function enable/disable signal is high and the fault occurrence signal is low, the output of the second AND gate is changed from high to low;
The output of the second AND gate changed to the low is,
A failure detection device maintained until the function activation/deactivation signal is changed to low in a state in which the failure occurrence signal is low and is changed to high. 3. The method of claim 2,
The state memory circuit,
a first diode having one end connected to a function activation/deactivation signal input;
a second diode having one end connected to the fault occurrence signal input terminal;
a third diode having one end connected to the first diode and the other end connected to an output terminal of the state memory circuit;
a fourth diode and a fifth diode having one end connected to a first node between the first diode and the third diode, the other end connected to the second diode, and connected to each other in parallel;
a first resistor having one end connected to the other end of the second diode;
a second resistor having one end connected to the reference voltage input terminal;
A gate is connected to a second node to which the second diode, the fourth diode, the fifth diode, and the first resistor are commonly connected, a source is connected to the other end of the first resistor, and a source is connected to the second resistor. FET to which the drain is connected; and
and a sixth diode having one end connected to the drain of the FET and the other end connected to the output terminal of the state memory circuit. 6. The method of claim 5,
The first diode, the fourth diode, and the fifth diode has an anode connected to the first node,
The second diode has a cathode connected to the second node,
The third diode and the sixth diode have an anode connected to an output terminal of the state memory circuit. 3. The method of claim 2,
The controller determines a current state through the failure state information, and when determining that the normal state is restored, the controller outputs the function activation/deactivation signal to the state memory circuit. According to claim 1,
The state memory circuit,
A failure detection device for receiving a failure signal from the failure detection unit when overvoltage, undervoltage, or overcurrent occurs at the power input terminal, and operates the cut-off unit to cut off the power to the power input terminal. a first AND gate and a second AND gate receiving a function activation/deactivation signal from a controller;
an OR gate that receives a failure occurrence signal from a failure detection circuit for detecting a failure of an input power source and receives an output signal of the first AND gate; and
a NOT gate that receives the output of the OR gate and inverts it;
The first AND gate receives the output of the OR gate together with the function activation/deactivation signal,
The second AND gate receives the output of the NOT gate together with the function activation/deactivation signal,
A state memory circuit in which an output of the second AND gate is output to a blocking circuit that cuts off the input power. 10. The method of claim 9,
When the fault occurrence signal is changed to high while the function enable/disable signal is high and the fault occurrence signal is low, the output of the second AND gate is changed from high to low;
The output of the second AND gate changed to the low is,
A state memory circuit that is maintained until the function activation/deactivation signal is changed to low in a state in which the fault occurrence signal is low, and is changed to high.

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