KR20220081503A - Liquid crystal display including conversion of digital signals - Google Patents

Abstract

Disclosed are a digital-to-analog converter, a driving device for a liquid crystal display including the same, and a liquid crystal display device. digi
The hair-to-analog converter converts a gradation voltage corresponding to a digital signal applied from the outside into a plurality of reference gradation voltages.
generated from and printed out. To this end, the half-gray pre-gray selects two half-gray voltages from among the plurality of reference gray-scale voltages.
a voltage selector and a gray voltage generator configured to generate a gray voltage from the intermediate gray voltage, wherein the gray voltage generator includes:
The grayscale voltage is generated according to a preset k bit among m bit digital signals. In addition, the halftone voltage selector
is, a first selector for selecting a first halftone voltage using a decoder of mk bits except for k bits among m bits, and
a plurality of decoders from a 1-bit decoder to a mk-1 bit decoder, and a second intermediate voltage different from the first halftone voltage.
and a second selector for selecting the grayscale voltage. In this way, the ratio provided by the second selector of the halftone voltage selector
It is not formed by one decoder corresponding to the number of bits, but by forming a plurality of decoders having a smaller number of bits.
Accordingly, it is possible to significantly reduce the number of necessary transistors.

Description

Liquid crystal display including conversion of digital signals

The present invention relates to a liquid crystal display device, and more particularly, to a digital display device included in a driving device of the liquid crystal display device.

It relates to an analog conversion device.

In accordance with the reduction in weight and thickness of personal computers and televisions, display devices are also required to be lighter and thinner.

In response to these demands, flat-type displays such as liquid crystal displays are becoming common.

The liquid crystal display device applies an electric field to a liquid crystal material having an anisotropic dielectric constant injected between two substrates, thereby

It is a display device that obtains an image signal by controlling the amount of light transmitted from the light source to the substrate.

Such a liquid crystal display is a representative among flat panel displays that are easy to carry, and among them,

TFT-LCD (Thin Film Transistor-Liquid Crystal Display) using a transistor as a switching element is mainly used.

All.

In general, in the liquid crystal display device, among a plurality of gray scale voltages generated based on a reference gray scale voltage,

A voltage corresponding to input digital data to select a gradation voltage corresponding to a gradation to be displayed through each pixel

Use a decoder that outputs

1 is a diagram schematically illustrating a decoder structure of a conventional conventional liquid crystal display device.

As shown in Fig. 1, a general decoder that outputs a voltage corresponding to 8-bit input digital data is

510(2

8

+2

7

+2

6

+2

5

+2

4

+2

3

+2

2

+2

One

) transistors. However, in this way, corresponding to the number of bits of digital data

The number of transistors included in the conventional decoder depends on the cost of implementing the liquid crystal display as well as the cost of the liquid crystal display.

There is a problem in that the implementation area increases.

The present invention has been devised to solve the above-mentioned problems of the prior art, and is a digital analog used in a liquid crystal display device.

In implementing the conversion device, the realization area of the liquid crystal display is reduced by significantly reducing the number of transistors required.

An object of the present invention is to provide a digital-to-analog conversion device that enables

In order to achieve the above object, a digital-to-analog conversion device according to the present invention converts a digital signal applied from the outside into a digital signal.

A corresponding gradation voltage is generated from the plurality of reference gradation voltages and output.

To this end, a half-gray voltage selector for selecting two half-gray voltages from among the plurality of reference gray voltages, and a half-gray voltage

and a gradation voltage generator generating a gradation voltage from the voltage, wherein the gradation voltage generator is an m-bit digital signal.

Among them, the grayscale voltage is generated according to the preset k bits.

In addition, the half-gray voltage selector is configured to perform the first half-tone before the first half gray level using a decoder of m-k bits except for k bits among m bits.

a first selector that selects a pressure, and a plurality of decoders from a 1-bit decoder to an m-k-1 bit decoder, wherein the first

and a second selector configured to select a second half-gray voltage different from the half-gray voltage.

As described above, the number of necessary transistors is greatly reduced by forming the second selection unit of the halftone voltage selection unit by a plurality of decoders having a smaller number of bits, rather than being formed by one decoder corresponding to the number of bits provided.

be able to

In this case, the second selector may further include m-k+2 serial switches, and the m-k+2 serial switches are 2-bit serial switches.

Multiple serial switches from earl switch to m-k bit serial switch, and three m-k+1 bit serial switches

can be configured.

In addition, a liquid crystal display including the digital-to-analog converter, and a driving device thereof are claimed together.

According to the present invention, in realizing a digital-to-analog converter used in a liquid crystal display, a necessary transistor

By significantly reducing the number of , it is possible to remarkably reduce the realization area of the liquid crystal display.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a schematic block diagram of an embodiment of a digital-to-analog converter according to the present invention.

In FIG. 2 , the digital-to-analog converter 100 includes a grayscale voltage selector 110 and a grayscale voltage generator 120 .

and the half-tone voltage selector 110 includes a first selector 112 and a second selector 114 again, and a gray-scale voltage generator

120 includes a data alignment block 122 and an output amplifier 124 .

The digital-to-analog converter 100 includes a plurality of gradation voltages supplied with a digital signal applied from the outside.

It is generated from the reference grayscale voltage and output. In other words, by simply selecting the gradation voltage from the reference gradation voltage,

Instead of outputting the gradation voltage, the gradation voltage is generated and outputted from the reference gradation voltage.

To this end, the halftone voltage selector 110 selects two halftone voltages from among the plurality of reference grayscale voltages.

The first selector 112 of the gray voltage selector 110 selects k bits used by the gray voltage generator 120 among the m bits applied.

The first halftone voltage is selected using a decoder of m-k bits except for the m-k bit.

The second selector 114 selects a second halftone voltage different from the first halftone voltage, and like the first selector 112 ,

It is not composed of one decoder, but a plurality of decoders from 1-bit decoder to m-k-1 bit decoder.

include

In addition, the second selector 114 includes m-k+2 serial switches together with a plurality of decoders, m-k+2 serial switches.

The switch consists of multiple serial switches from a 2-bit serial switch to an m-k bit serial switch, and three m-k+1 ratios.

It consists of a serial switch.

The grayscale voltage generator 120 generates a grayscale voltage from the halftone voltage selected by the halftone selector 110, and the data alignment block 122 is configured according to a preset k bit among m-bit digital signals applied from the outside. halftone selection

The values output from the unit 110 are repeatedly selected and output, and the output amplifier 124 is output from the data alignment block 122 .

Finally, a grayscale voltage is generated using the output values.

In this way, the second selector 114 of the half-gray voltage selector 110 is formed into one decoder corresponding to the number of bits provided.

By forming a plurality of decoders having a smaller number of bits rather than

can be significantly reduced.

Hereinafter, the present invention will be described in more detail with specific examples.

Fig. 3 is a schematic block diagram of the actual implementation of Fig. 2;

Compared with FIG. 1, the conventional Real 8-bit decoder has been changed to a 6+2 bit decoder, and the conventional simple-function output amplifier

is a function of synthesizing one grayscale voltage from four input values received from a 6+2 bit decoder in the present invention.

turned into an output amplifier.

In the present invention, using such a configuration, a decoder can be implemented with 162 transistors, thereby

The area of the contrast decoder can be reduced to 1/3.

4 is a schematic block diagram of the 6+2 bit decoder of FIG. 2 .

In FIG. 3, the 6+2 bit decoder is a 5-bit decoder using the upper 5 bits of the digital signal, and a 5-bit decoder using the upper 6 bits.

It can be seen that it is composed of a pseudo decoder and a data alignment block using the lower 3 bits.

FIG. 5 is a schematic block diagram of the 5-bit decoder of FIG. 4 .

The 5-bit decoder is a general decoder, and a preset reference gradation voltage according to the applied 5-bit signal (D[7] to D[3]).

Select one (out2) of (V1, V33 .. V31, V63) and output it.

6 is a schematic block diagram of the 5-bit pseudo decoder of FIG.

The 5-bit pseudo decoder is not implemented as a single decoder, but several decoders with a small number of bits and a

Implemented using Earl Switch. The number of selectable data in a 5-bit pseudo decoder is 2

5

+1 or pick it up

This requires 6 bits of data.

In FIG. 6, each decoder selects and outputs a preset reference gradation voltage according to an applied digital signal, and

The real switch outputs the input reference grayscale voltage as it is when a preset digital signal is applied.

For example, in the 1-bit decoder of FIG. 6, two standards are set so that only D[7] bits are distinguished and not D[6] to D[2] are distinguished.

Selects one of the grayscale voltages, and the 2-bit decoder is divided into D[7] and D[6] bits, and there is no distinction between D[5] and D[2] bits.

Select one of the four reference gradation voltages set not to be disabled.

7 is a table showing the input/output configuration of the data alignment block of FIG. 4 .

Outputting four reference grayscale voltages overlappingly selected from out1 and out2 according to the three lower bits applied in FIG. 7 .

can confirm.

8 is a table showing an input/output configuration of the 5-bit decoder of FIG. 4 .

In FIG. 8, the 5-bit decoder indicates that the reference grayscale voltage is set to correspond to the input 5-bit digital signal, respectively.

can be checked

9 is a table showing an input/output configuration of the 5-bit pseudo decoder of FIG. 4 .

As can be seen in FIG. 9 , the 5-bit pseudo decoder is standard to correspond to all input 6-bit signals, respectively.

Rather than setting the gradation voltage, the same reference gradation voltage may be set for different digital signal inputs.

do.

In addition, the set reference gradation voltage is a reference gradation voltage different from that of the 5-bit decoder, and the upper one bit D of the digital signal

Two reference grayscale voltages are distinguished by [7], and four reference grayscale voltages are distinguished by the upper two bits D[7], D[6].

set in a distinct way.

10 is a table showing the input/output configuration of the 5-bit decoder, the 5-bit pseudo decoder, and the entire digital-to-analog converter of FIG. 4 .

As can be seen in FIG. 10, the 5-bit decoder is set so that the output value corresponds to the upper five bits of the digital signal.

is determined, and the 5-bit pseudo decoder is divided by the D[2] input value and is larger or smaller than the output value of each 5-bit decoder.

set to correspond to

Finally, the gradation voltage finally output by this configuration is the output value of the 5-bit decoder and the 5-bit pseudo decoder and

These are the three values synthesized between all adjacent outputs of the two decoders.

Although the present invention has been described by way of some preferred embodiments, the scope of the present invention should not be limited thereby.

And, it should also be limited to the modification or improvement of the above embodiment supported by the claims.

Claims (5)

A grayscale voltage corresponding to an externally applied digital signal is generated and output from a plurality of reference grayscale voltages.
A digital-to-analog converter comprising:
a half gray voltage selector selecting two half gray voltages from among the plurality of reference gray voltages, and the half gray voltage
and a gradation voltage generator configured to generate the gradation voltage from a voltage, wherein the gradation voltage generator includes an m-bit phase.
generating the gradation voltage according to a preset k bit among the digital signals,
The half-gray voltage selector,
A first line for selecting a first halftone voltage using a decoder of mk bits except for the k bits among the m bits
housekeeper; and
a plurality of decoders ranging from a 1-bit decoder to a mk-1 bit decoder, wherein the second half-tone voltage is different from the first halftone voltage.
and a second selector for selecting the half-gray voltage. The method of claim 1,
The second selection unit
Digital-to-analog converter, characterized in that it further comprises m-k + 2 serial switches. 3. The method of claim 2,
The m-k+2 serial switches are a plurality of serial switches from a 2-bit serial switch to a mk-bit serial switch.
Digital-to-analog converter, characterized in that it consists of a value, and three m-k+1 bit serial switches. A grayscale voltage corresponding to an externally applied digital signal is generated and output from a plurality of reference grayscale voltages.
A driving device for a liquid crystal display including a digital-to-analog converter, comprising:
a half gray voltage selector selecting two half gray voltages from among the plurality of reference gray voltages, and the half gray voltage
and a gradation voltage generator configured to generate the gradation voltage from a voltage, wherein the gradation voltage generator includes an m-bit phase.
generating the gradation voltage according to a preset k bit among the digital signals,
The half-gray voltage selector,
A first line for selecting a first halftone voltage using a decoder of mk bits except for the k bits among the m bits
housekeeper; and
a plurality of decoders ranging from a 1-bit decoder to a mk-1 bit decoder, wherein the second half-tone voltage is different from the first halftone voltage.
and a second selector for selecting a half-tone voltage. A grayscale voltage corresponding to an externally applied digital signal is generated and output from a plurality of reference grayscale voltages.
A liquid crystal display device comprising a digital-to-analog converter, comprising:
a half gray voltage selector selecting two half gray voltages from among the plurality of reference gray voltages, and the half gray voltage
and a gradation voltage generator configured to generate the gradation voltage from a voltage, wherein the gradation voltage generator includes an m-bit phase.
generating the gradation voltage according to a preset k bit among the digital signals,
The half-gray voltage selector,
A first line for selecting a first halftone voltage using a decoder of mk bits except for the k bits among the m bits
housekeeper; and
a plurality of decoders ranging from a 1-bit decoder to a mk-1 bit decoder, wherein the second half-tone voltage is different from the first halftone voltage.
and a second selector for selecting a half-tone voltage.