KR20220079772A - Display device and inspection method thereof - Google Patents

Abstract

The display device includes a display panel and an antireflection layer disposed on the display panel, wherein the display panel is disposed inside a first edge of the display panel and the first edge of the display panel when viewed in a plan view and a mark defining layer disposed between the second edges of the antireflection layer to define a mark, wherein the mark defining layer includes a first extension extending in a first direction, and spaced apart from each other in the first direction, a plurality of second extensions extending from the first extension in a second direction intersecting the first direction, wherein the mark may be defined as a region surrounded by the first and second extensions. .

Description

Display device and its inspection method

The present invention relates to a display device and an inspection method thereof.

In general, electronic devices such as smart phones, digital cameras, notebook computers, navigation devices, and smart TVs that provide images to users include display devices for displaying images. The display device generates an image and provides the generated image to a user.

A display device includes a display panel that generates an image and functional elements that provide various functions to a user. The functional elements include a speaker, a camera, a sensor, a function button, and the like.

The unit panels may be cut from a parent panel including a plurality of unit panels, and each of the unit panels may be used as a display panel.

SUMMARY OF THE INVENTION An object of the present invention is to provide a mark that is visually recognized more accurately in order to inspect a cut line of a display panel.

A display device according to an exemplary embodiment includes a display panel and an anti-reflection layer disposed on the display panel, wherein the display panel includes a first edge of the display panel and the display panel of the display panel when viewed in a plan view. and a mark defining layer disposed between a second edge of the antireflection layer disposed inside the first edge to define a mark, wherein the mark defining layer includes a first extension extending in a first direction, and the second edge a plurality of second extensions spaced apart from each other in a first direction and extending from the first extension in a second direction intersecting the first direction, wherein the mark is surrounded by the first and second extensions This can be defined as an area.

The marks may be spaced apart from the first edge by a first interval, and may be spaced apart from the second edge by a second interval.

The first interval may be different from the second interval.

The first interval may be the same as the second interval.

The first interval and the second interval are set to 50 μm to 70 μm.

The first interval and the second interval may be distances measured from a reference point of the mark, and the reference point may be adjacent to the first extension.

Inner surfaces of the second extensions facing each other may extend in the second direction, and inner surfaces of the first extension connected to the inner surfaces of the second extensions may extend in the first direction.

The display panel may further include a pixel, and the pixel may include a transistor including a source, a drain, and a gate, a light emitting device connected to the transistor, and a connection electrode connecting the transistor to the light emitting device.

The mark defining layer may be formed of the same material as the gate and disposed on the same layer as the gate.

The mark defining layer may be formed of the same material as the connection electrode and disposed on the same layer as the connection electrode.

The display panel may further include a sensing electrode disposed on the pixel, and the mark defining layer may be formed of the same material as the sensing electrode and disposed on the same layer as the sensing electrode.

A plurality of mark defining layers may be provided, and a cut line of the display panel may be defined by the plurality of mark defining layers.

The display device is spaced apart from the first extension in the second direction to extend in the first direction, and has a third extension extending from one of the second extensions to the second extension of the other. It may further include a portion, wherein the mark may be defined as a region surrounded by the first, second, and third extensions.

The mark may have a rectangular shape.

The mark may have a circular shape.

The inner surfaces of the second extensions facing each other and the inner surfaces of the first extension connected to the inner surfaces of the second extensions may be defined as continuous curved surfaces.

A method of inspecting a display device according to an exemplary embodiment of the present invention includes providing a mother panel including a plurality of display panels and anti-reflection layers respectively disposed on the display panels, and cutting the display panels and the anti-reflection layers. and inspecting a cutting line of each of the display panels defined by an edge of each of the display panels, wherein the display panel includes a first edge and the first edge of the display panel when viewed in a plan view. and a mark defining layer disposed between second edges of the antireflection layer disposed inside the first edge of the display panel to define a mark, wherein the mark defining layer includes a first extension extending in a first direction , and and a plurality of second extension portions spaced apart from each other in the first direction and extending from the first extension portion in a second direction intersecting the first direction, and inspecting the cutting line includes the first and and examining a gap between the cut line and the mark by recognizing the mark defined as an area surrounded by the second extensions.

The display panel further includes a pixel and a sensing electrode disposed on the pixel, wherein the pixel includes a transistor including a source, a drain, and a gate, a light emitting device connected to the transistor, and the transistor connected to the light emitting device and a connecting electrode for connecting, wherein the mark defining layer is formed of the same material as at least one of the gate, the connecting electrode, and the sensing electrode to form the same layer as the gate, the same layer as the connecting electrode, and the sensing It may be disposed on at least one of the layers such as the electrode.

When light is irradiated toward the mark defining layer, the mark may be viewed brighter than the mark defining layer.

In the inspection method of the display device, a reference interval between the mark and the mark and the adjacent cutting line is set to 50 μm to 70 μm, and the interval between the mark and the mark and the adjacent cutting line is greater than the reference interval, or The method may further include determining the display device as a good product, and determining the display device as a defective product when the mark and the distance between the mark and the cutting line adjacent to the mark are smaller than the reference distance.

According to an embodiment of the present invention, a mark defining layer may be formed of a metal around a position where a mark is disposed, and a mark may be defined in an area surrounded by the mark defining layer. In this case, to the camera inspecting the cut line of the display panel, the cut line, the mark defining layer, and the antireflection layer adjacent to the mark defining layer are viewed as dark, and the components other than the cut line, the mark defining layer, and the antireflection layer are viewed brightly. can That is, unlike the previous inventions in which the mark was darkly recognized, the mark of the present invention can be viewed brightly.

Even when the mark and the antireflection layer and the mark and the cutting line are disposed adjacently, the distance between the mark and the antireflection layer and the distance between the mark and the cutting line due to the difference in luminance can be recognized more clearly than the conventional inventions. .

Accordingly, the distance between the antireflection layer and the mark in consideration of the tolerance for attachment of the antireflection layer is reduced compared to the prior art, and thus a dead space of the display panel may be reduced.

In addition, the distance between the cutting line and the mark in consideration of the error of the cutting line is reduced compared to the prior inventions, so that the dead space of the display panel may be reduced.

1 is a perspective view of a display device according to an exemplary embodiment.
2 is a plan view exemplarily illustrating a mother panel including a plurality of display panels.
FIG. 3 is a plan view exemplarily illustrating one of the display panels shown in FIG. 2 .
4 is a view exemplarily illustrating a state in which the mother panel shown in FIG. 2 is disposed on the stage of the cutting device.
FIG. 5 is a view exemplarily illustrating a display panel cut by the cutting device shown in FIG. 4 .
6 is a cross-sectional view of the display panel shown in FIG. 5 .
7 is a plan view of the display panel shown in FIG. 5 .
8A is a cross-sectional view illustrating a display panel including a mark defining layer in a circuit element layer.
8B is a cross-sectional view illustrating a display panel including a mark defining layer on the same layer as sensing electrodes.
FIG. 9A is an enlarged view of area AA shown in FIG. 5 .
FIG. 9B is a view exemplarily illustrating a case in which an anti-reflection layer partially overlaps the mark shown in FIG. 9A.
9C is a view exemplarily illustrating a case in which a cutting line is adjacent to the mark shown in FIG. 9A.
10 is a cross-sectional view taken along line I-I' shown in FIG. 9A.
11 is a cross-sectional view of a display panel according to another exemplary embodiment.
12 is a cross-sectional view of a display panel according to another exemplary embodiment.
13 is a cross-sectional view of a display panel according to another exemplary embodiment.

In this specification, when a component (or region, layer, portion, etc.) is referred to as being “on,” “connected to,” or “coupled to” another component, it is directly disposed/on the other component. It means that it can be connected/coupled or a third component can be placed between them.

Like reference numerals refer to like elements. In addition, in the drawings, thicknesses, ratios, and dimensions of components are exaggerated for effective description of technical content.

“and/or” includes any combination of one or more that the associated configurations may define.

Terms such as first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component. The singular expression includes the plural expression unless the context clearly dictates otherwise.

In addition, terms such as "below", "below", "above", and "upper side" are used to describe the relationship of the components shown in the drawings. The above terms are relative concepts, and are described based on directions indicated in the drawings.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. In addition, terms such as terms defined in commonly used dictionaries should be construed as having a meaning consistent with the dictionary meaning in the context of the related art, and unless interpreted in an ideal or overly formal sense, expressly here can be defined in

Terms such as “comprise” or “have” are intended to designate that a feature, number, step, action, component, part, or combination thereof described in the specification is present, and includes one or more other features, number, or step. , it should be understood that it does not preclude in advance the possibility of the existence or addition of an operation, an element, a part, or combinations thereof.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1 is a perspective view of a display device according to an exemplary embodiment.

Referring to FIG. 1 , a display device DD according to an exemplary embodiment has short sides extending in a first direction DR1 and long sides extending in a second direction DR2 intersecting the first direction DR1 . It may have a rectangular shape with However, the present invention is not limited thereto, and the display device DD may have various shapes, such as a circular shape and a polygonal shape.

The display device DD may have a thin thickness in the third direction DR3 . The third direction DR3 indicates a direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 . In the present specification, the meaning of “viewed on a plane” may refer to a state viewed in the third direction DR3.

The upper surface of the display device DD may be defined as the display surface DS and may have a plane defined by the first direction DR1 and the second direction DR2 . The images IM generated by the display device DD may be provided to the user through the display surface DS.

The display surface DS may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA may display an image, and the non-display area NDA may not display an image. The non-display area NDA may surround the display area DA and define a border of the display device DD printed in a predetermined color.

2 is a plan view exemplarily illustrating a mother panel including a plurality of display panels.

Referring to FIG. 2 , the mother panel MS may include a plurality of display panels DP. Although it is illustrated that eight display panels DP are included in the mother panel MS, this is illustrated as an example, and a larger number of display panels DP may be included in the mother panel MS.

The mother panel MS may have a rectangular shape having long sides extending in the first direction DR1 and short sides extending in the second direction DR2 .

The display panels DP may be partitioned apart from each other at regular intervals. The display panels DP may have a rectangular shape having short sides extending in the first direction DR1 and long sides extending in the second direction DR2 . However, the present invention is not limited thereto, and the display panels DP may have various shapes, such as circular and polygonal shapes.

Each of the display panels DP may include a mark defining layer MKS. In an embodiment of the present invention, a plurality of mark defining layers MKS may be provided. For example, each of the plurality of mark defining layers MKS may be disposed adjacent to the outside of the display panel DP. Although eight mark defining layers MKS are exemplarily illustrated in the display panel DP, the number of mark defining layers MKS is not limited thereto.

Marks MK may be defined by mark defining layers MKS. The marks MK may be used in a process of aligning the display panel DP with a cutting device MM to be described later and checking whether the cut display panel DP is defective.

FIG. 3 is a plan view exemplarily illustrating one of the display panels shown in FIG. 2 .

Referring to FIG. 3 , an anti-reflection layer RPL may be disposed on the display panel DP. An outline of the display panel DP may be defined as a first edge BDL1 , and an outline of the anti-reflection layer RPL may be defined as a second edge BDL2 . When viewed in a plan view, the anti-reflection layer RPL may be disposed inside the display panel DP rather than the first edge BDL1 of the display panel DP. That is, the second edge BDL2 may be disposed inside the first edge BDL1 . The anti-reflection layer RPL may overlap the display panel DP. The anti-reflection layer RPL may have a rectangular shape having short sides extending in the first direction DR1 and long sides extending in the second direction DR2 .

The mark defining layer MKS includes a plurality of first mark defining layers MKS1, a plurality of second mark defining layers MKS2, a plurality of third mark defining layers MKS3, and a plurality of fourth mark defining layers. layers MKS4.

The cutting line CL may include a first cutting line CL1 , a second cutting line CL2 , a third cutting line CL3 , and a fourth cutting line CL4 .

The mark defining layer MKS may be disposed between the first edge BDL1 and the second edge BDL2 in a plan view. Accordingly, the mark MK defined by the mark defining layer MKS may be disposed between the first edge BDL1 and the second edge BDL2 .

The first mark defining layers MKS1 may be disposed between a right side surface of the first edge BDL1 and a right side surface of the second edge BDL2 when viewed in a plan view. One surface of the mark MK that is not adjacent to the first mark defining layer MKS1 may be disposed toward a right surface of the first edge BDL1 . However, the present invention is not limited thereto, and one surface of the mark MK that is not adjacent to the first mark defining layer MKS1 may be disposed toward the right surface of the second edge BDL2 . The first cut line CL1 may be aligned by the first mark defining layers MKS1 .

The second mark defining layers MKS2 may be disposed between a lower surface of the first edge BDL1 and a lower surface of the second edge BDL2 when viewed in a plan view. One surface of the mark MK that is not adjacent to the second mark defining layer MKS2 may be disposed toward the lower surface of the first edge BDL1 . However, the present invention is not limited thereto, and one surface of the mark MK that is not adjacent to the second mark defining layer MKS2 may be disposed toward the lower surface of the second edge BDL2 . A second cut line CL2 may be aligned with the second mark defining layers MKS2 .

The third mark defining layers MKS3 may be disposed between a left surface of the first edge BDL1 and a left surface of the second edge BDL2 when viewed in a plan view. One surface of the mark MK that is not adjacent to the third mark defining layer MKS3 may be disposed toward the left surface of the first edge BDL1 . However, the present invention is not limited thereto, and one surface of the mark MK that is not adjacent to the third mark defining layer MKS3 may be disposed toward the left surface of the second edge BDL2 . A third cut line CL3 may be aligned with the third mark defining layers MKS3 .

The fourth mark defining layers MKS4 may be disposed between the top surface of the first edge BDL1 and the top surface of the second edge BDL2 when viewed in a plan view. One surface of the mark MK that is not adjacent to the fourth mark defining layer MKS4 may be disposed toward the upper surface of the first edge BDL1 . However, the present invention is not limited thereto, and one surface of the mark MK that is not adjacent to the fourth mark defining layer MKS4 may be disposed toward the upper surface of the second edge BDL2 . A fourth cut line CL4 may be aligned with the fourth mark defining layers MKS4 .

The cutting line CL may be spaced apart from the mark reference points MKP of the marks MK by a reference interval set by a predetermined distance. The predetermined distance may be the first interval GD1.

The cutting line CL may have a rectangular shape having short sides extending in the first direction DR1 and long sides extending in the second direction DR2 when viewed in a plan view. The cutting line CL may correspond to the first edge BDL1 of the display panel DP.

A mark reference point MKP may be defined in the mark MK. The mark reference point MKP may be defined on a long side adjacent to the mark MK and the mark defining layer MKS. The mark reference point MKP may be defined at a central portion of the long side. The mark MK, the mark defining layer MKS, and the mark reference point MKP will be described in detail below with reference to FIGS. 9A, 9B, and 9C.

4 is a view exemplarily illustrating a state in which the mother panel shown in FIG. 2 is disposed on the stage of the cutting device.

Referring to FIG. 4 , the mother panel MS may be disposed on the stage STG, and the cutting device MM may be disposed on the mother panel MS. The stage STG may support the mother panel MS while the cutting device MM performs a cutting process.

The cutting device MM may be disposed adjacent to the parent panel MS. The cutting device MM may cut the mother panel MS disposed on the stage STG. The cutting device MM may cut each of the display panels DP from the mother panel MS along the cutting line CL shown in FIG. 3 . For example, the cutting device MM may cut the target object by irradiating a laser beam to the mother panel MS. To this end, the cutting device MM may include a laser beam generator for generating a laser beam, a scanner for determining an irradiation point of the laser beam, a lens for diffusing/condensing the laser beam, and the like. However, the method of cutting the mother panel MS by the cutting device MM is not limited to the laser beam irradiation method.

FIG. 5 is a view exemplarily illustrating a display panel cut by the cutting device shown in FIG. 4 .

Referring to FIG. 5 , the display panel DP may be separated from the mother panel MS by the cutting device MM illustrated in FIG. 4 . An inspection may be performed to determine whether the separated display panel DP is normally cut along the cutting line CL shown in FIG. 3 . When the display panel DP is normally cut, the first edge BDL1 of the display panel DP may correspond to the cutting line CL shown in FIG. 3 .

Whether the display panel DP is normally cut may be determined by checking the mark reference point MKP of the mark MK. A distance from each of the mark reference points MKP to the first edge BDL1 may be measured. Whether the display panel DP is normally cut will be described in detail below with reference to FIGS. 9A, 9B, and 9C .

6 is a cross-sectional view of the display panel shown in FIG. 5 .

Referring to FIG. 6 , the display device DD may include a display panel DP, an input sensing unit ISP, and an anti-reflection layer RPL.

The display panel DP according to an embodiment of the present invention may be a light emitting display panel. For example, the display panel DP may be an organic light emitting display panel or a quantum dot light emitting display panel. The emission layer of the organic light emitting display panel may include an organic light emitting material. The emission layer of the quantum dot light emitting display panel may include quantum dots and quantum rods. Hereinafter, the display panel DP will be described as an organic light emitting display panel.

The display panel DP may generate an image through an organic light emitting material. The image generated by the display panel DP may be viewed by the user through the display surface DS shown in FIG. 1 . The display panel DP may include a substrate SUB, a circuit element layer DP-CL, a display element layer OL, and a thin film encapsulation layer TFE.

The substrate SUB may be a base layer of the display panel DP. The substrate SUB may include a flexible substrate. For example, the substrate SUB may include polyimide (PI) or polyethylene terephthalate (PET). However, the material of the substrate SUB is not limited thereto. The substrate SUB may include other flexible materials.

The circuit element layer DP-CL may be disposed on the substrate SUB. The circuit element layer DP-CL may overlap the display area DA and the non-display area NDA.

The circuit element layer DP-CL may include an insulating layer, a semiconductor pattern, a conductive pattern, and a signal line. An insulating layer, a semiconductor layer, and a conductive layer are formed on the substrate SUB by a method such as coating and deposition, and thereafter, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned through a plurality of photolithography processes. . Thereafter, a semiconductor pattern, a conductive pattern, and a signal line of the circuit element layer DP-CL may be formed.

The display element layer OL may be disposed on the circuit element layer DP-CL. The display element layer OL may overlap the display area DA. The display element layer OL may include a light emitting element. For example, the display device layer OL may include an organic light emitting material, quantum dots, quantum rods, or micro LEDs.

The thin film encapsulation layer TFE may be disposed on the display element layer OL. More specifically, a central region of the thin film encapsulation layer TFE may be disposed on the display element layer OL, and an edge region of the thin film encapsulation layer TFE may be disposed on the circuit element layer DP-CL.

The thin film encapsulation layer TFE may include at least two inorganic layers and an organic layer disposed between the inorganic layers. The inorganic layers may include an inorganic material and may protect the display element layer OL from moisture/oxygen. The organic layer may include an organic material and may protect the display element layer OL from foreign substances such as dust particles.

The input sensing unit ISP may be disposed on the display panel DP. The input sensing unit ISP may sense an external input (eg, a user's touch), change it into a predetermined input signal, and provide the input signal to the display panel DP. The display panel DP may receive an input signal from the input detection unit ISP and may generate an image corresponding to the input signal.

The anti-reflection layer RPL may be disposed on the display panel DP. The anti-reflection layer (RPL) may be an external light anti-reflection film. The anti-reflection layer RPL may reduce reflectivity of external light incident toward the display panel DP from the top of the display device DD. For example, the anti-reflection layer RPL may include a retarder and/or a polarizer.

However, the cross-sectional structure of the display device DD is not limited thereto. The display device DD may include other functional layers.

7 is a plan view of the display panel shown in FIG. 5 .

Referring to FIG. 7 , the display panel DP may include a display area DA and a non-display area NDA surrounding the display area DA.

The display panel DP includes a plurality of pixels PX, a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, a plurality of light emitting lines EL1 to ELm, first and It may include second control lines CSL1 and CSL2 , first and second power lines PL1 and PL2 , connection lines CNL, and a plurality of pads PD. m and n are natural numbers.

The pixels PX may be disposed in the display area DA. The scan driver SDV and the light emission driver EDV may be disposed in the non-display area NDA adjacent to the long sides of the display panel DP, respectively. The data driver DDV may be disposed in the non-display area NDA adjacent to any one of the short sides of the display panel DP. When viewed in a plan view, the data driver DDV may be adjacent to the lower end of the display panel DP.

The scan lines SL1 to SLm may extend in the first direction DR1 to be connected to the pixels PX and the scan driver SDV. The data lines DL1 to DLn may extend in the second direction DR2 to be connected to the pixels PX and the data driver DDV. The emission lines EL1 to ELm may extend in the first direction DR1 to be connected to the pixels PX and the emission driver EDV.

The first power line PL1 may extend in the second direction DR2 and be disposed in the non-display area NDA. The first power line PL1 may be disposed between the display area DA and the light emission driver EDV, but is not limited thereto, and may be disposed between the display area DA and the scan driver SDV.

The connection lines CNL may extend in the first direction DR1 and may be arranged in the second direction DR2 . The connection lines CNL may be connected to the first power line PL1 and the pixels PX. A first voltage may be applied to the pixels PX through the first power line PL1 and the connection lines CNL connected to each other.

The second power line PL2 may be disposed in the non-display area NDA. The second power line PL2 may extend along long sides of the display panel DP and the other short side of the display panel DP on which the data driver DDV is not disposed. The second power line PL2 may be disposed outside the scan driver SDV and the light emission driver EDV.

Although not shown, the second power line PL2 may extend toward the display area DA and be connected to the pixels PX. A second voltage having a lower level than the first voltage may be applied to the pixels PX through the second power line PL2 .

The first control line CSL1 may be connected to the scan driver SDV and may extend toward a lower end of the display panel DP when viewed in a plan view. The second control line CSL2 is connected to the light emission driver EDV and may extend toward the lower end of the display panel DP when viewed in a plan view. The data driver DDV may be disposed between the first control line CSL1 and the second control line CSL2 .

The pads PD may be disposed on the display panel DP. The pads PD may be closer to the lower end of the display panel DP than the data driver DDV. The data driver DDV, the first power line PL1 , the second power line PL2 , the first control line CSL1 , and the second control line CSL2 may be connected to the pads PD. The data lines DL1 to DLn may be connected to the data driver DDV, and the data driver DDV may be connected to the pads PD corresponding to the data lines DL1 to DLn.

Although not shown, a timing controller for controlling operations of the scan driver SDV, the data driver DDV, and the light emission driver EDV and a voltage generator for generating first and second voltages are disposed on the printed circuit board can be The timing controller and the voltage generator may be connected to the corresponding pads PD through a printed circuit board.

The scan driver SDV may generate a plurality of scan signals, and the scan signals may be applied to the pixels PX through the scan lines SL1 to SLm. The data driver DDV may generate a plurality of data voltages, and the data voltages may be applied to the pixels PX through the data lines DL1 to DLn. The emission driver EDV generates a plurality of emission signals, and the emission signals may be applied to the pixels PX through the emission lines EL1 to ELm.

The pixels PX may receive data voltages in response to scan signals. The pixels PX may display an image by emitting light having a luminance corresponding to the data voltages in response to the emission signals. The emission time of the pixels PX may be controlled by the emission signals.

8A is a cross-sectional view illustrating a display panel including a mark defining layer in a circuit element layer. 8B is a cross-sectional view illustrating a display panel including a mark defining layer on the same layer as sensing electrodes.

For convenience of description, the same components as those of the display device illustrated in FIG. 6 are denoted by the same reference numerals, and descriptions thereof are omitted.

8A and 8B , the pixel PX may include a transistor TR and a light emitting device OLED. The light emitting device OLED may include a first electrode AE, a second electrode CE, a hole control layer HCL, an electron control layer ECL, and an emission layer EML. The first electrode AE may be an anode electrode, and the second electrode CE may be a cathode electrode.

The transistor TR and the light emitting device OLED may be disposed on the substrate SUB. Although one transistor TR is illustrated as an example, the pixel PX may include a plurality of transistors and at least one capacitor for driving the light emitting device OLED.

The display area DA may include a light emitting part PA corresponding to the pixel PX and a non-emission part NPA around the light emitting part PA. The light emitting device OLED may be disposed on the light emitting part PA.

A buffer layer BFL is disposed on the substrate SUB, and the buffer layer BFL may be an inorganic layer.

A semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon. However, the present invention is not limited thereto, and the semiconductor pattern may include amorphous silicon or metal oxide.

The semiconductor pattern may be doped with an N-type dopant or a P-type dopant. The semiconductor pattern may include a highly doped region and a low doped region. The conductivity of the highly doped region is greater than that of the low doped region, and may substantially serve as a source electrode and a drain electrode of the transistor TR. The low doped region may substantially correspond to the active (or channel) of the transistor.

The source S, the active A, and the drain D of the transistor TR may be formed from a semiconductor pattern. A first insulating layer INS1 may be disposed on the semiconductor pattern. A gate G of the transistor TR may be disposed on the first insulating layer INS1 . A second insulating layer INS2 may be disposed on the gate G. A third insulating layer INS3 may be disposed on the second insulating layer INS2 .

The circuit element layer DP-CL may include a mark defining layer MKS. The mark defining layer MKS is formed when the source S, active A, drain D, and gate G of the transistor TR are formed, the source S, active A, and drain D ), and the gate (G) may be formed of the same material. The mark defining layer MKS may be disposed on the same layer as the source S, the active A, and the drain D. The mark defining layer MKS may be disposed on the same layer as the gate G. The mark defining layer MKS may be disposed adjacent to the edge of the circuit element layer DP-CL in a plan view.

The connection electrode CNE may be disposed between the transistor TR and the light emitting device OLED to connect the transistor TR and the light emitting device OLED. The connection electrode CNE may include a first connection electrode CNE1 and a second connection electrode CNE2 .

The first connection electrode CNE1 is disposed on the third insulating layer INS3 and is connected to the drain D through the first contact hole CH1 defined in the first to third insulating layers INS1 to INS3 . can be connected The fourth insulating layer INS4 may be disposed on the first connection electrode CNE1 . A fifth insulating layer INS5 may be disposed on the fourth insulating layer INS4 .

The second connection electrode CNE2 may be disposed on the fifth insulating layer INS5 . The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through the second contact hole CH2 defined in the fifth insulating layer INS5 . A sixth insulating layer INS6 may be disposed on the second connection electrode CNE2 . The first insulating layer INS1 to the sixth insulating layer INS6 may be an inorganic layer or an organic layer.

When the first connection electrode CNE1 and the second connection electrode CNE2 are formed, the mark defining layer MKS may be formed of the same material as the first connection electrode CNE1 and the second connection electrode CNE2. . The mark defining layer MKS may be disposed on the same layer as the first connection electrode CNE1. The mark defining layer MKS may be disposed on the same layer as the second connection electrode CNE2 . The mark defining layer MKS may be disposed adjacent to the edge of the circuit element layer DP-CL in a plan view.

The first electrode AE may be disposed on the sixth insulating layer INS6 . The first electrode AE may be connected to the second connection electrode CNE2 through the third contact hole CH3 defined in the sixth insulating layer INS6 . A pixel defining layer PDL exposing a predetermined portion of the first electrode AE may be disposed on the first electrode AE and the sixth insulating layer INS6 . An opening PX_OP for exposing a predetermined portion of the first electrode AE may be defined in the pixel defining layer PDL.

The hole control layer HCL may be disposed on the first electrode AE and the pixel defining layer PDL. The hole control layer HCL may be disposed in common in the light emitting part PA and the non-emission part NPA. The hole control layer HCL may include a hole transport layer and a hole injection layer.

The emission layer EML may be disposed on the hole control layer HCL. The emission layer EML may be disposed in a region corresponding to the opening PX_OP. The emission layer EML may include an organic material and/or an inorganic material. The emission layer EML may generate any one of red, green, and blue light.

The electron control layer ECL may be disposed on the emission layer EML and the hole control layer HCL. The electronic control layer ECL may be commonly disposed on the light emitting part PA and the non-emission part NPA. The electron control layer (ECL) may include an electron transport layer and an electron injection layer.

The second electrode CE may be disposed on the electronic control layer ECL. The second electrode CE may be disposed in common to the pixels PX.

A first voltage may be applied to the first electrode AE through the transistor TR, and a second voltage having a lower level than the first voltage may be applied to the second electrode CE. Holes and electrons injected into the light emitting layer EML combine to form an exciton, and as the exciton transitions to a ground state, the light emitting device OLED may emit light.

The input sensing unit ISP may be disposed on the thin film encapsulation layer TFE. The input sensing unit ISP includes a plurality of first and second sensing electrodes TE1 and TE2, a first sensing insulating layer IL1, and a second sensing insulating layer IL2 for sensing an external input in a capacitive manner. ), and a third sensing insulating layer IL3. The input sensing unit ISP may be directly manufactured on the display panel DP when the display device DD is manufactured. However, the present invention is not limited thereto, and the input sensing unit ISP may be manufactured as a separate panel from the display panel DP, and may be attached to the display panel DP by an adhesive layer.

A first sensing insulating layer IL1 may be disposed on the thin film encapsulation layer TFE. The first sensing insulating layer IL1 may be an inorganic layer including at least one of silicon nitride, silicon oxynitride, and silicon oxide. Alternatively, the first sensing insulating layer IL1 may be an organic layer including an epoxy resin, an acrylic resin, or an imide-based resin.

The second sensing electrodes TE2 may be disposed on the first sensing insulating layer IL1 . A second sensing insulating layer IL2 may be disposed on the second sensing electrodes TE2 . The first sensing electrodes TE1 may be disposed on the second sensing insulating layer IL2 . A third sensing insulating layer IL3 may be disposed on the first sensing electrodes TE1 . The third sensing insulating layer IL3 may cover the first sensing electrodes TE1 .

At least one of the second sensing insulating layer IL2 and the third sensing insulating layer IL3 may include an inorganic layer. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

At least one of the second sensing insulating layer IL2 and the third sensing insulating layer IL3 may include an organic layer. The organic film is at least any one of acrylic resin, methacrylic resin, polyisoprene, vinyl-based resin, epoxy-based resin, urethane-based resin, cellulose-based resin, siloxane-based resin, polyimide-based resin, polyamide-based resin, and pellylene-based resin may include

The mark defining layer MKS is made of the same material as the first sensing electrodes TE1 and the second sensing electrodes TE2 when the first sensing electrodes TE1 and the second sensing electrodes TE2 are formed. can be formed. The mark defining layer MKS may be disposed on the same layer as the first sensing electrodes TE1 . The mark defining layer MKS may be disposed on the same layer as the second sensing electrodes TE2 . The mark defining layer MKS may be disposed adjacent to the edge of the input sensing unit ISP when viewed in a plan view.

FIG. 9A is an enlarged view of area AA shown in FIG. 5 . FIG. 9A is a view of the display panel DP normally cut along the cutting line CL. The cutting line CL may correspond to the first edge BDL1 shown in FIG. 5 .

Referring to FIG. 9A , the mark defining layer MKS may be disposed between the second edge BDL2 of the anti-reflection layer RPL and the cut line CL.

The mark defining layer MKS may include a first extension part EXP1 and a plurality of second extension parts EXP2 . The first extension part EXP1 may extend in the first direction DR1 . The second extension parts EXP2 may be spaced apart from each other in the first direction DR1 , and may extend from the first extension part EXP1 in the second direction DR2 .

The inner surfaces of the second extensions EXP2 may face each other and extend in the second direction DR2 . The inner surfaces of the first extensions EXP1 may be connected to inner surfaces of the second extensions EXP2 . An inner surface of the first extension EXP1 may extend in the first direction.

A mark MK may be defined by the first extension parts EXP1 and the second extension parts EXP2 . That is, the mark MK may be defined as an area surrounded by the first extension parts EXP1 and the second extension parts EXP2 .

The mark reference point MKP may be defined on an adjacent surface of the mark MK and the first extension EXP1 . That is, the mark reference point MKP may be disposed at the center of the inner surface of the first extension part EXP1.

The marks MK may be spaced apart from the first edge BDL1 by the first gap GD1 , and may be spaced apart from the second edge BDL2 by the second gap GD2 . The first interval GD1 may be defined as a distance between the first edge BDL1 and the mark reference point MKP. The second gap GD2 may be defined as a distance between the second edge BDL2 and the mark reference point MKP.

The first interval GD1 may be set to 50 μm to 70 μm. The second interval GD2 may be set to 50 μm to 70 μm. The first interval GD1 and the second interval GD2 may have different values. The first interval GD1 and the second interval GD2 may have the same value.

The first gap GD1 may be set to align the cutting line CL. A cutting line CL may be defined at a distance spaced apart from the mark reference points MKP by the first interval GD1. By checking the first gap GD1 , it may be determined whether the display panel DP is normally cut. A method of inspecting the cut line CL of the display panel DP will be described in detail below with reference to FIG. 9C .

The second gap GD2 may be set in consideration of an attachment tolerance of the anti-reflection layer RPL. The adhesion tolerance of the anti-reflection layer (RPL) will be described in detail below with reference to FIG. 9B .

FIG. 9B is a view exemplarily illustrating a case in which an anti-reflection layer partially overlaps the mark shown in FIG. 9A. For convenience of description, the same components as those of the display device illustrated in FIG. 9A are denoted by the same reference numerals, and descriptions thereof are omitted.

Referring to FIG. 9B , when disposing the anti-reflection layer RPL on the display panel DP, a tolerance may occur. The anti-reflection layer RPL may be more adjacent to or more spaced apart from the mark reference point MKP than the second gap GD2 illustrated in FIG. 9A . For example, in FIG. 9B , the anti-reflection layer RPL is disposed closer to the mark reference point MKP than the second gap GD2 .

A distance between the anti-reflection layer RPL and the mark reference point MKP may be a third gap GD3 . The third interval GD3 may be smaller than the second interval GD2 .

Although not shown, the light of transmitted illumination is irradiated to the display panel DP to check whether the display panel DP is normally cut along the cutting line CL, and the vicinity of the cut surface of the display panel DP is moved by the camera. can be imaged.

In the case of the existing inventions, the mark MK, the anti-reflection layer (RPL), and the cutting line (CL) are viewed darkly by the camera, and the vicinity other than the mark (MK), the anti-reflection layer (RPL), and the cutting line (CL) is can be brightly recognized. In this case, when the darkly viewed antireflection layer RPL and the darkly viewed mark MK are adjacent to each other by the third gap GD3, the antireflection layer RPL and the mark MK may be recognized as being in contact with each other. . That is, the third interval GD3 may not be visually recognized. Accordingly, in order to visually recognize the third gap GD3 , the anti-reflection layer RPL and the mark MK may require a greater tolerance distance than the second gap GD2 illustrated in FIG. 9A .

In the case of the present invention, the mark defining layer (MKS), the antireflection layer (RPL), and the cut line (CL) are darkly viewed by the camera, and the mark defining layer (MKS) including the mark (MK), the antireflection layer (RPL) , and the vicinity other than the cutting line CL may be visually recognized brightly.

When the antireflection layer RPL is disposed adjacent to the mark MK, between the antireflection layer RPL and the mark MK due to the difference in luminance between the darkly viewed antireflection layer RPL and the brightly viewed mark MK. The separation distance of can be recognized. That is, the third interval GD3 may be visually recognized. Accordingly, the distance between the anti-reflection layer RPL and the mark defining layer MKS in consideration of the attachment tolerance of the anti-reflection layer RPL is reduced compared to the prior art, so that the dead space of the display panel DP may be reduced.

FIG. 9C is a view exemplarily illustrating a case in which a cutting line is adjacent to the mark shown in FIG. 9A. For convenience of description, the same components as those of the display device illustrated in FIG. 9A are denoted by the same reference numerals, and descriptions thereof are omitted.

Referring to FIG. 9C , when the display panel DP is cut along the cutting line CL, the cutting line CL′ is at the mark reference point MKP than the cutting line CL shown in FIG. 9A due to an error. They may be more adjacent or more spaced apart. Exemplarily, in FIG. 9C , the cutting line CL′ is disposed closer to the mark reference point MKP than the first interval GD1.

A distance between the cutting line CL′ and the mark reference point MKP may be a fourth interval GD4. The fourth interval GD4 may be smaller than the first interval GD1 .

In the case of the existing inventions, the cutting line CL' may be viewed darkly by the camera, and the vicinity other than the cutting line CL' may be viewed brightly. In this case, when the darkly recognized cutting line CL' and the darkly viewed mark MK are adjacent to each other by the fourth distance GD4, the cutting line CL' and the mark MK will be recognized as being in contact with each other. can That is, the fourth interval GD4 may not be viewed. Accordingly, in order to visually recognize the fourth gap GD4 , the cut line CL and the mark MK may require a larger distance than the first gap GD1 illustrated in FIG. 9A .

In the case of the present invention, the mark defining layer (MKS), the antireflection layer (RPL), and the cut line (CL') are darkly visually recognized by the camera, and the mark defining layer (MKS) including the mark (MK), the antireflection layer (RPL) ), and the vicinity other than the cut line CL' may be visually recognized brightly.

When the cutting line CL' is disposed adjacent to the mark MK, due to the difference in luminance between the darkly viewed cutting line CL' and the brightly viewed mark MK, the cutting line CL' and the mark MK The separation distance between MK) can be recognized. That is, the fourth interval GD4 may be visually recognized. Accordingly, the distance between the cutting line CL′ and the mark defining layer MKS in consideration of the error of the cutting line CL′ is reduced compared to the conventional embodiments, so that the dead space of the display panel DP can be reduced. .

10 is a cross-sectional view taken along line I-I' shown in FIG. 9A. For convenience of description, the same components as those of the display device illustrated in FIG. 8A are denoted by the same reference numerals, and descriptions thereof are omitted.

Referring to FIG. 10 , the mark defining layer MKS is exemplarily formed of the same material as the gate G when the gate G shown in FIG. 8A is formed, and disposed on the same layer as the gate G became The anti-reflection layer RPL may be disposed on the third sensing insulating layer IL3 .

A distance between the normally cut cutting line CL and the mark reference point MKP in the second direction DR2 may be the first distance GD1 .

A distance spaced apart from the second edge BDL2 of the antireflection layer RPL disposed without a tolerance in the second direction DR2 of the mark reference point MKP may be the second gap GD2 .

11 is a cross-sectional view of a display panel according to another exemplary embodiment. For convenience of explanation, the same components as those of the display panel illustrated in FIGS. 5 and 9A are denoted by the same reference numerals, and descriptions thereof are omitted.

Referring to FIG. 11 , the mark defining layer MKS′ may be disposed at a position corresponding to the mark defining layer MKS shown in FIG. 5 . The inner surfaces of the second extension portions EXP2 facing each other of the mark defining layer MKS′ and the inner surface of the first extension portion EXP1 connected to inner surfaces of the second extension portions EXP2 are continuous curved surfaces. can be defined as That is, the mark MK' may have a semicircular shape.

The mark reference point MKP' may be defined on an inner surface of the first extension EXP1 spaced apart from the center of the semicircle in the second direction DR2. However, the present invention is not limited thereto, and the mark reference point MKP' may be defined at various positions of the mark MK'.

12 is a cross-sectional view of a display panel according to another exemplary embodiment. For convenience of explanation, the same components as those of the display panel illustrated in FIGS. 5 and 9A are denoted by the same reference numerals, and descriptions thereof are omitted.

Referring to FIG. 12 , the mark defining layer MKS″ may further include a third extension EXP3 than the mark defining layer MKS illustrated in FIG. 9A .

The third extension EXP3 may be spaced apart from the first extension EXP1 in the second direction DR2 to extend in the first direction DR1 . The third extension EXP3 may extend from one of the second extensions EXP2 to the other second extension EXP2.

The mark MK'' may be defined as an area surrounded by the first, second, and third extensions EXP1, EXP2, and EXP3 of the mark defining layer MKS''. That is, the mark MK'' may have a rectangular shape.

The mark reference point MKP'' may be defined at the center of the mark MK''. However, the present invention is not limited thereto, and the mark reference point MKP'' may be defined at the center of the inner surface of the first extension part EXP1 and the center of the inner surface of the third extension part EXP3.

13 is a cross-sectional view of a display panel according to another exemplary embodiment. For convenience of description, the same components as those of the display panel illustrated in FIG. 12 are denoted by the same reference numerals, and descriptions thereof are omitted.

Referring to FIG. 13 , inner surfaces of the second extensions EXP2 facing each other, inner surfaces of the first extension EXP1 connected to inner surfaces of the second extensions EXP2 , and the second extensions An inner surface of the third extension EXP3 connected to inner surfaces of EXP2 may be defined as a continuous curved surface. That is, the mark MK''' may have a circular shape.

The mark reference point MKP''' may be defined at the center of the mark MK'''. However, the present invention is not limited thereto, and the mark reference point MKP''' and the inner surface of the first extension EXP1 spaced apart from the center of the mark MK''' in the second direction DR2 and the mark MK' It may be defined at various positions such as the inner surface of the third extension EXP3 spaced apart from the center of the '' in the second direction DR2.

Although the above has been described with reference to the preferred embodiment of the present invention, those skilled in the art or those having ordinary knowledge in the technical field will not depart from the spirit and technical scope of the present invention described in the claims to be described later. It will be understood that various modifications and variations of the present invention can be made without departing from the scope of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

MS: mother panel MM: cutting device
MKS: mark definition layer MK: mark
MKP: Mark reference point CL: Cutting line
BDL1: first rim EXP1: first extension
GD1: first interval GD2: second interval
DP: Display panel RPL: Anti-reflection layer

Claims (20)

display panel; and
an anti-reflection layer disposed on the display panel;
The display panel includes a mark defining layer disposed between a first edge of the display panel and a second edge of the anti-reflection layer disposed inside the first edge of the display panel to define a mark when viewed in a plan view. including,
The mark defining layer may include: a first extension extending in a first direction; and
a plurality of second extension parts spaced apart from each other in the first direction and extending from the first extension part in a second direction intersecting the first direction;
The mark is defined as an area surrounded by the first and second extensions. The method of claim 1,
The mark is spaced apart from the first edge by a first interval, and is spaced apart from the second edge by a second interval. 3. The method of claim 2,
The first interval is different from the second interval. 3. The method of claim 2,
The first interval is the same as the second interval. 3. The method of claim 2,
The first interval and the second interval are set to 50 μm to 70 μm. 3. The method of claim 2,
The first interval and the second interval are distances measured from a reference point of the mark, and the reference point is adjacent to the first extension part. The method of claim 1,
Inner surfaces of the second extensions facing each other extend in the second direction, and inner surfaces of the first extension connected to the inner surfaces of the second extensions extend in the first direction. The method of claim 1,
The display panel further includes a pixel;
The pixel is
a transistor comprising a source, a drain, and a gate;
a light emitting device connected to the transistor; and
and a connection electrode connecting the transistor to the light emitting device. 9. The method of claim 8,
The mark defining layer is formed of the same material as the gate and is disposed on the same layer as the gate. 9. The method of claim 8,
The mark defining layer is formed of the same material as the connection electrode and is disposed on the same layer as the connection electrode. 9. The method of claim 8,
The display panel further includes a sensing electrode disposed on the pixel;
The mark defining layer is formed of the same material as the sensing electrode and disposed on the same layer as the sensing electrode. The method of claim 1,
The mark defining layer is provided in plurality,
A display device in which a cutting line of the display panel is defined by the plurality of mark defining layers. The method of claim 1,
Further comprising a third extension spaced apart from the first extension in the second direction, extending in the first direction, and extending from a second extension of one of the second extensions to a second extension of the other, ,
The mark is defined as an area surrounded by the first, second, and third extensions. 14. The method of claim 13,
The mark has a rectangular shape. 14. The method of claim 13,
The mark has a circular shape. The method of claim 1,
Inner surfaces of the second extensions facing each other and inner surfaces of the first extension connected to the inner surfaces of the second extensions are defined as continuous curved surfaces. providing a mother panel including a plurality of display panels and anti-reflection layers respectively disposed on the display panels;
cutting the display panels and the anti-reflection layers; and
examining a cut line of each of the display panels defined by an edge of each of the display panels;
The display panel may include a mark defining layer disposed between a first edge of the display panel and a second edge of the anti-reflection layer disposed inside the first edge of the display panel to define a mark when viewed in a plan view including,
The mark defining layer,
a first extension portion extending in a first direction; and
a plurality of second extension parts spaced apart from each other in the first direction and extending from the first extension part in a second direction intersecting the first direction;
The inspecting of the cutting line may include inspecting a gap between the cutting line and the mark by recognizing the mark defined as an area surrounded by the first and second extension parts. . 18. The method of claim 17,
The display panel may include: a pixel; and
Further comprising a sensing electrode disposed on the pixel,
The pixel is
a transistor comprising a source, a drain, and a gate;
a light emitting device connected to the transistor; and
and a connection electrode connecting the transistor to the light emitting device,
The mark defining layer is formed of the same material as at least one of the gate, the connection electrode, and the sensing electrode, and at least one of the same layer as the gate, the same layer as the connection electrode, and the same layer as the sensing electrode. An inspection method of a display device disposed on a layer of 18. The method of claim 17,
When light is irradiated toward the mark defining layer, the mark is visually recognized brighter than the mark defining layer. 18. The method of claim 17,
A reference distance between the mark and the cut line adjacent to the mark is set to 50 μm to 70 μm,
If the distance between the mark and the cut line adjacent to the mark is greater than or equal to the reference distance, determining the display device as a good product,
and determining the display device as defective when the distance between the mark and the cut line adjacent to the mark is smaller than the reference distance.

Images